MICROCHIP RTG4 Pākuʻi RTG4 FPGAs Papa Hoʻolālā a me ka Layout Guidelines

Hoʻolauna

ʻO kēia mea hoʻohui i AC439: Papa Hoʻolālā a me nā Papa kuhikuhi no ka RTG4 FPGA Application Note, e hāʻawi i ka ʻike hou aku, e hoʻoikaika i nā alakaʻi hoʻohālikelike lōʻihi DDR3 i paʻi ʻia ma ka hoʻoponopono 9 a i ʻole ma hope ma mua o ka hoʻolālā papa i hoʻohana ʻia no ka pahu kūkulu RTG4™. I ka wā mua, loaʻa wale ka pahu hoʻomohala RTG4 me Engineering Silicon (ES). Ma hope o ka hoʻokuʻu mua ʻia ʻana, ua hoʻopiha ʻia ka pahu me nā mea hana maʻamau (STD) a me ka -1 kime wikiwiki RTG4. ʻO nā helu ʻāpana, RTG4-DEV-KIT a me RTG4-DEV-KIT-1 e hele mai me ka papa wikiwiki STD a me nā mea hana papa wikiwiki -1.
Eia kekahi, ua komo kēia addendum i nā kikoʻī e pili ana i ka ʻenehana I/O no nā ʻano mana-up a me ka mana iho, a me ka ʻōlelo DEVRST_N i ka wā o ka hana maʻamau.

ʻIkepili o ka RTG4-DEV-KIT DDR3 Papa Hoʻolālā

• Hoʻokomo ka pahu hoʻomohala RTG4 i kahi ʻikepili 32-bit a me 4-bit ECC DDR3 interface no kēlā me kēia o nā mea hoʻokele RTG4 FDDR i kūkulu ʻia a me nā poloka PHY (FDDR Hikina a me West). Hoʻonohonoho kino ʻia ke kikowaena ma ke ʻano he ʻelima mau ala byte data.
• Ke hahai nei ka pahu i ka lele ma ke ala alahele e like me ia i wehewehe ʻia ma ka ʻāpana DDR3 Layout Guidelines o AC439: Papa Hoʻolālā a me nā Papa kuhikuhi no ka RTG4 FPGA Application Note. Eia naʻe, ʻoiai ua hoʻolālā ʻia kēia pahu hoʻomohala ma mua o ka paʻi ʻana i ka palapala noi, ʻaʻole ia i kūlike me nā alakaʻi hoʻohālikelike lōʻihi i hōʻano hou ʻia i wehewehe ʻia ma ka palapala noi. Ma ka kikoʻī DDR3, aia kahi +/- 750 ps palena ma ka skew ma waena o ka strobe data (DQS) a me ka uaki DDR3 (CK) ma kēlā me kēia memo hoʻomanaʻo DDR3 i ka wā o kahi kālepa kākau (DSS).
• Ke hahai ʻia nā alakaʻi hoʻohālikelike lōʻihi ma ka AC439 revision 9 a i ʻole nā ​​mana hope o ka palapala noi, e hoʻokō ka papa kuhikuhi papa RTG4 i ka palena tDQSS no nā mea ʻelua -1 a me STD i ka wikiwiki o ke kaʻina holoʻokoʻa, voltage, a me ka wela (PVT) pae hana i kākoʻo ʻia e nā mea hana hana RTG4. Hoʻokō ʻia kēia ma ka helu ʻana i ka skew hopena ʻino loa ma waena o DQS a me CK ma nā pine RTG4. ʻOiaʻiʻo, i ka wā e hoʻohana ai i ka
  kūkulu ʻia ʻo RTG4 FDDR mana me PHY, alakaʻi ka DQS iā CK e 370 ps ke kiʻekiʻe no kahi mea -1 wikiwiki a me DQS Leads CK ma 447 ps kiʻekiʻe no kahi hāmeʻa STD wikiwiki, ma nā kūlana ʻino loa.
• Ma muli o ka hōʻike ʻana i hōʻike ʻia ma ka Papa 1-1, ʻike ka RTG4-DEV-KIT-1 i nā palena tDQSS ma kēlā me kēia memo hoʻomanaʻo, ma nā kūlana hana ʻino loa no ka RTG4 FDDR. Eia nō naʻe, e like me ka mea i hōʻike ʻia ma ka Papa 1-2, ʻo ka ʻōnaehana RTG4-DEV-KIT, i hoʻopiha ʻia me nā hāmeʻa STD speed grade RTG4, ʻaʻole i kūpono i ka tDQSS no nā mea hoʻomanaʻo ʻehā a me ka ʻelima i ka topology lele, ma nā kūlana hana ʻino loa. no ka RTG4 FDDR. Ma keʻano laulā, hoʻohana ʻia ka RTG4-DEV-KIT i nā kūlana maʻamau, e like me ka wela o ka lumi ma kahi ʻoihana lab. No laila, ʻaʻole pili kēia loiloi hihia ʻino loa i ka RTG4-DEV-KIT i hoʻohana ʻia i nā kūlana maʻamau. He exampʻO ke kumu he mea nui e hahai i nā kuhikuhi pili i ka lōʻihi o DDR3 i helu ʻia ma AC439, i hiki ai i kahi hoʻolālā papa hoʻohana ke hālāwai me tDQSS no kahi noi lele.
• No ka wehewehe ʻana i kēia example, a hōʻike i ke ʻano o ka uku lima ʻana no kahi papa RTG4 papa ʻaʻole hiki ke hoʻokō i nā alakaʻi hoʻohālikelike ʻana i ka lōʻihi o ka AC439 DDR3, hiki i ka RTG4-DEV-KIT me nā mea papa wikiwiki STD ke hālāwai me tDQSS i kēlā me kēia memo hoʻomanaʻo, i nā kūlana ʻino loa, no ka mea hiki i ka mea hoʻoponopono RTG4 FDDR i kūkulu ʻia me PHY ke hoʻopaneʻe statically i ka hōʻailona DQS ma kēlā me kēia alana byte data. Hiki ke hoʻohana ʻia kēia hoʻololi static e hoʻemi i ka skew ma waena o DQS a me CK ma kahi mea hoʻomanaʻo me kahi tDQSS> 750 ps. E ʻike i ka ʻāpana Hoʻomaʻamaʻa DRAM, ma UG0573: RTG4 FPGA High Speed ​​DDR Interfaces User Guide no ka ʻike hou aku e pili ana i ka hoʻohana ʻana i nā mana hoʻopaneʻe static (ma ka papa inoa REG_PHY_WR_DQS_SLAVE_RATIO) no DQS i ka wā o kahi kālepa kākau. Hiki ke hoʻohana ʻia kēia waiwai lohi ma Libero® SoC i ka wā e hoʻomaka ai i kahi mea hoʻoponopono FDDR me ka hoʻomaka ʻana ma o ka hoʻololi ʻana i ka code hoʻomaka ʻana o CoreABC FDDR. Hiki ke hoʻohana ʻia kahi kaʻina hana like i kahi hoʻolālā papa hoʻohana i kū ʻole i ka tDQSS ma kēlā me kēia memo hoʻomanaʻo.

Papa 1-1. Ka Loiloi o RTG4-DEV-KIT-1 tDQSS Heluhelu No -1 Mahele a me FDDR1 Interface

ʻIke ʻia ke ala	Ka lōʻihi o ka uaki (mils)	Hoʻopaneʻe ka hoʻolaha ʻana o ka uaki (ps)	Ka lōʻihi o ka ʻikepili (mils)	Hoʻolaha ʻikepili n Hoʻopaneʻe (ps)	ʻOkoʻa ma waena o CLKDQS ma muli o ke alahele (mils)	tDQSS i kēlā me kēia hoʻomanaʻo, ma hope o ka papa skew+FPGA DQSCLK skew (ps)
FPGA-1st Memory	2578	412.48	2196	351.36	61.12	431.12
Hoʻomanaʻo FPGA-2	3107	497.12	1936	309.76	187.36	557.36
Hoʻomanaʻo FPGA-3	3634	581.44	2231	356.96	224.48	594.48
FPGA-4th Memory	4163	666.08	2084	333.44	332.64	702.64
FPGA-5th Memory	4749	759.84	2848	455.68	304.16	674.16

Nānā: Ma nā kūlana maikaʻi loa, RTG4 FDDR DDR3 DQS-CLK skew no nā mea -1 he 370 ps ka nui a me ka 242 ps ka liʻiliʻi.

Papa 1-2. Ka Loiloi o ka helu RTG4-DEV-KIT tDQSS no nā ʻāpana STD a me ka Interface FDDR1

ʻIke ʻia ke ala	Ka lōʻihi o ka uaki (mils)	Hoʻopaneʻe ka hoʻolaha ʻana o ka uaki (ps)	Ka lōʻihi o ka ʻikepili (mils)	Hoʻolaha ʻIkepili n Hoʻopaneʻe (ps)	ʻOkoʻa ma waena o CLKDQS ma muli o ke alahele (mils)	tDQSS i kēlā me kēia hoʻomanaʻo, ma hope o ka papa skew+FPGA DQSCLK skew (ps)
FPGA-1st Memory	2578	412.48	2196	351.36	61.12	508.12
Hoʻomanaʻo FPGA-2	3107	497.12	1936	309.76	187.36	634.36
Hoʻomanaʻo FPGA-3	3634	581.44	2231	356.96	224.48	671.48
FPGA-4th Memory	4163	666.08	2084	333.44	332.64	779.64
FPGA-5th Memory	4749	759.84	2848	455.68	304.16	751.16

Nānā:  Ma nā kūlana maikaʻi loa, ʻo RTG4 FDDR DDR3 DQS-CLK skew no nā mea STD he 447 ps ka nui a me 302 ps ka liʻiliʻi.
Nānā: Ua hoʻohana ʻia ka manaʻo hoʻolāʻihi o ka hoʻolaha ʻana o ka papa o 160 ps/inch i kēia loiloi example no ke kuhikuhi. ʻO ka lōʻihi o ka hoʻolaha ʻana o ka papa no ka papa mea hoʻohana e pili ana i ka papa kikoʻī e nānā ʻia.

Ka Kakau Mana

ʻO kēia mea hoʻohui i AC439: Papa Hoʻolālā a me nā Papa kuhikuhi no ka RTG4 FPGA Application Note, hāʻawi i ka ʻike hou, e hoʻoikaika i ka koʻikoʻi e hahai i nā alakaʻi Hoʻolālā Papa. E mālama i nā alakaʻi e pili ana i ka Power-Up a me ka Power-Down.

Mana-Hoʻonui
Hōʻike ka papa ma lalo nei i nā hihia hoʻohana i manaʻo ʻia a me kā lākou mau alakaʻi alakaʻi mana.

Papa 2-1. Nā Kūlana Power-Up

Hoʻohana i ka hihia	Pono Kakau	ʻAno	Nā memo
DEVRST_N Manaʻo ʻia i ka wā e piʻi ai ka mana, a hiki i nā lako mana RTG4 āpau i nā kūlana hana i manaʻo ʻia	ʻAʻohe r kikoʻīamp- pono ke kauoha. Hoolako ramppono e piʻi monotonically.	Ke hiki i ka VDD a me ka VPP i nā paepae ho'āla (VDD ~= 0.55V, VPP ~= 2.2V) a Hoʻokuʻu ʻia ʻo DEVRST_N, e holo ka POR Delay Counter no ~ 40ms maʻamau (50ms max), a laila pili ka mana o ka mea hana i nā kiʻi 11 a 12 (DEVRST_N PUFT) o Ke alakaʻi alakaʻi o ka mea hoʻohana (UG0576). Ma nā huaʻōlelo ʻē aʻe, lawe kēia kaʻina i 40 ms + 1.72036 ms (maʻamau) mai ke kiko DEVRST_N i hoʻokuʻu ʻia. E hoʻomaopopo ʻaʻole e kali ka hoʻohana ʻana o DEVRST_N ka POR counter e hoʻokō i ka mana-up i nā hana hana a no laila e lawe kēia kaʻina i ka 1.72036 ms (maʻamau).	Ma ka hoʻolālā, hoʻopau ʻia nā mea hoʻopuka (ʻo ia hoʻi ka lana) i ka wā e hoʻonui ai i ka mana. I ka manawa e loaʻa ai ka helu POR ua hoʻopau ʻia, ua hoʻokuʻu ʻia ʻo DEVRST_N a ua loaʻa nā lako VDDI I/O āpau i kā lākou ~ 0.6V paepae, a laila e tristated ka I/Os me ka nawaliwali huki huki ho'ā 'ia, a hiki i ka hoʻololi 'ana i ka mea hoʻohana mana hoʻohana, ma nā Kiʻi 11 a me 12 o UG0576. ʻO nā mea hoʻopuka koʻikoʻi pono e noho haʻahaʻa i ka wā e hoʻonui ai i ka mana e koi i kahi pale huki huki waho 1K-ohm.
DEVRST_N huki-i ka VPP a me na lako a pau ramp i ka manawa like	ʻAʻole pono ʻo VDDPLL i ka ka mana hope loa i ramp piʻi, a pono e hōʻea i ka vol voltage ma mua o ka lako hope loa (VDD aiʻole VDDI) hoʻomaka rampe pale ana i ka puka paʻa PLL nā pilikia. E nānā i ka RTG4 Clocking Resources User Guide (UG0586) no ka wehewehe ʻana i ka hoʻohana ʻana i ka CCC/PLL READY_VDDPLL hoʻokomo e wehe i nā koi hoʻonohonoho no ka lako mana VDDPLL. E hoʻopaʻa iā SERDES_x_Lyz_VDDAIO i ka lako like me VDD, a i ʻole e hoʻopaʻa i ka mana i ka manawa like.	Ke hiki aku ka VDD a me ka VPP i nā paepae ho'āla (VDD ~= 0.55V, VPP ~= 2.2V) ka 50 ms POR hoʻopaneʻe helu e holo. Hoʻopili ka mana o ka hāmeʻa i ka manawa hana Nā Kiʻi 9 a me 10 (VDD PUFT) o ke alakaʻi alakaʻi o ka mea hoʻohana (UG0576). ʻO ia hoʻi, ʻo ka nui o ka manawa he 57.95636 ms.	Ma ka hoʻolālā, hoʻopau ʻia nā mea hoʻopuka (ʻo ia hoʻi ka lana) i ka wā e hoʻonui ai i ka mana. I ka manawa e loaʻa ai ka helu POR ua hoʻopau ʻia, ua hoʻokuʻu ʻia ʻo DEVRST_N a ua loaʻa nā lako VDDI IO āpau i kā lākou ~ 0.6V paepae, a laila e tristated ka I/Os me ka nawaliwali huki huki ho'ā 'ia, a hiki i ka hoʻololi 'ana i ka mea hoʻohana mana hoʻohana, ma nā Kiʻi 9 a me 10 o UG0576. ʻO nā mea hoʻopuka koʻikoʻi pono e noho haʻahaʻa i ka wā e hoʻonui ai i ka mana e koi i kahi pale huki huki waho 1K-ohm.

Hoʻohana i ka hihia	Pono Kakau	ʻAno	Nā memo
VDD/ SERDES_VD DAIO -> VPP/VDDPLL ->	Ua helu ʻia ke kaʻina ma ke kolamu Scenario. Ua huki ʻia ʻo DEVRST_N i VPP.	Ke hiki i ka VDD a me ka VPP i nā paepae hoʻāla (VDD ~= 0.55V, VPP ~= 2.2V) ka 50ms E holo ana ka helu hoʻopaneʻe POR. Hoʻopili ka mana o ka hāmeʻa i ka manawa hana i nā Kiʻi 9 a me 10 (VDD PUFT) o Ke alakaʻi alakaʻi o ka mea hoʻohana (UG0576). ʻO ka pau ʻana o ke kaʻina hana mana a me ka mana i ka manawa hana e pili ana i ka lako VDDI hope loa i hoʻohana ʻia.	Ma ka hoʻolālā, hoʻopau ʻia nā mea hoʻopuka (ʻo ia hoʻi ka lana) i ka wā e hoʻonui ai i ka mana. I ka manawa e loaʻa ai ka helu POR ua hoʻopau ʻia, ua hoʻokuʻu ʻia ʻo DEVRST_N a ua loaʻa nā lako VDDI I/O āpau i kā lākou ~ 0.6V paepae, a laila e tristated na IOs me ka nawaliwali huki-up ho'ā 'ia, a hiki i ka hoʻololi 'ana i ka hoʻohana mana hoʻohana, ma nā Kiʻi 9 a me 10 o UG0576. ʻAʻohe hana huki huki nāwaliwali i ka wā o ka mana-up a hiki i nā lako VDDI a pau i ka ~ 0.6V. ʻO ka pōmaikaʻi kī ʻO kēia kaʻina ʻo ia ka lako VDDI hope loa i hiki ʻAʻole e hoʻāla ʻia ka huki huki nāwaliwali ma kēia paepae hoʻāla a e hoʻololi pololei ʻia mai ke ʻano kīnā i ke ʻano i wehewehe ʻia e ka mea hoʻohana. Hiki i kēia ke kōkua i ka hōʻemi ʻana i ka nui o nā mea pale huki huki waho 1K i koi ʻia no nā hoʻolālā i loaʻa ka hapa nui o nā panakō I/O i hoʻoikaika ʻia e ka VDDI hope e piʻi. No nā panakō I/O ʻē aʻe i hoʻohana ʻia e kekahi lako VDDI ʻē aʻe ma mua o ka lako VDDI hope e piʻi aʻe, ʻo nā huahana koʻikoʻi e noho haʻahaʻa i ka wā o ka hoʻoulu ʻana e koi i kahi mea pale huki huki 1K-ohm waho.
E kali ma kahi o 51ms ->
VDDI (A pau IO nā panakō)
OR
VDD/ SERDES_VD DAIO ->
VPP/ VDDPLL/ 3.3V_VDDI ->
E kali ma kahi o 51ms ->
VDDI (ʻaʻole-3.3V_VD DI)

 Nā noʻonoʻo i ka wā DEVRST_N Assertion and Power-Down

Inā ʻaʻole hahai ʻia nā alakaʻi alakaʻi no ka hoʻolālā ʻana o ka Papa a me ka Layout no RTG439 FPGA.view nā kikoʻī aʻe:

1. No nā kaʻina hoʻohaʻahaʻa i hāʻawi ʻia ma ka Papa 2-2, ʻike paha ka mea hoʻohana i nā glitches I/O a i ʻole inrush a me nā hanana transient o kēia manawa.
2. E like me ka mea i hōʻike ʻia ma ka Customer Advisory Notification (CAN) 19002.5, hiki ke hoʻoulu i kahi ʻano transient ma ka 4V VDD ka hoʻokaʻawale ʻana mai ke kaʻina mana iho i ʻōlelo ʻia ma ka ʻikepili RTG1.2. Inā he 3.3V VPP lako rampMa mua o ka hoʻolako ʻana i ka 1.2V VDD, e ʻike ʻia kahi manawa transient ma VDD e like me ka VPP a me DEVRST_N (mana ʻia e VPP) a hiki i ka 1.0V. ʻAʻole hiki mai kēia manawa transient inā hoʻopau ʻia ka VPP ma hope, e like me ka ʻōlelo aʻoaʻo datasheet.
   1. ʻO ka nui a me ka lōʻihi o ka manawa transient e pili ana i ka hoʻolālā i hoʻolālā ʻia i ka FPGA, ka papa decoupling capacitance kūikawā, a me ka pane transient o ka vol 1.2V.tage hooponopono. I nā hihia liʻiliʻi, ua ʻike ʻia kahi manawa transient a hiki i 25A (a i ʻole 30 Watts ma kahi lako 1.2V VDD nominal). Ma muli o ke ʻano puʻupuʻu o kēia manawa transient VDD ma waena o ka lole FPGA holoʻokoʻa (ʻaʻole i ʻike ʻia i kahi wahi kikoʻī), a me kona manawa pōkole, ʻaʻohe hopohopo hilinaʻi inā ʻo 25A a i ʻole ka liʻiliʻi.
   2. Ma ke ʻano he hana hoʻolālā maikaʻi loa, e hahai i ka ʻōlelo aʻoaʻo datasheet e pale aku ai i ke au transient.
3. He 1.7V paha nā glitches I/O no 1.2 ms.
   1. Hiki ke ʻike ʻia ka hewa kiʻekiʻe ma nā huahana e hoʻokele Low a i ʻole Tristate.
   2. Hiki ke ʻike ʻia ka haʻahaʻa haʻahaʻa ma ka hoʻokuʻu ʻana i ke kiʻekiʻe (ʻaʻole hiki ke hoʻēmi ʻia ka haʻahaʻa haʻahaʻa ma ka hoʻohui ʻana i kahi huki huki 1 KΩ).
4. ʻO ka hoʻohaʻahaʻa ʻana i ka VDDIx mua e ʻae i ka hoʻololi monotonic mai ke Kiʻekiʻe a i ka Haʻahaʻa, akā hoʻokuʻu pōkole ka hopena e pili ana i kahi papa hoʻohana e hoʻāʻo e huki i waho i ka puka kiʻekiʻe ke hoʻopau ʻia ʻo RTG4 VDDIx. Pono ʻo RTG4 ʻaʻole e hoʻokele waho ʻia nā I/O Pads ma luna o ka waihona waihona waihona VDDixtaga no laila inā hoʻohui ʻia kahi pale pale i waho i kahi kaila mana ʻē aʻe, pono ia e hoʻohaʻahaʻa i ka manawa like me ka lako VDDIx.
   Papa 2-2. ʻO nā hiʻohiʻona I/O Glitch i ka wā ʻaʻole e hahai i ke kaʻina mana-down i manaʻo ʻia ma AC439

   Mokuʻāina Hoʻopuka Paʻamau	VDD (1.2V)	VDDIx (<3.3V) VDDIx (3.3V)	VPP (3.3V)	DEVRST_N	Ka mana iho
   					ʻAʻole I/O	I kēia manawa In- Rush
   I/O Kaa Haahaa a Tristated paha	Ramp iho ma hope o VPP ma kekahi kauoha		Ramp iho mua	Hoʻopili ʻia iā VPP	ʻAe1	ʻAe
   	Ramp i lalo i kekahi kauoha ma hope o ka ʻōlelo a DEVRST_N			Ua ʻōlelo ʻia ma mua o kekahi lako ramp iho	ʻAe1	ʻAʻole
   I/O Kaa Kiekie	Ramp iho ma hope o VPP ma kekahi kauoha		Ramp iho mua	Hoʻopili ʻia iā VPP	ʻAe	ʻAe
   	Ramp i lalo i kekahi kauoha ma mua o VPP		Ramp iho hope	Hoʻopili ʻia iā VPP	ʻAʻole2	ʻAʻole
   	Ramp i lalo i kekahi kauoha ma hope o ka ʻōlelo a DEVRST_N			Ua ʻōlelo ʻia ma mua o kekahi lako ramp iho	ʻAe	ʻAʻole

   1. Manaʻo ʻia kahi mea pale huki huki waho 1 KΩ e hoʻēmi i ka glitch kiʻekiʻe ma nā I/O koʻikoʻi, pono e noho haʻahaʻa i ka wā o ka mana.
   2. ʻIke wale ʻia kahi kuhi haʻahaʻa no kahi I/O i huki ʻia i waho i kahi lako mana e hoʻomau ʻia e like me VPP ramps lalo. Eia naʻe, he uhaki kēia i nā kūlana hana i manaʻo ʻia no ka mea ʻaʻole pono ke kiʻekiʻe o ka PAD ma hope o ka VDDIx r pili.amps lalo.
5. Inā ʻōlelo ʻia ʻo DEVRST_N, hiki i ka mea hoʻohana ke ʻike i ka haʻahaʻa haʻahaʻa ma kekahi puka I/O e holo kiʻekiʻe a huki ʻia hoʻi i waho ma o ka pale ʻana iā VDDI. No example, me ka 1KΩ huki-i pale, he haʻahaʻa glitch hiki i ka liʻiliʻi voltage o 0.4V me ka lōʻihi o 200 ns hiki ke loaʻa ma mua o ka hoʻopuka 'ana.

Nānā: ʻAʻole pono e huki ʻia ʻo DEVRST_N ma luna o ka vol VPPtage. No ka pale ʻana i nā mea i luna aʻe, makemake nui ʻia e hahai i ka mana-up a me ka mana-down sequence i wehewehe ʻia ma AC439: Papa Hoʻolālā a me nā Papa kuhikuhi no ka RTG4 FPGA Application Note.

Moolelo Hooponopono

Hōʻike ka mōʻaukala hoʻoponopono i nā loli i hoʻokō ʻia ma ka palapala. Hoʻopaʻa ʻia nā hoʻololi e ka loiloi, e hoʻomaka ana me ka hoʻolaha o kēia manawa.

Papa 3-1. Moolelo Hooponopono

Hoʻoponopono	Lā	wehewehe
A	04/2022	• I ka manawa DEVRST_N, e hoʻokaʻawale ʻia nā RTG4 I/O a pau. Hiki i nā mea hoʻopuka i hoʻokiʻekiʻe ʻia e ka lole FPGA a huki kiʻekiʻe ma waho o ka papa ke loaʻa i kahi glitch haʻahaʻa ma mua o ke komo ʻana i ke kūlana tristate. Pono e nānā ʻia kahi hoʻolālā papa me kahi hiʻohiʻona hoʻopuka no ka hoʻomaopopo ʻana i ka hopena o nā pilina pili i nā huahana FPGA i hiki ke hele hewa ke ʻōlelo ʻia ʻo DEVRST_N. No ka 'ike hou aku, e nana i ka Papa 5 ma ka pauku 2.2. Nā noʻonoʻo i ka wā DEVRST_N Assertion and Power-Down. • Kapa hou ia Mana-Iho i ka pauku 2.2. Nā noʻonoʻo i ka wā DEVRST_N Assertion and Power-Down. • Hoʻololi ʻia i ka laʻana Microchip.
2	02/2022	• Hoʻohui i ka ʻāpana Power-Up. • Hoʻohui i ka ʻāpana Power Sequencing.
1	07/2019	ʻO ka paʻi mua ʻana o kēia palapala.

Kākoʻo FPGA Microchip

Hoʻihoʻi ka hui huahana Microchip FPGA i kāna mau huahana me nā lawelawe kākoʻo like ʻole, me ka Customer Service, Customer Technical Support Center, a webkahua, a me nā keʻena kūʻai honua. Manaʻo ʻia nā mea kūʻai aku e kipa i nā kumuwaiwai pūnaewele Microchip ma mua o ka hoʻopili ʻana i ke kākoʻo no ka mea ua pane ʻia kā lākou mau nīnau.
E hoʻokaʻaʻike i ke kikowaena kākoʻo ʻenehana ma o ka webpaena ma www.microchip.com/support. E haʻi i ka helu ʻāpana Mea Hana FPGA, koho i ka māhele hihia kūpono, a hoʻouka i ka hoʻolālā files i ka hana ʻana i kahi hihia kākoʻo ʻenehana.
Hoʻokaʻaʻike i ka Customer Service no ke kākoʻo huahana ʻole, e like me ke kumu kūʻai huahana, hoʻonui huahana, ʻike hou, kūlana kauoha, a me ka ʻae.

• Mai ʻAmelika ʻĀkau, e kelepona iā 800.262.1060
• ke koena o ka honua, e kelepona iā 650.318.4460
• Fax, mai nā wahi a pau o ka honua, 650.318.8044

ʻO ka Microchip Webpaena

Hāʻawi ʻo Microchip i ke kākoʻo pūnaewele ma o kā mākou webkahua ma www.microchip.com/. ʻO kēia webhoʻohana ʻia ka pūnaewele e hana files a me ka 'ike maʻalahi i nā mea kūʻai mai. Aia kekahi o nā mea i loaʻa:

• Kākoʻo Huahana - Nā pepa ʻikepili a me nā hewa, nā palapala noi a me nā sampnā papahana, nā kumuwaiwai hoʻolālā, nā alakaʻi a me nā palapala kākoʻo ʻenehana, nā hoʻokuʻu polokalamu hou loa a me nā polokalamu waihona
• Kākoʻo ʻenehana nui - Nā nīnau i nīnau pinepine ʻia (FAQ), nā noi kākoʻo ʻenehana, nā hui kūkākūkā pūnaewele, ka papa inoa o nā lālā o ka papahana hoʻolālā Microchip.
• ʻOihana o Microchip - Ka mea koho huahana a me nā alakaʻi kauoha, nā hoʻolaha paʻi Microchip hou loa, ka papa inoa o nā seminar a me nā hanana, nā papa inoa o nā keʻena kūʻai Microchip, nā mea hoʻolaha a me nā ʻelele hale hana.

Hana Hoʻolaha Hoʻololi Huahana

Kōkua ka lawelawe hoʻolaha hoʻololi huahana a Microchip e mālama i nā mea kūʻai aku i nā huahana Microchip. E loaʻa ka leka uila i ka poʻe kākau inoa inā loaʻa nā loli, nā mea hou, nā hoʻoponopono a i ʻole nā ​​hewa e pili ana i kahi ʻohana huahana kikoʻī a i ʻole nā ​​​​mea hana hoʻomohala hoihoi.
No ka hoʻopaʻa inoa, hele i www.microchip.com/pcn a hahai i na kuhikuhi kakau inoa.

Kākoʻo mea kūʻai aku

Hiki i nā mea hoʻohana o nā huahana Microchip ke loaʻa ke kōkua ma o nā ala he nui:

• Mea hoolaha a Lunamakaainana paha
• Keena Kūʻai Kūloko
• ʻEnekinia Hoʻoponopono Hoʻokomo ʻia (ESE)
• Kākoʻo ʻenehana

Pono nā mea kūʻai aku e hoʻokaʻaʻike i kā lākou mea hoʻolaha, ʻelele a i ʻole ESE no ke kākoʻo. Loaʻa nā keʻena kūʻai kūloko e kōkua i nā mea kūʻai aku. Aia kekahi papa inoa o nā keʻena kūʻai a me nā wahi i loko o kēia palapala.
Loaʻa ke kākoʻo ʻenehana ma o ka webkahua ma: www.microchip.com/support

Nā hiʻohiʻona pale code microchip

E nānā i nā kikoʻī aʻe o ka hiʻohiʻona pale code ma nā huahana Microchip:

• Hoʻokō nā huahana Microchip i nā kikoʻī i loko o kā lākou Microchip Data Sheet.
• Manaʻo ʻo Microchip ua paʻa kona ʻohana huahana ke hoʻohana ʻia ma ke ʻano i manaʻo ʻia, i loko o nā kikoʻī hana, a ma lalo o nā kūlana maʻamau.
• ʻO nā waiwai Microchip a pale ikaika i kāna mau pono waiwai naʻauao. Ua pāpā loa ʻia ka hoʻāʻo ʻana e uhaki i nā hiʻohiʻona pale code o ka huahana Microchip a hiki ke hōʻeha i ke Digital Millennium Copyright Act.
• ʻAʻole hiki i ka Microchip a me nā mea hana semiconductor ʻē aʻe ke hōʻoia i ka palekana o kāna code. ʻAʻole manaʻo ka pale code e hōʻoiaʻiʻo ana mākou i ka huahana "unbreakable". Ke ulu mau nei ka pale code. Ua kūpaʻa ʻo Microchip i ka hoʻomaikaʻi mau ʻana i nā hiʻohiʻona pale code o kā mākou huahana.

Hoolaha Kanawai

• Hiki ke hoʻohana ʻia kēia hoʻolaha a me ka ʻike ma ʻaneʻi me nā huahana Microchip, me ka hoʻolālā, hoʻāʻo, a hoʻohui pū i nā huahana Microchip me kāu noi. ʻO ka hoʻohana ʻana i kēia ʻike ma nā ʻano ʻē aʻe e kūʻē i kēia mau ʻōlelo. Hāʻawi ʻia ka ʻike e pili ana i nā noi hāmeʻa no kou ʻoluʻolu a hiki ke hoʻololi ʻia
  na mea hou. Nau ke kuleana e hōʻoia i ka hoʻokō ʻana o kāu noi me kāu mau kikoʻī. E kelepona i kāu keʻena kūʻai Microchip kūloko no ke kākoʻo hou a i ʻole, e kiʻi i ke kākoʻo hou ma www.microchip.com/en-us/support/design-help/client-support-services.
• HOʻolako ʻia kēia ʻike e MICROCHIP "AS IS". ʻAʻole hana ʻo MICROCHIP i nā hōʻike ʻana a i ʻole nā ​​palapala hōʻoia o kēlā me kēia ʻano inā i hōʻike ʻia a i ʻole i ʻōlelo ʻia, i kākau ʻia a i ʻole waha, kānāwai.
  A I ʻole, e pili ana i ka ʻike me ka ʻaʻole i kaupalena ʻia i nā palapala hōʻoia no ka hōʻino ʻole, ke kūʻai aku, a me ka pono no kahi kumu, a i ʻole nā ​​palapala hōʻoia e pili ana i kona kūlana, kūlana, a i ʻole hana.
• ʻAʻole e kuleana ʻo MICROCHIP no kekahi mea ʻole, kūikawā, PUNITIVE, INCIDENTAL, a i ʻole nā ​​hopena hopena, ʻino, kumu, a i ʻole nā ​​lilo o kēlā me kēia ʻano mea e pili ana i ka ʻike a i ʻole kona hoʻohana ʻana, akā naʻe, ua hana ʻia, ʻoiai he hewa. HIKI A I OLE E IKE AUANEI NA POINO. I KA LOA LOA I A'E IA E KE KANAWAI, AOLE E OI KA NUI O NA KUKU, IA ANA, A IA KAU I UKU pololei aku ai ia MICROCHIP.
  ʻO ka hoʻohana ʻana i nā polokalamu Microchip i ke kākoʻo ola a / a i ʻole nā ​​noi palekana e pili ana i ka mea kūʻai aku, a ʻae ka mea kūʻai aku e pale, hoʻopaʻa a hoʻopaʻa ʻole i ka Microchip mai nā pōʻino, nā koi, nā hoʻopiʻi, a me nā lilo i hopena mai ia hoʻohana. ʻAʻole hāʻawi ʻia nā laikini, ma ke ʻano a i ʻole, ma lalo o nā kuleana waiwai naʻauao Microchip ke ʻole ka ʻōlelo ʻē aʻe.

Nā hōʻailona

• ʻO ka inoa Microchip a me ka hōʻailona, ​​ka logo Microchip, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash , Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, a me XMEGA he mau inoa inoa inoa o Microchip Technology Incorporated ma USA a me nā ʻāina ʻē aʻe.
• AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed ​​Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Wire, ʻO SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, WinPath, a me ZL he mau inoa inoa inoa o Microchip Technology Incorporated ma USA.
• Kāohi kī pili, AKS, Analog-no-ka-Digital Age, Kekahi Capacitor, AnyIn, AnyOut, Hoʻololi i hoʻonui ʻia, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching , ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralling, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB i hōʻoia ʻia ka logo, MPLIB, MPLINK, MultiTRAK, NetDetach, NVM Express, NVMe, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE , Palena Ripple, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Endurance Total, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewʻO Span, WiperLock, XpressConnect, a me ZENA nā hōʻailona o Microchip Technology Incorporated i ka
  USA a me nā ʻāina ʻē aʻe.
• ʻO SQTP kahi hōʻailona lawelawe o Microchip Technology Incorporated in the USA ʻO ka logo Adaptec, Frequency on Demand, Silicon Storage Technology, Symmcom, a me Trusted Time he mau inoa inoa inoa o Microchip Technology Inc. ma nā ʻāina ʻē aʻe.
• He hōʻailona inoa inoa ʻo GestIC o Microchip Technology Germany II GmbH & Co. KG, he lālā o Microchip Technology Inc., ma nā ʻāina ʻē aʻe.
  ʻO nā hōʻailona ʻē aʻe a pau i ʻōlelo ʻia ma ʻaneʻi, he waiwai ia o kā lākou hui.
  © 2022, Microchip Technology Incorporated a me kāna mau lālā. Mālama ʻia nā kuleana a pau.
  ISBN: 978-1-6683-0362-7

Pūnaehana hoʻokele maikaʻi

No ka 'ike e pili ana i ka Microchip's Quality Management Systems, e 'olu'olu e kipa www.microchip.com/quality.

Nā Kūʻai a me nā lawelawe o ka honua holoʻokoʻa

AMERIKA	ASIA/PAKIPIKA	ASIA/PAKIPIKA	EUROPA
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© 2022 Microchip Technology Inc. a me kāna mau lālā

Palapala / Punawai

MICROCHIP RTG4 Pākuʻi RTG4 FPGAs Papa Hoʻolālā a me ka Layout Guidelines [pdf] Ke alakaʻi hoʻohana RTG4 Addendum RTG4 FPGAs Papa Hoʻolālā a me ka Layout Guidelines, RTG4, Addendum RTG4 FPGAs Board Design and Layout Guidelines, Design and Layout Guidelines

Nā kuhikuhi

• Palapala Hoʻohana