F-Tile DisplayPort FPGA IP Design Example
Wogwiritsa Ntchito

F-Tile DisplayPort FPGA IP Design Example

Zasinthidwa ku Intel® Quartus® Prime Design Suite: 22.2 IP Version: 21.0.1

DisplayPort Intel FPGA IP Design Exampndi Quick Start Guide

Zida za DisplayPort Intel® F-tile zimakhala ndi testbench yoyeserera komanso kapangidwe ka Hardware komwe kamathandizira kuphatikiza ndi kuyesa kwa hardware FPGA IP design ex.ampLes za Intel Agilex™
DisplayPort Intel FPGA IP imapereka mawonekedwe otsatirawaampzochepa:

• DisplayPort SST parallel loopback popanda gawo la Pixel Clock Recovery (PCR).
• DisplayPort SST kufanana loopback ndi AXIS Video Interface

Mukapanga zojambula zakaleampndi, mkonzi wa parameter amangopanga files zofunika kuyerekezera, kusonkhanitsa, ndi kuyesa mapangidwe mu hardware.
Chithunzi 1. Chitukuko StagesZambiri Zogwirizana

• DisplayPort Intel FPGA IP User Guide
• Kusamukira ku Intel Quartus Prime Pro Edition

Malingaliro a kampani Intel Corporation Maumwini onse ndi otetezedwa. Intel, logo ya Intel, ndi zizindikiro zina za Intel ndi zizindikiro za Intel Corporation kapena mabungwe ake. Intel imatsimikizira kugwira ntchito kwa FPGA yake ndi zida za semiconductor malinga ndi zomwe zili pano malinga ndi chitsimikizo cha Intel, koma ili ndi ufulu wosintha zinthu ndi ntchito zilizonse nthawi iliyonse popanda kuzindikira. Intel sakhala ndi udindo kapena udindo chifukwa chakugwiritsa ntchito kapena kugwiritsa ntchito zidziwitso zilizonse, malonda, kapena ntchito zomwe zafotokozedwa pano kupatula monga momwe Intel adavomerezera momveka bwino. Makasitomala a Intel amalangizidwa kuti apeze mtundu waposachedwa kwambiri wamakina a chipangizocho asanadalire zidziwitso zilizonse zosindikizidwa komanso asanayike maoda azinthu kapena ntchito.
*Mayina ena ndi mtundu zitha kunenedwa kuti ndi za ena.
ISO 9001:2015 Adalembetsedwa
1.1. Kapangidwe ka Kalozera
Chithunzi 2. Kalozera Kapangidwe

Table 1. Design Exampndi Components

Mafoda	Files
rtl/core	dp_core.ip
	dp_rx ndi. ip
	dp_tx ndi. ip
rtl/rx_phy	dp_gxb_rx/ ((chida chomangira cha DP PMA UX)
	dp_rx_data_fifo. ip
	rx_top_phy. sv
rtl/tx_phy	dp_gxb_rx/ ((chida chomangira cha DP PMA UX)
	dp_tx_data_fifo.ip
	dp_tx_data_fifo.ip

1.2. Zofunikira pa Hardware ndi Mapulogalamu
Intel imagwiritsa ntchito zida ndi mapulogalamu otsatirawa kuyesa kapangidwe kakaleampLe:
Zida zamagetsi

• Intel Agilex I-Series Development Kit
• DisplayPort Source GPU
• DisplayPort Sink (Monitor)
• Bitec DisplayPort FMC khadi mwana wamkazi Revision 8C
• Zingwe za DisplayPort

Mapulogalamu

• Intel Quartus® Prime
• Synopsy * VCS Simulator

1.3. Kupanga Mapangidwe
Gwiritsani ntchito DisplayPort Intel FPGA IP parameter editor mu Intel Quartus Prime software kuti mupange zojambulazoample.
Chithunzi 3. Kupanga Mapangidwe Oyenda

1.  Sankhani Zida ➤ IP Catalog, ndikusankha Intel Agilex F-tile ngati banja lazida zomwe mukufuna.
   Zindikirani: Mapangidwe example imangothandizira zida za Intel Agilex F-tile.
2. Mu Catalog ya IP, pezani ndikudina kawiri DisplayPort Intel FPGA IP. Zenera la New IP Variation likuwonekera.
3. Tchulani dzina lapamwamba lamitundu yanu ya IP. Mkonzi wa parameter amasunga zosintha za IP mu a file dzina .ip.
4. Sankhani chipangizo cha Intel Agilex F-tile m'munda wa Chipangizo, kapena sungani chosankha cha chipangizo cha Intel Quartus Prime.
5. Dinani Chabwino. The parameter editor ikuwonekera.
6. Konzani magawo omwe mukufuna a TX ndi RX.
7. Pansi pa Design Examppa tabu, sankhani DisplayPort SST Parallel Loopback Popanda PCR.
8. Sankhani Kayeseleledwe kupanga testbench, ndi kusankha kaphatikizidwe kupanga hardware kapangidwe example. Muyenera kusankha chimodzi mwazosankha izi kuti mupange zojambula zakaleample files. Mukasankha zonse ziwiri, nthawi ya m'badwo imakhala yayitali.
9. Kwa Target Development Kit, sankhani Intel Agilex I-Series SOC Development Kit. Izi zimapangitsa chipangizo chandamale chomwe chasankhidwa mu gawo 4 kuti chisinthe kuti chifanane ndi chipangizo chomwe chili pazida zachitukuko. Kwa Intel Agilex I-Series SOC Development Kit, chipangizo chokhazikika ndi AGIB027R31B1E2VR0.
10. Dinani Pangani Exampndi Design.

1.4. Kutsanzira Mapangidwe
Mapangidwe a DisplayPort Intel FPGA IP example testbench imatengera kapangidwe ka serial loopback kuchokera pa TX kupita ku RX. Gawo lamkati la jenereta lamavidiyo limayendetsa chiwonetsero cha DisplayPort TX ndipo mawonekedwe a kanema a RX amalumikizana ndi zowunikira za CRC mu testbench.
Chithunzi 4. Kupanga Kuyerekeza Kuyenda

1. Pitani ku chikwatu cha Synopsys simulator ndikusankha VCS.
2. Thamangani script yoyeserera.
   Gwero vcs_sim.sh
3. Zolemba zimapanga Quartus TLG, zimaphatikiza ndikuyendetsa testbench mu simulator.
4. Unikani zotsatira zake.
   Kuyerekeza kopambana kumatha ndi kufananitsa kwa Source ndi Sink SRC.

1.5. Kulemba ndi Kuyesa Mapangidwe
Chithunzi 5. Kupanga ndi Kutsanzira MapangidweKupanga ndikuyesa kuyesa kwachiwonetsero pa hardware example design, tsatirani izi:

1. Onetsetsani kuti hardware example design generation yatha.
2. Yambitsani pulogalamu ya Intel Quartus Prime Pro Edition ndikutsegula /quartus/agi_dp_demo.qpf.
3. Dinani Kukonza ➤ Yambani Kuphatikiza.
4. Pambuyo pophatikiza bwino, pulogalamu ya Intel Quartus Prime Pro Edition imapanga .sof file mu chikwatu chomwe mwasankha.
5. Lumikizani cholumikizira cha DisplayPort RX pa khadi la Bitec ku gwero lakunja la DisplayPort, monga khadi lojambula pa PC.
6. Lumikizani cholumikizira cha DisplayPort TX pa khadi la Bitec ku chipangizo chakuya cha DisplayPort, monga chowunikira makanema kapena chowunikira pa PC.
7.  Onetsetsani kuti masiwichi onse pa bolodi lachitukuko ali pamalo osakhazikika.
8. Konzani chipangizo chosankhidwa cha Intel Agilex F-Tile pa bolodi lachitukuko pogwiritsa ntchito .sof yopangidwa file (Zida ➤ Wokonza Mapulogalamu).
9. Chipangizo chozama cha DisplayPort chikuwonetsa kanema wopangidwa kuchokera kugwero lamavidiyo.

Zambiri Zogwirizana
Intel Agilex I-Series FPGA Development Kit User Guide/
1.5.1. Kusintha kwa ELF File
Mwachikhazikitso, ELF file amapangidwa mukapanga dynamic design example.
Komabe, nthawi zina, muyenera kukonzanso ELF file ngati musintha pulogalamuyo file kapena sinthaninso dp_core.qsys file. Kupanganso dp_core.qsys file zosintha za .sopcinfo file, zomwe zimafuna kuti mukonzenso ELF file.

1. Pitani ku / mapulogalamu ndikusintha code ngati kuli kofunikira.
2. Pitani ku /script ndikuchita zotsatirazi: source build_sw.sh
   • Pa Windows, fufuzani ndi kutsegula Nios II Command Shell. Mu Nios II Command Shell, pitani ku /script ndikuchita gwero build_sw.sh.
   Zindikirani: Kuti mugwiritse ntchito zomanga Windows 10, makina anu amafunikira Windows Subsystems ya Linux (WSL). Kuti mumve zambiri za masitepe oyika WSL, onani buku la Nios II Software Developer Handbook.
   • Pa Linux, yambitsani Platform Designer, ndi kutsegula Zida ➤ Nios II Command Shell. Mu Nios II Command Shell, pitani ku /script ndikuchita gwero build_sw.sh.
3. Onetsetsani kuti .elf file imapangidwa mu /software/dp_demo.
4. Tsitsani wopanga .elf file kulowa mu FPGA popanda kubwezeretsanso .sof file poyendetsa zotsatirazi: nios2-kutsitsa /software/dp_demo/*.elf
5. Dinani batani lokhazikitsiranso pa bolodi la FPGA kuti pulogalamu yatsopanoyo igwire ntchito.

1.6. DisplayPort Intel FPGA IP Design Exampndi Parameters
Table 2. DisplayPort Intel FPGA IP Design Exampndi QSF choletsa cha Intel Agilex Ftile Chipangizo

Mtengo wa QSF	Kufotokozera
set_global_assignment -dzina VERILOG_MACRO “__DISPLAYPORT_thandizo___=1”	Kuyambira Quartus 22.2 kupita mtsogolo, cholepheretsa cha QSF ichi ndichofunika kuti DisplayPort mwambo SRC (Soft Reset Controller) kuyenda.

Table 3. DisplayPort Intel FPGA IP Design Example Ma Parameters a Intel Agilex F-tile Chipangizo

Parameter	Mtengo	Kufotokozera
Mapangidwe Opezeka Example
Sankhani Design	•Palibe •DisplayPort SST Parallel Loopback popanda PCR •DisplayPort SST Parallel Loopback yokhala ndi AXIS Video Interface	Sankhani chitsanzo chojambulaample kuti apangidwe. • Palibe: Palibe kapangidwe kakaleample likupezeka pakusankha kwa parameter pano. •DisplayPort SST Parallel Loopback yopanda PCR: Kapangidwe kameneka kaleample imawonetsa kubwereza kofananira kuchokera kusinki ya DisplayPort kupita kugwero la DisplayPort popanda gawo la Pixel Clock Recovery (PCR) mukayatsa gawo la Yambitsani Chithunzi Chojambula cha Video. •DisplayPort SST Parallel Loopback yokhala ndi AXIS Video Interface: Kapangidwe kameneka kaleample ikuwonetsa kubwereza kofananira kuchokera kusinki ya DisplayPort kupita ku gwero la DisplayPort yokhala ndi mawonekedwe a Video ya AXIS pomwe Yambitsani Active Video Data Protocols ikhazikitsidwa kukhala AXIS-VVP Full.
Design Example Files
Kuyerekezera	Yatsani, Off	Yatsani izi kuti mupange zofunikira files ya testbench yoyeserera.
Kaphatikizidwe	Yatsani, Off	Yatsani izi kuti mupange zofunikira files ya Intel Quartus Prime compilation ndi hardware design.
Mtundu Wopangidwa wa HDL
Pangani File Mtundu	Verilog, VHDL	Sankhani mtundu womwe mumakonda wa HDL wamapangidwe opangidwa kaleample fileset. Zindikirani: Izi zimangotsimikizira mtundu wa IP yapamwamba yopangidwa files. Zina zonse files (mwachitsanzo Eksample testbenches ndi mlingo wapamwamba files zowonetsera za hardware) zili mu mtundu wa Verilog HDL.
Chida Chachitukuko cha Target
Sankhani Board	• Palibe Zida Zachitukuko •Intel Agilex I-Series Zida Zachitukuko	Sankhani bolodi la mapangidwe omwe mukufunaample.

Parameter	Mtengo	Kufotokozera
		• No Development Kit: Izi sizimaphatikizapo mbali zonse za hardware zamapangidwe example. P core imayika magawo onse a pini kukhala ma pini enieni. •Intel Agilex I-Series FPGA Development Kit: Njira iyi imangosankha chipangizo chandamale cha polojekiti kuti chigwirizane ndi chipangizo chomwe chili pazitukukozi. Mutha kusintha chipangizo chomwe mukufuna kugwiritsa ntchito Change Target Device parameter ngati bolodi lanu liri ndi chida chosiyana. IP core imayika magawo onse a pini malinga ndi zida zachitukuko. Chidziwitso: Mapangidwe Oyambirira Example silinatsimikizidwe bwino pa hardware mu kutulutsidwa kwa Quartus. •Custom Development Kit: Njira iyi imalola zojambula zakaleample kuti ayesedwe pa zida zachitukuko chachitatu ndi Intel FPGA. Mungafunike kukhazikitsa ma pin assignments nokha.
Chida Cholowera
Sinthani Chipangizo Chotsatira	Yatsani, Off	Yatsani njira iyi ndikusankha chosinthira chomwe mumakonda cha zida zachitukuko.

Parallel Loopback Design Examples

Mapangidwe a DisplayPort Intel FPGA IP examples kuwonetsa kubwereza kofananira kuchokera pa chitsanzo cha DisplayPort RX kupita ku DisplayPort TX popanda gawo la Pixel Clock Recovery (PCR).
Table 4. DisplayPort Intel FPGA IP Design Example kwa Intel Agilex F-tile Chipangizo

Design Example	Kusankhidwa	Mtengo wa Data	Njira Yama Channel	Mtundu wa Loopback
DisplayPort SST kufanana loopback popanda PCR	Chithunzi cha DisplayPort SST	RBR, HRB, HRB2, HBR3	Simplex	Kufanana popanda PCR
DisplayPort SST kufanana loopback ndi AXIS Video Interface	Chithunzi cha DisplayPort SST	RBR, HRB, HRB2, HBR3	Simplex	Kufanana ndi AXIS Video Interface

2.1. Intel Agilex F-tile DisplayPort SST Parallel Loopback Design Mawonekedwe
SST parallel loopback design exampkuwonetsa kutumizira vidiyo imodzi kuchokera kusinki ya DisplayPort kupita kugwero la DisplayPort.
Malingaliro a kampani Intel Corporation Maumwini onse ndi otetezedwa. Intel, logo ya Intel, ndi zizindikiro zina za Intel ndi zizindikiro za Intel Corporation kapena mabungwe ake. Intel imatsimikizira kugwira ntchito kwa FPGA yake ndi zida za semiconductor malinga ndi zomwe zili pano malinga ndi chitsimikizo cha Intel, koma ili ndi ufulu wosintha zinthu ndi ntchito zilizonse nthawi iliyonse popanda kuzindikira. Intel sakhala ndi udindo kapena udindo chifukwa cha kugwiritsa ntchito kapena kugwiritsa ntchito zidziwitso zilizonse, malonda, kapena ntchito zomwe zafotokozedwa pano kupatula monga momwe Intel adavomerezera momveka bwino. Makasitomala a Intel amalangizidwa kuti apeze mtundu waposachedwa kwambiri wamakina a chipangizocho asanadalire zidziwitso zilizonse zosindikizidwa komanso asanayike maoda azinthu kapena ntchito. *Mayina ena ndi mtundu zitha kunenedwa kuti ndi za ena.
ISO 9001:2015 Adalembetsedwa
Chithunzi 6. Intel Agilex F-tile DisplayPort SST Parallel Loopback popanda PCR

• M'mitundu iyi, gawo la DisplayPort source, TX_SUPPORT_IM_ENABLE, limayatsidwa ndipo mawonekedwe amakanema amagwiritsidwa ntchito.
• Sinki ya DisplayPort imalandira makanema kapena kutulutsa mawu kuchokera kugwero lakunja lamavidiyo monga GPU ndikuisintha kukhala mawonekedwe ofanana ndi makanema.
• Kutulutsa kwamavidiyo a DisplayPort kumayendetsa mwachindunji mawonekedwe a kanema wa DisplayPort ndikuyika pa ulalo waukulu wa DisplayPort musanatumize ku polojekiti.
• IOPLL imayendetsa masinki onse a DisplayPort ndi mawotchi amakanema pafupipafupi.
• Ngati DisplayPort sinki ndi MAX_LINK_RATE magawo ake asinthidwa kukhala HBR3 ndipo PIXELS_PER_CLOCK asinthidwa kukhala Quad, wotchi ya kanema imayenda pa 300 MHz kuti igwirizane ndi 8Kp30 pixel rate (1188/4 = 297 MHz).

Chithunzi 7. Intel Agilex F-tile DisplayPort SST Parallel Loopback ndi AXIS Video Chiyankhulo

• M'mitundu iyi, gwero la DisplayPort ndi sink parameter, sankhani AXIS-VVP FULL mu ENABLE ACTIVE VIDEO DATA PROTOCOLS kuti athe Axis Video Data Interface.
• Sinki ya DisplayPort imalandira makanema kapena kutulutsa mawu kuchokera kugwero lakunja lamavidiyo monga GPU ndikuisintha kukhala mawonekedwe ofanana ndi makanema.
• DisplayPort Sink imatembenuza mayendedwe amakanema kukhala mavidiyo a axis ndikuyendetsa mawonekedwe a DisplayPort source axis data kudzera pa VVP Video Frame Buffer. DisplayPort Source imatembenuza mavidiyo a axis kukhala ulalo waukulu wa DisplayPort musanatumize ku polojekiti.
• M'mapangidwe awa, pali mawotchi akuluakulu atatu a kanema, omwe ndi rx/tx_axi4s_clk, rx_vid_clk, ndi tx_vid_clk. axi4s_clk imayenda pa 300 MHz pama module onse a AXIS mu Source ndi Sink. rx_vid_clk runsDP Sink Video pipeline pa 300 MHz (kuthandizira kusamvana kulikonse mpaka 8Kp30 4PIPs), pamene tx_vid_clk imayendetsa payipi ya DP Source Video pamafupipafupi a Pixel Clock (yogawidwa ndi PIPs).
• Makina osinthika awa amakonza ma frequency a tx_vid_clk kudzera pa I2C pulogalamu kupita pa SI5391B OSC pomwe kapangidwe kake kamazindikira kusintha.
• Kusiyanasiyana kwapangidweku kumangowonetsa zigamulo zokhazikika monga momwe zafotokozedwera mu pulogalamu ya DisplayPort, yomwe ndi:
  - 720p60, RGB
  - 1080p60, RGB
  4K30, RGB
  4K60, RGB

2.2. Clock Scheme
Chiwembu chowotchera chikuwonetsa madera omwe ali mu DisplayPort Intel FPGA IP kapangidwe kakeample.
Chithunzi 8. Intel Agilex F-tile DisplayPort Transceiver clocking schemeTable 5. Zizindikiro za Clock Scheme

Wotchi pachithunzi	Kufotokozera
Kusintha kwa SysPLL	Wotchi ya F-tile System PLL yomwe imatha kukhala mawotchi aliwonse omwe amatha kugawidwa ndi System PLL pama frequency omwe amachokera. M'mapangidwe awa example, system_pll_clk_link ndi rx/tx refclk_link amagawana zofanana 150 MHz SysPLL refclk.

Wotchi pachithunzi	Kufotokozera
	Iyenera kukhala wotchi yaulere yomwe imalumikizidwa kuchokera pa wotchi yodzipatulira ya transceiver kupita ku doko lolowera la Reference ndi System PLL Clocks IP, musanalumikizane ndi doko lofananira ndi DisplayPort Phy Top. Zindikirani: Kwa kapangidwe kake example, konzani Clock Controller GUI Si5391A OUT6 mpaka 150 MHz.
system pll clk ulalo	Kuchepa kwapang'onopang'ono kwa System PLL kumathandizira kuchuluka kwa DisplayPort ndi 320 MHz. Mapangidwe awa example amagwiritsa ntchito ma frequency a 900 MHz (apamwamba kwambiri) kotero kuti SysPLL refclk ikhoza kugawidwa ndi rx/tx refclk_link yomwe ili 150 MHz.
rx_cdr_refclk_link / tx_pll_refclk_link	Rx CDR ndi Tx PLL Link refclk yomwe idakhazikika ku 150 MHz kuti ithandizire kuchuluka kwa data ya DisplayPort.
rx_ls_clkout / tx_ls_clkout	DisplayPort Link Speed ​​​​Clock kuti mutsegule pachimake cha DisplayPort IP. Mafupipafupi ofanana ndi Deta Rate gawani ndi data yofananira m'lifupi mwake. ExampLe: Frequency = kuchuluka kwa data / kuchuluka kwa data = 8.1G (HBR3) / 40 bits = 202.5 MHz

2.3. Simulation Testbench
Testbench yoyeserera imatsanzira DisplayPort TX serial loopback ku RX.
Chithunzi 9. DisplayPort Intel FPGA IP Simplex Mode Simulation Testbench Block DiagramTable 6. Zida za Testbench

Chigawo	Kufotokozera
Video Pattern Generator	Jenereta iyi imapanga mitundu ya mipiringidzo yomwe mutha kuyikonza. Mukhoza parameterize kanema mtundu nthawi.
Testbench Control	Chida ichi chimayang'anira kutsatizana koyeserera ndikupangira zidziwitso zofunikira pakatikati pa TX. Chotchinga chowongolera cha testbench chimawerengeranso mtengo wa CRC kuchokera kugwero ndi kuzama kuti mufananize.
RX Link Speed ​​​​Clock Frequency Checker	Chowunikirachi chimatsimikizira ngati ma transceiver a RX omwe adachira mawotchi amafanana ndi zomwe mukufuna.
TX Link Speed ​​​​Clock Frequency Checker	Chowunikirachi chimatsimikizira ngati ma transceiver a TX omwe adachira mawotchi amafanana ndi kuchuluka kwa data komwe mukufuna.

Testbench yoyeserera imatsimikizira izi:
Table 7. Testbench Verifications

Zoyeserera	Kutsimikizira
• Lumikizani Maphunziro pa Data Rate HBR3 • Werengani ma registanti a DPCD kuti muwone ngati DP Status imakhazikitsa ndikuyesa ma frequency a TX ndi RX Link Speed.	Imaphatikiza Frequency Checker kuyeza Kuthamanga kwa Ulalo kutulutsa pafupipafupi kwa wotchi kuchokera ku TX ndi RX transceiver.
• Kuthamanga kanema chitsanzo kuchokera TX kuti RX. • Tsimikizirani gwero ndi sinki ya CRC kuti muwone ngati ikugwirizana	• Imalumikiza jenereta ya mavidiyo ku DisplayPort Source kuti ipangitse mawonekedwe a kanema. • Kuwongolera kwa Testbench kumawerengera onse Source ndi Sink CRC kuchokera ku DPTX ndi DPRX registry ndikuyerekeza kuti zitsimikizire kuti ma CRC onse ndi ofanana. Zindikirani: Kuti muwonetsetse kuti CRC yawerengedwa, muyenera kuyatsa gawo la Support CTS test automation parameter.

Mbiri Yokonzanso Zolemba za F-Tile DisplayPort Intel FPGA IP Design Exampndi User Guide

Document Version	Intel Quartus Prime Version	Mtundu wa IP	Zosintha
2022.09.02	22.	20.0.1	•Mutu wa zikalata zosinthidwa kuchokera ku DisplayPort Intel Agilex F-Tile FPGA IP Design Example Wogwiritsa Ntchito F-Tile DisplayPort Intel FPGA IP Design Exampndi User Guide. •Mapangidwe a Kanema a AXIS Exampndi zosiyanasiyana. •Anachotsa kapangidwe ka Static Rate ndikusintha ndi Multi Rate Design Example. •Anachotsa cholemba mu DisplayPort Intel FPGA IP Design Example Quick Start Guide yomwe imati mtundu wa pulogalamu ya Intel Quartus Prime 21.4 imangothandiza Preliminary Design Examples. •Idasinthitsa chithunzi cha Directory Structure ndi chithunzi cholondola. •Anawonjezera gawo Lopanganso ELF File pansi pa Kulemba ndi Kuyesa Mapangidwe. •Idasinthidwa gawo la Hardware and Software Requirements kuti likhale ndi zida zowonjezera zofunika.
2021.12.13	21.	20.0.0	Kutulutsidwa koyamba.

Malingaliro a kampani Intel Corporation Maumwini onse ndi otetezedwa. Intel, logo ya Intel, ndi zizindikiro zina za Intel ndi zizindikiro za Intel Corporation kapena mabungwe ake. Intel imatsimikizira kugwira ntchito kwa FPGA yake ndi zida za semiconductor malinga ndi zomwe zili pano malinga ndi chitsimikizo cha Intel, koma ili ndi ufulu wosintha zinthu ndi ntchito zilizonse nthawi iliyonse popanda kuzindikira. Intel sakhala ndi udindo kapena udindo chifukwa chakugwiritsa ntchito kapena kugwiritsa ntchito zidziwitso zilizonse, malonda, kapena ntchito zomwe zafotokozedwa pano kupatula monga momwe Intel adavomerezera momveka bwino. Makasitomala a Intel amalangizidwa kuti apeze mtundu waposachedwa kwambiri wamakina a chipangizocho asanadalire zidziwitso zilizonse zosindikizidwa komanso asanayike maoda azinthu kapena ntchito.
*Mayina ena ndi mtundu zitha kunenedwa kuti ndi za ena.
ISO 9001:2015 Adalembetsedwa

Baibulo Lomasulira
Tumizani Ndemanga
UG-20347
ID: 709308
Mtundu: 2022.09.02

Zolemba / Zothandizira

Intel F-Tile DisplayPort FPGA IP Design Example [pdf] Buku Logwiritsa Ntchito F-Tile DisplayPort FPGA IP Design Example, F-Tile DisplayPort, DisplayPort, FPGA IP Design Exampndi, IP Design Example, UG-20347, 709308

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• Buku Logwiritsa Ntchito