DisplayPort Agilex F-Tile FPGA IP Design Example
Ntuziaka onye ọrụ
Emelitere maka Intel® Quartus® Prime Design Suite: 21.4
Ụdị IP: 21.0.0

DisplayPort Intel FPGA IP Design Exampna Ntuziaka mmalite ngwa ngwa

DisplayPort Intel® FPGA IP imewe examples maka ngwaọrụ Intel Agilex™ F-tile nwere njiri simulating testbench na ngwaike na-akwado mkpokọta na nnwale ngwaike.
The DisplayPort Intel FPGA IP na-enye ndị a imewe examples:

• DisplayPort SST yiri loopback na-enweghị modul Pixel Clock Recovery (PCR) na ọnụego kwụ ọtọ

Mgbe ị na-emepụta design example, paramita nchịkọta akụkọ na-akpaghị aka na-emepụta filedị mkpa iji megharịa, chịkọta, na nwalee imewe na ngwaike.
Mara: Ụdị ngwanrọ Intel Quartus® Prime 21.4 na-akwado naanị Preliminary Design Example maka Simulation, Synthesis, Compilation, and Time analysis purpose. Achọpụtaghị ọrụ ngwaike nke ọma.
Ọgụgụ 1. Mmepe Stages

Ozi metụtara

• DisplayPort Intel FPGA IP ntuziaka onye ọrụ
• Na-akwaga na Intel Quartus Prime Pro Edition

1.1. Ọdịdị ndekọ
Ọgụgụ 2. Nhazi ndekọ aha

Tebụl 1. Imepụta Exampna akụrụngwa

Mpempe akwụkwọ	Files
rtl/isi	dp_core.ip
	dp_rx.ip
	dp_tx.ip
rtl/rx_phy	dp_gxb_rx/ ((DP PMA UX ngọngọ ụlọ)
	dp_rx_data_fifo.ip
	rx_top_phy.sv
rtl/tx_phy	dp_gxb_rx/ ((DP PMA UX ngọngọ ụlọ)
	dp_tx_data_fifo.ip
	dp_tx_data_fifo.ip

1.2. Achọrọ ngwaike na ngwanrọ
Intel na-eji ngwaike na ngwanrọ ndị a iji nwalee imewe exampLe:
Akụrụngwa

• Agilex I-Series Development Kit

Ngwa ngwa

• Intel Quartus Prime
• Synopsys * VCL Simulator

1.3. Ịmepụta Nhazi
Jiri DisplayPort Intel FPGA IP parameter editọ na Intel Quartus Prime sọftụwia iji wepụta ihe nrụpụta example.
Onyonyo 3. Ịmepụta usoro nhazi

1. Họrọ Ngwaọrụ ➤ IP katalọgụ, wee họrọ Intel Agilex F-tile dị ka ezinụlọ ngwaọrụ ebumnuche.
   Mara: Nhazi example naanị akwado Intel Agilex F-tile ngwaọrụ.
2. Na katalọgụ IP, chọta wee pịa DisplayPort Intel FPGA IP ugboro abụọ. Window mgbanwe IP ọhụrụ na-egosi.
3. Ezipụta aha ọkwa dị elu maka ụdị IP gị nkeonwe. Onye ndezi paramita na-echekwa ntọala IP dị iche na a file aha ya .ip.
4. Ị nwere ike họrọ otu Intel Agilex F-tile ngwaọrụ n'ọhịa ngwaọrụ, ma ọ bụ debe nhọrọ ngwaọrụ ngwanrọ Intel Quartus Prime ndabara.
5. Pịa OK. Ihe ndezi paramita na-egosi.
6. Hazie paramita achọrọ maka ma TX na RX
7. Na imewe Exampna tab, họrọ DisplayPort SST Parallel Loopback enweghị PCR.
8. Họrọ Simulation ka ịmepụta testbench, wee họrọ Synthesis iji mepụta ngwaike imewe example. Ị ga-ahọrọ ma ọ dịkarịa ala otu n'ime nhọrọ ndị a ka ịmepụta example files. Ọ bụrụ na ị họrọ ha abụọ, oge ọgbọ na-adị ogologo.
9. Pịa n'ịwa Example Design.

1.4. Ịmepụta atụmatụ ahụ
Ihe ngosi DisplayPort Intel FPGA IP imewe example testbench na-egosipụta usoro loopback serial site na ihe atụ TX ruo ihe atụ RX. Modul ihe nrụpụta vidiyo dị n'ime na-ebugharị ihe atụ DisplayPort TX yana mmepụta vidiyo RX na-ejikọ na ndị na-enyocha CRC na testbench.
Ọgụgụ 4. Ntugharị Simulation Design

1. Gaa na folda simulator Synopsys wee họrọ VCS.
2. Gbaa edemede ịme anwansị.
   Isi mmalite vcs_sim.sh
3. Edemede a na-arụ Quartus TLG, na-achịkọta ma na-agba testbench na simulator.
4. Nyochaa nsonaazụ ya.
   Simulation na-aga nke ọma na-ejedebe na ntụnyere Source na Sink SRC.

1.5. Ịchịkọta na ịmegharị atụmatụ ahụ
Ọgụgụ 5. Ịchịkọta na Ịmepụta Nhazi ahụ

Iji chịkọta ma mee nnwale ngosi na ngwaike exampka imewe, soro usoro ndị a:

1. Gbaa mbọ hụ na ngwaike example imewe ọgbọ zuru ezu.
2. Mepee sọftụwia Intel Quartus Prime Pro wee mepee /quartus/agi_dp_demo.qpf.
3. Pịa Nhazi ➤ Malite Nchịkọta.
4. Chere ruo mgbe nchịkọta agwụla.

Mara: Imewe example anaghị arụ ọrụ nyocha nke mbido mbụ Example na ngwaike na ntọhapụ Quartus a.
Ozi metụtara
Intel Agilex I-Series FPGA Development Kit Guide User

1.6. DisplayPort Intel FPGA IP Design Example Parameters
Tebụl 2. DisplayPort Intel FPGA IP Design ExampNhọrọ maka Intel Agilex F-tile Device

Oke	Uru	Nkọwa
Imepụta dị Example
Họrọ imewe	• Ọ dịghị • Nyiri DisplayPort SST Akwụghachi azụ na-enweghị PCR	Họrọ imewe example ka emeputa. • Ọ dịghị: Enweghị imewe example dị maka nhọrọ oke dị ugbu a • DisplayPort SST Parallel Loopback na-enweghị PCR: Nke a imewe example na-egosiputa loopback yiri ya site na DisplayPort sink gaa na isi iyi DisplayPort na-enweghị modul Pixel Clock Recovery (PCR) mgbe ị na-agbanye Kwado ihe ntinye ihe onyonyo vidiyo.
Imepụta Example Files
ịme anwansị	Gbanyụọ, Gbanyụọ	Gbanwuo nhọrọ a ka ịmepụta ihe dị mkpa files maka simulation testbench.
Synthesis	Gbanyụọ, Gbanyụọ	Gbanwuo nhọrọ a ka ịmepụta ihe dị mkpa files maka nhazi Intel Quartus Prime na nhazi ngwaike.
Ụdị HDL emepụtara
Mepụta File Usoro	Verilog, VHDL	Họrọ usoro HDL nke masịrị gị maka imewe emepụtara example filesetịpụrụ. Mara: Nhọrọ a na-ekpebi naanị usoro maka ọkwa IP dị elu emepụtara files. Ndị ọzọ niile files (dịka ọmụmaatụample testbenches na elu larịị files maka ngosipụta ngwaike) dị na ụdị Verilog HDL.
Ngwa mmepe ebumnuche
Họrọ bọọdụ	• Enweghị ngwa mmepe • Intel Agilex I-Series Ngwa mmepe	Họrọ osisi maka atụmatụ ezubere iche example. • Enweghị ngwa mmepe: Nhọrọ a na-ewepu akụkụ ngwaike niile maka imewe example. Isi IP na-edobe ọrụ ntụtụ niile na ntụtụ mebere. • Intel Agilex I-Series FPGA Development Kit: Nhọrọ a na-ahọrọ ngwa ngwa ebumnuche nke oru ngo iji dakọ na ngwaọrụ dị na ngwa mmepe a. Ị nwere ike ịgbanwe iche ngwaọrụ site na iji Change Target Device oke ma ọ bụrụ na gị osisi revision nwere dị iche iche ngwaọrụ variant. Isi IP na-edobe ọrụ ntụtụ niile dịka ngwa mmepe siri dị. Mara: Nhazi mbido ExampA naghị akwado nke ọma na ngwaike na ntọhapụ Quartus a. • Ngwa mmepe omenala: Nhọrọ a na-enye ohere imewe exampA ga-anwale ya na ngwa mmepe nke ndị ọzọ yana Intel FPGA. Ị nwere ike ịtọ ntọala pin n'onwe gị.
	Ngwa ebumnuche
Gbanwee ngwaọrụ ebumnuche	Gbanyụọ, Gbanyụọ	Gbanwuo nhọrọ a wee họrọ ụdị ngwaọrụ dị iche iche maka ngwa mmepe.

Myirịta Loopback Design Examples

Ihe ngosi DisplayPort Intel FPGA IP imewe examples gosi njikọ azụ azụ site na ihe atụ DisplayPort RX ruo ihe atụ DisplayPort TX na-enweghị modul Pixel Clock Recovery (PCR) na ọnụego kwụ ọtọ.
Tebụl 3. DisplayPort Intel FPGA IP Design Exampmaka Intel Agilex F-tile Device

Imepụta Example	Nhọpụta	Ọnụego data	Ọnọdụ Channel	Ụdị Loopback
DisplayPort SST yiri loopback na-enweghị PCR	DisplayPort SST	HBR3	Simplex	Yiri na-enweghị PCR

2.1. Intel Agilex F-tile DisplayPort SST Parallel Loopback atụmatụ atụmatụ
The SST yiri loopback imewe exampma gosipụta nnyefe nke otu iyi vidiyo site na DisplayPort sink gaa na isi iyi DisplayPort na-enweghị Pixel Clock Recovery (PCR) na ọnụego kwụ ọtọ.

Ọgụgụ 6. Intel Agilex F-tile DisplayPort SST Parallel Loopback na-enweghị PCR

• N'ụdị dị iche iche a, agbanyere paramita isi iyi DisplayPort, TX_SUPPORT_IM_ENABLE ma jiri ihu onyonyo onyonyo.
• The DisplayPort sink na-enweta vidiyo na ma ọ bụ ọdịyo ọdịyo sitere na isi iyi vidiyo dị n'èzí dị ka GPU wee depụta ya na interface vidiyo yiri ya.
• Mmepụta vidiyo sink nke DisplayPort na-ebugharị ngwa ngwa vidiyo isi iyi nke DisplayPort wee tinye ya na njikọ isi DisplayPort tupu ebunye ya na onye nleba anya.
• IOPLL na-ebugharị ma DisplayPort sink na isi iyi vidiyo na oge a kapịrị ọnụ.
• Ọ bụrụ na ahaziri ihe ngosi DisplayPort na isi iyi MAX_LINK_RATE ka HBR3 wee hazie PIXELS_PER_CLOCK ka ọ bụrụ Quad, elekere vidiyo na-aga na 300 MHz iji kwado ọnụego pikselụ 8Kp30 (1188/4 = 297 MHz).

2.2. Atụmatụ elekere
Atụmatụ clocking na-egosi ngalaba elekere na DisplayPort Intel FPGA IP imewe example.
Ọgụgụ 7. Intel Agilex F-tile DisplayPort Transceiver clocking atụmatụ

Tebụl 4. Ngosipụta atụmatụ elekere

Elekere na eserese	Nkọwa
SysPLL refclk	F-tile Sistemu Ntụaka Elekere PLL nke nwere ike ịbụ ugboro elekere ọ bụla nke Sistemu PLL na-eke maka oge mmepụta ahụ. Na nke a imewe example, system_pll_clk_link na rx/tx refclk_link na-ekerịta otu SysPLL refclk nke bụ 150Mhz. Ọ ga-abụrịrị elekere na-agba ọsọ n'efu nke ejikọtara site na pin elekere ntụgharị transceiver raara onwe ya nye n'ọdụ ụgbọ mmiri ntinye aka nke Reference na Sistemụ PLL Clocks IP, tupu ijikọ ọdụ ụgbọ mmiri kwekọrọ na DisplayPort Phy Top.
system_pll_clk_link	Opekempe mmepụta PLL Sistemu iji kwado ọnụego DisplayPort niile bụ 320Mhz. Nke a imewe example na-eji 900Mhz (kachasị elu) mmepụta ugboro ka SysPLL refclk wee nwee ike ịkekọrịta na rx/tx refclk_link nke bụ 150Mhz.
rx_cdr_refclk_link/tx_pll_refclk_link	Rx CDR na Tx PLL Link refclk nke edobere na 150Mhz iji kwado ọnụego data DisplayPort niile.
rx_ls_clkout/tx bụ clkout	DisplayPort Njikọ Ọsọ elekere ruo elekere DisplayPort IP isi. Ugboro nke dabara na nkewa ọnụego data site na obosara data yiri ya. ExampLe: Ugboro = ọnụego data/obosara data = 8.1G (HBR3) / 40bits = 202.5Mhz

2.3. Testbench Simulation
Testbench simulation na-eme ka ngosipụta nke DisplayPort TX laghachi azụ na RX.
Ọgụgụ 8. DisplayPort Intel FPGA IP Simplex Mode Simulation Testbench Block Eserese

Tebụl 5. Ngwa Testbench

Akụkụ	Nkọwa
Ihe Nlereanya vidiyo	Igwe ọkụ a na-emepụta ụkpụrụ mmanya agba nke ị nwere ike hazie. Ị nwere ike parameterize video usoro oge.
Njikwa Testbench	Ihe mgbochi a na-achịkwa usoro ule nke ịme anwansị ahụ ma wepụta akara mkpali dị mkpa na isi TX. Ihe mgbochi testbench na-agụkwa uru CRC sitere na isi mmalite na sink iji mee ntụnyere.
Onye nlele elekere ọsọ ọsọ RX	Ihe nlele anya a na-enyocha ma ọ bụrụ na transceiver RX enwetara ugboro elekere dabara na ọnụego data achọrọ.
TX Njikọ Ọsọ elekere ugboro ugboro	Ihe nlele a na-enyocha ma ọ bụrụ na transceiver TX enwetara ugboro elekere dabara na ọnụego data achọrọ.

Testbench simulation na-eme nkwenye ndị a:
Tebụl 6. Nyochaa Testbench

Nlele ule	Nyocha
• Ọzụzụ njikọ na ọnụego data HBR3 • Gụọ ndekọ DPCD ka ịlele ma Ọnọdụ DP na-ahazi ma tụọ ma TX na RX Njikọ Ọsọ ọsọ.	Na-ejikọta ihe nlele ugboro ugboro iji tụọ mmepụta ugboro elekere njikọ ọsọ site na TX na RX transceiver.
• Gbaa ụkpụrụ vidiyo site na TX ruo RX. • Nyochaa CRC maka isi iyi na sink ka ịlele ma ha dabara	• Jikọọ vidiyo ụkpụrụ generator na DisplayPort Isi iyi ka iwepụta video ụkpụrụ. • Njikwa Testbench na-agụpụta ma Source na Sink CRC sitere na ndekọ DPTX na DPRX ma tụnyere iji hụ na ụkpụrụ CRC abụọ ahụ bụ otu. Mara: Iji hụ na agbakọrọ CRC, ị ga-emerịrị ihe nkwado CTS akpaaka akpaaka.

Akụkọ ngbanwe akwụkwọ maka DisplayPort Intel

Agilex F-tile FPGA IP Design Example ntuziaka onye ọrụ

Ụdị akwụkwọ	Intel Quartus Prime Version	Ụdị IP	Mgbanwe
2021.12.13	21.4	21.0.0	Ntọhapụ mbụ.

Ụlọ ọrụ Intel. Ikike niile echekwabara. Intel, akara Intel, na akara Intel ndị ọzọ bụ ụghalaahịa nke Intel Corporation ma ọ bụ ndị enyemaka ya. Intel nyere ikike ịrụ ọrụ nke FPGA na ngwaahịa semiconductor na nkọwapụta ugbu a dịka akwụkwọ ikike ọkọlọtọ Intel siri dị, mana nwere ikike ịme mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Intel anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Intel kwetara na ederede. A dụrụ ndị ahịa Intel ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ.
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Version nke Ntanetị
Zipu nzaghachi
UG-20347
ID: 709308
Ụdị: 2021.12.13

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intel DisplayPort Agilex F-Tile FPGA IP Design Example [pdf] Ntuziaka onye ọrụ DisplayPort Agilex F-Tile FPGA IP Design Example, DisplayPort Agilex, F-Tile FPGA IP Design Example, F-Tile FPGA IP Design, FPGA IP Design Example, IP Design Example, IP Design, UG-20347, 709308

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