STMicroelectronics STM32MP133C F 32-bit Arm Cortex-A7 1GHz MPU Taiala mo Tagata

Mataupu lalafi

1 STMicroelectronics STM32MP133C F 32-bit Arm Cortex-A7 1GHz MPU

2 Fa'amatalaga

3 Arm Cortex-A7 Subsystem

8 Fa'amatalaga Fa'atatau

STMicroelectronics STM32MP133C F 32-bit Arm Cortex-A7 1GHz MPU

Fa'amatalaga

Autu: Arm Cortex-A7
Manatua: SDRAM fafo, SRAM faʻapipiʻi

Pasi Fa'amatalaga: 16-bit parallel interface
Saogalemu/Saogalemu: Toe Seti ma Pulea Malosiaga, LPLV-Stop2, Standby

afifi: LFBGA, TFBGA ma min pitch 0.5 mm
Pulega o Uati

Fa'amoemoega Lautele Ulufale/Galue
Feso'ota'i Matrix

4 DMA Pule
Feso'ota'iga Peripheral: E o'o i le 29

Va'aiga Fa'atusa: 6
Taimi: E oo atu i le 24, Watchdogs: 2

Faatelevaveina o Meafaigaluega
Faiga Debug

Fuses: 3072-bit e aofia ai ID tulaga ese ma HUK mo AES 256 ki
ECOPACK2 tausisia

Arm Cortex-A7 Subsystem

O le Arm Cortex-A7 subsystem o le STM32MP133C/F e maua ai…

Faamanatuga

O le masini e aofia ai le SDRAM fafo ma le SRAM faʻapipiʻi mo le teuina o faʻamaumauga ...

DDR Pule

O le DDR3/DDR3L/LPDDR2/LPDDR3 pule e pulea le mauaina o manatua…

Puleaina o le Malosiaga
O le polokalame o le sapalai eletise ma le supavaisa faʻamautinoa le tuʻuina atu o le paoa ...

Pulega o Uati
O le RCC e fa'atautaia le tufatufaina atu o uati ma fa'atonuga...

Fa'amoemoega Lautele Ulufale/Galue (GPIOs)
O le GPIO e tuʻuina atu faʻaoga gafatia mo masini fafo ...

Pule Puipuia TrustZone
O le ETZPC e faʻaleleia le saogalemu o le polokalama e ala i le puleaina o aia tatau ...

Bus-Feso'ota'i Matrix
O le matrix e faafaigofie ai le fesiitaiga o faamatalaga i le va o modules eseese…

FAQs

Q: Ole a le maualuga ole numera ole telefoni feso'ota'iga e lagolagoina?
A: O le STM32MP133C/F e lagolagoina e oʻo atu i le 29 telefoni fesoʻotaʻiga.

Q: E fia ni telefoni fa'aigoa o lo'o maua?
A: O le masini e ofoina atu 6 analog peripherals mo galuega analog eseese.

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STM32MP133C STM32MP133F

Arm® Cortex®-A7 e oʻo atu i le 1 GHz, 2 × ETH, 2 × CAN FD, 2 × ADC, 24 taimi, leo, crypto ma adv. saogalemu
Pepa faʻamaumauga - faʻamaumauga o gaosiga

Vaega
E aofia ai ST fa'aonaponei fa'atekonolosi pateni
Autu
· 32-bit Arm® Cortex®-A7 L1 32-Kbyte I / 32-Kbyte D 128-Kbyte tulaga fa'atasi 2 cache Arm® NEONTM ma Arm® TrustZone®

Faamanatuga
· Faʻamatalaga DDR fafo e oʻo atu i le 1 Gbyte e oʻo atu i le LPDDR2/LPDDR3-1066 16-bit e oʻo atu i le DDR3/DDR3L-1066 16-bit
· 168 Kbytes o le SRAM i totonu: 128 Kbytes o le AXI SYSRAM + 32 Kbytes o le AHB SRAM ma le 8 Kbytes o le SRAM i le Backup domain
· Lua Quad-SPI fa'aoga fa'amanatuga · Fa'atonu le fa'atonu i fafo e o'o atu i
16-bit data pasi: faʻaoga tutusa e faʻafesoʻotaʻi fafo ICs ma SLC NAND manatua e oʻo atu ile 8-bit ECC
Saogalemu/saogalemu
· Fa'amaufa'ailoga fa'a, TrustZone® peripherals, 12 xtamper pine e aofia ai le 5 x galue tampers
· Temperature, voltagu, taimi ma 32 kHz mataituina
Toe seti ma pulea le malosi
· 1.71 V i le 3.6 VI / Os tuʻuina atu (5 V-tolerant I / Os) · POR, PDR, PVD ma BOR · LDOs i luga o le masini (USB 1.8 V, 1.1 V) · Faʻatonu faʻapipiʻi (~ 0.9 V) · Faʻalogo vevela i totonu · Faiga maualalo: Moe, Taofi, LPLV-Stop
LPLV-Stop2 ma Standby

LFBGA

TFBGA

LFBGA289 (14 × 14mm) Pitch 0.8 mm

TFBGA289 (9 × 9 mm) TFBGA320 (11 × 11 mm)
min pitch 0.5 mm

· Fa'atumauina DDR i le tulaga Standby · Pulea mo le pu'upu'u soa PMIC

Puleaina o le uati
· Oscillator i totonu: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz LSI oscillator
· Oscillators fafo: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator
· 4 × PLLs fa'atasi ai ma faiga fa'a-vaega

Fa'aoga fa'amoemoe lautele
· E oʻo atu i le 135 faʻamautu I/O ports ma faʻalavelave faʻalavelave
· E oo atu i le 6 alafa'i

Feso'ota'i matrix
· 2 matrices pasi 64-bit Arm® AMBA® AXI fesoʻotaʻi, e oʻo atu i le 266 MHz 32-bit Arm® AMBA® AHB fesoʻotaʻi, e oʻo atu i le 209 MHz

4 DMA pule e la'u ese le PPU
· 56 auala faʻaletino i le aofaʻi
· 1 x maualuga-saosaoa lautele-faamoemoega matai pulea tuusaʻo manatua avanoa (MDMA)
· 3 × DMAs lua-taulaga ma le FIFO ma talosagaina le gafatia o le router mo le pulega sili ona lelei

Setema 2024
Ole fa'amatalaga lea ile oloa ile gaosiga atoa.

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www.st.com

STM32MP133C/F

E oʻo atu i le 29 fesoʻotaʻiga peripherals
· 5 × I2C FM+ (1 Mbit/s, SMBus/PMBusTM) · 4 x UART + 4 x USART (12.5 Mbit/s,
ISO7816 fa'aoga, LIN, IrDA, SPI) · 5 × SPI (50 Mbit/s, e aofia ai le 4 fa'atasi ai ma le fa'aluaina atoa.
I2S leo sa'o vasega e ala ile PLL leo totonu po'o le uati fafo)(+2 QUADSPI + 4 ma USART) · 2 × SAI (leo leo: I2S, PDM, SPDIF Tx) · SPDIF Rx fa'atasi ma 4 mea fa'aoga · 2 × SDMMC e o'o atu i le 8 bits (SD/e·MMCTM/SDIO) × FD supporting × CTM2. maualuga-saosaoa Host poʻo 2 × USB 2.0 maualuga-saoasaoa Host

+ 1 × USB 2.0 maualuga-saosaoa OTG i le taimi e tasi · 2 x Ethernet MAC/GMAC IEEE 1588v2 meafaigaluega, MII/RMII/RGMII
6 peripheral analog
· 2 × ADCs ma le 12-bit max. iugafono e oo atu i le 5 Msps
· 1 x vevela sensor · 1 x faamama numera mo sigma-delta modulator
(DFSDM) faʻatasi ai ma laina 4 ma 2 filiga · Faʻamatalaga ADC i totonu poʻo fafo VREF +
E oʻo atu i le 24 taimi ma le 2 leoleo
· 2 × 32-bit timers ma e oʻo atu i le 4 IC/OC/PWM poʻo le fata pusi ma le quadrature (faʻaopoopo) faʻaoga encoder.
· 2 × 16-bit taimi alualu i luma · 10 × 16-bit fa'amoemoe lautele (e aofia ai
2 taimi fa'avae e aunoa ma le PWM) · 5 × 16-bit fa'amaulalo-malosi taimi · Saogalemu RTC fa'atasi ai ma le sa'o-lua ma
kalena meafaigaluega · 4 Cortex®-A7 taimi faʻatulagaina (saogalemu,
le saogalemu, virtual, hypervisor) · 2 × tutoatasi leoleo leoleo
Fa'avaveina meafaigaluega
· AES 128, 192, 256 DES/TDES

2 (tutoatasi, malu puipuia) 5 (2 malu puipuia) 4 5 (3 malu puipuia)
4 + 4 (e aofia ai le 2 securable USART), o nisi e mafai ona avea ma faʻaupuga
2 (e oʻo atu i le 4 ala leo), faʻatasi ai ma le I2S matai / pologa, faʻaoga PCM, SPDIF-TX 2 ports
HSPHY fa'apipi'i ma le BCD Fa'apipi'i le HS PHY fa'atasi ma le BCD (securable), e mafai ona avea ma fa'apogai ta'avale.
2 × HS fa'asoa i le va o le Host ma le OTG 4 fa'aoga

2 (1 × TTCAN), fa'avasegaina o le uati, 10 Kbyte fa'asoa fa'atasi 2 (8 + 8 bits) (securable), e·MMC po'o le SD e mafai ona avea ma fa'apogai ta'avale 2 sapalai mana tuto'atasi faitalia mo fa'afeso'ota'i kata SD.
1 (lua-quad) (securable), e mafai ona avea ma se faʻaupuga

–
–
Boot
–
Boot
Boot Boot
(1)

Tulaga tutusa/fa'amatalaga 8/16-bit FMC Fa'atasi AD-mux 8/16-bit
NAND 8/16-bit 10/100M/Gigabit Ethernet DMA Cryptography
Hash True random number generator Fuses (e tasi le taimi e mafai ona polokalame)

4 × CS, e oʻo atu i le 4 × 64 Mbyte
Ioe, 2 × CS, SLC, BCH4 / 8, e mafai ona avea ma se faʻavae faʻavae 2 x (MII, RMI, RGMII) ma PTP ma EEE (securable)
3 fa'ata'ita'iga (1 fa'amautu), 33-auala MDMA PKA (fa'atasi ai ma le puipuiga o le DPA), DES, TDES, AES (fa'atasi ma le puipuiga o le DPA)
(e malu puipuia uma) SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-3, HMAC
(securable) Moni-RNG (securable) 3072 pa'u aoga (saogalemu, 1280 bits avanoa mo le tagata fa'aoga)

–
Se'a -
–

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DS13875 Faaaliga 5

STM32MP133C/F

Fa'amatalaga

Fuafuaga 1. STM32MP133C/F foliga ma numera pito i tua (fa'aauau)

STM32MP133CAE STM32MP133FAE STM32MP133CAG STM32MP133FAG STM32MP133CAF STM32MP133FAF Eseese

Vaega

LFBGA289

TFBGA289

TFBGA320

GPIO fa'alavelave (fa'ato'atoa faitau)

135(2)

Fa'amaufa'ailogaina GPIOs Fafafafa pine

O mea uma
6

Tamper pine (toaga tamper)

12 (5)

DFSDM E oʻo i le 12-bit faʻatasi ADC

4 auala fa'aoga ma 2 filiga

–

2(3) (e oo atu i le 5 Msps i luga ole 12-bit taitasi) (securable)

ADC1: 19 auala e aofia ai 1x totonu, 18 auala avanoa mo

12-bit ADC auala atoa(4)

tagata fa'aoga e aofia ai le 8x differential

–

ADC2: 18 auala e aofia ai 6x totonu, 12 auala avanoa mo

tagata fa'aoga e aofia ai le 6x differential

I totonu ADC VREF VREF+ fa'aoga pine

1.65 V, 1.8 V, 2.048 V, 2.5 V po'o VREF+ fa'aoga -
Ioe

1. E mafai e le QUADSPI ona ta'a'a mai GPIO tu'ufa'atasia po'o le fa'aogaina o nisi FMC Nand8 boot GPIOs (PD4, PD1, PD5, PE9, PD11, PD15 (silasila i le Laulau 7: STM32MP133C/F fa'amatalaga polo).
2. Ole aofa'iga ole GPIO e aofia ai le fa JTAG GPIO ma tolu BOOT GPIO e fa'atapula'aina le fa'aoga (e ono fete'ena'i ma feso'ota'iga masini i fafo a'o su'esu'e tuaoi po'o le ta'avale).
3. A fa'aoga uma ADC, e tatau ona tutusa le uati o le fatu mo ADC uma ma e le mafai ona fa'aogaina le fa'apipi'i ADC.
4. E le gata i lea, o loʻo i ai foʻi ala i totonu: - ADC1 auala i totonu: VREFINT - ADC2 auala i totonu: vevela, vol i totonutage fa'asino, VDDCORE, VDDCPU, VDDQ_DDR, VBAT / 4.

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Fa'amatalaga 18/219

STM32MP133C/F

Ata 1. STM32MP133C/F poloka ata

IC sapalai

@VDDA

HSI

AXIM: Lima 64-bit AXI feso'ota'i (266 MHz) T

@VDDCPU

GIC

Cortex-A7 CPU 650/1000 MHz + MMU + FPU + NEONT

32K D$

32K I$

CNT (taimi) T

ETM

2561K2B8LK2B$L+2$SCU T
async

128 pito

CSI

LSI

Debug taimiamp

generator TSGEN

DAP
(JTAG/SWD)

SYSRAM 128KB

ROM 128KB

2 x ETH MAC
10/100/1000(leai se GMII)

FIFO

BKPSRAM 8KB

RNG

HASH

16b FILO

DDRCTRL 58
LPDDR2/3, DDR3/3L

async

CRYP

SAES

DDRMCE T TZC T

DDRPHYC
T

TAIMI

8b QUADSPI (lua) T

16b

FMC

CRC

DLYBSD1

(SDMMC1 DLY pulega)

DLYBSD2

(SDMMC2 DLY pulega)

DLYBQS

(QUADSPI DLY pulega)

FIFO FIFO

DLY DLY

14 8b SDMMC1 T 14 8b SDMMC2 T

PHY

USBH

(2xHS Talimalo)

PLLUSB

FIFO

PKA

FIFO

T MDMA 32 alavai

AXIMC TT

17 16b Su'ega uafu

ETZPC

IWDG1

@VBAT

BSEC

OTP Fuse

@VDDA

RTC / AWU

TAMP / Fa'amaumauga faaleoleo T

@VBAT

LSE (32kHz XTAL)

Taimi faiga STGENC

tupulaga

STGENR

USBPHYC
(USB 2 x PHY pule)
IWDG2

@VBAT

@VDDA

VREFBUF

16b LPTIM2

16b LPTIM3

16b LPTIM4

16b LPTIM5

BOOT pine

SYSCFG

HDP

10 16b TIM1/PWM 10 16b TIM8/PWM

SAI1

SAI2

4ch DFSDM

Puipui 10KB CCU

FDCAN1

FDCAN2

FIFO FIFO
APB2 (100 MHz)

8KB FIFO
APB5 (100MHz)

APB3 (100 MHz)

APB4

async AHB2APB

SRAM1 16KB T SRAM2 8KB T SRAM3 8KB T

AHB2APB

DMA1
8 vaitafe
DMAMUX1
DMA2
8 vaitafe

DMAMUX2

DMA3
8 vaitafe

PMB (mata'itū faiga)
DTS (fa'avevela le vevela)

Voltagu fa'atonu

@VDDA

Vaavaaiga sapalai

FIFO

2x2 fa'ameamea
AHB2APB

64 bits AXI

64bits AXI matai

32 bits AHB 32 bits AHB matai

32 bits APB

T TrustZone puipuiga malu

AHB2APB

APB2 (100 MHz)

APB1 (100 MHz)
FIFO FIFO FIFO FIFO FIFO

MLAHB: Arm 32-bit tele-AHB pasi matrix (209 MHz)
APB6
FIFO FIFO FIFO FIFO

@VBAT
T
FIFO

HSE (XTAL)

PLL1/2/3/4

RCC

T PWR

EXTI

16isi

176

USBO

(OTG HS)

PHY

12b ADC1

12b ADC2

GPIOA

16b

GPIOB

16b

GPIOC

16b

GPIOD

16b

GPIOE

16b

GPIOF

16b

GPIOG 16b 16

GPIOH

16b

GPIOI

16b

AHB2APB

USART1

Smartcard IrDA

USART2

Smartcard IrDA

SPI4/I2S4

SPI5

I2C3/SMBUS

I2C4/SMBUS

I2C5/SMBUS

Fa'amama Filifiliga

TIM12

16b

TIM13

16b

TIM14

16b

TIM15

16b

TIM16

16b

TIM17

16b

TIM2 TIM3 TIM4

32b

16b

TIM5 TIM6 TIM7

32b

16b

LPTIM1 16b

USART3

Smartcard IrDA

UART4

UART5

UART7

UART8

Filter Filter

I2C1/SMBUS

I2C2/SMBUS

SPI2/I2S2

SPI3/I2S3

USART6

Smartcard IrDA

SPI1/I2S1

FIFO FIFO

MSv67509V2

DS13875 Faaaliga 5

STM32MP133C/F

Faʻaaoga lugaview

3.1
3.1.1
3.1.2

Arm Cortex-A7 subsystem
Vaega
· ARMv7-A architecture · 32-Kbyte L1 fa'atonuga cache · 32-Kbyte L1 fa'amaumauga cache · 128-Kbyte level2 cache · Arm + Thumb®-2 seti fa'atonuga · Arm TrustZone security technology · Arm NEON advanced SIMD · DSP ma SIMD extensions · VFPv4 floating-point · Hardware virtualization support · (Embedded trace) fa'apipi'i fa'apipi'i (Embedded trace) 160 fa'alavelave fa'alavelave fa'atasi · Taimi fa'atasi (CNT)
Ua umaview
O le Cortex-A7 processor o se faiga e sili ona lelei le malosi o talosaga ua fuafuaina e maua ai le tele o faatinoga i mea e mafai ona maua i luga o le pito i luga, ma isi mea e fa'aogaina ma fa'atau. E tu'uina atu i le 20% sili atu fa'atinoga o filo e tasi nai lo le Cortex-A5 ma maua ai fa'atinoga tutusa nai lo le Cortex-A9.
O le Cortex-A7 o loʻo tuʻufaʻatasia uma vaega o le Cortex-A15 ma le CortexA17 processors maualuga, e aofia ai le lagolago faʻapitoa i meafaigaluega, NEON, ma le 128-bit AMBA 4 AXI bus interface.
O le Cortex-A7 processor e fausia i luga o le malosi-lelei 8-stage paipa o le Cortex-A5 processor. E faʻamanuiaina foʻi mai se faʻapipiʻi L2 faʻapipiʻi faʻatulagaina mo le maualalo o le mana, faʻatasi ai ma le laititi o fefaʻatauaiga ma faʻaleleia le lagolago OS mo le tausiga o le cache. I luga o lenei mea, o loʻo i ai le faʻaleleia atili o le lala ma le faʻaleleia o le faʻaogaina o le polokalama, faʻatasi ai ma le 64-bit loadstore path, 128-bit AMBA 4 AXI pasi ma faʻateleina le TLB (256 ulufale, mai le 128 ulufale mo Cortex-A9 ma Cortex-A5), faʻateleina le faʻatinoga mo galuega tetele e pei o le web suʻega
Thumb-2 tekinolosi
Tuuina atu le maualuga o le faʻatinoga o le Arm code masani aʻo tuʻuina atu foi i le 30% faʻaititia o manaʻoga mo le teuina o faatonuga.
tekinolosi TrustZone
Fa'amautinoa le fa'atuatuaina o le fa'atinoina o talosaga mo le puipuiga e amata mai i le pulega o aia tatau fa'atekinolosi i le totogiina fa'aeletoroni. Lagolago lautele mai tekinolosi ma pa'aga tau alamanuia.

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Faʻaaoga lugaview

STM32MP133C/F

NEON
NEON tekinolosi e mafai ona faatelevaveina faʻasalalauga faʻasalalauga ma faʻailoga algorithms e pei o le vitio encode / decode, 2D / 3D faʻataʻitaʻiga, taʻaloga, faʻalogo leo ma tautalaga, faʻasologa o ata, telefoni, ma le faʻaogaina o leo. O le Cortex-A7 e maua ai se afi e ofoina atu uma le faʻatinoga ma le faʻatinoga o le Cortex-A7 floating-point unit (FPU) ma se faʻatinoga o le NEON advanced SIMD faʻatonuga seti mo le faʻavavevaveina o galuega faʻasalalau ma faʻailoga. O le NEON e faʻalauteleina le Cortex-A7 processor FPU e tuʻuina atu ai se quad-MAC ma faʻaopoopo 64-bit ma 128-bit seti resitala e lagolagoina ai se seti mauoa o faʻagaioiga SIMD i luga ole 8-, 16- ma le 32-bit integer ma le 32-bit floating-point data quantities.
Fa'atekonolosi masini
E sili atu ona lelei meafaigaluega lagolago mo faʻamaumauga ma faʻatalanoaga, lea e mafai ai e le tele o siʻosiʻomaga polokalama ma a latou talosaga ona maua i le taimi e tasi le mafai gafatia. O lenei mea e mafai ai ona faʻaalia masini e malosi, faʻatasi ai ma siʻosiʻomaga faʻapitoa e vaʻaia lelei mai le tasi ma le isi.
Fa'alelei L1 caches
Fa'atinoga ma le malosi sili L1 fa'aoga e tu'ufa'atasia la'ititi la'ititi auala e mafai ai ona fa'ateleina le fa'atinoga ma fa'aitiitia le fa'aogaina o le eletise.
L2 fa'apipi'i fa'atonu
Tuuina atu le maualalo o le latency ma le maualuga-bandwidth avanoa i manatua cache i le maualuga-televave, poʻo le faʻaitiitia o le faʻaogaina o le eletise e fesoʻotaʻi ma le avanoa e manatua ai fafo-chip.
Cortex-A7 vaega fa'afefeteina (FPU)
O le FPU o lo'o tu'uina atu ai fa'atonuga fa'a-fa'a'a'e fa'ato'a fa'asolo ma ta'ilua e fetaui ma le fa'ata'ita'iga o le Arm VFPv4 lea o lo'o fa'aogaina le komipiuta fa'atasi ma augatupulaga muamua o le Arm floating-point coprocessor.
Snoop control unit (SCU)
O le SCU e nafa ma le faʻafoeina o fesoʻotaʻiga, faʻatalanoaga, fesoʻotaʻiga, faʻaoga i le faʻaoga ma le faʻaogaina o mea e manatua ai, faʻaogaina o le cache ma isi gafatia mo le gaosiga.
O lenei faiga fa'aogaina e fa'aitiitia ai fo'i le lavelave o polokalama fa'akomepiuta o lo'o a'afia i le fa'atumauina o feso'ota'iga polokalame i totonu o ta'avale OS ta'itasi.
Pule fa'alavelave lautele (GIC)
O le fa'atinoina o le fa'atonuina ma le fa'atulagaina o fa'alavelave fa'alavelave, o le GIC e tu'uina atu ai se auala mauoa ma fetuutuuna'i i feso'ota'iga va'ava'ai va'aiga ma le ta'avaleina ma le fa'amuamua o fa'alavelave fa'aletonu.
Lagolagoina e o'o atu i le 192 fa'alavelave tuto'atasi, i lalo o le fa'atonutonuina o polokalame, fa'amuamua meafaigaluega, ma fa'asolo i le va o le faiga fa'aoga ma le vaega o le pulega o polokalama faakomepiuta TrustZone.
O lenei faʻaogaina o fesoʻotaʻiga ma le lagolago mo le faʻaogaina o faʻalavelave i totonu o le faiga faʻaoga, e maua ai se tasi o vaega taua e manaʻomia e faʻaleleia ai le gafatia o se fofo e faʻaaoga ai se hypervisor.

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DS13875 Faaaliga 5

STM32MP133C/F

Faʻaaoga lugaview

3.2
3.2.1
3.2.2

Faamanatuga
SDRAM fafo
O masini STM32MP133C/F o loʻo faʻapipiʻiina se pule mo SDRAM fafo e lagolagoina mea nei: · LPDDR2 poʻo LPDDR3, 16-bit data, e oʻo atu i le 1 Gbyte, e oʻo atu i le 533 MHz uati · DDR3 poʻo DDR3L, 16-bit data, e oʻo atu i le 1 Gbyte, e oʻo atu i le 533 MHz uati
SRAM fa'apipi'i
O masini uma e fa'aalia: · SYSRAM: 128 Kbytes (fa'atasi ai ma le sone malu puipuia) · AHB SRAM: 32 Kbytes (securable) · BKPSRAM (backup SRAM): 8 Kbytes
O mea o lo'o i totonu o lenei vaega e puipuia mai avanoa tusitusi e le mana'omia, ma e mafai ona taofia i le Standby po'o le VBAT mode. BKPSRAM e mafai ona faauigaina (i le ETZPC) e mafai ona maua e na'o polokalama malupuipuia.

3.3

DDR3/DDR3L/LPDDR2/LPDDR3 pule (DDRCTRL)

DDRCTRL tu'ufa'atasia ma DDRPHYC e maua ai se fa'afofoga fa'aoga atoatoa mo le DDR memory subsystem. · Tasi 64-bit AMBA 4 AXI ports interface (XPI) · AXI clock asynchronous to the controller · DDR memory cypher engine (DDRMCE) fa'aalia AES-128 DDR on-the-fly write
fa'amalamalamaga/faitau fa'ailoga. · Tulaga lagolago:
JEDEC DDR3 SDRAM faʻamatalaga, JESD79-3E mo DDR3 / 3L faʻatasi ma le 16-bit interface
JEDEC LPDDR2 SDRAM faʻamatalaga, JESD209-2E mo LPDDR2 faʻatasi ma le 16-bit interface
JEDEC LPDDR3 SDRAM faʻamatalaga, JESD209-3B mo LPDDR3 faʻatasi ai ma le 16-bit interface
· Faʻatonu faʻatulagaina ma le faʻatonuina o le SDRAM · Faʻapipiʻiina le lautele o faʻamatalaga (16-bit) poʻo le afa faʻamatalaga lautele (8-bit) · Fesoasoani maualuga QoS ma le tolu vasega fefaʻatauaʻiga i luga o le faitau ma lua vasega fefaʻatauaʻiga i luga o le tusitusi · Filifiliga e aloese ai mai le matelaina o feoaiga maualalo maualalo · Faʻamautinoa le felagolagomaʻi mo le tusitusi-pe-ma-faitau (WAR) ma le faitau-pe-ma-tusi (RAW) i luga
AXI ports · Polokalama lagolago mo le pa'u umi filifiliga (4, 8, 16) · Tusi fa'atasi e fa'ataga ai le tele o tusitusiga i le tuatusi e tasi e tu'ufa'atasia i se
tusi e tasi · Fa'atulagaina tulaga e tasi

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· Lagolago o le SDRAM otometi le ulufale ma alu ese e mafua mai i le leai o se taunuʻuga tau fefaʻatauaʻiga mo taimi faʻapipiʻi
· Lagolago o le otometi taofi uati (LPDDR2/3) ulufale ma alu ese e mafua ona o le leai o se taunuu mai fefaatauaiga
· Lagolagoina otometi fa'agaoioiga fa'aletonu e mafua mai i le leai o se taunu'u mai fefa'ataua'iga mo le taimi e mafai ona fa'apolokalameina e ala i meafaigaluega e maualalo le mana
· Faiga fa'akomepiuta e mafai ona fa'apolokalameina · Lagolago o le otometi po'o lalo ole polokalame fa'apolokalame le fa'afouina o le tagata lava ia ulufale ma alu i fafo · Lagolago o le loloto o le malosi-lalo ulufale ma alu ese i lalo o le fa'atonutonuina o polokalama (LPDDR2 ma
LPDDR3) · Lagolagoina o fa'afouga o le resitalaina o le SDRAM fa'apitoa i lalo o le fa'atonutonuina o polokalama fa'akomepiuta · Fa'atonu fetuutuuna'i fa'afanua fa'afanua e fa'ataga ai le fa'afanua fa'atatau o le laina, koluma,
pili faletupe · Filifiliga toe faʻaleleia e le tagata faʻaoga-filifiliga · poloka poloka DDRPERFM e fesoasoani mo le mataʻituina o le faatinoga ma le faʻalogo
E mafai ona faauigaina le DDRCTRL ma le DDRPHYC (i le ETZPC) e mafai ona maua e na'o polokalama malupuipuia.
O le DDRMCE (DDR memory cypher engine) vaega autu o loʻo lisiina i lalo: · AXI system bus master/slave interfaces (64-bit) · In-line encryption (mo tusitusiga) ma le decryption (mo faitau), faʻavae i luga o puipui puipui.
polokalame · Lua fa'ailoga fa'ailoga i le itulagi (maualuga tasi le itulagi): leai se fa'ailoga (faiga fa'afefe),
poloka le faiga o le cipher · Amata ma faaiʻuga o itulagi ua faʻamatalaina i le 64-Kbyte granularity · Faʻamalo faʻamama (itulagi 0): soʻo se avanoa e tuʻuina atu · Faʻasalaga avanoa a le Itulagi: leai se
Cipher poloka lagolago: AES Lagolago le faiga o filifili · Faiga poloka ma le AES cipher e fetaui ma le ECB mode ua faʻamaonia i le NIST FIPS faʻasalalauga 197 tulaga faʻailoga maualuga (AES), faʻatasi ai ma se galuega faʻavae autu e faʻavae i luga o le Keccak-400 algorithm lomia i luga o https://keckak.team webnofoaga. · Tasi seti o tusi-na'o tusi ma loka matai tusi resitala · AHB fetuutuunaiga uafu, fa'apitoa iloa

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3.4

TrustZone fa'atonu avanoa avanoa mo DDR (TZC)

O lo'o fa'aogaina le TZC e fa'amama ai avanoa faitau/tusi i le DDR controller e tusa ai ma aia tatau a TrustZone ma e tusa ai ma le matai e le-secure (NSAID) e o'o atu i le iva vaega e mafai ona fa'apolokalameina: · Fa'atonu e lagolagoina e na'o polokalama fa'atuatuaina · Tasi iunite fa'amama · E iva itulagi:
Itulagi 0 o lo'o fa'aagaina i taimi uma ma e aofia uma ai le tuatusi tuatusi. Itulagi 1 i le 8 o lo'o i ai polokalame fa'avae-/mu'u tuatusi ma e mafai ona tofia i
so'o se tasi po'o mea uma e lua. · Fa'atagaga saogalemu ma le le saogalemu ua fa'apolokalameina i itulagi ta'itasi · Avanoa e le malu puipuia e tusa ai ma le NSAID · Itulagi e pulea e le faamama e tasi e le tatau ona felavasa'i · Fa'aletonu faiga ma mea sese ma/po'o le fa'alavelave · Talia gafatia = 256 · Faitotoa leoleo manatu e mafai ai ma fa'amalo ai fa'amama ta'itasi · Avanoa fa'apitoa

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3.5

Fa'ailoga fa'a

I le amataga, o le punavai faʻaaogaina e le boot ROM e filifilia e le BOOT pine ma OTP bytes.

Laulau 2. Fa'avae fa'aa'e

BOOT2 BOOT1 BOOT0 Fa'avae amata

Fa'amatalaga

Faatali le feso'ota'iga ulufale mai ile:

UART ma le USB(1)

USART3/6 ma UART4/5/7/8 i pine faaletonu

Masini televave USB ile OTG_HS_DP/DM pine(2)

1 Serial NOR flash(3) Serial NOR moli ile QUADSPI(5)

e·MMC(3)

e·MMC i le SDMMC2 (fa'aletonu)(5)(6)

NAND flash(3)

SLC NAND emo ile FMC

Fa'auta fa'atupuina (leai se fa'afa'ailoga fa'amalama)

Fa'aaoga e maua ai le fa'aogaina o le debug e aunoa ma se ta'a mai le flash memory(4)

SD card(3)

SD card i luga ole SDMMC1 (fa'aletonu)(5)(6)

Faatali le feso'ota'iga ulufale mai ile:

0 UART ma le USB(1)(3) USART3/6 ma UART4/5/7/8 i pine ua faaletonu.

Masini televave USB ile OTG_HS_DP/DM pine(2)

1 Serial NAND flash(3) Serial NAND flash on QUADSPI(5)

1. E mafai ona fa'aletonu e ala ile OTP. 2. O le USB e mana'omia le HSE Clock/crystal (silasila i le AN5474 mo alaleo lagolagoina ma e aunoa ma se faatulagaga OTP). 3. E mafai ona suia le puna faʻaoso e ala ile OTP (mo faʻataʻitaʻigaample uluaʻi taʻavale i luga o le SD card, ona e·MMC faʻatasi ma faʻatulagaga OTP). 4. Cortex®-A7 i totonu o le matasele e le i'u o lo'o fesuia'i PA13. 5. E mafai ona suia pine masani e le OTP. 6. I le isi itu, o se isi fa'aoga SDMMC nai lo lenei faaletonu e mafai ona filifilia e le OTP.

E ui lava ina fai le seevae maualalo i le faʻaogaina o uati i totonu, ST na tuʻuina atu pusa polokalama faʻapea foʻi ma fesoʻotaʻiga tetele i fafo e pei ole DDR, USB (ae le gata i) e manaʻomia se tioata poʻo se oscillator fafo e faʻafesoʻotaʻi i pine HSE.
Va'ai RM0475 "STM32MP13xx advanced Arm®-based 32-bit MPUs" po'o AN5474 "Amataina ile STM32MP13xx laina fa'atupuina meafaigaluega" mo tapula'a ma fautuaga e uiga i le feso'ota'iga pine HSE ma laina lagolago.

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3.6

Pulea sapalai eletise

3.6.1
Lapata'iga:

Polokalama sapalai eletise
· VDD o le sapalai autu mo I / Os ma totonu o loʻo faʻaauau pea le malosi i le taimi o le Standby mode. Fa'aoga voltage 1.71 V i le 3.6 V (1.8 V, 2.5 V, 3.0 V po'o le 3.3 V typ.)
VDD_PLL ma VDD_ANA e tatau ona fa'afeso'ota'i fetu ile VDD. · VDDCPU o le Cortex-A7 CPU tuuto voltagu sapalai, o lona tau e faalagolago i le
mana'omia ole PPU fa'atele. 1.22 V i le 1.38 V ile fa'agasolo. E tatau ona iai le VDD i luma ole VDDCPU. · VDDCORE o le numera autu numera voltagu ma e masani ona tapunia i le taimi o le Standby mode. Voltago le laina ole 1.21 V i le 1.29 V ile ta'avale mode. E tatau ona iai le VDD i luma ole VDDCORE. · E mafai ona feso'ota'i le pine VBAT i le ma'a fafo (1.6 V <VBAT <3.6 V). Afai e leai se maa i fafo e faʻaaogaina, e tatau ona faʻafesoʻotaʻi lenei pine ile VDD. · VDDA o le analog (ADC/VREF), sapalai voltage (1.62 V i le 3.6 V). O le faʻaaogaina o le VREF + i totonu e manaʻomia ai le VDDA tutusa pe maualuga atu nai lo le VREF + + 0.3 V. · O le VDDA1V8_REG pine o le gaioiga lea a le faʻatonuga i totonu, fesoʻotaʻi totonu i le USB PHY ma le USB PLL. O le VDDA1V8_REG regulator i totonu e mafai e ala i le faaletonu ma e mafai ona pulea e polokalama. E tapuni i taimi uma i le taimi o le Standby mode.
Ole pine fa'apitoa ole BYPASS_REG1V8 e le tatau ona tu'u fa'afefe. E tatau ona faʻafesoʻotaʻi i le VSS poʻo le VDD e faʻagaoioia pe faʻamalo le voltage fa'atonu. A VDD = 1.8 V, BYPASS_REG1V8 e tatau ona seti. · VDDA1V1_REG pine o le gaioiga lea a le pule fa'alotoifale, feso'ota'i totonu ile USB PHY. O le VDDA1V1_REG regulator i totonu e mafai e ala i le faaletonu ma e mafai ona pulea e polokalama. E tapuni i taimi uma i le taimi o le Standby mode.
· VDD3V3_USBHS o le sapalai televave USB. Voltage 3.07 V i le 3.6 V.
VDD3V3_USBHS e le tatau ona i ai se'i vagana ua iai VDDA1V8_REG, a leai e ono tupu le fa'aleagaina tumau ile STM32MP133C/F. E tatau ona fa'amautinoa e ala i le fa'atonuga o le PMIC po'o le fa'atasi ai ma vaega i fafo pe a fa'apea o le fa'atinoina o le tu'uina atu o le paoa.
· VDDSD1 ma le VDDSD2 o lo'o fa'asolosolo SDMMC1 ma SDMMC2 SD card sapalai eletise e lagolago ai le ultra-high-speed mode.
· VDDQ_DDR o le DDR IO sapalai. 1.425 V i le 1.575 V mo feso'ota'iga DDR3 manatua (1.5 V typ.)
1.283 V i le 1.45 V mo feso'ota'iga DDR3L manatua (1.35 V typ.)
1.14 V i le 1.3 V mo feso'ota'iga LPDDR2 po'o LPDDR3 manatua (1.2 V typ.)
I le taimi o le faʻaleleia ma le paʻu i lalo, e tatau ona faʻaaloalogia manaʻoga faʻasologa o malosiaga nei:
· A oʻo i lalo le VDD i le 1 V, o isi sapalai eletise (VDDCORE, VDDCPU, VDDSD1, VDDSD2, VDDA, VDDA1V8_REG, VDDA1V1_REG, VDD3V3_USBHS, VDDQ_DDR) e tatau ona tumau i lalo ole VDD + 300 mV.
· A maualuga le VDD i le 1 V, e tuto'atasi uma sapalai eletise.
A'o fa'agasolo le eletise, e mafai ona fa'aitiitia le VDD nai lo isi sapalai pe'āfai e tumau pea le malosi e tu'uina atu i le STM32MP133C/F i lalo ole 1 mJ. Ole mea lea e mafai ai ona fa'ate'a fa'alava i fafo capacitors i taimi fa'asolo eseese ile taimi ole la'asaga le tumau le paoa.

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V 3.6
VBOR0 1

Ata 2. Fa'asologa o le malosi i luga/lalo

STM32MP133C/F

VDDX(1) VDD

3.6.2
Manatua: 26/219

0.3

Malosiaga

Faiga fa'agaioiga

Malosiaga-lalo

taimi

E le aoga le vaega o sapalai

VDDX <VDD + 300 mV

VDDX tutoatasi mai VDD

MSv47490V1

1. VDDX o lo'o fa'atatau i so'o se sapalai eletise i totonu o VDDCORE, VDDCPU, VDDSD1, VDDSD2, VDDA, VDDA1V8_REG, VDDA1V1_REG, VDD3V3_USBHS, VDDQ_DDR.

supavaisa sapalai eletise

O masini o lo'o i ai se feso'ota'iga tu'ufa'atasiga o le power-on (POR)/ power-down reset (PDR) fa'atasi ma le fa'asologa o le Brownout reset (BOR):
· Toe fa'aola le malosi (POR)
O le POR supavaisa e mata'ituina le VDD power supply ma fa'atusatusa i se tulaga fa'amautu. O masini e tumau i le toe setiina pe a oʻo i lalo le VDD i lalo o lenei faʻailoga, · Toe faʻaleleia le eletise (PDR)
E mata'ituina e le supavaisa le VDD le sapalai eletise. E faia se toe setiina pe a pa'ū le VDD i lalo o se tapulaa tumau.
· Toe setiina Brownout (BOR)
O le BOR supavaisa e mata'ituina le VDD sapalai eletise. Tolu BOR thresholds (mai 2.1 i le 2.7 V) e mafai ona configured e ala i filifiliga bytes. E faia se toe setiina pe a pa'ū le VDD i lalo o lenei tulaga.
· Toe fa'aola le VDDCORE (POR_VDDCORE) O le supavaisa o le POR_VDDCORE e mata'ituina le VDDCORE sapalai eletise ma fa'atusatusa i se tulaga fa'amautu. O le VDDCORE domain e tumau pea i le toe setiina pe a o'o i lalo VDDCORE i lalo o lenei tulaga.
· Toe fa'aleleia le eletise VDDCORE (PDR_VDDCORE) O le supavaisa o le PDR_VDDCORE e mata'ituina le sapalai eletise VDDCORE. Ole VDDCORE toe setiina ole vaega e fa'atupuina pe a pa'ū VDDCORE i lalo ole tulaga fa'amautu.
· VDDCPU (POR_VDDCPU) O le supavaisa o le POR_VDDCPU e mata'ituina le sapalai eletise VDDCPU ma fa'atusatusa i se tulaga fa'amautu. O le VDDCPU domain e tumau i le toe setiina pe a VDDCORE o loʻo i lalo ifo o lenei tulaga.
Ole pine PDR_ON e fa'aagaga mo su'ega gaosiga STMicroelectronics ma e tatau ona feso'ota'i i taimi uma ile VDD ile talosaga.

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3.7

Fuafuaga maualalo-malosi

E tele auala e fa'aitiitia ai le fa'aogaina o le paoa ile STM32MP133C/F: · Fa'aitiitia le fa'aogaina o le malosi e ala ile fa'agesegese ole uati ole CPU ma/po'o le
uati matrix ma/po'o le pulea o uati pito i tua ta'itasi. · Faasaoina le faʻaogaina o le eletise pe a IDLE le PPU, e ala i le filifilia i totonu o avanoa maualalo-
mana modes e tusa ai ma manaoga o le tagata e faaaogāina talosaga. Ole mea lea e mafai ai ona maua le fetuutuunaiga sili ile va ole taimi amata, maualalo le malosi, faʻapea foʻi ma punaoa fafagu avanoa, e ausia. · Fa'aaoga le DVFS (dynamic voltagu ma fa'asolo fa'asolo) fa'agaoioi vaega e fa'atonutonu sa'o le taimi ole uati ole PPU fa'apea fo'i ma le VDDCPU sapalai.
O faiga fa'aoga e mafai ai ona pulea le tufatufaina o le uati i vaega eseese o le polokalama ma le malosi o le faiga. O le faiga fa'aogaina o lo'o fa'atautaia e le MPU sub-system.
O le MPU sub-system low-power modes o loʻo lisi atu i lalo: · CSleep: Ua taofi le uati o le PPU ma o loʻo galue le uati pito i luga.
na seti muamua i le RCC (toe setiina ma le uati pule). · CStop: Ua taofi le uati pito i luga ole CPU. · CSstandby: VDDCPU OFF
Ole CSleep ma le CStop low-power modes e fa'aulu e le PPU pe a fa'atino le WFI (fa'atali mo le fa'alavelave) po'o le WFE (fa'atali mo mea na tupu).
O faiga fa'aogaina o lo'o maua e pei ona ta'ua i lalo: · Ta'avale (fa'atonu i lona fa'atinoga atoatoa, VDDCORE, VDDCPU ma uati ON) · Taofi (Uati OFF) · LP-Taofi (OFF OFF) · LPLV-Stop (uati OFF, VDDCORE ma VDDCPU tulaga tu'uina atu e mafai ona tu'u i lalo) · LPLV-Stop OFF2, VDDCPU tu'u lalo) (VDDCPU, VDDCORE, ma uati OFF)

Fuafuaga 3. Faiga fa'asaga i le fa'aogaina o le CPU

Faiga malosi faiga

PPU

Faiga tamo'e

CRun poʻo le CSleep

Taofi ala LP-Stop mode LPLV-Stop mode LPLV-Stop2 mode
Faiga tūtū

CStop poʻo CStandby CStandby

3.8

Toe seti ma pulea le uati (RCC)

O le uati ma le toe setiina pule e pulea le gaosiga o uati uma, faapea foi ma le uati gating, ma le pulea o le faiga ma peripheral resets.RCC e maua ai se fetuutuunai maualuga i le filifiliga o punaoa uati ma faatagaina le faaaogaina o fua faatatau o le uati e faaleleia ai le faaaogaina o le eletise. E le gata i lea, i luga o nisi o fesoʻotaʻiga peripherals e mafai ona galulue faatasi

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3.8.1 3.8.2

lua vaega ole uati eseese (pe o se bus interface clock po o se kernel peripheral clock), e mafai ona suia le faiga masani e aunoa ma le suia o le baudrate.
Puleaina o le uati
O masini e fa'apipi'i fa'aoso i totonu, lua oscillator ma tioata fafo po'o resonator, tolu oscillators i totonu ma le taimi vave amata ma le fa PLLs.
E maua e le RCC mea e maua mai ai uati nei: · Oscillators i totonu:
64 MHz HSI uati (1 % sa'o) 4 MHz CSI uati 32 kHz LSI uati · Oscillators fafo: 8-48 MHz HSE uati 32.768 kHz LSE uati
O le RCC o lo'o tu'uina atu ai PLL e fa: · PLL1 fa'apitoa mo le fa'ailoga CPU · PLL2 tu'uina atu:
uati mo le AXI-SS (e aofia ai APB4, APB5, AHB5 ma AHB6 alalaupapa) uati mo le DDR interface · PLL3 saunia: uati mo le tele-Layer AHB ma peripheral pasi matrix (e aofia ai le APB1,
APB2, APB3, APB6, AHB1, AHB2, ma AHB4) uati fatu mo peripherals · PLL4 fa'apitoa mo le fa'atupuina o uati fatu mo peripherals eseese
E amata le faiga ile uati HSI. E mafai e le tagata fa'aoga ona filifili le fa'atulagaina o le uati.
Punaoa toe setiina faiga
O le toe setiina o le malosi e amata ai resitala uma sei vagana ai le debug, o se vaega o le RCC, o se vaega o le RTC ma le pule o le eletise e resitalaina tulaga, faʻapea foʻi ma le Backup power domain.
O le toe setiina o talosaga e maua mai i se tasi o punaoa nei: · toe setiina mai le NRST pad · toe setiina mai le POR ma le PDR faailo (e masani ona taʻua o le power-on reset) · se toe setiina mai le BOR (e masani ona taʻua brownout) · toe setiina mai le leoleo tutoatasi 1 · toe setiina mai le leoleo tutoatasi 2 · o se polokalama faakomepiuta toe setiina mai le Cortex-A7 le tulaga (i luga o le C HPUSE-AXNUMX) le tulaga (i luga ole C HPUSE) fa'agaoioia
O le toe setiina o le faiga e maua mai i se tasi o punaoa nei: · se toe setiina o talosaga · toe setiina mai le faailo POR_VDDCORE · se alu ese mai le Standby mode i le Run mode

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O le toe setiina o le MPU processor e gaosia mai se tasi o punaoa nei: · toe setiina faiga · taimi uma e alu ese ai le MPU i le Cstandby · se seti MPU polokalama mai le Cortex-A7 (CPU)

3.9

Fa'atotonuga-lautele fa'aulufalega (GPIOs)

O pine GPIO ta'itasi e mafai ona fa'atulagaina e ala i polokalama fa'akomepiuta (push-pull po'o tatala-vai, fa'atasi pe leai foi se toso i luga po'o toso i lalo), e fai ma fa'aoga (fa'atasi pe leai se toso i luga po'o le toso i lalo) po'o le fa'aogaina o galuega. Ole tele ole pine GPIO o lo'o fa'asoa ile numera po'o le analog isi galuega. O GPIO uma e maualuga i le taimi nei ma e iai saosaoa filifiliga e pulea lelei ai le pisa i totonu, faʻaogaina o le eletise ma le eletise eletise.
A uma ona toe setiina, o GPIO uma o loʻo i le analog mode e faʻaitiitia ai le faʻaaogaina o le eletise.
E mafai ona loka le fa'atulagaga I/O pe a mana'omia e ala i le mulimulita'i i se fa'asologa fa'apitoa ina ia 'alofia ai le tusitusi pepelo i tusi resitala I/Os.
O pine GPIO uma e mafai ona setiina ta'ito'atasi e malupuipuia, o lona uiga o lo'o fa'aogaina le polokalama i nei GPIOs ma fa'aoga feso'ota'iga e fa'amatalaina o le saogalemu e fa'atapula'aina e fa'amautu polokalama fa'aoga ile PPU.

3.10
Fa'aaliga:

Pule ole puipuiga ole TrustZone (ETZPC)
O lo'o fa'aogaina le ETZPC e fa'atulaga ai le saogalemu o le TrustZone o matai pasi ma pologa fa'atasi ai ma uiga fa'apolokalame-saogalemu (securable resources). Mo se fa'ata'ita'iga: · E mafai ona fa'apolokalameina le tele o le itulagi saogalemu i luga ole masini SYSRAM. · AHB ma APB peripherals e mafai ona malupuipuia pe leai foi. · AHB SRAM e mafai ona malupuipuia pe leai foi.
Ona o le faaletonu, SYSRAM, AHB SRAMs ma securable peripherals ua setiina e faʻamautu avanoa, o lea, e le mafai ona maua e matai le saogalemu e pei ole DMA1/DMA2.

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STM32MP133C/F

3.11

Matrix feso'ota'i pasi
O masini e faʻaalia ai le AXI matrix matrix, tasi le AHB pasi matrix ma alalaupapa pasi e mafai ai ona fesoʻotaʻi matai pasi ma pologa pasi (silasila i le ata o loʻo i lalo, o togitogi e faʻatusalia ai fesoʻotaʻiga matai/pologa mafai).
Ata 3. STM32MP133C/F pasi matrix

MDMA

SDMMC2

SDMMC1

DBG Mai MLAHB feso'ota'i USBH

PPU

ETH1 ETH2

128-bit

AXIM

M1 M2

M11

S1 S2 S3 S4 S5 S6 S7 S8 S9

pologa fa'aletonu AXIMC

NIC-400 AXI 64 bits 266 MHz – 10 matai / 10 pologa

Mai AXIM feso'ota'i DMA1 DMA2 USBO DMA3

M1 M2

M3 M4

M6 M7

S4 S5 Feso'ota'i AHB 32 bits 209 MHz – 8 matai / 6 pologa

DDRCTRL 533 MHz AHB alalaupapa i AHB6 I MLAHB feso'ota'i FMC/NAND QUADSPI SYSRAM 128 KB ROM 128 KB AHB alalaupapa i AHB5 APB alalaupapa i APB5 APB alalaupapa i DBG APB
AXI 64 uafu matai soofaatasi AXI 64 uafu pologa synchronous AXI 64 uafu matai asynchronous AXI 64 uafu pologa asynchronous AHB 32 uafu matai soofaatasi AHB 32 uafu pologa synchronous AHB 32 uafu pologa asynchronous AHB 32 uafu pologa asynchronous
Alalaupapa i AHB2 SRAM1 SRAM2 SRAM3 I AXIM feso'ota'i Alalaupapa i AHB4
MSv67511V2

MLAHB

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3.12

fa'atonu DMA
O masini o lo'o fa'aalia ai le DMA modules e la'u ai le fa'agaioiga o le PPU: · o se master direct memory access (MDMA)
O le MDMA o se fa'atonu DMA maualuga, o lo'o nafa ma ituaiga uma o fa'aliliuga fa'amanatu ( peripheral-to-memory, memory-to-memory, memory-to-peripheral), e aunoa ma se gaioiga CPU. O loʻo faʻaalia ai se matai matai AXI. E mafai e le MDMA ona fa'afeso'ota'i ma isi fa'atonu DMA e fa'alautele le agava'a DMA, pe mafai fo'i ona fa'atautaia sa'o talosaga DMA. O auala taʻitasi e 32 e mafai ona faʻafeiloaʻi poloka poloka, faʻafeiloaʻi faʻasolosolo poloka ma fesoʻotaʻiga lisi fesoʻotaʻiga. E mafai ona setiina le MDMA e faia ni fa'aliliuga saogalemu i manatuaga malupuipuia. · tolu fa'atonu DMA (e le fa'amautu le DMA1 ma le DMA2, fa'atasi ai ma le DMA3 fa'amautu) E tofu le ta'ita'i ma le lua-taulaga AHB, mo le aofa'iga o le 16 e le fa'amautu ma le valu fa'amautu auala DMA e fa'atino ai le fa'aliliuina o poloka poloka a le FIFO.
E lua DMAMUX iunite multiplex ma faʻaogaina le DMA peripheral talosaga i le tolu DMA controllers, faʻatasi ai ma le maualuga o le fetuutuunai, faʻateleina le numera o talosaga DMA o loʻo faʻasolosolo faʻatasi, faʻapea foʻi ma le faʻatupuina o talosaga DMA mai faʻalavelave faʻapitoa poʻo mea DMA.
DMAMUX1 fa'afanua talosaga a le DMA mai fa'aoga e le malu puipuia ile DMA1 ma DMA2 alalaupapa. DMAMUX2 fa'afanua talosaga DMA mai fa'aoga fa'amautu i ala DMA3.

3.13

Fa'alavelave fa'alautele ma fa'atonu mea e tutupu (EXTI)
O le extended interrupt and event controller (EXTI) e fa'afoeina le PPU ma le fafagu o faiga e ala i mea e mafai ona fa'aogaina ma tuusa'o. E tuʻuina atu e le EXTI talosaga fafagu i le pule o le eletise, ma faʻatupuina se talosaga faʻalavelave i le GIC, ma mea e tutupu i le faʻaogaina o le CPU.
O talosaga fafagu a le EXTI e mafai ai ona fafagu le faiga mai le Stop mode, ma le CPU e fafagu mai CStop ma CStandby modes.
Ole talosaga fa'alavelave ma le fa'atupuina ole talosaga e mafai fo'i ona fa'aoga ile faiga Run.
O le EXTI e aofia ai foi le EXTI IOport filifiliga.
O fa'alavelave ta'itasi po'o mea e tutupu e mafai ona fa'amautu ina ia fa'atapula'aina le avanoa i na'o polokalama fa'akomepiuta.

3.14

Vaega o su'esu'ega fa'ata'amilomilo (CRC)
O le CRC (cyclic redundancy check) e fa'aaogaina e maua ai se fa'ailoga CRC e fa'aoga ai le polynomial e mafai ona fa'apolokalameina.
Faatasi ai ma isi talosaga, o auala faʻavae CRC e faʻaaogaina e faʻamaonia ai le tuʻuina atu o faʻamatalaga poʻo le teuina o le faamaoni. I le lautele o le EN / IEC 60335-1 faʻataʻitaʻiga, latou te ofoina atu se auala e faʻamaonia ai le faʻamaoni o le mafaufau. Ole vaega ole fa'atatau ole CRC e fesoasoani ile fa'atulagaina o se saini ole polokalame ile taimi ole taimi, e fa'atusaina ma se saini fa'asino na faia ile taimi-so'otaga ma teu i se nofoaga e manatua ai.

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3.15

Fa'atonu fa'atonuga manatua (FMC)
Ole vaega autu ole fa'atonu a le FMC o mea nei: · Fa'afeso'ota'i ma masini fa'afanua fa'amaufa'ailoga e aofia ai:
NOR flash memory Static po'o pseudo-static random access memory (SRAM, PSRAM) NAND flash memory with 4-bit/8-bit BCH hardware ECC · 8-,16-bit data bus width · Tuto'atasi chip-filifilia pulea mo faletupe manatua taitasi · Tuto'atasi faatulagaga mo faletupe manatua taitasi · Tusi FIFO
E mafai ona fa'amautu le resitalaina o le FMC.

3.16

Lua Quad-SPI fa'aoga manatua (QUADSPI)
O le QUADSPI ose feso'ota'iga fa'apitoa feso'ota'iga e fa'atatau i manatuaga moli ta'ito'atasi, lua po'o le quad SPI. E mafai ona fa'agaoioia i so'o se auala e tolu o lo'o mulimuli mai: · Fa'asinomaga Fa'atonu: o fa'agaioiga uma o lo'o fa'atinoina e fa'aaoga ai tusi resitala QUADSPI. · Tulaga-faiga palota: o le tusi resitala tulaga manatua flash fafo e faitau ma
e mafai ona fa'atupu se fa'alavelave pe a fa'atulaga le fu'a. · Fa'asologa o mea e manatua ai: o lo'o fa'afanua le mea e manatua ai le flash i le avanoa o le tuatusi
ma e va'aia e le faiga e pei o se manatua i totonu.
E mafai ona fa'aopoopoina fa'alua fa'alua le fa'aogaina ma le gafatia e fa'aaoga ai le lua-flash mode, lea e lua Quad-SPI flash manatua e maua i le taimi e tasi.
QUADSPI o loʻo tuʻufaʻatasia ma se poloka tuai (DLYBQS) faʻatagaina le lagolago o faʻamatalaga faʻamatalaga fafo i luga ole 100 MHz.
E mafai ona malupuipuia le resitalaina o le QUADSPI, faʻapea foʻi ma lona poloka tuai.

3.17

Fa'aliliuga fa'atusa-i-numera (ADC1, ADC2)
O masini e faʻapipiʻi lua analog-to-digital converters, o la latou iugafono e mafai ona faʻatulagaina i le 12-, 10-, 8- poʻo le 6-bit. O ADC taʻitasi e faʻasoa i luga ole 18 auala fafo, faʻaalia suiga i le ata e tasi pe faʻataʻitaʻi. I le faʻataʻitaʻiga faʻataʻitaʻiga, o le liua otometi e faia i luga o se vaega filifilia o mea faʻaoga analog.
O ADC uma e lua o lo'o i ai feso'ota'iga pasi fa'amautu.
O ADC ta'itasi e mafai ona tu'uina atu e le DMA pule, ma fa'ataga ai le fa'aliliuina otometi o tau fa'aliliuina ADC i se nofoaga e alu i ai e aunoa ma se gaioiga fa'apolokalame.
E le gata i lea, o se analog watchdog feature e mafai ona mataʻituina saʻo le vol liliutage tasi, nisi po'o ala uma ua filifilia. E fa'atupuina se fa'alavelave pe a liliu le voltagu i fafo atu o tulaga fa'apolokalame.
Ina ia fa'amaopoopoina le suiga o le A/D ma taimi, e mafai ona fa'aosoina ADC e so'o se TIM1, TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, LPTIM1, LPTIM2 ma LPTIM3 timers.

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3.18

Su'e vevela
O masini e fa'apipi'i ai se masini vevela e maua ai le voltage (VTS) e fesuisuia'i laina ma le vevela. O lenei masini vevela e fesoʻotaʻi i totonu i le ADC2_INP12 ma e mafai ona fuaina le vevela o le masini mai le 40 i le +125 °C ma le saʻo o le ±2%.
O le masini vevela o loʻo i ai se laina lelei, ae e tatau ona faʻavasegaina ina ia maua ai se sao atoatoa lelei o le fuaina o le vevela. A'o fesuia'i le fa'a'avevela o le vevela e ese'ese mai lea pu'upu'u i lea va'a ona o suiga fa'agaioiga, e talafeagai le fa'aogaina o le vevela i totonu e le'i fa'avasegaina mo talosaga e na'o suiga o le vevela. Ina ia faʻaleleia le saʻo o le fuaina o le vevela, o masini taʻitasi e faʻapipiʻiina taʻitasi e ST. O fa'amaumauga fa'avasegaina o fale gaosi vevela e teu e ST i le vaega o le OTP, lea e mafai ona maua i le na'o le faitau.

3.19

Fa'amatalaga o le vevela fa'anumera (DTS)
O masini e fa'apipi'i ai le fa'aoso fa'aoso fa'aoso le vevela. E faitau e le DTS le taimi e fa'atatau i le LSE po'o le PCLK e tu'uina atu ai fa'amatalaga o le vevela.
O lo'o lagolagoina galuega nei: · fa'alavelave fa'atupuina e ala i le maualuga o le vevela · fa'atupu fa'ailoga fafagu e ala i le maualuga o le vevela.

3.20
Fa'aaliga:

VBAT galuega
O le VBAT power domain o lo'o i ai le RTC, tusi resitala fa'amaumauga ma le SRAM fa'asao.
Ina ia faʻamalieina le umi o le maʻa, o lenei vaega o le malosiaga e tuʻuina atu e le VDD pe a maua poʻo le voltage fa'aoga ile VBAT pine (pe a le maua le VDD sapalai). E sui le mana VBAT pe a iloa e le PDR ua pa'ū le VDD i lalo ole tulaga PDR.
Le voltage i luga o le VBAT pine e mafai ona saunia e se maa fafo, se supercapacitor pe tuusao e VDD. I le tulaga mulimuli ane, e le aoga le VBAT mode.
E fa'agaoioia le VBAT pe a le o iai le VDD.
E leai se tasi o nei mea na tutupu (faalavelave i fafo, TAMP mea na tupu, poʻo le RTC alarm / mea tutupu) e mafai ona toe faʻafoʻi saʻo le VDD sapalai ma faʻamalosi le masini mai le gaioiga VBAT. Ae ui i lea, TAMP mea tutupu ma RTC alarm/mea tutupu e mafai ona faʻaaogaina e faʻatupu ai se faʻailoga i se vaʻaiga fafo (e masani lava o le PMIC) e mafai ona toe faʻaleleia le VDD sapalai.

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3.21

Voltage fa'amaufa'ailoga fa'amau (VREFBUF)
O masini fa'apipi'i se voltage fa'amaufa'ailoga pa'u e mafai ona fa'aaogaina e pei o voltagu fa'amatalaga mo le ADCs, fa'apea fo'i ma voltage fa'asinoga mo vaega i fafo e ala i le VREF+ pine. VREFBUF e mafai ona malupuipuia. O le VREFBUF i totonu e lagolagoina le fa voltage: · 1.65 V · 1.8 V · 2.048 V · 2.5 V Ole voli fafotage mafai ona tu'uina atu fa'amatalaga e ala i le VREF+ pine pe a pe le VREFBUF totonu.
Ata 4. Voltagu fa'asinoga pa'u

VREFINT

–

VREF+

VSSA

MSv64430V1

3.22

Filifiliga numera mo sigma-delta modulator (DFSDM)
O masini e fa'apipi'i ai le tasi DFSDM fa'atasi ai ma le lagolago mo masini fa'atekinolosi e lua ma laina fa'aulu fa'aulu (transceivers) po'o isi fa'aoga tutusa i totonu.
O le DFSDM faʻafesoʻotaʻi faʻasalalauga fafo i le masini ma faʻatino le faʻaogaina o numera o faʻamaumauga o faʻamaumauga. fa'aoga fa'aogaina e fa'aliliu ai fa'ailo fa'atusa i ala fa'afuainumera-fa'asologa o lo'o fa'auluina ai mea fa'aoga a le DFSDM.
E mafai foi e le DFSDM ona faʻafesoʻotaʻi le PDM (pulse-density modulation) microphones ma faʻatino le PDM i le PCM liua ma le faʻamama (faʻavaveina meafaigaluega). O le DFSDM o lo'o fa'aalia ai fa'amatalaga fa'atusa fa'atasi mai le ADC po'o le manatua o le masini (e ala i le DMA/CPU fa'aliliu i le DFSDM).
E lagolagoina e le DFSDM transceivers le tele o fa'asologa o feso'ota'iga (e lagolago ai modulators eseese). DFSDM fa'akomepiuta faamama modules fa'atino fa'agaioiga fa'akomepiuta e tusa ai ma fa'amaufa'ailoga fa'amanino fa'aoga e o'o atu ile 24-bit fa'ai'uga a le ADC.

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Le DFSDM peripheral lagolago: · Fa multiplexed input numera laina laina laina:
fa'afeso'ota'i fa'aoga SPI e fa'afeso'ota'i le tele o modulators e mafai ona fa'aogaina Manchester coded 1-wire interface PDM (pulse-density modulation) fa'aoga masini faaleotele leo le maualuga o le fa'aogaina o le taimi e o'o atu ai i le 20 MHz (10 MHz mo Manchester coding) fa'asologa o le uati mo modulators (0 i le 20 MHz) · Isi mea fa'aoga mai fa'amatalaga fa'akomepiuta fa'atasi fa'amaumauga (e o'o i le 16 fa'amaumauga fa'akomepiuta fa'alotoifale i totonu o le ADC1) (DMA) · E lua masini fa'afuainumera fa'akomepiuta fa'atasi ai ma fetu'una'iga fa'ailoga fa'ailoga numera: Sincx fa'amama: fa'atonuga fa'amama/ituaiga (5 i le XNUMX), ova.ampling ratio (1 i le 1024) integrator: ovaampling ratio (1 i le 256) · E oo atu i le 24-bit output data resolution, saini faʻasologa o faʻamaumauga o faʻamaumauga · Faʻasaʻo faʻamaumauga otometi (offset teuina i le resitara e le tagata faʻaoga) · Faʻaauau pe tasi le liua · Amata-o-faʻaliliuina faʻaosoina e: software faʻaoso i totonu timers mea i fafo amata-o-faaliliuina synchronously ma le uluai numera faamama faʻamaumauga (DFSdoge faʻatusa) ma le tau maualuga: Analog-o le faʻatauga maualuga resitala fa'apitoa Sincx fa'amama numera (poloka = 1 i le 3,
ovaampling ratio = 1 i le 32) fa'aulu mai fa'amaumauga fa'ai'u po'o mai fa'aulu filifilia ala fa'afuainumera fa'aauau mata'ituina tuto'atasi mai le fa'aliliuga masani · Pu'upu'u va'ava'ai e iloa ai tau fa'aoga analog tumu (lalo ma le pito i luga): e o'o atu i le 8-bit fa'atau e iloa ai le 1 i le 256 soso'o 0's po'o le 1's i luga o fa'amaumauga fa'asologa mata'ituina fa'aauauina ta'itasi fa'aulu i luga o le fa'asologa fa'asologa o mea tutupu - Breakdog mea na tutupu fa'afuase'i va'aiga va'aiga fa'ailo fa'asolo fa'asolo mea tutupu - Breakdog mea e tutupu i luga o le laina fa'asolo fa'ata Extremes detector: teuina o tau maualalo ma le maualuga o faʻamatalaga liua mulimuli toe faʻafouina e le polokalama · DMA gafatia e faitau le faʻamatalaga mulimuli o le liua · Faʻalavelave: faʻaiʻuga o le liua, faʻafefe, analog watchdog, puʻupuʻu vaʻavaʻa, faʻaoga laina laina uati toesea · "Regular" or "injected" liua: "masani" liua e mafai ona talosagaina i soo se taimi pe oʻo lava i le faʻaauau faiga
e aunoa ma le i ai o se aafiaga i le taimi o le "tuiina" liua "tuiina" liua mo le taimi tonu ma le maualuga o le liliuga faamuamua

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3.23

Fa'atupu numera fa'afuase'i moni (RNG)
O masini e faʻapipiʻi ai le tasi RNG e tuʻuina atu numera faʻafuaseʻi 32-bit na gaosia e se fesoʻotaʻiga analog tuʻufaʻatasia.
O le RNG e mafai ona faauigaina (i le ETZPC) e mafai ona maua e na'o polokalama malupuipuia.
O le RNG moni e feso'ota'i i fa'amaufa'ailoga AES ma PKA e ala i se pasi fa'apitoa (e le mafai ona faitau e le PPU).

3.24

Cryptographic ma hash processors (CRYP, SAES, PKA ma HASH)
O masini e fa'apipi'i ai se tasi faiga fa'ata'ita'i e lagolago ai fa'ata'ita'i fa'ata'ita'i algorithms e masani ona mana'omia e fa'amautinoa ai le agatapuia, fa'amaoni, fa'amaoni fa'amaumauga ma le le fa'afitia pe a felafoa'i fe'au ma se aumea.
O lo'o fa'apipi'i fo'i i masini se fa'amautu fa'amautu fa'amautu AES 128- ma le 256-bit key (SAES) ma le fa'auiga fa'auiga/decryption accelerator meafaigaluega a le PKA, fa'atasi ai ma pasi fa'apitoa e le mafai ona maua e le PPU.
CRYP vaega autu: · DES/TDES (fa'amatalaga fa'amatalaga tulaga/fa'ailoga fa'ailoga fa'ailoga tolu): ECB (eletise
codebook) ma le CBC (cipher block chaining) chaining algorithms, 64-, 128- po o le 192-bit key · AES (advanced encryption standard): ECB, CBC, GCM, CCM, ma le CTR (counter mode) filifili algorithms, 128-, 192- po o le 256-bit key
Universal HASH vaega autu: · SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-3 (secure HASH algorithms) · HMAC
E lagolagoina e le fa'avavevave fa'amatalaga DMA le fa'atupuina ole talosaga.
CRYP, SAES, PKA ma HASH e mafai ona faauigaina (i le ETZPC) e mafai ona maua e na'o polokalama malupuipuia.

3.25

Fa'asagaga ma le saogalemu ma le fa'atonuina o le OTP (BSEC)
O le BSEC (boot and security and OTP control) o loʻo faʻamoemoe e pulea se pusa fuse OTP (tasi-taimi e mafai ona faʻaogaina), faʻaaogaina mo le faʻapipiʻiina o mea e le faʻafefeteina mo le faʻatulagaina o masini ma le saogalemu. O nisi vaega o le BSEC e tatau ona fa'atulaga e mafai ona maua e na'o polokalama faakomepiuta.
E mafai e le BSEC ona fa'aoga upu OTP mo le teuina o le HWKEY 256-bit mo le SAES (secure AES).

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3.26

Taimi ma leoleo
O masini e aofia ai taimi e lua e pulea ai le tele o taimi, e sefulu taimi fa'amoemoe lautele (e fitu o lo'o fa'amautu), lua taimi fa'avae, lima taimi maualalo, lua leoleoga, ma fa'atonu fa'atonu i Cortex-A7 ta'itasi.
E mafai ona fa'aisa uma fa'asologa o le taimi i le faiga fa'a-debug.
O le laulau o lo'o i lalo o lo'o fa'atusatusaina ai foliga o le fa'atonu-sili atu, fa'amoemoe lautele, fa'avae ma le maualalo o le malosi.

Ituaiga taimi

Taimi

Laulau 4. Fa'atusatusaga fa'atusa o le taimi

tali i'uga-
tion

Ituaiga counter

Prescaler factor

DMA talosaga fa'atupuina

Pu'e/fa'atusatusa auala

Galuega fa'aopoopo

Max fa'aoga
uati (MHz)

Max
taimi
uati (MHz)(1)

TIM1 maualuga, -pulea TIM8

16-bit

Luga, So'o se numera i lalo, i le va o le 1 luga/lalo ma le 65536

Ioe

TIM2 TIM5

32-bit

Luga, So'o se numera i lalo, i le va o le 1 luga/lalo ma le 65536

Ioe

TIM3 TIM4

16-bit

Luga, So'o se numera i lalo, i le va o le 1 luga/lalo ma le 65536

Ioe

Soo se numera atoa

TIM12(2) 16-bit

I le va o le 1

Leai

lautele

ma le 65536

faamoemoe

TIM13(2) TIM14(2)

16-bit

So'o se numera Tu'u i le va o le 1
ma le 65536

Leai

Soo se numera atoa

TIM15(2) 16-bit

I le va o le 1

Ioe

ma le 65536

TIM16(2) TIM17(2)

16-bit

So'o se numera Tu'u i le va o le 1
ma le 65536

Ioe

Fa'avae

TIM6, TIM7

16-bit

So'o se numera Tu'u i le va o le 1
ma le 65536

Ioe

LPTIM1,

Malosi maualalo

LPTIM2(2), LPTIM3(2),
LPTIM4,

16-bit

1, 2, 4, 8, Up 16, 32, 64,
128

Leai

LPTIM5

104.5

209

Leai

104.5

209

Leai

104.5

209

Leai

104.5

209

Leai

104.5

209

104.5

209

104.5

209

Leai

104.5

209

1(3)

Leai

104.5 104.5

1. O le taimi maualuga uati e oo atu i le 209 MHz e faalagolago i le TIMGxPRE bit i le RCC. 2. Taimi saogalemu. 3. Leai se auala pu'e ile LPTIM.

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3.26.1 3.26.2 3.26.3

Taimi fa'atonuga maualuga (TIM1, TIM8)
O taimi fa'atonutonu maualuga (TIM1, TIM8) e mafai ona va'aia e tolu-vaega PWM generators fa'atele i luga ole 6 alalaupapa. E iai a latou galuega faatino a le PWM fa'atasi ai ma polokalame fa'aofi taimi mate. E mafai fo'i ona fa'atatauina o fa'amaumauga atoa mo fa'amoemoega lautele. E mafai ona fa'aoga a latou auala tuto'atasi e fa mo: · pu'eina fa'aoga · fa'atusatusaga o galuega fa'atino · fa'atupuina o le PWM (tulaga-po'o le fa'aoga ogatotonu)
Afai e fa'atulagaina e pei o taimi masani 16-bit, e tutusa lava foliga ma taimi fa'amoemoe lautele. Afai e faʻapipiʻiina e pei o 16-bit PWM generators, latou te maua atoatoa le gafatia (0-100%).
E mafai ona galulue fa'atasi le taimi fa'atonutonu fa'atasi ma taimi fa'amoemoe lautele e ala i le feso'ota'iga taimi mo le fa'amaopoopo po'o le filifiliina o mea e tutupu.
TIM1 ma le TIM8 lagolago tuto'atasi ole DMA ole fa'atupuina ole talosaga.
Taimi fa'amoemoe lautele (TIM2, TIM3, TIM4, TIM5, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17)
E sefulu taimi fa'akomepiuta fa'atatau lautele o lo'o fa'apipi'iina i masini STM32MP133C/F (silasila i le Laulau 4 mo eseesega). · TIM2, TIM3, TIM4, TIM5
TIM 2 ma le TIM5 e fa'avae ile 32-bit auto-reload up/down counter ma le 16-bit prescaler, ae TIM3 ma TIM4 e fa'avae ile 16-bit auto-reload up/downcounter ma le 16-bit prescaler. O taimi uma e fa'aalia ai ala tuto'atasi se fa mo le fa'aogaina o le pu'eina/fa'atusatusaga o mea, PWM po'o le tasi-pulse mode output. E tu'uina atu i le 16 fa'aoga pu'e/fa'atusa fa'atusa/PWM i luga ole afifi tele. E mafai ona galulue fa'atasi nei taimi fa'amoemoe lautele, pe fa'atasi ma isi taimi fa'amoemoe lautele ma taimi fa'atonu TIM1 ma le TIM8, e ala i le feso'ota'iga taimi mo le fa'amaopoopo po'o le filifiliina o mea e tutupu. E mafai ona fa'aoga so'o se tasi o nei taimi fa'apitoa e fa'atupu ai galuega a le PWM. TIM2, TIM3, TIM4, TIM5 o lo'o iai uma le fa'atupuina o talosaga DMA. E mafai ona latou fa'atautaia fa'ailoga fa'ailoga (fa'aopoopo) encoder fa'ailoga ma mea fa'atekinolosi mai le tasi i le fa fa'afiafiaga fa'afiafiaga. · TIM12, TIM13, TIM14, TIM15, TIM16, TIM17 O nei taimi e fa'avae i luga o le 16-bit auto-reload upcounter ma le 16-bit prescaler. O le TIM13, TIM14, TIM16 ma le TIM17 o loʻo faʻaalia ai le ala tutoʻatasi e tasi, ae o le TIM12 ma le TIM15 e lua auala tutoʻatasi mo le faʻaogaina o le puʻeina / faʻatusatusaga, PWM poʻo le tasi-pulse mode output. E mafai ona fa'amaopoopoina fa'atasi ma le TIM2, TIM3, TIM4, TIM5 fa'ata'ita'iga atoa taimi fa'amoemoe lautele pe fa'aaoga e fai ma fa'amaumauga faigofie. O nei taimi ta'itasi e mafai ona fa'amalamalamaina (i le ETZPC) e mafai ona maua e na'o polokalama fa'akomepiuta.
Taimi autu (TIM6 ma le TIM7)
O nei taimi e masani ona faʻaaogaina e avea o se 16-bit time base.
TIM6 ma le TIM7 lagolago tuto'atasi ole DMA ole fa'atupuina ole talosaga.

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Faʻaaoga lugaview

3.26.4
3.26.5 3.26.6

Taimi e maualalo le malosi (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5)
E iai le uati tuto'atasi ta'itasi e maualalo le malosi ma e fa'agasolo fo'i ile faiga Taofi pe a fa'amauina e le LSE, LSI po'o se uati fafo. E mafai e le LPTIMx ona fafagu le masini mai le Stop mode.
O nei timers e maualalo le malosi e lagolagoina ai vaega nei: · 16-bit up counter with 16-bit autoreload register · 16-bit compare register · Configurable output: pulse, PWM · Fa'aauau/tasi-shot mode · Filifili polokalame/megana fa'aoso fa'aoso · Filifilia puna uati:
puna'oa o le uati i totonu: LSE, LSI, HSI po'o le APB fa'apogai o le uati i fafo i luga ole LPTIM fa'aoga (galue e tusa lava pe leai se uati i totonu.
puna o loʻo faʻaogaina, faʻaaogaina e le faʻaogaina o le pulupulu faʻatau) · Polokalama numera glitch filiga · Encoder mode
LPTIM2 ma le LPTIM3 e mafai ona faauigaina (i le ETZPC) e mafai ona maua e na'o polokalama malupuipuia.
Taile leoleo tutoatasi (IWDG1, IWDG2)
O se ta'ifau tuto'atasi e fa'avae ile 12-bit downcounter ma le 8-bit prescaler. O lo'o lokaina mai le RC tuto'atasi 32 kHz i totonu (LSI) ma, a'o galue tuto'atasi mai le uati autu, e mafai ona fa'agaioi i tulaga Taofi ma Standby. E mafai ona fa'aogaina le IWDG e fai ma ta'ifau e toe fa'afo'i le masini pe a tupu se fa'afitauli. O meafaigaluega-po'o le softwareconfigurable e ala i le filifiliga bytes.
IWDG1 e mafai ona faauigaina (i le ETZPC) e mafai ona maua e na'o polokalama malupuipuia.
Taimi lautele (Cortex-A7 CNT)
Cortex-A7 taimi lautele fa'apipi'i i totonu o Cortex-A7 o lo'o fafaga i le tau mai le fa'atulagaina o taimi (STGEN).
O le Cortex-A7 processor e maua ai taimi nei: · taimi faʻaletino mo le faʻaogaina i le saogalemu ma le le saogalemu.
O tusi resitala mo le taimi faʻaletino e teu faʻapipiʻi e tuʻuina atu ai kopi saogalemu ma le le malu puipuia. · taimi fa'akomepiuta mo le fa'aoga i faiga e le maluelue · taimi fa'aletino mo le fa'aoga ile hypervisor mode
O taimi fa'apitoa e le'o ni fa'afanua e fa'amaufa'ailogaina ai ma e na'o fa'atonuga fa'apitoa o le coprocessor Cortex-A7 e mafai ona maua (cp15).

3.27

Fa'atupuina o le taimi (STGEN)
O le faʻatulagaina o taimi faʻatulagaina (STGEN) e faʻatupuina ai se tau-tau aofaʻi e maua ai se faʻaauau view o taimi mo taimi uma Cortex-A7.

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O le fa'atulagaina o taimi fa'atulagaina o lo'o i ai vaega taua nei: · 64-bit lautele e aloese ai mai fa'alavelave fa'alavelave · Amata mai le zero po'o se tau fa'apolokalameina · Pulea le APB interface (STGENC) e mafai ai ona fa'asaoina ma toe fa'afo'i le taimi.
i luga o fa'alavelave fa'aletonu · Faitau-na'o le APB interface (STGENR) e mafai ai ona faitau le tau e le o
saogalemu polokalame ma mea faigaluega debug · Fa'atuputeleina le tau o le taimi e mafai ona taofia i le taimi o le debug system
STGENC e mafai ona faauigaina (i le ETZPC) e mafai ona maua e na'o polokalama malupuipuia.

3.28

Uati taimi-moni (RTC)
O le RTC e maua ai se fafagu otometi e pulea uma auala maualalo-malosi. RTC o se BCD timer / counter tutoʻatasi ma e maua ai se taimi-o-aso uati / kalena ma faʻalavelave faʻalavelave faʻapipiʻi.
O le RTC e aofia ai fo'i se fu'a fafagu fa'apolokalame fa'apolokalame fa'atasi ma le mafai fa'alavelave.
E lua 32-bit resitala o loʻo i ai sekone, minute, itula (12- poʻo le 24-itula faʻatulagaina), aso (aso o le vaiaso), aso (aso o le masina), masina, ma le tausaga, faʻaalia i le binary coded decimal format (BCD). O lo'o maua fo'i le fa'asologa o lua-lua.
E lagolagoina le faiga binary e faafaigofie ai le pulega o avetaavale.
O taui mo le 28-, 29- (leap year), 30-, ma le 31-aso masina e fa'atinoina otometi. E mafai fo'i ona fa'atino taui o le taimi fa'aola.
Fa'aopoopo 32-bit resitara o lo'o i ai le fa'ailoga fa'apolokalame subseconds, sekone, minute, itula, aso, ma le aso.
O lo'o avanoa se fa'avasegaga fa'afuainumera e totogi ai so'o se fa'asesega i le sa'o o le oscillator tioata.
A mae'a le toe setiina o le vaega o le Backup, e puipuia uma resitara o le RTC mai avanoa e mafai ona tusia ai ni fa'ama'i ma puipuia e ala fa'amautu.
A'o le sapalai voltage tumau pea i totonu o le faʻaogaina, e le taofia le RTC, e tusa lava po o le a le tulaga o le masini (Run mode, low-power mode or under reset).
O vaega autu o le RTC o lo'o i lalo: · Kalena fa'atasi ma sekona, sekone, minute, itula (12 po'o 24 fa'atulagaina), aso (aso o
vaiaso), aso (aso o le masina), masina, ma le tausaga · Daylight saving taui e mafai ona fa'apolokalameina e le polokalame · Fa'apolokalame fa'ailo fa'atasi ai ma galuega fa'alavelave. O le fa'ailo e mafai ona fa'aoso e so'o se mea
tuufaatasiga o fanua kalena. · Otometi fafagu iunite fa'atupuina se fu'a fa'avaitaimi e fa'aosoina ai se fafafa fafao
fa'alavelave · Su'esu'eina uati fa'asino: o se uati puna lona lua e sili atu ona sa'o (50 po'o le 60 Hz) e mafai ona
fa'aaoga e fa'aleleia atili ai le sa'o o le kalena. · Fa'asa'o sa'o ma se uati i fafo e fa'aaoga ai le vaega o le sifi i lalo-lua.
fa'amalama fa'avasega o ni nai sekone

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· Taimiamp galuega mo le fa'asaoina o mea tutupu · Teuina o le SWKEY ile RTC fa'amaumauga fa'amaumauga fa'atasi ai ma le pasi sa'o ile SAE (leai
mafai ona faitau e le PPU) · Maskable fa'alavelave/mea tutupu:
Ala'u A Ala'ei B Fa'alavelave Taimiamp · Fesoasoani i le TrustZone: RTC e mafai ona malupuipuia atoatoa Alale A, fa'ailo B, taimi fafagu ma taimiamp saogalemu tagata taitoatasi pe leai foi
fetuutuunaiga RTC calibration faia i le saogalemu i luga o le le-saogalemu faatulagaga

3.29

Tamper ma tusi resitala (TAMP)
32 x 32-bit resitara fa'asao o lo'o fa'atumauina i faiga uma e maualalo le malosi fa'apea fo'i ile VBAT mode. E mafai ona fa'aoga e teu ai fa'amatalaga ma'ale'ale a'o puipuia a latou mea e atamper detection circuit.
Fitu tamper pine fa'aoga ma le lima tampo lo'o maua pine fa'apipi'i mo anti-tamper su'esu'ega. O fafo tampe mafai ona fa'atulagaina pine mo le su'esu'eina o le pito, pito ma le maualuga, su'esu'ega maualuga ma le fa'amama, po'o le malosi t.amper e fa'atuputeleina ai le tulaga saogalemu e ala ile siakiina ole tamper pine e le tatalaina i fafo pe pupuu.
TAMP vaega autu · 32 tusi resitala (TAMP_BKPxR) fa'atinoina i le RTC domain o lo'o tumau
fa'aola e VBAT pe a tape le eletise VDD · 12 tamper pine o lo'o maua (fitu mea fa'aoga ma lima galuega faatino) · So'o se tampO le su'esu'eina e mafai ona maua ai se taimi RTCamp mea na tupu. · So'o se tamper su'esu'ega e tape ai tusi resitala faaleoleo. · lagolago a TrustZone:
Tamper fa'amautu po'o le le fa'amautu le fa'aoga Fa'amaumauga Fa'asao resitalaina fa'atonuga i vaega e tolu e mafai ona fa'atulagaina-tele:
. tasi le vaega faitau/tusi malu . tasi le tusi saogalemu/faitau le nofoaga e le maluelue . tasi le vaega faitau/tusi e le maluelue · Fa'ailoga Monotonic

3.30

Feso'ota'iga feso'ota'iga fa'atasi (I2C1, I2C2, I2C3, I2C4, I2C5)
O masini faʻapipiʻi lima I2C fesoʻotaʻiga.
Ole fa'aoga ole pasi I2C e fa'atautaia feso'ota'iga ile va ole STM32MP133C/F ma le pasi I2C. E pulea uma I2C pasi-faʻapitoa faʻasologa, faʻasalalauga, faʻatalanoaga ma le taimi.

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O le I2C peripheral lagolago: · I2C-pasi fa'amatalaga ma fa'aoga tusi lesona rev. 5 fetaui:
Polokalama pologa ma matai, gafatia multimaster tulaga masani (Sm), ma le bitrate e oo atu i le 100 kbit/s Fast-mode (Fm), faatasi ai ma le bitrate e oo atu i le 400 kbit/s Fast-mode Plus (Fm+), faatasi ai ma le bitrate e oo atu i le 1 Mbit/s ma le 20 mA output drive I/Os 7-bits addressing mode ma le 10 setup slave mode tele ma ta'i taimi Fa'alilolilo uati filifiliga · Fa'atonuga o pasi fa'atonu (SMBus) toe fa'afouina 7 feso'ota'iga: Meafaigaluega PEC (su'eina mea sese) fa'atupuina ma fa'amaonia ma le ACK
fa'atonu le Fa'atonuga o le fa'aiuga o le tuatusi (ARP) lagolago SMBus alert · Fa'atonuga o le pulega o le malosiaga (PMBusTM) fa'amatalaga rev 1.1 feso'ota'iga · Uati Tuto'atasi: o se filifiliga o puna'oa tuto'atasi o le uati e mafai ai ona tuto'atasi le saoasaoa o feso'ota'iga I2C mai le toe fa'atulagaina o le PCLK · Fafagu mai le tulaga Taofi i luga o le tuatusi fetaui · Fa'apolokalameina analog ma fa'aigoa pisa filiga · 1-byte gafatia pa'u ma le DMA pa'u
I2C3, I2C4 ma le I2C5 e mafai ona faauigaina (i le ETZPC) e mafai ona maua e na'o polokalama malupuipuia.

3.31

Fa'asalalauga fa'asalalau fa'atasi fa'atasi (USART1, USART2, USART3, USART6 ma UART4, UART5, UART7, UART8)
O masini e fa fa'apipi'i fa'asalalauga fa'asalalau fa'atasi (USART1, USART2, USART3 ma USART6) fa'apea fo'i fa'asalalauga fa'asalalau lautele e fa (UART4, UART5, UART7 ma UART8). Va'ai le laulau o lo'o i lalo mo se aotelega o uiga USARTx ma UARTx.
O nei feso'ota'iga e maua ai feso'ota'iga asynchronous, IrDA SIR ENDEC lagolago, multiprocessor auala feso'ota'iga, tasi-uaea afa-duplex auala feso'ota'iga ma maua LIN matai / pologa gafatia. Latou te tuʻuina atu le faʻatonutonuina o meafaigaluega o faailoilo CTS ma RTS, ma le RS485 Avetaavale Enable. E mafai ona latou fesoʻotaʻi i le saoasaoa e oʻo atu i le 13 Mbit/s.
USART1, USART2, USART3 ma USART6 o loʻo tuʻuina atu foʻi le Smartcard mode (ISO 7816 compliant) ma SPI-pei o fesoʻotaʻiga gafatia.
O USART uma e iai le uati e tuto'atasi mai le uati o le CPU, e mafai ai e le USARTx ona fafaguina le STM32MP133C/F mai le Stop mode e fa'aaoga ai baudrates e o'o atu i le 200 Kbaud. O mea fafagu mai Stop mode e mafai ona fa'apolokalameina ma e mafai ona:
· amata le su'esu'ega
· so'o se fa'asologa o fa'amatalaga maua
· se fa'afanua fa'amaumauga fa'apitoa ua fa'apolokalameina

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O feso'ota'iga USART uma e mafai ona tu'uina atu e le DMA pule.

Laulau 5. USART/UART vaega

USART modes/features(1)

USART1/2/3/6

UART4/5/7/8

Fa'atonuga o masini mo le modem

Fesootaiga fa'aauau e fa'aaoga ai le DMA

Fesootaiga teleprocessor

Faiga fa'aoga SPI (matai/pologa)

–

Faiga Smartcard

–

Feso'ota'iga afa-duplex tasi uaea IrDA SIR ENDEC poloka

faiga LIN

Lua uati vaega ma fafagu mai ala maualalo le malosi

E fa'alavelave le taimi e maua ai feso'ota'iga Modbus

Su'esu'e fua o le pa'u ta'avale

Avetaavale Enable

USART umi fa'amaumauga

7, 8 ma 9 bits

1. X = lagolago.

USART1 ma le USART2 e mafai ona faauigaina (i le ETZPC) e mafai ona maua e na'o polokalama faakomepiuta.

3.32

Feso'ota'iga fa'apitonu'u (SPI1, SPI2, SPI3, SPI4, SPI5) feso'ota'iga leo fa'atasi (I2S1, I2S2, I2S3, I2S4)
O masini e oʻo atu i le lima SPI (SPI2S1, SPI2S2, SPI2S3, SPI2S4, ma SPI5) e faʻatagaina fesoʻotaʻiga e oʻo atu i le 50 Mbit / s i le matai ma le pologa modes, i le afa-duplex, fullduplex ma simplex modes. O le 3-bit prescaler e tu'uina atu ai le valu matai ala alaleo ma o le fa'avaa e mafai ona fa'atulagaina mai le 4 i le 16 bits. O feso'ota'iga SPI uma e lagolagoina le NSS pulse mode, TI mode, hardware CRC calculation ma fa'ateleina le 8-bit embedded Rx ma Tx FIFOs ma le DMA gafatia.
I2S1, I2S2, I2S3, ma le I2S4 o loʻo faʻapipiʻiina ma SPI1, SPI2, SPI3 ma SPI4. E mafai ona faʻaogaina i le matai poʻo le pologa mode, i le full-duplex ma le afa-duplex auala fesoʻotaʻiga, ma e mafai ona faʻapipiʻiina e faʻaogaina i le 16- poʻo le 32-bit iugafono e avea o se faʻaoga poʻo se auala faʻapipiʻi. Leo sampE lagolagoina alaleo ling mai le 8 kHz i le 192 kHz. O feso'ota'iga I2S uma e lagolagoina le fa'ateleina o le 8-bit fa'apipi'i Rx ma Tx FIFO fa'atasi ma le gafatia DMA.
SPI4 ma SPI5 e mafai ona faauigaina (i le ETZPC) e mafai ona maua e na'o polokalama malupuipuia.

3.33

Feso'ota'iga leo fa'asologa (SAI1, SAI2)
O masini e faʻapipiʻi ai SAI e lua e faʻatagaina ai le mamanu o le tele o faʻasalalauga leo poʻo mono leo

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pei ole I2S, LSB poʻo MSB-faʻamaonia, PCM/DSP, TDM poʻo AC'97. O lo'o maua se galuega fa'atino a le SPDIF pe a fa'atulagaina le poloka leo e fai ma transmitter. Ina ia aumaia lenei tulaga o le fetuutuunai ma le toe fetuutuunai, o SAI taitasi o loʻo iai ni poloka leo e lua tutoʻatasi. O poloka ta'itasi o lo'o i ai lana uati generator ma le I/O laina pule. Leo sampe lagolagoina alalesi e oo atu i le 192 kHz. E le gata i lea, e oʻo atu i le valu microphones e mafai ona lagolagoina faʻafetai i se faʻaoga PDM faʻapipiʻi. E mafai e le SAI ona galue i le faʻatonuga poʻo le pologa. O poloka laiti leo e mafai ona avea ma se tagata e taliaina poʻo se faʻasalalauga ma e mafai ona galue faʻatasi poʻo le asynchronously (e faʻatatau i le isi). E mafai ona feso'ota'i le SAI ma isi SAI e galulue fa'atasi.

3.34

SPDIF tali fa'afeso'ota'i (SPDIFRX)
O le SPDIFRX ua mamanuina e maua ai le S/PDIF tafega e tusa ai ma le IEC-60958 ma le IEC-61937. O nei tulaga fa'ata'atia e lagolago ai alavai fa'aleo faigofie e o'o atu i s maualugaample fua, ma fa'apipi'i tele alalaupapa si'osi'o leo, pei o na fa'amatalaina e le Dolby po'o le DTS (e o'o i le 5.1).
O vaega autu o le SPDIFRX o mea nei: · E oʻo atu i le fa faʻaoga o loʻo maua · Suʻesuʻeina fua o faʻailoga otometi · Faʻamaufaʻailoga maualuga: 12.288 MHz · Faʻalogo leo mai le 32 i le 192 kHz lagolagoina · Lagolago o leo IEC-60958 ma IEC-61937, talosaga tagata faʻatau · Parity bit pulega · Fesoʻotaʻiga faʻaoga DMA mo leo samples · Feso'ota'iga e fa'aaoga ai le DMA mo le fa'atonutonuina ma fa'amatalaga alala'au fa'aoga · Fa'alavelave fa'alavelave
O le SPDIFRX receiver e tuʻuina atu mea uma e manaʻomia e iloa ai le fua faʻatusa, ma faʻavasega le faʻasologa o faʻamatalaga o loʻo oʻo mai. E mafai e le tagata fa'aoga ona filifili le SPDIF e mana'omia, ma pe a maua se fa'ailoga fa'amaonia, toe fa'afo'i le SPDIFRXample fa'ailoga o lo'o sau, fa'aliliu le vaitafe o Manaseta, ma iloa fa'ava'a, fa'ava'a laiti ma poloka elemene. O le SPDIFRX e tuʻuina atu i le PPU faʻamatalaga faʻamaonia, ma faʻailoga tulaga faʻatasi.
O le SPDIFRX e ofoina atu foi se faailo e igoa spdif_frame_sync, lea e sui i le S/PDIF sub-frame fua faatatau lea e faʻaaogaina e faʻatusatusa ai le s saʻo.ample fua faatatau mo le uati tafe algorithms.

3.35

Saogalemu feso'ota'iga fa'akomepiuta/tuuina atu MultiMediaCard (SDMMC1, SDMMC2)
E lua feso'ota'iga fa'akomepiuta fa'akomupiuta ma fa'aulufalega MultiMediaCard (SDMMC) e maua ai se feso'ota'iga i le va o le pasi AHB ma kata manatua SD, kata SDIO ma masini MMC.
O vaega o le SDMMC e aofia ai mea nei: · Tausi ma le Fa'apipi'iina o le MultiMediaCard System Specification Version 5.1
Lagolago pepa mo auala eseese e tolu fa'amaumauga: 1-bit (fa'aletonu), 4-bit ma le 8-bit

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(HS200 SDMMC_CK saoasaoa fa'atapula'a i le maualuga fa'atagaina I/O saosaoa)(HS400 e le lagolagoina)
· Fegalegaleai atoatoa ma lomiga muamua o MultiMediaCards (fesoʻotaʻiga i tua)
· Fa'amalie atoatoa i fa'amatalaga fa'amatalaga SD card memory version 4.1 (SDR104 SDMMC_CK saoasaoa fa'atapula'a i le maualuga fa'atagaina I/O saosaoa, SPI mode ma UHS-II mode le lagolagoina)
· O le tausisia atoatoa o le SDIO card specification version 4.0 Card support mo auala eseese e lua o databus: 1-bit (default) ma le 4-bit (SDR104 SDMMC_CK speed faatapulaaina i le maualuga faatagaina I/O speed, SPI mode ma UHS-II mode e le lagolagoina)
· Fa'aliliuina fa'amatalaga e o'o atu i le 208 Mbyte/s mo le 8-bit mode (fa'alagolago i le maualuga fa'atagaina I/O saoasaoa)
· Fa'amaumauga ma fa'atonuga e mafai ai e fa'ailo ona pulea ta'avale ta'i lua
· Fa'apitoa DMA fa'atonu fa'apipi'iina i totonu o le SDMMC fa'afeiloa'iga fa'afeiloa'iga, fa'atagaina le televave o fe'avea'iga i le va o le fa'aoga ma le SRAM
· IDMA feso'ota'iga lisi lagolago
· Sapalai eletise tu'ufa'atasia, VDDSD1 ma VDDSD2 mo SDMMC1 ma SDMMC2 ta'itasi, aveese le mana'omia mo le fa'aofiina o tulaga-shifter i luga o le SD card interface i le UHS-I mode
Na'o nisi GPIO mo SDMMC1 ma SDMMC2 o lo'o avanoa i luga o se pine fa'apitoa VDDSD1 po'o VDDSD2. O vaega ia o le fa'aletonu o le boot GPIOs mo SDMMC1 ma SDMMC2 (SDMMC1: PC[12:8], PD[2], SDMMC2: PB[15,14,4,3], PE3, PG6). E mafai ona iloa i latou i le isi laulau fa'atino e ala i fa'ailo o lo'o iai se suffix "_VSD1" po'o le "_VSD2".
O SDMMC ta'itasi o lo'o tu'ufa'atasia ma se poloka tuai (DLYBSD) e fa'atagaina ai le lagolago o fa'amatalaga fa'amatalaga fafo i luga ole 100 MHz.
O fesoʻotaʻiga SDMMC uma e iai ni faʻamautu faʻamautu.

3.36

Feso'ota'iga a le vaega e pulea (FDCAN1, FDCAN2)
Ole vaega ole vaega ole pulega (CAN) subsystem e aofia ai le lua CAN modules, se fe'au fefa'asoaa'i RAM manatua ma se iunite fa'avasega uati.
O vaega uma e lua o le CAN (FDCAN1 ma le FDCAN2) e ogatasi ma le ISO 11898-1 (CAN protocol specification version 2.0 part A, B) ma le CAN FD protocol specification version 1.0.
O le 10-Kbyte message RAM memory e faʻaaogaina ai filiga, maua FIFOs, maua paʻu, faʻasalalau mea FIFO faʻalavelave ma faʻafeiloaʻi paʻu (faʻatasi ma faʻaosoina mo TTCAN). O lenei savali RAM o loʻo faʻasoa i le va o le FDCAN1 ma le FDCAN2 modules.
O le iunite fa'avasega masani o le uati e filifili. E mafai ona fa'aogaina e fa'atupu ai se uati fa'avasega mo FDCAN1 ma FDCAN2 mai le HSI i totonu RC oscillator ma le PLL, e ala i le iloiloina o fe'au CAN na maua e le FDCAN1.

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Faʻaaoga lugaview

STM32MP133C/F

3.37

Ta'ita'i pasi fa'asalalau fa'asalalau fa'asalalau maualuga (USBH)
O masini e faʻapipiʻi ai le tasi USB telefoni feaveaʻi (e oʻo atu i le 480 Mbit/s) faʻatasi ai ma ports faaletino e lua. E lagolagoina e le USBH ia galuega e lua maualalo, saoasaoa atoa (OHCI) faapea foi ma le saoasaoa maualuga (EHCI) i luga o uafu taitasi. E tu'ufa'atasia ni transceivers se lua e mafai ona fa'aoga mo le maualalo-saosaoa (1.2 Mbit/s), atoa-saosaoa (12 Mbit/s) po'o le saoasaoa maualuga (480 Mbit/s). O le transceiver maualuga lona lua e faʻasoa faʻatasi ma le OTG maualuga-saoasaoa.
O le USBH e ogatasi ma le USB 2.0 faʻamatalaga. O le USBH controllers e manaʻomia ni uati faʻapitoa e gaosia e se PLL i totonu ole PHY televave USB.

3.38

USB i luga ole alu ole saoasaoa maualuga (OTG)
O masini e fa'apipi'i tasi le USB OTG maualuga-saosaoa (e o'o atu i le 480 Mbit/s) masini/host/OTG peripheral. O le OTG e lagolagoina uma le saosaoa atoa ma le televave o gaioiga. O le transceiver mo le saoasaoa maualuga (480 Mbit / s) e faʻasoa i le USB Host lona lua uafu.
O le USB OTG HS e ogatasi ma le USB 2.0 faʻamatalaga ma le OTG 2.0 faʻamatalaga. O lo'o iai le fa'atonuga fa'ai'uga e mafai ona fa'aogaina e le software ma e lagolagoina le fa'agata/fa'aauau. O le USB OTG controllers e manaʻomia se uati 48 MHz tuʻufaʻatasia e gaosia e se PLL i totonu o le RCC poʻo totonu ole PHY televave USB.
O le USB OTG HS autu autu o loʻo lisiina i lalo: · Tuʻufaʻatasia Rx ma Tx FIFO tele o 4 Kbyte ma dynamic FIFO sizing · SRP (sesion request protocol) ma le HNP (host negotiation protocol) lagolago · E valu bidirectional endpoints · 16 host channels with periodic OUT support · Software configurable to OTG1.3 ma le OTG2.0 pulega. · Fa'atonuga o le fa'atonuga o le maa 2.0 lagolago · HS OTG PHY lagolago · USB DMA i totonu · HNP / SNP / IP i totonu (leai se mana'oga mo so'o se fa'alavelave i fafo) · Mo OTG / Host modes, e mana'omia se ki o le eletise i le tulaga o masini e fa'aogaina ai pasi.
fesootai.
O le USB OTG configuration port e mafai ona malupuipuia.

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DS13875 Faaaliga 5

STM32MP133C/F

Faʻaaoga lugaview

3.39

Gigabit Ethernet MAC feso'ota'iga (ETH1, ETH2)
O masini e maua ai le IEEE-802.3-2002-compliant gigabit media access controllers (GMAC) mo fesoʻotaʻiga Ethernet LAN e ala i se atinaʻe tutoʻatasi-tutoatasi (MII), se faʻaitiitiga tutoʻatasi-tutoatasi (RMII), poʻo se faʻaititia o le gigabit medium-independent interface (RGMII).
O masini e manaʻomia se masini faʻaoga faʻapitoa i fafo (PHY) e faʻafesoʻotaʻi i le pasi LAN faaletino (twisted-pair, fiber, etc.). O le PHY e fesoʻotaʻi i le masini uafu e faʻaaoga ai faailo 17 mo MII, 7 faailo mo RMII, poʻo 13 faailoilo mo RGMII, ma e mafai ona lokaina e faʻaaoga ai le 25 MHz (MII, RMII, RGMII) poʻo le 125 MHz (RGMII) mai le STM32MP133C/F poʻo le PHY.
O masini e aofia ai vaega nei: · Faiga fa'aogaina ma feso'ota'iga PHY
10-, 100-, ma le 1000-Mbit/s fua faatatau fe'avea'i Lagolago o fa'agaioiga atoa-duplex ma le afa-duplex feso'ota'iga MII, RMII ma RGMII PHY · Pulea fa'agaoioiga Fa'avasegaina o Pa'u Fa'atele: Fa'amama MAC ile puna (SA) ma le taunu'uga (DA)
tuatusi fa'atasi ma fa'amama atoatoa ma hash, VLAN tag-fa'avae fa'amama fa'atasi ma le fa'amama atoatoa ma le hash, Layer 3 fa'amama i luga ole IP puna (SA) po'o le taunu'uga (DA) tuatusi, Layer 4 fa'amama ile puna (SP) po'o le taunu'uga (DP) uafu Fa'alua VLAN fa'aogaina: fa'aofiina e o'o atu i le lua VLAN tags i le auala faʻasalalau, tag fa'amama i le ala maua IEEE 1588-2008/PTPv2 lagolago Lagolagoina fa'amaumauga o feso'ota'iga ma fa'atauga RMON/MIB (RFC2819/RFC2665) · Fa'agaoioiga o mea faigaluega fa'apipi'i Fa'atomuaga ma fa'amatalaga amata-o-fa'a (SFD) fa'aofi po'o le tapeina Fa'amaoni siaki su'esu'e afi afi mo le fa'auluina IP/ICMPCP/ulaga totogi fa'auluina le fa'auluina o le IP ma le TMPCP/UD. fa'atatauga siaki ma fa'atusatusaga Otometi ARP talosaga tali ma le masini MAC tuatusi TCP vaevaega: vaeluaga otometi o le tele lafo TCP pepa i le tele o tama'i afifi · Low-power mode Malosiaga lelei Ethernet (standard IEEE 802.3az-2010) Fafagu fafagu mamao ma AMD Magic PacketTM iloa.
O le ETH1 ma le ETH2 e mafai ona faʻapipiʻiina e saogalemu. A malupuipuia, fefaʻatauaʻiga i luga o le AXI interface e malupuipuia, ma o le resitara faʻatulagaina e mafai ona suia e ala i avanoa saogalemu.

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Faʻaaoga lugaview

STM32MP133C/F

3.40

Debug infrastructure
O masini e ofoina atu le debug ma su'esu'e vaega nei e lagolago ai le atina'eina o polokalama ma le tu'ufa'atasia o le faiga: · Fa'apalapala va'ava'a · Su'esu'eina o le fa'atinoina o tulafono · Fa'apolokalame meafaigaluega · JTAG uaea fa'aleaga uaea fa'aoso fa'aoso fa'aoso fa'aoso ma fa'aulufalega fa'aoso fa'ailoga uafu su'esu'e le lima CoreSight debug ma su'e vaega
E mafai ona pulea le debug e ala ile JTAG/serial-wire debug avanoa uafu, fa'aoga meafaigaluega fa'apipi'i tulaga masani o alamanuia.
O le fa'ailoga uafu e mafai ai ona pu'e fa'amaumauga mo le fa'amauina ma au'ili'ili.
O le fa'aogaina o le debug i nofoaga fa'amautu e mafai e fa'ailoga fa'amaonia i le BSEC.

48/219

DS13875 Faaaliga 5

STM32MP133C/F

Pinout, faʻamatalaga pine ma isi galuega

Ata 5. STM32MP133C/F LFBGA289 palota

VSS

PA9

PD10

PB7

PE7

PD5

PE8

PG4

PH9

PH13

PC7

PB9

PB14

PG6

PD2

PC9

VSS

PD3

PF5

PD14

PE12

PE1

PE9

PH14

PE10

PF1

PF3

PC6

PB15

PB4

PC10

PC12

DDR_DQ4 DDR_DQ0

PB6

PH12

PE14

PE13

PD8

PD12

PD15

VSS

PG7

PB5

PB3

VDDSD1

PF0

PC11

DDR_DQ1

DDR_ DQS0N

DDR_ DQS0P

PB8

PD6

VSS

PE11

PD1

PE0

PG0

PE15

PB12

PB10

VDDSD2

VSS

PE3

PC8

DDR_ DQM0

DDR_DQ5 DDR_DQ3

PG9

PD11

PA12

PD0

VSS

PA15

PD4

PD9

PF2

PB13

PH10

VDDQ_ DDR

DDR_DQ2 DDR_DQ6 DDR_DQ7 DDR_A5

DDR_ RESETN

PG10

PG5

PG8

PH2

PH8

VDDCPU

VDD

VDDCPU VDDCPU

VDD

VDDQ_ DDR

VSS

DDR_A13

VSS

DDR_A9

DDR_A2

PF9

PF6

PF10

PG15

PF8

VDD

VSS

VDDQ_ DDR

DDR_BA2 DDR_A7

DDR_A3

DDR_A0 DDR_BA0

PH11

PI3

PH7

PB2

PE4

VDDCPU

VSS

VDDCORE VDDCORE VDDCORE

VSS

VDDQ_ DDR

DDR_WEN

VSS

DDR_ODT DDR_CSN

DDR_ RASN

PD13

VBAT

PI2

VSS_PLL VDD_PLL VDDCPU

VSS

VDDCORE

VSS

VDDCORE

VSS

VDDQ_ DDR

VDDCORE DDR_A10

DDR_ CASN

DDR_ CLKP

DDR_ CLKN

PC14OSC32_IN

PC15OSC32_
IFO

VSS

PC13

PI1

VDD

VSS

VDDCORE VDDCORE VDDCORE

VSS

VDDQ_ DDR

DDR_A11 DDR_CKE DDR_A1 DDR_A15 DDR_A12

PE2

PF4

PH6

PI0

PG3

VDD

VSS

VDDQ_ DDR

DDR_ATO

DDR_ DTO0

DDR_A8 DDR_BA1 DDR_A14

PF7

PA8

PG11

VDD_ANA VSS_ANA

VDD

VDDQ_ DDR

DDR_ VREF

DDR_A4

VSS

DDR_ DTO1

DDR_A6

PE6

PG1

PD7

VSS

PB11

PF13

VSSA

PA3

NJTRST

VSS_USB VDDA1V1_

REG

VDDQ_ DDR

PWR_LP

DDR_ DQM1

DDR_ DQ10

DDR_DQ8 DDR_ZQ

PH0OSC_IN

PH1OSC_OUT

PA13

PF14

PA2

VREF-

VDDA

PG13

PG14

VDD3V3_ USBHS

VSS

PI5-BOOT1 VSS_PLL2 PWR_ON

DDR_ DQ11

DDR_ DQ13

DDR_DQ9

PG2

PH3

PWR_CPU _ON

PA1

VSS

VREF+

PC5

VSS

VDD

PF15

VDDA1V8_ REG

PI6-BOOT2

VDD_PLL2

PH5

DDR_ DQ12

DDR_ DQS1N

DDR_ DQS1P

PG12

PA11

PC0

PF12

PC3

PF11

PB1

PA6

PE5

PDR_ON USB_DP2

PA14

USB_DP1

BYPASS_ REG1V8

PH4

DDR_ DQ15

DDR_ DQ14

VSS

PA7

PA0

PA5

PA4

PC4

PB0

PC1

PC2

NRST

USB_DM2

USB_ RREF

USB_DM1 PI4-BOOT0

PA10

PI7

VSS

MSv65067V5

O le ata o loʻo i luga o loʻo faʻaalia ai le pito i luga o le afifi view.

DS13875 Faaaliga 5

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97

Pinout, faʻamatalaga pine ma isi galuega

STM32MP133C/F

Ata 6. STM32MP133C/F TFBGA289 palota

VSS

PD4

PE9

PG0

PD15

PE15

PB12

PF1

PC7

PC6

PF0

PB14

VDDSD2 VDDSD1 DDR_DQ4 DDR_DQ0

VSS

PE12

PD8

PE0

PD5

PD9

PH14

PF2

VSS

PF3

PB13

PB3

PE3

PC12

VSS

DDR_DQ1

DDR_ DQS0N

DDR_ DQS0P

PE13

PD1

PE1

PE7

VSS

VDD

PE10

PG7

PG4

PB9

PH10

PC11

PC8

DDR_DQ2

DDR_ DQM0

DDR_DQ3 DDR_DQ5

PF5

PA9

PD10

VDDCPU

PB7

VDDCPU

PD12

VDDCPU

PH9

VDD

PB15

VDD

VSS

VDDQ_ DDR

DDR_ RESETN

DDR_DQ7 DDR_DQ6

PD0

PE14

VSS

PE11

VDDCPU

VSS

PA15

VSS

PH13

VSS

PB4

VSS

VDDQ_ DDR

VSS

VDDQ_ DDR

VSS

DDR_A13

PH8

PA12

VDD

VDDCPU

VSS

VDDCORE

PD14

PE8

PB5

VDDCORE

PC10

VDDCORE

VSS

VDDQ_ DDR

DDR_A7

DDR_A5

DDR_A9

PD11

PH2

PB6

PB8

PG9

PD3

PH12

PG15

PD6

PB10

PD2

PC9

DDR_A2 DDR_BA2 DDR_A3

DDR_A0 DDR_ODT

PG5

PG10

PF8

VDDCPU

VSS

VDDCORE

PH11

PI3

PF9

PG6

BYPASS_ REG1V8

VDDCORE

VSS

VDDQ_ DDR

DDR_BA0 DDR_CSN DDR_WEN

J VDD_PLL VSS_PLL

PG8

PI2

VBAT

PH6

PF7

PA8

PF12

VDD

VDDA1V8_ REG

PA10

DDR_ VREF

DDR_ RASN

DDR_A10

VSS

DDR_ CASN

PE4

PF10

PB2

VDD

VSS

VDDCORE

PA13

PA1

PC4

NRST

VSS_PLL2 VDDCORE

VSS

VDDQ_ DDR

DDR_A15

DDR_ CLKP

DDR_ CLKN

PF6

VSS

PH7

VDD_ANA VSS_ANA

PG12

PA0

PF11

PE5

PF15

VDD_PLL2

PH5

DDR_CKE DDR_A12 DDR_A1 DDR_A11 DDR_A14

PC14OSC32_IN

PC15OSC32_
IFO

PC13

VDD

VSS

PB11

PA5

PB0

VDDCORE

USB_ RREF

PI6-BOOT2 VDDCORE

VSS

VDDQ_ DDR

DDR_A6

DDR_A8 DDR_BA1

PD13

VSS

PI0

PI1

PA11

VSS

PA4

PB1

VSS

PI5-BOOT1

VSS

VDDQ_ DDR

VSS

VDDQ_ DDR

VSS

DDR_ATO

PH0OSC_IN

PH1OSC_OUT

PF4

PG1

VSS

VDD

PC3

PC5

VDD

PI4-BOOT0

VDD

VSS

VDDQ_ DDR

DDR_A4 DDR_ZQ DDR_DQ8

PG11

PE6

PD7

PWR_ CPU_ON

PA2

PA7

PC1

PA6

PG13

NJTRST

PA14

VSS

PWR_ON

DDR_ DQM1

DDR_ DQ12

DDR_ DQ11

DDR_DQ9

PE2

PH3

PF13

PC0

VSSA

VREF-

PA3

PG14

USB_DP2

VSS

VSS_ USBHS

USB_DP1

PH4

DDR_ DQ13

DDR_ DQ14

DDR_ DQS1P

DDR_ DQS1N

VSS

PG3

PG2

PF14

VDDA

VREF+

PDR_ON

PC2

USB_DM2

VDDA1V1_ REG

VDD3V3_ USBHS

USB_DM1

PI7

O le ata o loʻo i luga o loʻo faʻaalia ai le pito i luga o le afifi view.

PWR_LP

DDR_ DQ15

DDR_ DQ10

VSS

MSv67512V3

50/219

DS13875 Faaaliga 5

STM32MP133C/F

Pinout, faʻamatalaga pine ma isi galuega

Ata 7. STM32MP133C/F TFBGA320 palota
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

VSS

PA9

PE13 PE12

PD12

PG0

PE15

PG7

PH13

PF3

PB9

PF0

PC10 PC12

PC9

VSS

PD0

PE11

PF5

PA15

PD8

PE0

PE9

PH14

PE8

PG4

PF1

VSS

PB5

PC6

PB15 PB14

PE3

PC11

DDR_ DQ4

DDR_ DQ1

DDR_ DQ0

PB6

PD3

PE14 PD14

PD1

PB7

PD4

PD5

PD9

PE10 PB12

PH9

PC7

PB3

VDD SD2

PB4

PG6

PC8

PD2

DDR_ DDR_ DQS0P DQS0N

PB8

PD6

PH12

PD10

PE7

PF2

PB13

VSS

DDR_ DQ2

DDR_ DQ5

DDR_ DQM0

PH2

PH8

VSS

VDD PPU

PE1

PD15

VDD PPU

VSS

VDD

PB10

PH10

VDDQ_ DDR

VSS

VDD SD1

DDR_ DQ3

DDR_ DQ6

PF8

PG9

PD11 PA12

VSS

DDR_ DQ7

DDR_ A5

VSS

PF6

PG10

PG5

VDD PPU

PE4

PF10 PG15

PG8

PH7

PD13

PB2

PF9

VDD PPU

VSS

VDD

VDD PPU

VDD CORE

VSS

VDD

VSS

VDDQ_ DDR

VSS

VDD

VSS

VDD CORE

VSS

VDD

VDD CORE

VDDQ_ DDR

DDR_ A13

DDR_ A2

DDR_ A9

DDR_ RESET
N

DDR_ BA2

DDR_ A3

DDR_ A0

DDR_ A7

DDR_ BA0

DDR_ CSN

DDR_ ODT

VSS_ PLL

VDD_ PLL

PH11

VDD PPU

PC15-

VBAT OSC32 PI3

VSS

_IFO

PC14-

VSS OSC32 PC13

_IN

VDD

PE2

PF4

PH6

PI2

VDD PPU
VDD CORE
VSS
VDD

VSS

VDD CORE

VSS

VDD CORE

VSS

VDD

VDD CORE

VSS

VDD

VDD CORE

VDDQ_ DDR
VSS
VDDQ_ DDR
VDD CORE

VDDQ_ DDR

DDR_ WEN

DDR_ RASN

VSS

DDR_ A10

DDR_ CASN

DDR_ CLKN

VDDQ_ DDR

DDR_ A12

DDR_ CLKP

DDR_ A15

DDR_ A11

DDR_ A14

DDR_ CKE

DDR_ A1

PA8

PF7

PI1

PI0

VSS

DDR_ DTO1

DDR_ ATO

DDR_ A8

DDR_ BA1

PG1

PG11

PH3

VDD

VSS

VDD

VDD CORE

VSS

VDD

VDD CORE

VSS

VDDQ_ DDR

DDR_ A4

DDR_ ZQ

DDR_ A6

VSS

PE6

PH0OSC_IN

PA13

VSS

DDR_ VREF

DDR_ DQ10

DDR_ DQ8

VSS

PH1OSC_ OUT

VSS_ ANA

VSS

VDD

VDDA VSSA

PA6

VSS

VDD CORE

VSS

VDD VDDQ_ CORE DDR

VSS

PWR_ ON

DDR_ DQ13

DDR_ DQ9

PD7

VDD_ ANA

PG2

PA7

VREF-

NJ TRST

VDDA1 V1_ REG

VSS

PWR_ DDR_ DDR_ LP DQS1P DQS1N

PWR_

PG3

PG12 PPU_ PF13

PC0

PC3 VREF+ PB0

PA3

PE5

VDD

USB_ RREF

PA14

VDD 3V3_ USBHS

VDDA1 V8_ REG

VSS

BYPAS S_REG
1V8

PH5

DDR_ DQ12

DDR_ DQ11

DDR_ DQM1

PA11

PF14

PA0

PA2

PA5

PF11

PC4

PB1

PC1

PG14

NRST

PF15

USB_ VSS_

PI6-

USB_

PI4-

VDD_

DM2 USBHS BOOT2 DP1 BOOT0 PLL2

PH4

DDR_ DQ15

DDR_ DQ14

VSS

PB11

PA1

PF12

PA4

PC5

PG13

PC2

PDR_ ON

USB_ DP2

PI5-

USB_

BOOT1 DM1

VSS_ PLL2

PA10

PI7

VSS

O le ata o loʻo i luga o loʻo faʻaalia ai le pito i luga o le afifi view.

MSv65068V5

DS13875 Faaaliga 5

51/219
97

Pinout, faʻamatalaga pine ma isi galuega

STM32MP133C/F

Laulau 6. Talatu'u/fa'apu'upu'u o lo'o fa'aogaina ile laulau fa'amau

Igoa

Faapuupuuga

Uiga

Igoa pine Ituaiga pine
I/O fausaga
Fa'amatalaga Galuega fa'aopoopo Galuega fa'aopoopo

Se'i vagana ua fa'amaoti mai, o le pine i le taimi ma pe a uma ona toe setiina e tutusa ma le pine moni

Sapalai pine

Ulufale na'o pine

Na'o pine fa'aulu

I/O

Pin fa'aulu/ulu

Analog po'o se pine fa'apitoa

FT(U/D/PD) 5 V fa'apalepale I/O (ma toso i luga / toso i lalo / toso i lalo e mafai ona fa'apolokalame)

DDR

1.5 V, 1.35 V po'o le 1.2 VI/O mo DDR3, DDR3L, LPDDR2/LPDDR3 fa'aoga

Fa'ailoga fa'atusa

RST

Toe setiina le pine i le toso i luga vaivai

_f(1) _a(2) _u(3) _h(4)

Filifiliga mo FT I/Os I2C FM+ filifiliga Analog filifiliga (tuuina mai e VDDA mo le analog vaega o le I/O) filifiliga USB (tuuina atu e VDD3V3_USBxx mo le vaega USB o le I/O) Saosaoa galuega faatino mo 1.8V typ. VDD (mo SPI, SDMMC, QUADSPI, TRACE)

_vh(5)

Filifiliga sili-maualuga-saosaoa mo 1.8V typ. VDD (mo ETH, SPI, SDMMC, QUADSPI, TRACE)

Se'i vagana ua fa'amaoti mai e se fa'amatalaga, o I/O uma ua fa'atulaga e pei o mea fa'apipi'i i le taimi ma pe a uma ona toe setiina

Galuega filifilia e ala ile GPIOx_AFR resitala

Fa'atino filifilia sa'o/fa'aagaaga e ala i tusi resitala pito i luga

1. O fausaga I/O e fesootai i le Laulau 7 o: FT_f, FT_fh, FT_fvh 2. O fausaga I/O fesootai i le Laulau 7 o: FT_a, FT_ha, FT_vha 3. O fausaga I/O e fesootai i le Laulau 7 o: FT_u 4. O fausaga I/O e fesootai i le Laulau 7: FT_a, FT_ha, FT_vha 5. FT_fvh, FT_vh, FT_ha, FT_vha 7. O fausaga I/O feso'ota'i ile Laulau XNUMX o: FT_vh, FT_vha, FT_fvh

52/219

DS13875 Faaaliga 5

STM32MP133C/F

Pinout, faʻamatalaga pine ma isi galuega

Numera Pin

Laulau 7. STM32MP133C/F fa'amatalaga polo

Galuega polo

Igoa pine (gaioiga pe a uma
toe setiina)

O galuega e suitulaga

Galuega fa'aopoopo

LFBGA289 TFBGA289 TFBGA320
Fauga I/O ituaiga pine
Fa'amatalaga

K10 F6 U14 A2 D2 A2 A1 A1 T5 M6 F3 U7
D4 E4 B2
B2 D1 B3 B1 G6 C2
C3 E2 C3 F6 D4 E7 E4 E1 B1
C2 G7 D3
C1 G3 C1

VDDCORE S

–

PA9

I/O FT_h

VSS VDD

–

PE11

I/O FT_vh

PF5

I/O FT_h

PD3

I/O FT_f

PE14

I/O FT_h

VDDCPU

–

PD0

I/O FT

PH12

I/O FT_fh

PB6

I/O FT_h

–

TIM1_CH2, I2C3_SMBA,

–

DFSDM1_DATIN0, USART1_TX, UART4_TX,

FMC_NWAIT(fa'a)

–

TIM1_CH2,

USART2_CTS/USART2_NSS,

SAI1_D2,

–

SPI4_MOSI/I2S4_SDO, SAI1_FS_A, USART6_CK,

ETH2_MII_TX_ER,

ETH1_MII_TX_ER,

FMC_D8(fa'a)/FMC_AD8

–

TRACED12, DFSDM1_CKIN0, I2C1_SMBA, FMC_A5

TIM2_CH1,

–

USART2_CTS/USART2_NSS, DFSDM1_CKOUT, I2C1_SDA,

SAI1_D3, FMC_CLK

TIM1_BKIN, SAI1_D4,

UART8_RTS/UART8_DE,

–

QUADSPI_BK1_NCS,

QUADSPI_BK2_IO2,

FMC_D11(fa'a)/FMC_AD11

–

SAI1_MCLK_A, SAI1_CK1,

–

FDCAN1_RX,

FMC_D2(fa'a)/FMC_AD2

USART2_TX, TIM5_CH3,

DFSDM1_CKIN1, I2C3_SCL,

–

SPI5_MOSI, SAI1_SCK_A, QUADSPI_BK2_IO2,

SAI1_CK2, ETH1_MII_CRS,

FMC_A6

FA'AIGA6, TIM16_CH1N,

TIM4_CH1, TIM8_CH1,

–

USART1_TX, SAI1_CK2, QUADSPI_BK1_NCS,

ETH2_MDIO, FMC_NE3,

HDP6

–
–
–
TAMP_IN6 –
–
–

DS13875 Faaaliga 5

53/219
97

Pinout, faʻamatalaga pine ma isi galuega

STM32MP133C/F

Numera Pin

Laulau 7. STM32MP133C/F fa'amatalaga polo (fa'aauau)

Galuega polo

Igoa pine (gaioiga pe a uma
toe setiina)

O galuega e suitulaga

Galuega fa'aopoopo

LFBGA289 TFBGA289 TFBGA320
Fauga I/O ituaiga pine
Fa'amatalaga

A17 A17 T17 M7 – J13 D2 G9 D2 F5 F1 E3 D1 G4 D1
E3 F2 F4 F8 D6 E10 F4 G2 E2 C8 B8 T21 E2 G1 F3
E1 G5 F2 G5 H3 F1 M8 – M5

VSS VDD PD6 PH8 PB8
PA12 VDDCPU
PH2 VSS PD11
PG9 PF8 VDD

–

I/O FT

I/O FT_fh

I/O FT_f

I/O FT_h

–

I/O FT_h

–

I/O FT_h

I/O FT_f

I/O FT_h

–

TIM16_CH1N, SAI1_D1, SAI1_SD_A, UART4_TX(fa'a)

TRACED9, TIM5_ETR,

–

USART2_RX, I2C3_SDA,

FMC_A8, HDP2

TIM16_CH1, TIM4_CH3,

I2C1_SCL, I2C3_SCL,

–

DFSDM1_DATIN1,

UART4_RX, SAI1_D1,

FMC_D13(fa'a)/FMC_AD13

TIM1_ETR, SAI2_MCLK_A,

USART1_RTS/USART1_DE,

–

ETH2_MII_RX_DV/ETH2_

RGMII_RX_CTL/ETH2_RMII_

CRS_DV, FMC_A7

–

LPTIM1_IN2, UART7_TX,

QUADSPI_BK2_IO0(fa'a),

–

ETH2_MII_CRS,

ETH1_MII_CRS, FMC_NE4,

ETH2_RGMII_CLK125

–

LPTIM2_IN2, I2C4_SMBA,

USART3_CTS/USART3_NSS,

SPDIFRX_IN0,

–

QUADSPI_BK1_IO2,

ETH2_RGMII_CLK125,

FMC_CLE(fa'a)/FMC_A16,

UART7_RX

DBTRGO, I2C2_SDA,

–

USART6_RX, SPDIFRX_IN3, FDCAN1_RX, FMC_NE2,

FMC_NCE(fa'a)

TIM16_CH1N, TIM4_CH3,

–

TIM8_CH3, SAI1_SCK_B, USART6_TX, TIM13_CH1,

QUADSPI_BK1_IO0(fa'a)

–

–
–
WKUP1
–

54/219

DS13875 Faaaliga 5

STM32MP133C/F

Pinout, faʻamatalaga pine ma isi galuega

Numera Pin

Laulau 7. STM32MP133C/F fa'amatalaga polo (fa'aauau)

Galuega polo

Igoa pine (gaioiga pe a uma
toe setiina)

O galuega e suitulaga

Galuega fa'aopoopo

LFBGA289 TFBGA289 TFBGA320
Fauga I/O ituaiga pine
Fa'amatalaga

F3 J3 H5
F9 D8 G5 F2 H1 G3 G4 G8 H4
F1 H2 G2 D3 B14 U5 G3 K2 H3 H8 F10 G2 L1 G1 D12 C5 U6 M9 K4 N7 G1 H9 J5

PG8

I/O FT_h

VDDCPU PG5

–

I/O FT_h

PG15

I/O FT_h

PG10

I/O FT_h

VSS

–

PF10

I/O FT_h

VDDCORE S

–

PF6

I/O FT_vh

VSS VDD

–

PF9

I/O FT_h

TIM2_CH1, TIM8_ETR,

SPI5_MISO, SAI1_MCLK_B,

USART3_RTS/USART3_DE,

–

SPDIFRX_IN2,

QUADSPI_BK2_IO2,

QUADSPI_BK1_IO3,

FMC_NE2, ETH2_CLK

–

TIM17_CH1, ETH2_MDC, FMC_A15

USART6_CTS/USART6_NSS,

–

UART7_CTS, QUADSPI_BK1_IO1,

ETH2_PHY_INTN

SPI5_SCK, SAI1_SD_B,

–

UART8_CTS, FDCAN1_TX, QUADSPI_BK2_IO1(fa'a),

FMC_NE3

–

TIM16_BKIN, SAI1_D3, TIM8_BKIN, SPI5_NSS, – USART6_RTS/USART6_DE, UART7_RTS/UART7_DE,
QUADSPI_CLK(fa'a)

–

TIM16_CH1, SPI5_NSS,

UART7_RX(fa'a),

–

QUADSPI_BK1_IO2, ETH2_MII_TX_EN/ETH2_

RGMII_TX_CTL/ETH2_RMII_

TX_EN

–

TIM17_CH1N, TIM1_CH1,

DFSDM1_CKIN3, SAI1_D4,

–

UART7_CTS, UART8_RX, TIM14_CH1,

QUADSPI_BK1_IO1(fa'a),

QUADSPI_BK2_IO3, FMC_A9

TAMP_IN4
–
TAMP_IN1 –

DS13875 Faaaliga 5

55/219
97

Pinout, faʻamatalaga pine ma isi galuega

STM32MP133C/F

Numera Pin

Laulau 7. STM32MP133C/F fa'amatalaga polo (fa'aauau)

Galuega polo

Igoa pine (gaioiga pe a uma
toe setiina)

O galuega e suitulaga

Galuega fa'aopoopo

LFBGA289 TFBGA289 TFBGA320
Fauga I/O ituaiga pine
Fa'amatalaga

H5 K1 H2 H6 E5 G7 H4 K3 J3 E5 D13 U11 H3 L3 J1
H1 H7 K3
J1 N1 J2 J5 J1 K2 J4 J2 K1 H2 H8 L4 K4 M3 M3

PE4 VDDCPU
PB2 VSS PH7
PH11
PD13 VDD_PLL VSS_PLL
PI3 PC13

I/O FT_h

–

I/O FT_h

–

I/O FT_fh

I/O FT_h

–

I/O FT

SPI5_MISO, SAI1_D2,

DFSDM1_DATIN3,

TIM15_CH1N, I2S_CKIN,

–

SAI1_FS_A, UART7_RTS/UART7_DE,

–

UART8_TX,

QUADSPI_BK2_NCS,

FMC_NCE2, FMC_A25

–

RTC_OUT2, SAI1_D1,

I2S_CKIN, SAI1_SD_A,

–

UART4_RX,

QUADSPI_BK1_NCS(fa'a),

ETH2_MDIO, FMC_A6

TAMP_IN7

–

SAI2_FS_B, I2C3_SDA,

SPI5_SCK,

–

QUADSPI_BK2_IO3, ETH2_MII_TX_CLK,

–

ETH1_MII_TX_CLK,

QUADSPI_BK1_IO3

SPI5_NSS, TIM5_CH2,

SAI2_SD_A,

SPI2_NSS/I2S2_WS,

–

I2C4_SCL, USART6_RX, QUADSPI_BK2_IO0,

–

ETH2_MII_RX_CLK/ETH2_

RGMII_RX_CLK/ETH2_RMII_

REF_CLK, FMC_A12

LPTIM2_ETR, TIM4_CH2,

TIM8_CH2, SAI1_CK1,

–

SAI1_MCLK_A, USART1_RX, QUADSPI_BK1_IO3,

–

QUADSPI_BK2_IO2,

FMC_A18

–

(1)

SPDIFRX_IN3,

TAMP_IN4/TAMP_

ETH1_MII_RX_ER

OUT5, WKUP2

RTC_OUT1/RTC_TS/

(1)

–

RTC_LSCO, TAMP_IN1/TAMP_

OUT2, WKUP3

56/219

DS13875 Faaaliga 5

STM32MP133C/F

Pinout, faʻamatalaga pine ma isi galuega

Numera Pin

Laulau 7. STM32MP133C/F fa'amatalaga polo (fa'aauau)

Galuega polo

Igoa pine (gaioiga pe a uma
toe setiina)

O galuega e suitulaga

Galuega fa'aopoopo

LFBGA289 TFBGA289 TFBGA320
Fauga I/O ituaiga pine
Fa'amatalaga

J3 J4 N5

PI2

I/O FT

(1)

SPDIFRX_IN2

TAMP_IN3/TAMP_ OUT4, WKUP5

K5 N4 P4

PI1

I/O FT

(1)

SPDIFRX_IN1

RTC_OUT2/RTC_ LSCO,
TAMP_IN2/TAMP_ OUT3, WKUP4

F13 L2 U13

VSS

–

J2 J5 L2

VBAT

–

L4 N3 P5

PI0

I/O FT

(1)

SPDIFRX_IN0

TAMP_IN8/TAMP_ OUT1

K2 M2

PC15OSC32_OUT

I/O

(1)

–

OSC32_OUT

F15 N2 U16

VSS

–

K1 M1 M2

PC14OSC32_IN

I/O

(1)

–

OSC32_IN

G7 E3 V16

VSS

–

H9 K6 N15 VDDCORE S

–

M10 M4 N9

VDD

–

G8 E6 W16

VSS

–

USART2_RX,

L2 P3 N2

PF4

I/O FT_h

–

ETH2_MII_RXD0/ETH2_ RGMII_RXD0/ETH2_RMII_

–

RXD0, FMC_A4

MCO1, SAI2_MCLK_A,

TIM8_BKIN2, I2C4_SDA,

SPI5_MISO, SAI2_CK1,

M2 J8 P2

PA8

I/O FT_fh –

USART1_CK, SPI2_MOSI/I2S2_SDO,

–

OTG_HS_SOF,

ETH2_MII_RXD3/ETH2_

RGMII_RXD3, FMC_A21

TRACECLK, TIM2_ETR,

I2C4_SCL, SPI5_MOSI,

SAI1_FS_B,

L1 T1 N1

PE2

I/O FT_fh

–

USART6_RTS/USART6_DE, SPDIFRX_IN1,

–

ETH2_MII_RXD1/ETH2_

RGMII_RXD1/ETH2_RMII_

RXD1, FMC_A23

DS13875 Faaaliga 5

57/219
97

Pinout, faʻamatalaga pine ma isi galuega

STM32MP133C/F

Numera Pin

Laulau 7. STM32MP133C/F fa'amatalaga polo (fa'aauau)

Galuega polo

Igoa pine (gaioiga pe a uma
toe setiina)

O galuega e suitulaga

Galuega fa'aopoopo

LFBGA289 TFBGA289 TFBGA320
Fauga I/O ituaiga pine
Fa'amatalaga

M1 J7 P3

PF7

I/O FT_vh –

M3 R1 R2

PG11

I/O FT_vh –

L3 J6 N3

PH6

I/O FT_fh –

N2 P4 R1

PG1

I/O FT_vh –

M11 – N12

VDD

–

N1 R2 T2

PE6

I/O FT_vh –

P1 P1 T3 PH0-OSC_IN I/O FT

–

G9 U1 N11

VSS

–

P2 P2 U2 PH1-OSC_OUT I/O FT

–

R2 T2 R3

PH3

I/O FT_fh –

M5 L5 U3 VSS_ANA S

–

TIM17_CH1, UART7_TX(fa'a),
UART4_CTS, ETH1_RGMII_CLK125, ETH2_MII_TXD0/ETH2_ RGMII_TXD0/ETH2_RMII_
TXD0, FMC_A18
SAI2_D3, I2S2_MCK, USART3_TX, UART4_TX, ETH2_MII_TXD1/ETH2_ RGMII_TXD1/ETH2_RMII_
TXD1, FMC_A24
TIM12_CH1, USART2_CK, I2C5_SDA,
SPI2_SCK/I2S2_CK, QUADSPI_BK1_IO2,
ETH1_PHY_INTN, ETH1_MII_RX_ER, ETH2_MII_RXD2/ETH2_
RGMII_RXD2, QUADSPI_BK1_NCS
LPTIM1_ETR, TIM4_ETR, SAI2_FS_A, I2C2_SMBA,
SPI2_MISO/I2S2_SDI, SAI2_D2, FDCAN2_TX, ETH2_MII_TXD2/ETH2_ RGMII_TXD2, FMC_NBL0
–
MCO2, TIM1_BKIN2, SAI2_SCK_B, TIM15_CH2, I2C3_SMBA, SAI1_SCK_B, UART4_RTS/UART4_DE,
ETH2_MII_TXD3/ETH2_ RGMII_TXD3, FMC_A22
–
–
–
I2C3_SCL, SPI5_MOSI, QUADSPI_BK2_IO1, ETH1_MII_COL, ETH2_MII_COL, QUADSPI_BK1_IO0
–

–
–
–
OSC_IN OSC_OUT –

58/219

DS13875 Faaaliga 5

STM32MP133C/F

Pinout, faʻamatalaga pine ma isi galuega

Numera Pin

Laulau 7. STM32MP133C/F fa'amatalaga polo (fa'aauau)

Galuega polo

Igoa pine (gaioiga pe a uma
toe setiina)

O galuega e suitulaga

Galuega fa'aopoopo

LFBGA289 TFBGA289 TFBGA320
Fauga I/O ituaiga pine
Fa'amatalaga

L5 U2 W1

PG3

I/O FT_fvh –

TIM8_BKIN2, I2C2_SDA, SAI2_SD_B, FDCAN2_RX, ETH2_RGMII_GTX_CLK,
ETH1_MDIO, FMC_A13

M4 L4 V2 VDD_ANA S

–

R1 U3 V3

PG2

I/O FT

–

MCO2, TIM8_BKIN, SAI2_MCLK_B, ETH1_MDC

T1 L6 W2

PG12

I/O FT

LPTIM1_IN1, SAI2_SCK_A,

SAI2_CK2,

USART6_RTS/USART6_DE,

USART3_CTS,

–

ETH2_PHY_INTN,

ETH1_PHY_INTN,

ETH2_MII_RX_DV/ETH2_

RGMII_RX_CTL/ETH2_RMII_

CRS_DV

U7 P6 R5

VDD

–

G10 E8 T1

VSS

–

N3 R3 V1

MCO1, USART2_CK,

I2C2_SCL, I2C3_SDA,

SPDIFRX_IN0,

PD7

I/O FT_fh

–

ETH1_MII_RX_CLK/ETH1_ RGMII_RX_CLK/ETH1_RMII_

REF_CLK,

QUADSPI_BK1_IO2,

FMC_NE1

P3 K7 T4

PA13

I/O FT

–

DBTRGO, DBTRGI, MCO1, UART4_TX

R3 R4 W3 PWR_CPU_ON O FT

–

T2 N5 Y1

PA11

I/O FT_f

TIM1_CH4, I2C5_SCL,

SPI2_NSS/I2S2_WS,

USART1_CTS/USART1_NSS,

–

ETH2_MII_RXD1/ETH2_

RGMII_RXD1/ETH2_RMII_

RXD1, ETH1_CLK,

ETH2_CLK

N5 M6 AA2

PB11

TIM2_CH4, LPTIM1_OUT,

I2C5_SMBA, USART3_RX,

I/O FT_vh –

ETH1_MII_TX_EN/ETH1_

RGMII_TX_CTL/ETH1_RMII_

TX_EN

–
–
–
FA'AVAE -
–

DS13875 Faaaliga 5

59/219
97

Pinout, faʻamatalaga pine ma isi galuega

STM32MP133C/F

Numera Pin

Laulau 7. STM32MP133C/F fa'amatalaga polo (fa'aauau)

Galuega polo

Igoa pine (gaioiga pe a uma
toe setiina)

O galuega e suitulaga

Galuega fa'aopoopo

LFBGA289 TFBGA289 TFBGA320
Fauga I/O ituaiga pine
Fa'amatalaga

P4 U4

PF14(JTCK/SW CLK)

I/O

(2)

U3 L7 Y3

PA0

I/O FT_a –

JTCK/SWCLK
TIM2_CH1, TIM5_CH1, TIM8_ETR, TIM15_BKIN, SAI1_SD_B, UART5_TX,
ETH1_MII_CRS, ETH2_MII_CRS

N6 T3 W4

PF13

TIM2_ETR, SAI1_MCLK_B,

I/O FT_a –

DFSDM1_DATIN3,

USART2_TX, UART5_RX

G11 E10 P7

F10 –

–

R4 K8 AA3

P5 R5 Y4 U4 M7 Y5

VSS VDD PA1
PA2
PA5

–

I/O FT_a

I/O FT_a I/O FT_a

–

TIM2_CH2, TIM5_CH2, LPTIM3_OUT, TIM15_CH1N,
DFSDM1_CKIN0, – USART2_RTS/USART2_DE,
ETH1_MII_RX_CLK/ETH1_ RGMII_RX_CLK/ETH1_RMII_
REF_CLK

TIM2_CH3, TIM5_CH3, – LPTIM4_OUT, TIM15_CH1,
USART2_TX, ETH1_MDIO

TIM2_CH1/TIM2_ETR,

USART2_CK, TIM8_CH1N,

–

SAI1_D1, SPI1_NSS/I2S1_WS,

SAI1_SD_A, ETH1_PPS_OUT,

ETH2_PPS_OUT

T3 T4 W5

SAI1_SCK_A, SAI1_CK2,

PC0

I/O FT_ha –

I2S1_MCK, SPI1_MOSI/I2S1_SDO,

USART1_TX

T4 J9 AA4
R6 U6 W7 P7 U5 U8 P6 T6 V8

PF12

I/O FT_vha –

VREF+

–

VDDA

–

VREF-

–

SPI1_NSS/I2S1_WS, SAI1_SD_A, UART4_TX,
ETH1_MII_TX_ER, ETH1_RGMII_CLK125
–
–
–

–
ADC1_INP7, ADC1_INN3, ADC2_INP7, ADC2_INN3 ADC1_INP11, ADC1_INN10, ADC2_INP11, ADC2_INN10
–
ADC1_INP3, ADC2_INP3
ADC1_INP1, ADC2_INP1
ADC1_INP2
ADC1_INP0, ADC1_INN1, ADC2_INP0, ADC2_INN1, TAMP_IN3
ADC1_INP6, ADC1_INN2
–

60/219

DS13875 Faaaliga 5

STM3

Pepa / Punaoa

STMicroelectronics STM32MP133C F 32-bit Arm Cortex-A7 1GHz MPU [pdf] Taiala mo Tagata Fa'aoga
STM32MP133C F 32-bit Arm Cortex-A7 1GHz MPU, STM32MP133C, F 32-bit Arm Cortex-A7 1GHz MPU, Arm Cortex-A7 1GHz MPU, 1GHz, MPU

Fa'asinomaga

Tusi Taiala

STMicroelectronics STM32MP133C F 32-bit Arm Cortex-A7 1GHz MPU

Fa'amatalaga

Arm Cortex-A7 Subsystem

Faamanatuga

DDR Pule

FAQs

Pepa / Punaoa

Fa'asinomaga

Tuu se faamatalaga

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