STMicroelectronics STM32MP133C F 32-bit Arm Cortex-A7 1GHz MPU

Nā kikoʻī

• Ke kumu: Arm Cortex-A7
• Hoʻomanaʻo: SDRAM waho, SRAM i hoʻopili ʻia
• Kaʻa Kaʻa ʻIkepili: 16-bit parallel interface
• Palekana / Palekana: Hoʻoponopono a me ka Mana Mana, LPLV-Stop2, Standby
• Pūʻolo: LFBGA, TFBGA me ka min pitch 0.5 mm
• Hooponopono Uaki
• Hoʻokomo/Hana i ka manaʻo nui
• Pākuʻi pili
• 4 Nā mea hoʻoponopono DMA
• Nā Peripheral Communications: A hiki i ka 29
• Analog Peripheral: 6
• Nā manawa: a hiki i 24, kiaʻi: 2
• ʻO ka wikiwiki o nā lako lako
• ʻAno hoʻopololei
• Fuses: 3072-bit me ka ID kūikawā a me ka HUK no nā kī AES 256
• ECOPACK2 hoʻokō

Pūnaehana Pūnaehana ʻAlima Cortex-A7

Hāʻawi ka Arm Cortex-A7 subsystem o ka STM32MP133C/F…

Hoʻomanaʻo

Loaʻa i ka hāmeʻa ka SDRAM waho a me ka SRAM i hoʻopaʻa ʻia no ka mālama ʻikepili…

Hoʻoponopono DDR

Hoʻokele ka mea hoʻokele DDR3/DDR3L/LPDDR2/LPDDR3 i ke komo hoʻomanaʻo…

Mana Mana Mana
Hoʻopaʻa ka mana lako mana a me ka luna hoʻomalu i ka hoʻopuka mana paʻa…

Hooponopono Uaki
Mālama ka RCC i ka hāʻawi ʻana i ka uaki a me nā hoʻonohonoho…

Hoʻokomo/Hana i ka manaʻo nui (GPIO)
Hāʻawi nā GPIO i nā mea hiki ke hoʻohana no nā polokalamu waho ...

Manaʻo hoʻomalu TrustZone
Hoʻonui ka ETZPC i ka palekana ʻōnaehana ma o ka hoʻokele ʻana i nā kuleana komo…

Kaʻa-Interconnect Matrix
Mālama ka matrix i ka hoʻoili ʻikepili ma waena o nā modula like ʻole…

FAQs

Nīnau: He aha ka helu kiʻekiʻe o nā peripheral kamaʻilio i kākoʻo ʻia?
A: Kākoʻo ka STM32MP133C/F i 29 mau kikowaena kamaʻilio.

Nīnau: ʻEhia mau peripherals analog i loaʻa?
A: Hāʻawi ka hāmeʻa i nā peripheral analog 6 no nā hana analog like ʻole.

“`

STM32MP133C STM32MP133F

Arm® Cortex®-A7 a hiki i 1 GHz, 2×ETH, 2×CAN FD, 2×ADC, 24 mau manawa, leo, crypto a me adv. palekana
Pepa ʻikepili - ʻikepili hana

Nā hiʻohiʻona
Loaʻa iā ST ka ʻenehana patent ʻia
Core
· 32-bit Arm® Cortex®-A7 L1 32-Kbyte I / 32-Kbyte D 128-Kbyte i hui pū ʻia me ka pae 2 cache Arm® NEONTM a me Arm® TrustZone®

Hoʻomanaʻo
· Hoʻomanaʻo DDR waho a hiki i 1 Gbyte a hiki i LPDDR2/LPDDR3-1066 16-bit a hiki i DDR3/DDR3L-1066 16-bit
· 168 Kbytes o SRAM i loko: 128 Kbytes o AXI SYSRAM + 32 Kbytes o AHB SRAM a me 8 Kbytes o SRAM ma ka waihona Backup
· ʻElua Quad-SPI hoʻomanaʻo hoʻomanaʻo · Hoʻoponopono hoʻomanaʻo waho maʻalahi a hiki i
16-bit data bus: pili pili e hoʻopili i nā IC waho a me nā hoʻomanaʻo SLC NAND a hiki i ka 8-bit ECC
Palekana/palekana
· Paʻa paʻa, TrustZone® peripherals, 12 xtamper pine me 5 x active tampers
· Mahana, voltage, alapine a me 32 kHz nānā
Hoʻonohonoho hou a me ka hoʻokele mana
· 1.71 V a 3.6 VI/Os lako (5 V-hoomanawanui I/Os) · POR, PDR, PVD a me BOR · On-chip LDOs (USB 1.8 V, 1.1 V) · Backup regulator (~ 0.9 V) · Kuloko wela sensors Low-mana modes: Moe, Stop, LPLV-Stop
LPLV-Stop2 a me ka Standby

LFBGA

TFBGA

LFBGA289 (14 × 14mm) Pitch 0.8 mm

TFBGA289 (9 × 9 mm) TFBGA320 (11 × 11 mm)
min pitch 0.5 mm

· Paʻa DDR ma ke ʻano Standby · Nā mana no ka puʻupuʻu hoa PMIC

Hoʻoponopono uaki
· Nā oscillator i loko: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz LSI oscillator
· Nā oscillator o waho: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator
· 4 × PLL me ke ʻano hakina

Nā mea hoʻokomo/puka kumu nui
· A hiki i 135 mau awa I/O paa me ka hiki ke hoopau
· A hiki i 6 ala ala

matrix pili
· 2 matrices bus 64-bit Arm® AMBA® AXI interconnect, a hiki i ka 266 MHz 32-bit Arm® AMBA® AHB interconnect, a hiki i ka 209 MHz

4 DMA kaohi e wehe i ka CPU
· 56 mau ala kino i ka huina
· 1 x kiʻekiʻe-kiʻekiʻe-nui kumu nui kumu hoʻoponopono hoʻomanaʻo pololei (MDMA)
· 3 × DMA mau awa lua me FIFO a noi i nā mea hiki ke alalai no ka hoʻokele peripheral maikaʻi loa

Kepakemapa 2024
He ʻike kēia e pili ana i kahi huahana i ka hana piha.

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www.st.com

STM32MP133C/F

A hiki i 29 mau kikowaena pili
· 5 × I2C FM+ (1 Mbit/s, SMBus/PMBusTM) · 4 x UART + 4 x USART (12.5 Mbit/s,
ISO7816 interface, LIN, IrDA, SPI) · 5 × SPI (50 Mbit/s, me 4 me ka piha-duplex
ʻO ka pololei o ka papa leo I2S ma o ka PLL leo kūloko a i ʻole ka uaki waho)(+2 QUADSPI + 4 me USART) · 2 × SAI (leo stereo: I2S, PDM, SPDIF Tx) · SPDIF Rx me nā hoʻokomo 4 · 2 × SDMMC a hiki i 8 bits (SD/e·MMCTM/SDIO) × kākoʻo 2 × CADIO. Host kiʻekiʻe a i ʻole 2 × USB 2.0 kiʻekiʻe-wikiwiki Host

+ 1 × USB 2.0 kiʻekiʻe-wikiō OTG i ka manawa like · 2 x Ethernet MAC/GMAC IEEE 1588v2 lako lako, MII/RMII/RGMII
6 mau kikowaena analog
· 2 × ADC me 12-bit max. hoʻonā a hiki i ka 5 Msps
· 1 x ʻike wela · 1 x kānana kikohoʻe no ka modulator sigma-delta
(DFSDM) me nā kaha 4 a me nā kānana 2 · Kūloko a i ʻole waho ADC reference VREF+
A hiki i 24 mau manawa a me 2 mau ʻīlio kiaʻi
· 2 × 32-bit timers a hiki i ka 4 IC/OC/PWM a i ʻole pulse counter a me quadrature (incremental) encoder input
· 2 × 16-bit nā manawa holomua · 10 × 16-bit nā manawa hana maʻamau (me
2 mau manawa maʻamau me ka PWM ʻole) · 5 × 16-bit mau mana haʻahaʻa haʻahaʻa · Paʻa RTC me ka pololei ʻāpana-kekona a
'alemanaka lako kamepiula · 4 Cortex®-A7 ʻōnaehana manawa (paʻa,
palekana ʻole, virtual, hypervisor) · 2 × mau ʻīlio kiaʻi kūʻokoʻa
ʻO ka wikiwiki o nā lako
· AES 128, 192, 256 DES/TDES

2 (kūʻokoʻa, palekana kūʻokoʻa) 5 (2 palekana) 4 5 (3 palekana)
4 + 4 (me 2 USART i hoʻopaʻa ʻia), hiki i kekahi ke lilo i kumu boot
2 (a hiki i 4 mau leo ​​leo), me I2S master/slave, PCM input, SPDIF-TX 2 awa.
HSPHY Hoʻokomo ʻia me BCD Hoʻokomo ʻia ʻo HS PHY me BCD (paʻa), hiki ke lilo i kumu pahu
2 × HS kaʻana ma waena o Host a me OTG 4 hoʻokomo

2 (1 × TTCAN), calibration uaki, 10 Kbyte puʻupuʻu kaʻana like 2 (8 + 8 bits) (securable), e·MMC a i ʻole SD hiki ke lilo i kumu boot 2 koho i nā lako mana kūʻokoʻa no nā pā kāleka SD
1 (dual-quad) (securable), hiki ke lilo i kumu boot

–
–
Boot
–
Boot
Pua Pua
(1)

Helu helu/ʻikepili 8/16-bit FMC Parallel AD-mux 8/16-bit
NAND 8/16-bit 10/100M/Gigabit Ethernet DMA Cryptography
Hash True huahelu huahelu Fuses (hoʻokahi-manawa programmable)

4 × CS, a hiki i 4 × 64 Mbyte
ʻAe, 2 × CS, SLC, BCH4/8, hiki ke lilo i kumu kumu 2 x (MII, RMI, RGMII) me PTP a me EEE (hiki ke palekana)
3 manawa (1 palekana), 33-kanela MDMA PKA (me ka pale DPA), DES, TDES, AES (me ka pale DPA)
(hiki ke palekana) SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-3, HMAC
(securable) ʻOiaʻiʻo-RNG (securable) 3072 mau bits kūpono (palekana, 1280 mau bits i loaʻa no ka mea hoʻohana)

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Kāpae –
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DS13875 Hōʻike 5

STM32MP133C/F

wehewehe

Papa 1. Nā hiʻohiʻona STM32MP133C/F a me nā helu āpau (hoʻomau ʻia)

STM32MP133CAE STM32MP133FAE STM32MP133CAG STM32MP133FAG STM32MP133CAF STM32MP133FAF Nā mea like ʻole

Nā hiʻohiʻona

LFBGA289

TFBGA289

TFBGA320

Nā GPIO me ke keakea (helu helu)

135(2)

Nā pine Wakeup GPIO hiki ke hoʻopaʻa ʻia

ʻO nā mea a pau
6

Tampnā pine (tampa)

12 (5)

DFSDM A hiki i ka 12-bit synchronized ADC

4 mau ala komo me 2 kānana

–

2(3) (a hiki i 5 Msps ma 12-bit kēlā me kēia) (hiki ke palekana)

ADC1: 19 mau ala me 1x i loko, 18 mau kaha i loaʻa no

He 12-bit ADC ka nui (4)

mea hoʻohana me 8x ʻokoʻa

–

ADC2: 18 mau ala me 6x i loko, 12 mau kaha i loaʻa no

mea hoʻohana me 6x ʻokoʻa

Paʻa hoʻokomo ADC VREF VREF+ kūloko

1.65 V, 1.8 V, 2.048 V, 2.5 V a i ʻole VREF+ hoʻokomo –
ʻAe

1. Hiki i ka QUADSPI ke hoʻopaʻa mai nā GPIO i hoʻolaʻa ʻia a i ʻole ka hoʻohana ʻana i kekahi mau FMC Nand8 boot GPIO (PD4, PD1, PD5, PE9, PD11, PD15 (e nānā i ka Papa 7: STM32MP133C/F wehewehe pōlele).
2. Aia kēia helu helu GPIO ʻehā JTAG ʻO nā GPIO a me ʻekolu BOOT GPIO me ka hoʻohana palena ʻia (hiki ke paio me ka pilina o waho i ka wā o ka nānā ʻana a i ʻole ka boot).
3. Ke hoʻohana ʻia nā ADC ʻelua, pono e like ka uaki kernel no nā ADC ʻelua a ʻaʻole hiki ke hoʻohana ʻia nā prescalers ADC i hoʻokomo ʻia.
4. Eia kekahi, aia kekahi mau ala i loko: - ADC1 i loko: VREFINT - ADC2 mau ala i loko: wela, vol kūlokotage kuhikuhi, VDDCORE, VDDCPU, VDDQ_DDR, VBAT / 4.

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STM32MP133C/F

Kiʻi 1. STM32MP133C/F kiʻina poloka

lako IC

@VDDA

Naʻauao

AXIM: Hoʻopili lima 64-bit AXI (266 MHz) T

@VDDCPU

GIC

T

Cortex-A7 CPU 650/1000 MHz + MMU + FPU + NEONT

32K D$

32K I$

CNT (ka manawa) T

ETM

T

2561K2B8LK2B$L+2$SCU T
async

128 bit

TT

CSI

LSI

ʻO ka manawa debugamp

mīkini hana TSGEN

T

DAP
(JTAG/SWD)

SYSRAM 128KB

ROM 128KB

38

2 x ETH MAC
10/100/1000(ʻaʻohe GMII)

FIFO

TT

T

BKPSRAM 8KB

T

RNG

T

HASH

16b PHY

DDRCTRL 58
LPDDR2/3, DDR3/3L

async

T

CRYP

T

SAES

DDRMCE T TZC T

DDRPHYC
T

13

DLY

8b QUADSPI (ʻelua) T

37

16b

FMC

T

CRC

T

DLYBSD1

(SDMMC1 DLY mana)

T

DLYBSD2

(SDMMC2 DLY mana)

T

DLYBQS

(QUADSPI DLY mana)

FIFO FIFO

DLY DLY

14 8b SDMMC1 T 14 8b SDMMC2 T

PHY

2

USBH

2

(2xHS Host)

PLUSB

FIFO

T

PKA

FIFO

T MDMA 32 auwai

AXIMC TT

17 16b Kaha kiʻi

ETZPC

T

IWDG1

T

@VBAT

BSEC

T

OTP Fuses

@VDDA

2

RTC / AWU

T

12

TAMP / Hoʻopaʻa i nā regs T

@VBAT

2

LSE (32kHz XTAL)

T

Pūnaehana manawa STGENC

hanauna

STGENR

USBPHYC
(USB 2 x PHY mana)
IWDG2

@VBAT

@VDDA

1

VREFBUF

T

4

16b LPTIM2

T

1

16b LPTIM3

T

1

16b LPTIM4

1

16b LPTIM5

3

Nā pine BOOT

SYSCFG

T

8

8b

HDP

10 16b TIM1/PWM 10 16b TIM8/PWM

13

SAI1

13

SAI2

9

4ch DFSDM

Hoʻopaʻa 10KB CCU

4

FDCAN1

4

FDCAN2

FIFO FIFO
APB2 (100 MHz)

8KB FIFO
APB5 (100MHz)

APB3 (100 MHz)

APB4

async AHB2APB

SRAM1 16KB T SRAM2 8KB T SRAM3 8KB T

AHB2APB

DMA1
8 kahawai
DMAMUX1
DMA2
8 kahawai

DMAMUX2

DMA3
8 kahawai

T

PMB (nānā kaʻina hana)
DTS (ka mea ʻike wela kikohoʻe)

Voltage hooponopono

@VDDA

Mālama lako

FIFO

FIFO

FIFO

2×2 Matrix
AHB2APB

64 bits AXI

64bits AXI haku

32 bits AHB 32 bits AHB haku

32 mau bit APB

T TrustZone palekana palekana

AHB2APB

APB2 (100 MHz)

APB1 (100 MHz)
FIFO FIFO FIFO FIFO FIFO FIFO

MLAHB: Mana lima 32-bit multi-AHB matrix (209 MHz)
APB6
FIFO FIFO FIFO FIFO

@VBAT
T
FIFO

HSE (XTAL)

2

PLL1/2/3/4

T

RCC

5

T PWR

9

T

EXTI

16ext

176

T

USBO

(OTG HS)

PHY

2

T

12b ADC1

18

T

12b ADC2

18

T

GPIOA

16b

16

T

GPIOB

16b

16

T

GPIOC

16b

16

T

GPIOD

16b

16

T

GPIOE

16b

16

T

GPIOF

16b

16

T

GPIOG 16b 16

T

GPIOH

16b

15

T

GPIOI

16b

8

AHB2APB

T

USART1

Kāleka akamai IrDA

5

T

USART2

Kāleka akamai IrDA

5

T

SPI4/I2S4

5

T

SPI5

4

T

I2C3/SMBUS

3

T

I2C4/SMBUS

3

T

I2C5/SMBUS

3

Kānana kānana kānana

T

TIM12

16b

2

T

TIM13

16b

1

T

TIM14

16b

1

T

TIM15

16b

4

T

TIM16

16b

3

T

TIM17

16b

3

TIM2 TIM3 TIM4

32b

5

16b

5

16b

5

TIM5 TIM6 TIM7

32b

5

16b

16b

LPTIM1 16b

4

USART3

Kāleka akamai IrDA

5

UART4

4

UART5

4

UART7

4

UART8

4

Kānana kānana

I2C1/SMBUS

3

I2C2/SMBUS

3

SPI2/I2S2

5

SPI3/I2S3

5

USART6

Kāleka akamai IrDA

5

SPI1/I2S1

5

FIFO FIFO

FIFO FIFO

MSv67509V2

DS13875 Hōʻike 5

STM32MP133C/F

3

Pau ka hanaview

Pau ka hanaview

3.1
3.1.1
3.1.2

Pūnaehana lima ʻo Arm Cortex-A7
Nā hiʻohiʻona
· ARMv7-A hoʻolālā · 32-Kbyte L1 aʻo huna · 32-Kbyte L1 ʻikepili cache · 128-Kbyte level2 cache · Arm + Thumb®-2 hoʻonohonoho aʻo · Arm TrustZone ʻenehana palekana · Arm NEON advanced SIMD · DSP a me SIMD hoʻonui · VFPv4 floating-point · Hardware virtualization kākoʻo · (Embedded trace) 160 kaʻana like ʻana i nā mea āpau · Integrated generic timer (CNT)
Pauview
ʻO ke kaʻina hana Cortex-A7 he mea hoʻohana pono i ka ikehu i hoʻolālā ʻia e hāʻawi i ka hana waiwai i nā lole lole kiʻekiʻe, a me nā noi haʻahaʻa haʻahaʻa i hoʻopili ʻia a me nā mea kūʻai aku. Hāʻawi ia i ka 20% ʻoi aku ka nui o ka hana pae hoʻokahi ma mua o ka Cortex-A5 a hāʻawi i ka hana like ma mua o ka Cortex-A9.
Hoʻokomo ka Cortex-A7 i nā hiʻohiʻona a pau o nā kaʻina hana kiʻekiʻe ʻo Cortex-A15 a me CortexA17, me ke kākoʻo virtualization i nā lako, NEON, a me 128-bit AMBA 4 AXI bus interface.
Kūkulu ʻia ka mea hana Cortex-A7 ma luna o ka 8-s ikaikatage pipeline o ke kaʻina hana Cortex-A5. Loaʻa iā ia ka pōmaikaʻi mai kahi cache L2 i hoʻohui ʻia i hoʻolālā ʻia no ka mana haʻahaʻa, me nā latency kālepa haʻahaʻa a hoʻomaikaʻi i ke kākoʻo OS no ka mālama ʻana i ka cache. Ma luna o kēia, ua hoʻomaikaʻi ʻia ka wānana lālā a me ka hoʻomaikaʻi ʻana i ka hana ʻōnaehana hoʻomanaʻo, me 64-bit loadstore ala, 128-bit AMBA 4 AXI buses a hoʻonui i ka nui TLB (256 komo, mai ka 128 komo no Cortex-A9 a me Cortex-A5), hoʻonui i ka hana no nā hana nui e like me web mākaʻikaʻi.
ʻenehana Thumb-2
Hāʻawi i ka hana kiʻekiʻe o ka code Arm kuʻuna ʻoiai e hāʻawi ana i kahi hōʻemi o 30% i ka pono hoʻomanaʻo no ka mālama ʻana i nā kuhikuhi.
ʻenehana TrustZone
E hōʻoia i ka hoʻokō pono ʻana i nā noi palekana mai ka hoʻokele pono kīwila i ka uku uila. Kākoʻo nui mai ka ʻenehana a me nā hoa hana.

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Pau ka hanaview

STM32MP133C/F

NEON
Hiki i ka ʻenehana NEON ke hoʻolalelale i nā algorithms multimedia a me nā hōʻailona e like me ka video encode/decode, 2D/3D kiʻi, pāʻani, leo a me ka hoʻoponopono ʻōlelo, ka hoʻoili kiʻi, kelepona, a me ke kani kani. Hāʻawi ka Cortex-A7 i ka mīkini e hāʻawi ana i ka hana a me ka hana o ka Cortex-A7 floating-point unit (FPU) a me ka hoʻokō ʻana i ka NEON advanced SIMD aʻoaʻo i hoʻonohonoho ʻia no ka wikiwiki o ka media a me nā hana hoʻoili hōʻailona. Hoʻonui ka NEON i ka FPU kaʻina Cortex-A7 e hāʻawi i kahi quad-MAC a me 64-bit a me 128-bit hoʻopaʻa inoa hou e kākoʻo ana i kahi pūʻulu waiwai o nā hana SIMD ma luna o 8-, 16- a me 32-bit integer a me 32-bit floating-point data nui.
ʻO ka virtualization hardware
ʻO ke kākoʻo ʻenehana maikaʻi loa no ka hoʻokele ʻikepili a me ka hoʻopaʻapaʻa ʻana, kahi e hiki ai i nā ʻōnaehana polokalamu he nui a me kā lākou mau noi ke komo i ka mana o ka ʻōnaehana. ʻO kēia ka mea e hiki ai ke ʻike i nā mea paʻa, me nā kaiapuni virtual i hoʻokaʻawale maikaʻi ʻia mai kekahi i kekahi.
Hoʻonui ʻia nā ʻāpana L1
Hoʻohui ka hana a me ka mana i hoʻopaʻa ʻia i nā cache L1 i nā ʻenehana latency hiki ke hoʻonui i ka hana a hōʻemi i ka hoʻohana mana.
Hoʻopili ʻia ka mea hoʻokele huna L2
Hāʻawi i ka haʻahaʻa haʻahaʻa a me ka bandwidth kiʻekiʻe i ke komo ʻana i ka hoʻomanaʻo huna ʻia ma ke alapine kiʻekiʻe, a i ʻole e hōʻemi i ka hoʻohana ʻana i ka mana e pili ana me ke komo ʻana i ka hoʻomanaʻo off-chip.
ʻĀpana kiko lana ʻo Cortex-A7 (FPU)
Hāʻawi ka FPU i nā ʻōlelo kuhikuhi floating-point kiʻekiʻe a me ʻelua i kūpono me ka hoʻolālā Arm VFPv4 i kūpono i ka polokalamu me nā hanauna o mua o Arm floating-point coprocessor.
ʻĀpana hoʻomalu Snoop (SCU)
Na ka SCU ke kuleana no ka mālama ʻana i ka interconnect, arbitration, communication, cache to cache and system memory transfers, cache coherence and other capables for the processor.
Hoʻemi pū kēia ʻōnaehana ʻōnaehana i ka paʻakikī o ka polokalamu i ka mālama ʻana i ka lokahi polokalamu i loko o kēlā me kēia mea hoʻokele OS.
Mea hoʻoponopono hoʻopau maʻamau (GIC)
Ke hoʻokō nei i ka mea hoʻoponopono interruptized standardized a i kūkulu ʻia, hāʻawi ka GIC i kahi ala waiwai a maʻalahi i ke kamaʻilio inter-processor a me ke alahele a me ka hoʻonohonoho mua ʻana o nā ʻōnaehana.
Kākoʻo ʻana a hiki i 192 mau hoʻopalekana kūʻokoʻa, ma lalo o ka mana lako polokalamu, hoʻonohonoho pono ʻia nā lako, a hoʻokele ʻia ma waena o ka ʻōnaehana hana a me ka papa hoʻokele polokalamu TrustZone.
ʻO kēia alahele alahele a me ke kākoʻo no ka virtualization o nā interrupts i loko o ka ʻōnaehana hana, hāʻawi i kekahi o nā hiʻohiʻona nui e pono ai e hoʻonui i ka hiki o kahi hopena e hoʻohana ana i kahi hypervisor.

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3.2
3.2.1
3.2.2

Hoʻomanaʻo
SDRAM waho
Hoʻokomo nā mea STM32MP133C/F i mea hoʻoponopono no SDRAM waho e kākoʻo ana i kēia: · LPDDR2 a i ʻole LPDDR3, 16-bit data, a hiki i 1 Gbyte, a hiki i 533 MHz uaki · DDR3 a i ʻole DDR3L, 16-bit data, a hiki i 1 Gbyte, a hiki i 533 MHz uaki
SRAM hoʻokomo ʻia
Nā mea hana a pau: · SYSRAM: 128 Kbytes (me ka programmable size secure zone) · AHB SRAM: 32 Kbytes (securable) · BKPSRAM (backup SRAM): 8 Kbytes
Mālama ʻia ka ʻike o kēia wahi mai nā mea kākau makemake ʻole, a hiki ke mālama ʻia ma ke ʻano Standby a i ʻole VBAT. Hiki ke ho'ākāka 'ia ka BKPSRAM (ma ETZPC) e like me ka hiki ke loa'a e ka polokalamu palekana wale nō.

3.3

DDR3/DDR3L/LPDDR2/LPDDR3 mea hoʻoponopono (DDRCTRL)

ʻO DDRCTRL i hui pū ʻia me DDRPHYC e hāʻawi i kahi hopena hoʻomanaʻo hoʻomanaʻo piha no ka subsystem hoʻomanaʻo DDR. · Hoʻokahi 64-bit AMBA 4 AXI ports interface (XPI) · AXI clock asynchronous to the controller · DDR memory cypher engine (DDRMCE) me AES-128 DDR on-the-fly write
encryption/heluhelu decryption. · Nā kūlana i kākoʻo ʻia:
JEDEC DDR3 SDRAM kiko'ī, JESD79-3E no DDR3/3L me 16-bit interface
JEDEC LPDDR2 SDRAM kikoʻī, JESD209-2E no LPDDR2 me 16-bit interface
JEDEC LPDDR3 SDRAM kikoʻī, JESD209-3B no LPDDR3 me 16-bit interface
· Mea hoʻonohonoho kiʻekiʻe a me SDRAM kauoha generator · Programmable piha ʻikepili laula (16-bit) a i ʻole ka hapalua o ka laulā data (8-bit) · Kākoʻo QoS kiʻekiʻe me ʻekolu papa kaʻa ma ka heluhelu ʻana a me ʻelua mau papa kaʻa ma ke kākau ʻana · Nā koho e pale aku i ka pōloli o nā kaʻa haʻahaʻa haʻahaʻa.
Nā awa AXI · Kākoʻo polokalamu no nā koho lōʻihi pōhā (4, 8, 16) · Kākau i ka hui ʻana e ʻae i nā kākau he nui i ka helu helu hoʻokahi e hui ʻia i kahi
kākau hoʻokahi · hoʻonohonoho kūlana hoʻokahi

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· Kākoʻo i ke komo ʻana a me ka puka i waho o ka SDRAM ma muli o ka hiki ʻole o ke kālepa no ka manawa programmable
· Kākoʻo i ka hoʻokuʻu ʻana i ka uaki (LPDDR2/3) komo a puka i waho ma muli o ka nele o ka hōʻea ʻana mai
· Kākoʻo i ke ʻano hana haʻahaʻa haʻahaʻa haʻahaʻa ma muli o ka loaʻa ʻole o ka hōʻea ʻana o ke kālepa no ka manawa programmable ma o ka hāmeʻa haʻahaʻa mana haʻahaʻa
· Kākoʻo i ka polokalamu hoʻopaʻa palapala · Kākoʻo o ka ʻakomi a i ʻole ma lalo o ka mana lako polokalamu hoʻomaʻamaʻa ponoʻī i ke komo ʻana a me ka puka waho · Kākoʻo i ka hoʻokomo ʻana i ka mana hohonu a me ka puka ʻana ma lalo o ka mana polokalamu (LPDDR2 a
LPDDR3) · Kākoʻo i nā mea hou e hoʻopaʻa inoa ai i ke ʻano SDRAM ma lalo o ka mana lako polokalamu.
bank bits · Nā koho hoʻomaha hoʻomaha hou i koho ʻia e ka mea hoʻohana · DDRPERFM poloka pili e kōkua no ka nānā ʻana a me ke kani ʻana
Hiki ke wehewehe ʻia ʻo DDRCTRL a me DDRPHYC (ma ETZPC) i hiki ke loaʻa e nā polokalamu palekana wale nō.
ʻO ka DDRMCE (DDR memory cypher engine) nā hiʻohiʻona nui ma lalo nei: · AXI system bus master/slave interfaces (64-bit) · In-line encryption (no ke kākau) a me ka decryption (no ka heluhelu), ma muli o ka pā ahi i hoʻokomo ʻia.
hoʻopololei · ʻElua ʻano hoʻopunahele ma kēlā me kēia māhele (ʻoi loa o hoʻokahi māhele): ʻaʻohe hoʻopuna (mode bypass),
'ākeʻa cipher mode · Hoʻomaka a hoʻopau i nā ʻāpana i wehewehe ʻia me ka 64-Kbyte granularity · kānana paʻamau ('āpana 0): hāʻawi ʻia kekahi ʻae · Kānana komo ʻāpana: ʻaʻohe
Kākoʻo poloka cipher: AES Kākoʻo ʻia ke ʻano kaulahao · Kākoʻo ʻia ke ʻano poloka me ka AES cipher i kūpono me ke ʻano ECB i kuhikuhi ʻia ma ka NIST FIPS paʻi 197 maʻamau hoʻopunipuni kiʻekiʻe (AES), me kahi hana hoʻopili kī pili e pili ana i ka algorithm Keccak-400 i paʻi ʻia ma https://keccak.team webpaena. · Hoʻokahi pūʻulu o nā mea kākau inoa kākau wale nō a hiki ke laka ʻia · AHB hoʻonohonoho awa, ʻike pono

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3.4

ʻO ka mea hoʻoponopono kikowaena helu wahi TrustZone no DDR (TZC)

Hoʻohana ʻia ʻo TZC no ka kānana ʻana i nā mea heluhelu a kākau i ka mea hoʻoponopono DDR e like me nā kuleana TrustZone a ma muli o ka haku mālama ʻole (NSAID) a hiki i ʻeiwa mau ʻāpana programmable: · Kākoʻo ʻia e nā polokalamu hilinaʻi wale nō · Hoʻokahi ʻāpana kānana · ʻEiwa mau ʻāpana:
Hoʻohana ʻia ka ʻāpana 0 i nā manawa a pau a uhi ʻia ka pae helu helu holoʻokoʻa. Loaʻa i nā ʻāpana 1 a hiki i ka 8 ke kumu papahana-/hope-address a hiki ke hāʻawi ʻia i
kekahi a i ʻole nā ​​kānana ʻelua. · Ua hoʻolālā ʻia nā ʻae komo palekana a paʻa ʻole i kēlā me kēia ʻāpana · Kānā ʻia nā ʻae ʻole e like me ka NSAID · ʻAʻole pono e uhi ʻia nā ʻāpana i hoʻomalu ʻia e ka kānana hoʻokahi · ʻAʻole i uhi ʻia nā ʻano hana me ka hewa a/a i ʻole ke hoʻopau ʻia · Hiki ke ʻae ʻia = 256 · Manaʻo kiaʻi puka e hiki ai a hoʻopau i kēlā me kēia kānana.

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STM32MP133C/F

3.5

Nā ʻano boot

I ka hoʻomaka ʻana, koho ʻia ke kumu boot i hoʻohana ʻia e ka boot ROM e nā BOOT pin a me OTP bytes.

Papa 2. Nā ʻano hoʻomaka

BOOT2 BOOT1 BOOT0 ʻO ke ʻano pahu mua

Manaʻo manaʻo

E kali i ka pilina komo mai ma:

0

0

0

UART a me USB(1)

USART3/6 a me UART4/5/7/8 ma nā pine paʻamau

ʻO ke kelepona wikiwiki USB ma nā pine OTG_HS_DP/DM (2)

0

0

1 Serial NOR flash(3) Serial NOR flash ma QUADSPI(5)

0

1

0

e·MMC(3)

e·MMC ma SDMMC2 (paʻamau)(5)(6)

0

1

1

NAND flash(3)

SLC NAND flash ma FMC

1

0

0

Boot hoʻomohala (ʻaʻohe pahu hoʻomanaʻo flash)

Hoʻohana ʻia no ka loaʻa ʻana o ka debug me ka ʻole boot mai ka hoʻomanaʻo flash(4)

1

0

1

Kāleka SD(3)

Kāleka SD ma SDMMC1 (paʻamau)(5)(6)

E kali i ka pilina komo mai ma:

1

1

0 UART a me USB(1)(3) USART3/6 a me UART4/5/7/8 ma nā pine paʻamau

ʻO ke kelepona wikiwiki USB ma nā pine OTG_HS_DP/DM (2)

1

1

1 Uku uila NAND (3) uila uila NAND ma QUADSPI(5)

1. Hiki ke hoʻopau ʻia e nā hoʻonohonoho OTP. 2. Pono ka USB i ka uaki HSE/crystal (e nānā iā AN5474 no nā alapine i kākoʻo ʻia me ka ʻole o ka hoʻonohonoho OTP). 3. Hiki ke hoʻololi ʻia ke kumu kumu e nā hoʻonohonoho OTP (no ka exampka pahu mua ma ke kāleka SD, a laila e·MMC me nā hoʻonohonoho OTP). 4. ʻO Cortex®-A7 kumu i loko o ka loop loop pauʻole e huli ana i ka PA13. 5. Hiki ke hoʻololi ʻia nā pine paʻamau e OTP. 6. ʻO kahi ʻē aʻe, hiki ke koho ʻia kahi SDMMC ma mua o kēia paʻamau e OTP.

ʻOiai ua hana ʻia ka pahu haʻahaʻa haʻahaʻa me ka hoʻohana ʻana i nā uaki kūloko, ua hoʻolako ʻo ST i nā pūʻolo lako polokalamu a me nā pilina o waho nui e like me DDR, USB (akā ʻaʻole i kaupalena ʻia) koi i kahi aniani a i ʻole oscillator waho e hoʻopili ʻia ma nā pine HSE.
E ʻike iā RM0475 "STM32MP13xx advanced Arm®-based 32-bit MPUs" a i ʻole AN5474 "E hoʻomaka me STM32MP13xx lines hardware development" no nā kaohi a me nā ʻōlelo paipai e pili ana i ka pilina o nā pine HSE a me nā alapine kākoʻo.

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3.6

Ka hooponopono mana

3.6.1
akahele:

Hoʻolālā lako mana
· ʻO VDD ka lako nui no nā I/Os a me ka ʻāpana kūloko i mālama ʻia i ka wā Standby. Pono voltagʻO ka laulā he 1.71 V a i 3.6 V (1.8 V, 2.5 V, 3.0 V a i ʻole 3.3 V type.)
Pono e hoʻopili ʻia ʻo VDD_PLL a me VDD_ANA me VDD. · VDDCPU ʻo ka Cortex-A7 CPU i hoʻolaʻa ʻia voltage lako, nona ka waiwai e pili ana i ka
makemake pinepine CPU. 1.22 V a 1.38 V ma ke ano holo. Pono ʻo VDD ma mua o VDDCPU. · ʻO VDDCORE ka vol kikohoʻe nuitage a paʻa mau i ka wā Standby. VoltagʻO ka laulā he 1.21 V a 1.29 V ma ke ʻano holo. Pono ka VDD ma mua o VDDCORE. · Hiki ke hoʻopili ʻia ka pine VBAT i ka pākaukau waho (1.6 V < VBAT < 3.6 V). Inā ʻaʻole hoʻohana ʻia kahi pākaukau waho, pono e hoʻopili ʻia kēia pine iā VDD. · ʻO VDDA ka analog (ADC/VREF), hāʻawi voltage (1.62 V a 3.6 V). ʻO ka hoʻohana ʻana i ka VREF+ i loko e pono ai ʻo VDDA e like a ʻoi aku paha ma mua o VREF+ + 0.3 V. · ʻO ka pine VDDA1V8_REG ka mea hoʻopuka o ka mea hoʻoponopono kūloko, pili i loko i ka USB PHY a me USB PLL. Hoʻohana ʻia ka mea hoʻoponopono kūloko VDDA1V8_REG ma ka paʻamau a hiki ke hoʻomalu ʻia e ka polokalamu. Paʻa mau ia i ka wā Standby.
ʻAʻole pono e waiho ʻia ka pine kikoʻī BYPASS_REG1V8 e lana ana. Pono e hoʻopili ʻia me VSS a i ʻole VDD e hoʻāla a hoʻopau paha i ka voltage hooponopono. Ke hoʻonohonoho ʻia ʻo VDD = 1.8 V, BYPASS_REG1V8. · ʻO VDDA1V1_REG pine ka puka o ka mea hoʻoponopono kūloko, pili i loko me USB PHY. Hoʻohana ʻia ka mea hoʻoponopono VDDA1V1_REG kūloko ma ka paʻamau a hiki ke hoʻomalu ʻia e ka polokalamu. Paʻa mau ia i ka wā Standby.
· ʻO VDD3V3_USBHS ka USB kiʻekiʻe-wikiwiki lako. VoltagʻO ka laulā he 3.07 V a 3.6 V.
ʻAʻole pono ʻo VDD3V3_USBHS inā ʻaʻole aia ʻo VDDA1V8_REG, inā ʻaʻole hiki ke pōʻino mau ma ka STM32MP133C/F. Pono kēia e hōʻoia ʻia e ka PMIC kūlana kūlana a i ʻole me ka ʻāpana o waho i ka hihia o ka hoʻokō mana lako mana.
· ʻO VDDSD1 a me VDDSD2 nā lako mana kāleka SDMMC1 a me SDMMC2 SD e kākoʻo i ke ʻano ultra-high-speed.
ʻO VDDQ_DDR ka lako DDR IO. 1.425 V a i 1.575 V no ka hoʻopili ʻana i nā hoʻomanaʻo DDR3 (1.5 V typ.)
1.283 V a i 1.45 V no ka hoʻopili ʻana i nā hoʻomanaʻo DDR3L (1.35 V typ.)
1.14 V a i 1.3 V no ka hoʻopili ʻana i nā hoʻomanaʻo LPDDR2 a i ʻole LPDDR3 (1.2 V typ.)
I ka wā o ka hoʻonui ʻana a me ka hoʻohaʻahaʻa ʻana i ka mana, pono e mālama ʻia nā koi o ke kaʻina mana:
· Ke emi ka VDD ma lalo o 1 V, pono e noho nā lako mana ʻē aʻe (VDDCORE, VDDCPU, VDDSD1, VDDSD2, VDDA, VDDA1V8_REG, VDDA1V1_REG, VDD3V3_USBHS, VDDQ_DDR) ma lalo o VDD + 300 mV.
· Ke piʻi ka VDD ma luna o 1 V, kūʻokoʻa nā lako mana āpau.
I ka wā o ka hoʻohaʻahaʻa ʻana i ka mana, hiki i ka VDD ke lilo i haʻahaʻa ma mua o nā lako ʻē aʻe inā e mau ana ka ikehu i hāʻawi ʻia i ka STM32MP133C/F ma lalo o 1 mJ. ʻAe kēia i nā capacitors decoupling waho e hoʻokuʻu ʻia me nā manawa like ʻole i ka wā o ka manawa transient power down.

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V 3.6
VBOR0 1

Kiʻi 2. Ka mana-up/down sequence

STM32MP133C/F

VDDX(1) VDD

3.6.2
Nānā: 26/219

0.3

Kaha-uila

ʻAno hana

Mana-iho

manawa

Wahi hoʻolako kūpono ʻole

VDDX < VDD + 300 mV

VDDX kūʻokoʻa mai VDD

MSv47490V1

1. VDDX pili i kekahi lako mana ma waena o VDDCORE, VDDCPU, VDDSD1, VDDSD2, VDDA, VDDA1V8_REG, VDDA1V1_REG, VDD3V3_USBHS, VDDQ_DDR.

Luna hoʻolako mana

Loaʻa i nā hāmeʻa kahi kaapuni hoʻohui mana-on (POR)/ power-down reset (PDR) i hui pū ʻia me kahi circuitry Brownout reset (BOR):
· Hoʻihoʻi hou i ka mana (POR)
Mālama ka luna POR i ka lako mana VDD a hoʻohālikelike iā ia i kahi paepae paʻa. Noho nā mea hana ma ke ʻano hoʻihoʻi i ka wā VDD ma lalo o kēia paepae, · Power-down reset (PDR)
Mālama ka luna PDR i ka lako mana VDD. Hoʻokumu ʻia kahi hoʻoponopono hou i ka wā e hāʻule ai ka VDD ma lalo o kahi paepae paʻa.
· Hoʻihoʻi hou ʻia ʻo Brownout (BOR)
Mālama ka luna BOR i ka lako mana VDD. Hiki ke hoʻonohonoho ʻia nā paepae BOR ʻekolu (mai ka 2.1 a i ka 2.7 V) ma o nā bytes koho. Hoʻokumu ʻia kahi hoʻoponopono hou ke hāʻule ʻo VDD ma lalo o kēia paepae.
· Hoʻoponopono hou i ka mana VDDCORE (POR_VDDCORE) Mālama ka luna POR_VDDCORE i ka mana VDDCORE a hoʻohālikelike iā ia me kahi paepae paʻa. Noho ʻia ka waihona VDDCORE i ke ʻano hoʻonohonoho hou inā aia ʻo VDDCORE ma lalo o kēia paepae.
· Hoʻihoʻi hou i ka mana VDDCORE (PDR_VDDCORE) Mālama ka luna PDR_VDDCORE i ka lako mana VDDCORE. Hoʻokumu ʻia kahi hoʻonohonoho ʻāina VDDCORE ke hāʻule ʻo VDDCORE ma lalo o kahi paepae paʻa.
· Power-on-reset VDDCPU (POR_VDDCPU) Mālama ka luna POR_VDDCPU i ka mana VDDCPU a hoʻohālikelike iā ia me kahi paepae paʻa. Noho ʻia ka waihona VDDCPU i ke ʻano hoʻonohonoho hou inā aia ʻo VDDCORE ma lalo o kēia paepae.
Mālama ʻia ka pine PDR_ON no nā hoʻokolohua hana STMicroelectronics a pono e hoʻopili mau ʻia me VDD i kahi noi.

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3.7

Hoʻolālā mana haʻahaʻa

Nui nā ala e hōʻemi ai i ka hoʻohana ʻana i ka mana ma STM32MP133C/F: · E hoʻemi i ka hoʻohana ʻana i ka mana ikaika ma ka hoʻolohi ʻana i nā uaki CPU a/a i ʻole
nā uaki matrix kaʻaahi a/a i ʻole ka mālama ʻana i nā uaki peripheral pākahi. · E mālama i ka hoʻohana mana ke IDLE ka CPU, ma ke koho ʻana i waena o nā mea haʻahaʻa i loaʻa.
nā mana mana e like me ka pono o ka mea hoʻohana. ʻAe kēia i ka hoʻohālikelike maikaʻi loa ma waena o ka manawa hoʻomaka pōkole, ka hoʻohana haʻahaʻa haʻahaʻa, a me nā kumu ala ala i loaʻa, e hoʻokō ʻia. · E hoʻohana i ka DVFS (dynamic voltage a me ka hoʻonui pinepine ʻana) nā wahi hana e hoʻomalu pono ana i ke alapine o ka uaki CPU a me ka lako hoʻopuka VDDCPU.
Hāʻawi nā ʻano hana i ka mana o ka hāʻawi ʻana i ka uaki i nā ʻāpana ʻōnaehana like ʻole a me ka mana o ka ʻōnaehana. Hoʻokele ʻia ke ʻano hana ʻōnaehana e ka MPU sub-system.
Aia nā ʻano mana haʻahaʻa haʻahaʻa MPU sub-system: · CSleep: Hoʻopau ʻia nā wati CPU a ke hana nei ka uaki peripheral.
i hoʻonohonoho mua ʻia i ka RCC (reset and clock controller). · CStop: Hoʻopau ʻia nā uaki (nā) kikowaena CPU. · Cstandby: VDDCPU OFF
Hoʻokomo ʻia nā ʻano mana haʻahaʻa CSleep a me CStop e ka CPU i ka wā e hoʻokō ai i nā kuhikuhi WFI (kali no ka interrupt) a i ʻole WFE (kali no ka hanana).
ʻO nā ʻano hana hana ʻōnaehana i loaʻa penei: · Holo (pūnaewele i kāna hana piha, VDDCORE, VDDCPU a me nā uaki ON) · Kū (nā uaki OFF) · LP-Stop (nā uaki OFF) · LPLV-Stop (nā uaki OFF, VDDCORE a me VDDCPU pae lako hiki ke hoʻohaʻahaʻa ʻia) · LPLV-Stopby OFF2, VDDCPU OFF (VDDCPU) (VDDCPU, VDDCORE, a me nā uaki OFF)

Papa 3. Pūnaehana me ke ʻano mana CPU

ʻAno mana ʻōnaehana

CPU

Ke ano holo

CRun a i ʻole CSleep

ʻO ke ʻano hoʻomaha LP-Ke ʻano hoʻomaha LPLV-Ke ʻano hoʻomaha LPLV-Stop2 mode
Kūlana kū

CStop a i ʻole CStandby CStandby

3.8

Hoʻoponopono hou a me ka mea hoʻoponopono uaki (RCC)

Hoʻoponopono ka uaki a me ka hoʻoponopono hou i ka hanauna o nā wati a pau, a me ka uaki gating, a me ka mana o ka ʻōnaehana a me nā peripheral resets.RCC e hāʻawi i kahi kiʻekiʻe kiʻekiʻe i ke koho ʻana i nā kumu wati a ʻae i ka hoʻohana ʻana i nā lākiō uaki e hoʻomaikaʻi i ka hoʻohana ʻana i ka mana. Eia kekahi, ma kekahi mau peripheral kamaʻilio i hiki ke hana pū me

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3.8.1 3.8.2

ʻelua mau kikowaena uaki like ʻole (he uaki kaʻa kaʻa a i ʻole ka uaki peripheral kernel), hiki ke hoʻololi i ke alapine ʻōnaehana me ka ʻole o ka hoʻololi ʻana i ka baudrate.
Hoʻoponopono uaki
Hoʻokomo nā mea hana i ʻehā oscillators kūloko, ʻelua oscillators me ke aniani o waho a i ʻole resonator, ʻekolu oscillators kūloko me ka manawa hoʻomaka wikiwiki a me nā PLL ʻehā.
Loaʻa i ka RCC nā mea hoʻokomo kumu wati: · Nā oscillators kūloko:
64 MHz HSI uaki (1 % pololei) 4 MHz CSI uaki 32 kHz LSI uaki · Nā oscillators waho: 8-48 MHz HSE uaki 32.768 kHz LSE uaki
Hāʻawi ka RCC i ʻehā PLL: · PLL1 i hoʻolaʻa ʻia i ka CPU clocking · PLL2 hāʻawi:
nā uaki no ka AXI-SS (me nā alahaka APB4, APB5, AHB5 a me AHB6) nā uaki no ka interface DDR · PLL3 e hāʻawi ana: nā uaki no ka AHB multi-Layer a me ka matrix bus peripheral (me ka APB1,
APB2, APB3, APB6, AHB1, AHB2, a me AHB4) nā wati kernel no nā peripherals · PLL4 i hoʻolaʻa ʻia no ka hana ʻana i nā wati kernel no nā peripheral like ʻole.
Hoʻomaka ka ʻōnaehana ma ka uaki HSI. Hiki i ka mea hoʻohana ke koho i ka hoʻonohonoho uaki.
Pūnaehana hoʻonohonoho hou
Hoʻomaka ka mana hoʻihoʻi hou i nā papa inoa āpau koe wale no ka debug, kahi ʻāpana o ka RCC, kahi ʻāpana o ka RTC a me nā papa inoa mana mana, a me ka waihona mana Backup.
Hoʻokumu ʻia kahi hoʻoponopono hou ʻana mai kekahi o kēia mau kumu: · ka hoʻihoʻi ʻana mai ka NRST pad · ka hoʻihoʻi ʻana mai ka hōʻailona POR a me PDR (kapa pinepine ʻia ka mana-on reset) · ka hoʻihoʻi ʻana mai BOR (kapa ʻia ʻo brownout) · ka hoʻihoʻi ʻana mai ka ʻīlio kiaʻi kūʻokoʻa 1 · ka hoʻihoʻi hou ʻana mai ka kiaʻi kūʻokoʻa 2 · kahi ʻōnaehana polokalamu hoʻonohonoho hou mai ka HPUSE-A7 (ma ka ʻōnaehana Clock-AXNUMX) hoʻāla ʻia
Hoʻokumu ʻia kahi hoʻonohonoho ʻōnaehana mai kekahi o kēia mau kumu: · hoʻihoʻi hou i ka noi · hoʻihoʻi hou mai ka hōʻailona POR_VDDCORE · kahi puka mai ke ʻano Standby a i ke ʻano holo

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Hoʻokumu ʻia kahi hoʻoponopono MPU mai kekahi o kēia mau kumu: · hoʻoponopono ʻōnaehana · i kēlā me kēia manawa e puka ai ka MPU iā Cstandby · kahi polokalamu MPU hoʻoponopono hou mai ka Cortex-A7 (CPU)

3.9

Nā mea hoʻokomo/puka kumu nui (GPIO)

Hiki ke hoʻonohonoho ʻia kēlā me kēia o nā pine GPIO e ka lako polokalamu ma ke ʻano he puka (push-pull a wehe-waha, me ka huki ʻole a huki ʻole paha), ma ke ʻano he hoʻokomo (me ka huki ʻole a huki ʻole paha) a i ʻole he hana ʻokoʻa peripheral. Hoʻokaʻawale ʻia ka hapa nui o nā pine GPIO me nā hana kikohoʻe a i ʻole analog. Hiki i nā GPIO āpau ke kiʻekiʻe i kēia manawa a loaʻa iā lākou ke koho wikiwiki e hoʻokele maikaʻi i ka walaʻau kūloko, ka hoʻohana mana a me ka hoʻokuʻu electromagnetic.
Ma hope o ka hoʻonohonoho hou ʻana, aia nā GPIO āpau i ke ʻano analog e hōʻemi i ka hoʻohana mana.
Hiki ke laka ʻia ka hoʻonohonoho I/O inā pono ma ka hahai ʻana i kahi kaʻina kikoʻī i mea e pale aku ai i ke kākau hoʻopunipuni i nā papa inoa I/Os.
Hiki ke hoʻonohonoho paʻa ʻia nā pine GPIO a pau, ʻo ia hoʻi ke komo ʻana o ka polokalamu i kēia mau GPIO a me nā peripheral pili i wehewehe ʻia he palekana, ua kaupalena ʻia i ka hoʻopaʻa ʻana i nā polokalamu e holo ana ma ka CPU.

3.10
Nānā:

Mea hoʻomalu palekana TrustZone (ETZPC)
Hoʻohana ʻia ʻo ETZPC e hoʻonohonoho i ka palekana TrustZone o nā haku kaʻa a me nā kauā me nā hiʻohiʻona programmable-security (nā kumuwaiwai palekana). No ka laʻana: · Hiki ke hoʻolālā ʻia ka nui o ka ʻāina palekana SYSRAM ma ka chip. · Hiki ke hoʻopaʻa ʻia nā peripheral AHB a me APB. · Hiki ke hoʻopaʻa ʻia ka AHB SRAM.
Ma ka maʻamau, ua hoʻonohonoho ʻia nā SYSRAM, AHB SRAMs a me nā peripheral i hoʻopaʻa ʻia e hoʻopaʻa i ke komo wale nō, no laila, ʻaʻole hiki ke loaʻa e nā haku paʻa ʻole e like me DMA1/DMA2.

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3.11

ʻO ka matrix pili kaʻa kaʻa
Loaʻa nā mea hana i kahi matrix bus AXI, hoʻokahi matrix bus AHB nui a me nā alahaka kaʻa e hiki ai i nā haku kaʻa ke hui pū me nā kauā kaʻa (e nānā i ke kiʻi ma lalo nei, ʻo nā kiko e hōʻike ana i nā pilina haku/kauā i hiki).
Kiʻi 3. STM32MP133C/F bus matrix

MDMA

SDMMC2

SDMMC1

DBG Mai MLAHB hoʻopili USBH

CPU

ETH1 ETH2

128-bit

AXIM

M9

M0

M1 M2

M3

M11

M4

M5

M6

M7

S0

S1 S2 S3 S4 S5 S6 S7 S8 S9

Kauwa paʻamau AXIMC

NIC-400 AXI 64 bits 266 MHz – 10 haku / 10 kauā

Mai ka hui AXIM DMA1 DMA2 USBO DMA3

M0

M1 M2

M3 M4

M5

M6 M7

S0

S1

S2

S3

S4 S5 Interconnect AHB 32 bits 209 MHz – 8 haku / 6 kauā

DDRCTRL 533 MHz AHB alahaka i AHB6 To MLAHB interconnect FMC/NAND QUADSPI SYSRAM 128 KB ROM 128 KB AHB alahaka i AHB5 APB alahaka i APB5 APB alahaka i DBG APB
AXI 64 awa kauā like AXI 64 awa kauā like ʻole AXI 64 awa kukū asynchronous AXI 64 awa kauā asynchronous AHB 32 awa kauā like ʻole AHB 32 awa kauā like ʻole AHB 32 awa kukū asynchronous AHB 32 awa kauā like ʻole
Alahaka i AHB2 SRAM1 SRAM2 SRAM3 I AXIM pili Alahaka i AHB4
MSv67511V2

MLAHB

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3.12

Nā mea hoʻoponopono DMA
Hōʻike nā mea hana i kēia mau modula DMA e wehe ai i ka hana CPU: · he master direct memory access (MDMA)
ʻO ka MDMA kahi mea hoʻokele DMA kiʻekiʻe, nāna e mālama i nā ʻano hoʻololi hoʻomanaʻo āpau (peripheral-to-memory, memory-to-memory, memory-to-peripheral), me ka ʻole o ka hana CPU. Loaʻa iā ia kahi kikowaena master AXI. Hiki i ka MDMA ke hoʻopili me nā mea hoʻokele DMA ʻē aʻe e hoʻonui i nā mana DMA maʻamau, a i ʻole hiki ke hoʻokele pololei i nā noi DMA peripheral. Hiki i kēlā me kēia o nā kaha he 32 ke hana i ka hoʻololi ʻana i ka poloka, ka hoʻololi hou ʻana i ka poloka a me nā hoʻoili papa inoa pili. Hiki ke hoʻonohonoho ʻia ka MDMA e hana i nā hoʻololi paʻa i nā hoʻomanaʻo paʻa. · ʻekolu mau mea hoʻoponopono DMA (ʻaʻole paʻa DMA1 a me DMA2, a me DMA3 paʻa) ʻO kēlā me kēia mea hoʻoponopono he ʻelua awa AHB, no ka huina o 16 paʻa ʻole a me ʻewalu mau ala DMA paʻa e hana i nā hoʻoili poloka FIFO.
ʻElua mau ʻāpana DMAMUX multiplex a ala i nā noi peripheral DMA i nā mea hoʻokele DMA ʻekolu, me ka loli kiʻekiʻe, e hoʻonui i ka nui o nā noi DMA e holo like ana, a me ka hoʻopuka ʻana i nā noi DMA mai nā mea hoʻoiho peripheral output a i ʻole nā ​​hanana DMA.
Hoʻopili ʻo DMAMUX1 i nā noi DMA mai nā peripheral paʻa ʻole i nā kahawai DMA1 a me DMA2. Hoʻopili ʻo DMAMUX2 i nā noi DMA mai nā peripheral paʻa i nā kahawai DMA3.

3.13

Hoʻopaneʻe ʻia a me ka mea hoʻoponopono hanana hanana (EXTI)
Hoʻoponopono ka mea hoʻopau hoʻonui a me ka mea hoʻoponopono hanana (EXTI) i ka CPU a me ka ʻōnaehana wakeup ma o nā hoʻokomo hanana kūpono a pololei. Hāʻawi ʻo EXTI i nā noi wakeup i ka mana mana, a hoʻopuka i kahi noi interrupt i ka GIC, a me nā hanana i ka hoʻokomo hanana CPU.
ʻO nā noi wakeup EXTI e ʻae i ka ʻōnaehana e hoʻāla ʻia mai ka mode Stop, a e hoʻāla ʻia ka CPU mai nā ʻano CStop a me CStandby.
Hiki ke hoʻohana ʻia ka noi hoʻopau a me ka hana noi hanana ma ke ʻano holo.
Aia pū ka EXTI i ka koho EXTI IOport.
Hiki ke hoʻopaʻa ʻia kēlā me kēia hoʻopaʻapaʻa a i ʻole hanana i mea e kaupalena ʻia ai ke komo ʻana i nā polokalamu palekana wale nō.

3.14

ʻO ke kikowaena helu helu helu Cyclic redundancy (CRC)
Hoʻohana ʻia ka ʻāpana helu helu CRC (cyclic redundancy check) no ka loaʻa ʻana o kahi code CRC me ka hoʻohana ʻana i ka polynomial programmable.
Ma waena o nā noi ʻē aʻe, hoʻohana ʻia nā ʻenehana CRC e hōʻoia i ka lawe ʻana i ka ʻikepili a i ʻole ka mālama pono ʻana. Ma ke ʻano o ka maʻamau EN / IEC 60335-1, hāʻawi lākou i kahi ala e hōʻoia ai i ka pono o ka hoʻomanaʻo flash. Kōkua ka ʻāpana helu CRC i ka helu ʻana i kahi pūlima o ka polokalamu i ka wā holo, e hoʻohālikelike ʻia me kahi pūlima kuhikuhi i hana ʻia i ka manawa loulou a mālama ʻia ma kahi wahi hoʻomanaʻo.

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3.15

Mea hoʻoponopono hoʻomanaʻo maʻalahi (FMC)
ʻO nā hiʻohiʻona nui o ka mea hoʻokele FMC penei: · Ka pilina me nā mea hoʻopaʻa ʻia me ka hoʻomanaʻo static me:
NOR flash memory Static or pseudo-static random access memory (SRAM, PSRAM) NAND flash memory with 4-bit/8-bit BCH hardware ECC · 8-,16-bit data bus width · Kūʻokoʻa chip-koho mana no kēlā me kēia waihona hoʻomanaʻo · Hoʻonohonoho kūʻokoʻa no kēlā me kēia waihona hoʻomanaʻo · Kākau FIFO
Hiki ke mālama ʻia nā papa inoa hoʻonohonoho FMC.

3.16

Pākuʻi hoʻomanaʻo ʻelua Quad-SPI (QUADSPI)
ʻO ka QUADSPI kahi kikowaena kamaʻilio kūikawā e kuhikuhi ana i hoʻokahi, ʻelua a quad SPI hoʻomanaʻo flash. Hiki iā ia ke hana ma kekahi o kēia mau ʻano ʻekolu: · Ke ʻano kuhikuhi ʻole: hana ʻia nā hana āpau me ka hoʻohana ʻana i nā papa inoa QUADSPI. · Kūlana koho balota: heluhelu ʻia ka papa inoa o ke kūlana hoʻomanaʻo flash waho i kēlā me kēia manawa
hiki ke hoʻokuʻu ʻia ke hoʻonohonoho hae. · Ke ʻano palapala hoʻomanaʻo: hoʻopaʻa ʻia ka hoʻomanaʻo uila waho i ka wahi helu wahi
a ʻike ʻia e ka ʻōnaehana me he mea lā he hoʻomanaʻo i loko.
Hiki ke hoʻonui ʻia ka hiki a me ka hiki ke hoʻonui ʻia ʻelua me ka mode dual-flash, kahi e loaʻa ai nā hoʻomanaʻo uila ʻelua Quad-SPI i ka manawa like.
Hoʻohui ʻia ʻo QUADSPI me kahi poloka hoʻopaneʻe (DLYBQS) e ʻae i ke kākoʻo o ke alapine ʻikepili waho ma luna o 100 MHz.
Hiki ke paʻa nā papa inoa hoʻonohonoho QUADSPI, a me kāna poloka lohi.

3.17

Nā mea hoʻololi analog-to-digital (ADC1, ADC2)
Hoʻokomo nā mea hana i ʻelua mau mea hoʻololi analog-to-digital, nona ka hoʻonā hiki ke hoʻonohonoho ʻia i 12-, 10-, 8- a i ʻole 6-bit. Hāʻawi kēlā me kēia ADC i 18 mau kaha waho, e hana ana i nā hoʻololi ʻana ma ke ʻano pana hoʻokahi a i ʻole ke ʻano scan. Ma ke ʻano scan, hana ʻia ka hoʻololi ʻana ma kahi pūʻulu i koho ʻia o nā hoʻokomo analog.
Loaʻa i nā ADC ʻelua nā pilina kaʻa kaʻa.
Hiki ke lawelawe ʻia kēlā me kēia ADC e kahi mea hoʻoponopono DMA, no laila e ʻae i ka hoʻololi ʻana i nā waiwai i hoʻololi ʻia ADC i kahi wahi e hele ai me ka ʻole o ka hana polokalamu.
Eia kekahi, hiki i kahi hiʻohiʻona kiaʻi analog ke nānā pono i ka vol i hoʻololi ʻiatage o hoʻokahi, kekahi a i ʻole nā ​​mea a pau i koho ʻia. Hoʻopuka ʻia kahi hoʻopaʻapaʻa ke hoʻololi ʻia ka voltagaia ma waho o nā paepae i hoʻolālā ʻia.
No ka hoʻonohonoho like ʻana i ka hoʻololi A/D a me nā manawa, hiki ke hoʻoulu ʻia nā ADC e kekahi o TIM1, TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, LPTIM1, LPTIM2 a me LPTIM3 timers.

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3.18

ʻIke wela
Hoʻokomo nā mea hana i kahi mea ʻike wela e hoʻohua ai i kahi voltage (VTS) e like ana me ka wela. Hoʻopili ʻia kēia mea ʻike wela i ka ADC2_INP12 a hiki ke ana i ka wela ambient mai 40 a +125 °C me ka pololei o ±2%.
He linearity maikaʻi ka mea ʻike wela, akā pono ia e calibrated no ka loaʻa ʻana o ka pololei holoʻokoʻa maikaʻi o ke ana wela. E like me ka ʻokoʻa ʻana o ka mea ʻike wela mai ka chip a i ka chip ma muli o ka hoʻololi ʻana i ke kaʻina hana, ua kūpono ka mea ʻike wela i loko uncalibrated no nā noi e ʻike i nā loli wela wale nō. No ka hoʻomaikaʻi ʻana i ka pololei o ke ana ʻana o ke ana wela, ua hoʻopaʻa ʻia kēlā me kēia mea hana e ST. Mālama ʻia ka ʻikepili calibration hale hana sensor wela e ST ma kahi o OTP, hiki ke loaʻa i ke ʻano heluhelu-wale nō.

3.19

ʻIke wela kikohoʻe (DTS)
Hoʻokomo nā mea hana i kahi ʻike wela wela. Helu ʻo DTS i ka alapine ma muli o ka LSE a i ʻole PCLK e hāʻawi i ka ʻike wela.
Kākoʻo ʻia nā hana ma hope: · hana hoʻopau ma ka paepae wela · hana hōʻailona ala ma ka paepae wela

3.20
Nānā:

Hana VBAT
Aia ka mana mana VBAT i ka RTC, nā papa inoa hoʻopaʻa a me ka SRAM hoʻihoʻi.
I mea e hoʻonui ai i ka lōʻihi o ka pākaukau, hāʻawi ʻia kēia mana mana e VDD ke loaʻa a i ʻole ka voltage hoʻohana ʻia ma ka pine VBAT (ke loaʻa ʻole ka lako VDD). Hoʻololi ʻia ka mana VBAT ke ʻike ka PDR ua hāʻule ka VDD ma lalo o ka pae PDR.
ʻO ka voltage ma ka pine VBAT hiki ke hāʻawi ʻia e kahi pākahiko waho, kahi supercapacitor a pololei paha e VDD. I ka hihia hope, ʻaʻole hana ke ʻano VBAT.
Hoʻohana ʻia ka hana VBAT inā ʻaʻohe VDD.
ʻAʻohe o kēia mau hanana (nā hoʻopau waho, TAMP hiki ke hoʻihoʻi pololei i ka lako VDD a hoʻoneʻe i ka hāmeʻa mai ka hana VBAT. Eia naʻe, ʻo TAMP Hiki ke hoʻohana ʻia nā hanana a me nā mea hōʻailona RTC no ka hoʻopuka ʻana i kahi hōʻailona i kahi kaapuni waho (ʻo ka PMIC maʻamau) hiki ke hoʻihoʻi i ka lako VDD.

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3.21

Voltage hoʻopaʻa kuhikuhi (VREFBUF)
Hoʻokomo nā mea hana i kahi voltage reference buffer hiki ke hoʻohana like voltage kuhikuhi no na ADC, a pela no hoi ma voltage kuhikuhi no nā ʻāpana waho ma o ka pine VREF+. Hiki iā VREFBUF ke palekana. Kākoʻo ka VREFBUF kūloko i ʻehā voltages: · 1.65 V · 1.8 V · 2.048 V · 2.5 V He vol wahotagHiki ke hāʻawi ʻia ke kuhikuhi ma o ka pine VREF+ ke pio ka VREFBUF kūloko.
Helu 4. Voltage hoʻopaʻa kuhikuhi

VREFINT

+

–

VREF+

VSSA

MSv64430V1

3.22

kānana kikohoʻe no ka modulator sigma-delta (DFSDM)
Hoʻokomo nā mea hana i hoʻokahi DFSDM me ke kākoʻo no nā modula kānana kikohoʻe ʻelua a me ʻehā mau kikowaena hoʻokomo waho (transceivers) a i ʻole ʻehā mau mea hoʻokomo like ʻole.
Hoʻopili ka DFSDM i nā modulators waho i ka hāmeʻa a hana i ka kānana kikohoʻe o nā kahawai ʻikepili i loaʻa. hoʻohana ʻia nā modulators e hoʻohuli i nā hōʻailona analog i nā kahawai kikohoʻe-serial i hoʻokumu i nā mea hoʻokomo o ka DFSDM.
Hiki i ka DFSDM ke hoʻopili i nā microphones PDM (pulse-density modulation) a hana i ka PDM i ka hoʻololi ʻana a me ka kānana ʻana (hardware accelerated). Hōʻike ka DFSDM i nā hoʻokomo kahawai data parallel koho mai nā ADC a i ʻole mai ka hoʻomanaʻo ʻana o ka mea hana (ma o DMA/CPU hoʻololi i DFSDM).
Kākoʻo nā transceivers DFSDM i nā ʻano kikowaena serial-interface (e kākoʻo i nā modulators like ʻole). Hana ʻia nā modula kānana kikohoʻe DFSDM e like me nā ʻāpana kānana i wehewehe ʻia e ka mea hoʻohana a hiki i ka 24-bit ka hopena ADC hope loa.

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Kākoʻo ka DFSDM peripheral: · ʻEhā mau kaha kikohoʻe kikohoʻe hoʻokomo ʻehā:
Hiki ke hoʻonohonoho ʻia ke kikowaena SPI e hoʻohui i nā modulators ʻokoʻa hiki ke hoʻonohonoho ʻia Manchester coded 1-wire interface PDM (pulse-density modulation) microphone input maximum input clock frequency a hiki i ka 20 MHz (10 MHz for Manchester coding) puka uaki no nā modulators (0 a 20 MHz) · Nā hoʻokomo ʻē aʻe mai ʻehā mau kumu ʻikepili kūloko kūloko a i ʻole nā ​​kumu hoʻomanaʻo i loko ADC16. (DMA) · ʻElua ʻāpana kānana kikohoʻe me ka hoʻoponopono hōʻailona kikohoʻe hiki ke hoʻololi: Sincx kānana: kānana kauoha / ʻano (1 a 5), ​​keu.ampling ratio (1 a 1024) integrator: oversampratio ling (1 a 256) · A hiki i ka 24-bit ka hoʻonā ʻikepili puka, hōʻano ʻikepili puka pūlima · Hoʻoponopono ʻokoʻa ʻikepili offset (offset mālama ʻia ma ke kākau inoa e ka mea hoʻohana) · Hoʻololi mau a hoʻokahi paha · Hoʻomaka ka hoʻololi ʻana i hoʻomaka ʻia e: software trigger internal timers external events start-of-conversion synchronously with first digital filter module (DFSdoge featuring) hoʻopaʻa inoa i hoʻolaʻa ʻia ʻo Sincx kānana kikohoʻe (kauoha = 1 a 3,
oi akuampratio ling = 1 a 32) hoʻokomo mai ka ʻikepili hoʻopuka hope a i ʻole mai ka hoʻokomo ʻana i nā kaila serial kikohoʻe i koho ʻia ka nānā mau ʻana me ke kaʻawale mai ka hoʻololi maʻamau. ʻIke loa: ka mālama ʻana i nā waiwai liʻiliʻi a me ka nui o ka ʻikepili hoʻololi hope i hōʻano hou ʻia e ka lako polokalamu · Hiki iā DMA ke heluhelu i ka ʻikepili hoʻololi hope loa · Interrupts: pau o ka hoʻololi ʻana, overrun, analog watchdog, pōkole kaapuni, hoʻokomo serial channel clock absence · "Regular" a i ʻole "injected" conversions: "maʻamau" hiki ke noi ʻia i kēlā me kēia manawa a i ʻole ma ke ʻano hoʻomau.
me ka loaʻa ʻole o ka hopena i ka manawa o nā hoʻololi "injected" i nā hoʻololi ʻana no ka manawa kūpono a me ka hoʻololi kiʻekiʻe.

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3.23

Mea hoʻoheheʻe helu ʻoiaʻiʻo (RNG)
Hoʻokomo nā mea hana i hoʻokahi RNG e hāʻawi ana i nā helu helu 32-bit i hana ʻia e kahi kaapuni analog hoʻohui.
Hiki ke ho'ākāka 'ia ka RNG (ma ETZPC) i hiki ke loa'a e ka lako polokalamu palekana wale nō.
Hoʻopili ka RNG ʻoiaʻiʻo i nā peripheral AES a me PKA i hoʻopaʻa ʻia ma o kahi pahi hoʻolaʻa (ʻaʻole hiki ke heluhelu ʻia e ka CPU).

3.24

Nā mea hana cryptographic a me ka hash (CRYP, SAES, PKA a me HASH)
Hoʻokomo nā mea hana i hoʻokahi kaʻina hana cryptographic e kākoʻo ana i nā algorithm cryptographic holomua e koi pinepine ʻia e hōʻoia i ka hūnā, ka hōʻoia, ka pono ʻikepili a me ka hōʻole ʻole i ka wā e hoʻololi ai i nā memo me kahi hoa.
Hoʻokomo pū nā mea hana i kahi DPA kūpaʻa paʻa paʻa AES 128- a me 256-bit kī (SAES) a me ka PKA hardware encryption/decryption accelerator, me ka pahi paʻa paʻa ʻaʻole hiki ke loaʻa e ka CPU.
Nā hiʻohiʻona nui CRYP: · DES/TDES (ka maʻamau hoʻopuna ʻikepili / maʻamau hoʻopuna ʻike ʻekolu): ECB (electronic
codebook) a me CBC (cipher block chaining) chaining algorithms, 64-, 128- a i ʻole 192-bit kī · AES (advanced encryption standard): ECB, CBC, GCM, CCM, a me CTR (counter mode) chaining algorithms, 128-, 192- a i ʻole 256-bit kī
Nā hiʻohiʻona nui HASH Universal: · SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-3 (paʻa HASH algorithms) · HMAC
Kākoʻo ka cryptographic accelerator i ka hana noi DMA.
Hiki ke wehewehe ʻia ʻo CRYP, SAES, PKA a me HASH (ma ETZPC) i hiki ke loaʻa i nā polokalamu palekana wale nō.

3.25

ʻO ka pahu a me ka palekana a me ka mana OTP (BSEC)
ʻO ka BSEC (boot and security and OTP control) i manaʻo ʻia e hoʻomalu i kahi pahu fuse OTP (hoʻokahi manawa programmable), i hoʻohana ʻia no ka waiho ʻana i ka waiho ʻole-volatile no ka hoʻonohonoho ʻana i nā hāmeʻa a me nā palena palekana. Pono e hoʻonohonoho ʻia kekahi ʻāpana o BSEC i hiki ke loaʻa e nā polokalamu palekana wale nō.
Hiki i ka BSEC ke hoʻohana i nā huaʻōlelo OTP no ka mālama ʻana i ka HWKEY 256-bit no SAES (secure AES).

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3.26

ʻO nā wati a me nā kiaʻi kiaʻi
Aia i loko o nā mea hana ʻelua mau manawa hoʻokele holomua, ʻumi mau manawa hana maʻamau (ma loko o ia mau mea ʻehiku i hoʻopaʻa ʻia), ʻelua mau manawa maʻamau, ʻelima mau mana haʻahaʻa haʻahaʻa, ʻelua mau ʻīlio kiaʻi, a me ʻehā mau manawa ʻōnaehana i kēlā me kēia Cortex-A7.
Hiki ke hoʻopaʻa ʻia nā helu helu manawa āpau ma ke ʻano debug.
Hoʻohālikelike ka papa ma lalo i nā hiʻohiʻona o ka mana holomua, manaʻo nui, kumu a me ka mana haʻahaʻa.

ʻAno manawa

Ka manawa

Pakuhi 4. Hoʻohālikelike hiʻohiʻona hiʻohiʻona

hoʻoholo kūʻē-
tion

ʻAno helu

Prescaler kumu

Hanana noi DMA

Hopu/ hoʻohālikelike i nā kaha

Hoʻopuka hoʻohui

Kikowaena kiʻekiʻe
uaki (MHz)

Max
manawa manawa
uaki (MHz)(1)

TIM1 kiʻekiʻe, -hoʻomalu TIM8

16-bit

I luna, ʻO kēlā me kēia helu helu i lalo, ma waena o 1 i luna/lalo a me 65536

ʻAe

TIM2 TIM5

32-bit

I luna, ʻO kēlā me kēia helu helu i lalo, ma waena o 1 i luna/lalo a me 65536

ʻAe

TIM3 TIM4

16-bit

I luna, ʻO kēlā me kēia helu helu i lalo, ma waena o 1 i luna/lalo a me 65536

ʻAe

ʻO kēlā me kēia helu helu

TIM12(2) 16-bit

Ma waena o 1

ʻAʻole

Generala

a me 65536

kumu

TIM13(2) TIM14(2)

16-bit

ʻO kēlā me kēia helu Piʻi ma waena o 1
a me 65536

ʻAʻole

ʻO kēlā me kēia helu helu

TIM15(2) 16-bit

Ma waena o 1

ʻAe

a me 65536

TIM16(2) TIM17(2)

16-bit

ʻO kēlā me kēia helu Piʻi ma waena o 1
a me 65536

ʻAe

Kumu

TIM6, TIM7

16-bit

ʻO kēlā me kēia helu Piʻi ma waena o 1
a me 65536

ʻAe

LPTIM1,

Ka mana haʻahaʻa

LPTIM2(2), LPTIM3(2),
LPTIM4,

16-bit

1, 2, 4, 8, Piʻi 16, 32, 64,
128

ʻAʻole

LPTIM5

6

4

104.5

209

4

ʻAʻole

104.5

209

4

ʻAʻole

104.5

209

2

ʻAʻole

104.5

209

1

ʻAʻole

104.5

209

2

1

104.5

209

1

1

104.5

209

0

ʻAʻole

104.5

209

1(3)

ʻAʻole

104.5 104.5

1. ʻO ka nui o ka uaki manawa a hiki i ka 209 MHz ma muli o ka bit TIMGxPRE i ka RCC. 2. Hoʻopaʻa manawa paʻa. 3. ʻAʻohe ala hopu ma LPTIM.

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3.26.1 3.26.2 3.26.3

Nā manawa hoʻomalu holomua (TIM1, TIM8)
Hiki ke ʻike ʻia nā manawa hoʻokele holomua (TIM1, TIM8) ma ke ʻano he ʻekolu-phase PWM generators i hoʻonui ʻia ma nā kahawai 6. Loaʻa iā lākou nā huahana PWM hoʻohui me ka programmable hoʻokomo i nā manawa make. Hiki iā lākou ke noʻonoʻo ʻia he mau manawa holoʻokoʻa holoʻokoʻa. Hiki ke hoʻohana ʻia kā lākou mau ala kūʻokoʻa ʻehā no: · hopu hoʻokomo · hoʻohālikelike hoʻopuka · hana PWM (mau ʻaoʻao ʻaoʻao a i ʻole waena waena) · puka puka hoʻokahi-pulse.
Inā hoʻonohonoho ʻia e like me nā timers 16-bit maʻamau, loaʻa iā lākou nā hiʻohiʻona like me nā timers kumu nui. Inā hoʻonohonoho ʻia e like me 16-bit PWM generators, loaʻa iā lākou ka mana modulation piha (0-100%).
Hiki ke hana pū me nā mea hoʻohana maʻamau ma o ka hiʻohiʻona loulou manawa no ka hoʻonohonoho ʻana a i ʻole ke kaulahao hanana.
Kākoʻo ʻo TIM1 a me TIM8 i ka haku noi DMA kūʻokoʻa.
Nā manawa hana maʻamau (TIM2, TIM3, TIM4, TIM5, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17)
He ʻumi mau mea hoʻohana maʻamau i hoʻokomo ʻia i loko o nā polokalamu STM32MP133C/F (e nānā i ka Papa 4 no nā ʻokoʻa). · TIM2, TIM3, TIM4, TIM5
Hoʻokumu ʻia ʻo TIM 2 a me TIM5 ma kahi pākuʻi 32-bit auto-reload up/down counter a me kahi prescaler 16-bit, aʻo TIM3 a me TIM4 i hoʻokumu ʻia ma kahi 16-bit auto-reload up/downcounter a me kahi prescaler 16-bit. Hōʻike nā manawa āpau i ʻehā mau ala kūʻokoʻa no ka hoʻohālikelike hoʻokomo / hoʻohālikelike ʻana, PWM a i ʻole hoʻokahi-pulse mode output. Hāʻawi kēia i ka 16 hoʻokomo hopu / hoʻohālikelike hoʻohālikelike / PWM ma nā pūʻulu nui loa. Hiki ke hana pū kēia mau mea hoʻohana maʻamau, a i ʻole me nā mea hana maʻamau ʻē aʻe a me nā manawa hoʻokele holomua TIM1 a me TIM8, ma o ka hiʻohiʻona loulou manawa no ka hoʻonohonoho ʻana a i ʻole ke kaulahao hanana. Hiki ke hoʻohana ʻia kekahi o kēia mau mea hana maʻamau no ka hoʻohua PWM. Loaʻa iā TIM2, TIM3, TIM4, TIM5 nā hanauna noi DMA kūʻokoʻa. Hiki iā lākou ke lawelawe i nā hōʻailona encoder quadrature (incremental) a me nā huahana kikohoʻe mai hoʻokahi a ʻehā mau mea ʻike hall-effect. · TIM12, TIM13, TIM14, TIM15, TIM16, TIM17 Hoʻokumu ʻia kēia mau manawa ma kahi mea hoʻouka hou hou 16-bit a me kahi prescaler 16-bit. ʻO TIM13, TIM14, TIM16 a me TIM17 kahi kaila kūʻokoʻa hoʻokahi, ʻoiai ʻo TIM12 a me TIM15 ʻelua mau ala kūʻokoʻa no ka hoʻohālikelike hoʻokomo / hoʻohālikelike ʻana, PWM a i ʻole hoʻokahi-pulse mode output. Hiki iā lākou ke hoʻonohonoho pū ʻia me ka TIM2, TIM3, TIM4, TIM5 piha i ka hana maʻamau a i ʻole i hoʻohana ʻia ma ke ʻano he papa manawa maʻalahi. Hiki ke wehewehe ʻia kēlā me kēia mau manawa (ma ETZPC) i hiki ke loaʻa e nā polokalamu palekana wale nō.
Nā manawa kumu (TIM6 a me TIM7)
Hoʻohana nui ʻia kēia mau manawa ma ke ʻano he kumu manawa 16-bit generic.
Kākoʻo ʻo TIM6 a me TIM7 i ka haku noi DMA kūʻokoʻa.

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3.26.4
3.26.5 3.26.6

Nā manawa mana haʻahaʻa (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5)
He uaki kūʻokoʻa ko kēlā me kēia manawa mana haʻahaʻa a holo pū nō hoʻi ma ke ʻano Stop inā ua hoʻopaʻa ʻia e LSE, LSI a i ʻole kahi uaki waho. Hiki i kahi LPTIMx ke ho'āla i ke kelepona mai ke ʻano Stop.
Kākoʻo kēia mau mea mana haʻahaʻa i kēia mau hiʻohiʻona: · 16-bit up counter me 16-bit autoreload register · 16-bit hoʻohālikelike i ka helu · Configurable output: pulse, PWM · Continuous/one-shot mode · Selectable software/hardware input trigger · Waki ​​hiki ke koho.
kumu uaki kūloko: LSE, LSI, HSI a i ʻole APB kumu wati waho ma luna o ka LPTIM hoʻokomo (hana me ka ʻole o ka uaki kūloko.
e holo ana ke kumu, hoʻohana ʻia e ka noi pulse counter) · Programmable digital glitch kānana · Encoder mode
Hiki ke ho'ākāka 'ia ka LPTIM2 a me LPTIM3 (ma ETZPC) i hiki ke loa'a e ka lako polokalamu palekana wale nō.
Nā ʻīlio kiaʻi kūʻokoʻa (IWDG1, IWDG2)
Hoʻokumu ʻia kahi ʻīlio kiaʻi kūʻokoʻa ma kahi 12-bit downcounter a me kahi prescaler 8-bit. Hoʻopaʻa ʻia ia mai kahi 32 kHz kūloko RC (LSI) kūʻokoʻa a, ʻoiai e hana kūʻokoʻa ana ia mai ka uaki nui, hiki iā ia ke hana ma nā ʻano Stop a Standby. Hiki ke hoʻohana ʻia ʻo IWDG ma ke ʻano he kiaʻi e hoʻoponopono hou i ka hāmeʻa ke loaʻa kahi pilikia. ʻO ia ka lako- a i ʻole softwareconfigurable ma o nā koho bytes.
Hiki ke wehewehe ʻia ʻo IWDG1 (ma ETZPC) i hiki ke loaʻa e nā polokalamu palekana wale nō.
Nā manawa maʻamau (Cortex-A7 CNT)
Hāʻawi ʻia nā manawa maʻamau Cortex-A7 i hoʻokomo ʻia i loko o Cortex-A7 e ka waiwai mai ka ʻōnaehana manawa hoʻonohonoho (STGEN).
Hāʻawi ke kaʻina hana Cortex-A7 i kēia mau manawa: · ka manawa kino no ka hoʻohana ʻana i nā ʻano paʻa a paʻa ʻole.
Hoʻopaʻa ʻia nā papa inoa no ka manawa kino e hāʻawi i nā kope palekana a paʻa ʻole. · ka manawa virtual no ka hoʻohana ʻana i nā ʻano palekana ʻole · ka manawa kino no ka hoʻohana ʻana i ke ʻano hypervisor
ʻAʻole nā ​​ʻaoʻao i hoʻopaʻa ʻia i ka hoʻomanaʻo ʻana i nā manawa maʻamau a laila hiki ke ʻike ʻia e nā ʻōlelo kuhikuhi coprocessor Cortex-A7 (cp15).

3.27

Hoʻokumu ʻana i ka manawa manawa (STGEN)
Hoʻokumu ka ʻōnaehana manawa (STGEN) i kahi waiwai helu manawa e hāʻawi i kahi kūlike view o ka manawa no nā manawa maʻamau Cortex-A7.

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Aia nā hiʻohiʻona koʻikoʻi o ka hanauna manawa o ka ʻōnaehana: · 64-bit ākea e pale aku i nā pilikia roll-over · E hoʻomaka mai ka zero a i ʻole ka waiwai programmable · Control APB interface (STGENC) e hiki ai ke mālama a hoʻihoʻi ʻia ka manawa.
ma nā hanana hoʻohaʻahaʻa mana · Heluhelu-wale APB interface (STGENR) e hiki ai i ka helu manawa ke heluhelu ʻia e nā mea ʻole.
lako polokalamu palekana a me nā mea hana debug · Hoʻonui ka waiwai o ka manawa hiki ke hoʻōki i ka wā o ka debug ʻōnaehana
Hiki ke wehewehe ʻia ʻo STGENC (ma ETZPC) i hiki ke loaʻa e nā polokalamu palekana wale nō.

3.28

Uaki manawa maoli (RTC)
Hāʻawi ka RTC i kahi ala ala e hoʻokele i nā ʻano haʻahaʻa haʻahaʻa.
Hoʻokomo pū ka RTC i kahi hae hoʻāla i hoʻolālā ʻia me ka hiki ke hoʻopau.
Loaʻa i ʻelua mau papa inoa 32-bit nā kekona, nā minuke, nā hola (12- a i ʻole 24-hola format), lā (lā o ka pule), lā (lā o ka mahina), mahina, a me ka makahiki, i hōʻike ʻia ma ka format binary coded decimal (BCD). Loaʻa ka waiwai sub-kekona ma ke ʻano binary.
Kākoʻo ʻia ke ʻano binary e hōʻoluʻolu i ka hoʻokele hoʻokele polokalamu.
Hana ʻia nā uku no 28-, 29- (makahiki lele), 30-, a me 31 mau lā mahina. Hiki ke hana ʻia ka uku manawa mālama lā.
Aia nā papa inoa 32-bit hou i nā subseconds alarmable programmable, kekona, minuke, hola, lā, a me ka lā.
Loaʻa kahi hiʻohiʻona calibration kikohoʻe e hoʻopaʻi i ka ʻae ʻana i ka pololei oscillator kristal.
Ma hope o ka hoʻihoʻi hou ʻana i ka waihona Backup, pale ʻia nā papa inoa RTC āpau mai ka hiki ke komo i ka palapala parasitic a pale ʻia e ke komo paʻa.
ʻOiai ka loaʻa ʻana o ka voltage noho ana ma ka pae hana, ʻaʻole e pau ka RTC, me ka nānā ʻole i ke kūlana o ka mea hana (Run mode, low-power mode or under reset).
ʻO nā hiʻohiʻona nui o ka RTC penei: · Kalena me nā subseconds, kekona, minuke, hola (12 a i ʻole 24 format), lā (lā o
pule), lā (lā o ka mahina), mahina, a me ka makahiki · Daylight saving compensable programmable by software · Programmable alarm with interrupt function. Hiki ke hoʻāla ʻia ka ʻala e kekahi
hui pū ʻana o nā kahua kalena. · Hoʻokumu ʻia kahi hae hoʻāla ʻakomi e hoʻāla i kahi ala ala
hoʻopau · ʻIke uaki kuhikuhi: hiki ke loaʻa ka uaki kumu lua (50 a i ʻole 60 Hz) pololei.
hoʻohana ʻia no ka hoʻonui ʻana i ka pololei kalena. · ʻO ka hoʻonohonoho pololei ʻana me ka uaki waho me ka hoʻohana ʻana i ka hiʻohiʻona hoʻololi sub-kekona · Kaapuni calibration kikohoʻe (hoʻoponopono hoʻoponopono manawa): 0.95 ppm pololei, loaʻa i kahi
pukaaniani kalibrasi o kekahi mau kekona

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· Manawaamp hana no ka mālama ʻana i ka hanana · Ka waiho ʻana o SWKEY ma nā palapala hoʻopaʻa RTC me ke komo kaʻa pololei i SAE (ʻaʻole
hiki ke heluhelu ʻia e ka CPU) · Nā hana hoʻopololei a hiki i ka maskable:
Alarm A Alarm B Wakeup keakea manawaamp · Kākoʻo TrustZone: RTC i hoʻopaʻa paʻa ʻia ʻo Alarm A, alarm B, wakeup timer a me ka manawaamp paʻa a paʻa ʻole paha ke kanaka
ka hoʻonohonoho ʻana i ka calibration RTC i hana paʻa ʻia ma ka hoʻonohonoho paʻa ʻole

3.29

Tamper a me nā papa inoa hoʻopaʻa (TAMP)
Mālama ʻia nā papa inoa hoʻopaʻa 32 x 32-bit ma nā ʻano mana haʻahaʻa a me ke ʻano VBAT. Hiki ke hoʻohana ʻia e mālama i ka ʻikepili koʻikoʻi e like me ka mālama ʻia ʻana o kā lākou ʻike e atamper kaapuni ike.
ʻEhiku tamper pine komo a me elima tampLoaʻa nā pine puka no ka anti-tampʻike ʻia. ʻO ka waho tamphiki ke hoʻonohonoho ʻia nā pine no ka ʻike maka, ka ʻaoʻao a me ka pae, ka ʻike pae me ka kānana, a i ʻole ka t hana.ampʻo ia ka mea e hoʻonui ai i ka pae palekana ma o ka nānā ʻana i ka tampʻAʻole wehe ʻia nā pine ma waho a pōkole paha.
TAMP nā hiʻohiʻona nui · 32 papa inoa hoʻopaʻa (TAMP_BKPxR) i hoʻokō ʻia ma ka domain RTC i koe
hoʻohana ʻia e VBAT ke pio ka mana VDD · 12 tamper pine i loaʻa (ʻehiku hoʻokomo a ʻelima puka) · Kekahi tampHiki i ka ʻike ʻana ke hana i kahi manawa RTCamp hanana. · Kekahi tampʻO ka ʻike ʻana e holoi i nā papa inoa hoʻihoʻi. · Kākoʻo TrustZone:
Ua ʻōlelo ʻo Tampka hoʻonohonoho paʻa ʻole a i ʻole ka hoʻonohonoho paʻa ʻole.
. hoʻokahi wahi paʻa heluhelu/kākau . hoʻokahi kākau paʻa/heluhelu wahi paʻa ʻole . hoʻokahi wahi heluhelu/kākau ʻaʻole paʻa ʻia · Monotonic counter

3.30

Nā pilina kaapuni i hui pū ʻia (I2C1, I2C2, I2C3, I2C4, I2C5)
Hoʻokomo nā mea hana i ʻelima mau kikowaena I2C.
Hoʻohana ke kaʻa kaʻa I2C i nā kamaʻilio ma waena o ka STM32MP133C/F a me ke kaʻa I2C serial. Mālama ʻo ia i nā kaʻina I2C-specific sequencing, protocol, arbitration a me ka manawa.

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Kākoʻo ka I2C peripheral: · I2C-bus specification and user manual rev. 5 kūpono:
Nā ʻano kauā a me nā ʻano haku, ka mana multimaster Mode-mode (Sm), me ka bitrate a hiki i ka 100 kbit/s Fast-mode (Fm), me ka bitrate a hiki i ka 400 kbit/s Fast-mode Plus (Fm+), me ka bitrate a hiki i ka 1 Mbit/s a me 20 mA output drive I/Os 7-bites address a me 10 mau hoʻonohonoho hoʻonohonoho hoʻonohonoho ʻana i nā polokalamu he nui. a hoʻopaʻa i nā manawa E hoʻolōʻihi ʻia ka uaki koho · System management bus (SMBus) kikoʻī kikoʻī hou 7 kūpono: Lako PEC (packet error checking) generation and verification with ACK
Kākoʻo ʻo Address resolution protocol (ARP) kākoʻo SMBus alert · Power system management protocol (PMBusTM) specification rev 1.1 compatibility · Independent clock: kahi koho o nā kumu wati kūʻokoʻa e ʻae ana i ka wikiwiki kamaʻilio I2C e kūʻokoʻa mai ka PCLK reprogramming · Wakeup from Stop mode on address match · Programmable analog and digital noise filters · 1-byte capability buffer.
Hiki ke ho'ākāka 'ia ka I2C3, I2C4 a me I2C5 (ma ETZPC) ma o ka lako polokalamu palekana wale nō.

3.31

Mea hoʻouna hoʻokipa asynchronous like ʻole (USART1, USART2, USART3, USART6 a me UART4, UART5, UART7, UART8)
ʻEhā mau mea hoʻouna hoʻokipa hoʻokipa honua i hoʻokomo ʻia (USART1, USART2, USART3 a me USART6) a ʻehā mau mea hoʻouna hoʻokipa asynchronous honua (UART4, UART5, UART7 a me UART8). E nānā i ka papa ma lalo no ka hōʻuluʻulu o nā hiʻohiʻona USARTx a me UARTx.
Hāʻawi kēia mau kikowaena i ke kamaʻilio asynchronous, kākoʻo ʻo IrDA SIR ENDEC, mode kamaʻilio multiprocessor, mode kamaʻilio hapalua-duplex uea hoʻokahi a loaʻa iā LIN haku/kauā mana. Hāʻawi lākou i ka hoʻokele waiwai o nā hōʻailona CTS a me RTS, a me RS485 Driver Enable. Hiki iā lākou ke kamaʻilio me ka wikiwiki a hiki i 13 Mbit/s.
Hāʻawi pū kekahi ʻo USART1, USART2, USART3 a me USART6 i ke ʻano Smartcard (koko ISO 7816) a me ka hiki ke kamaʻilio like me SPI.
Loaʻa i nā USART a pau kahi kikowaena uaki kūʻokoʻa mai ka uaki CPU, e ʻae ana i ka USARTx e hoʻāla i ka STM32MP133C/F mai Stop mode me ka hoʻohana ʻana i nā baudrates a hiki i 200 Kbaud. ʻO nā hanana wakeup mai Stop mode he programmable a hiki ke:
· hoʻomaka i ka ʻike bit
· kekahi pahu ʻikepili i loaʻa
· kahi kiʻi ʻikepili i hoʻolālā ʻia

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Hiki ke lawelawe ʻia nā pilina USART a pau e ka mana DMA.

Papa 5. Nā hiʻohiʻona USART/UART

Nā ʻano/nā hiʻohiʻona USART(1)

USART1/2/3/6

UART4/5/7/8

Kahe kahe o ka lako paʻa no ka modem

X

X

Ke kamaʻilio hoʻomau me ka hoʻohana ʻana iā DMA

X

X

Kamaʻilio Multiprocessor

X

X

ʻO ke ʻano SPI like ʻole (master/slave)

X

–

Kāleka akamai

X

–

Hoʻokaʻaʻike haʻahaʻa-duplex uea hoʻokahi IrDA SIR ENDEC poloka

X

X

X

X

ʻano LIN

X

X

Kānāwai uaki pālua a me ke ala ʻana mai ke ʻano mana haʻahaʻa

X

X

Hoʻopau ka mea loaʻa i ka manawa pau i ke kamaʻilio Modbus

X

X

X

X

ʻImi i ka helu helu baud auto

X

X

Keaukaha Enable

X

X

USART ka lōʻihi o ka ʻikepili

7, 8 a me 9 mau bits

1. X = kākoʻo.

Hiki ke wehewehe ʻia ʻo USART1 a me USART2 (ma ETZPC) i hiki ke loaʻa i nā polokalamu palekana wale nō.

3.32

Nā pilina pili pū (SPI1, SPI2, SPI3, SPI4, SPI5) nā loulou kani i hoʻohui pū ʻia (I2S1, I2S2, I2S3, I2S4)
Loaʻa nā mea hana i ʻelima SPI (SPI2S1, SPI2S2, SPI2S3, SPI2S4, a me SPI5) e hiki ai ke kamaʻilio a hiki i ka 50 Mbit/s i nā ʻano haku a me nā kauā, i nā ʻano half-duplex, fullduplex a me simplex. Hāʻawi ka 3-bit prescaler i ʻewalu master mode frequency a hiki ke hoʻonohonoho ʻia ke kiʻi mai 4 a 16 mau bits. Kākoʻo nā pānaʻi SPI āpau i ke ʻano pulse NSS, ke ʻano TI, ka helu CRC hāmeʻa a hoʻonui i ka 8-bit i hoʻokomo ʻia i Rx a me Tx FIFO me ka mana DMA.
Hoʻohui ʻia ʻo I2S1, I2S2, I2S3, a me I2S4 me SPI1, SPI2, SPI3 a me SPI4. Hiki iā lākou ke hoʻohana ʻia ma ke ʻano haku a i ʻole ke kauā, ma nā ʻano kamaʻilio piha-duplex a me ka hapalua-duplex, a hiki ke hoʻonohonoho ʻia e hana me kahi hoʻonā 16- a i ʻole 32-bit ma ke ʻano he ala hoʻokomo a puka. Audio sampKākoʻo ʻia nā alapine leo mai 8 kHz a hiki i 192 kHz. Kākoʻo nā pānaʻi I2S āpau i ka hoʻonui ʻana i nā Rx 8-bit i hoʻokomo ʻia a me Tx FIFO me ka mana DMA.
Hiki ke ho'ākāka 'ia ka SPI4 a me SPI5 (ma ETZPC) i hiki ke 'ike 'ia e ka lako polokalamu palekana wale nō.

3.33

Nā loulou leo ​​pū (SAI1, SAI2)
Hoʻokomo nā mea hana i ʻelua SAI e ʻae i ka hoʻolālā ʻana o nā ʻano leo stereo a i ʻole mono

DS13875 Hōʻike 5

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STM32MP133C/F

e like me I2S, LSB a i ʻole MSB-pono, PCM/DSP, TDM a i ʻole AC'97. Loaʻa kahi puka SPDIF ke hoʻonohonoho ʻia ka poloka leo ma ke ʻano he transmitter. No ka lawe ʻana i kēia pae o ka maʻalahi a me ka hoʻoponopono hou ʻana, loaʻa i kēlā me kēia SAI ʻelua sub-block leo kūʻokoʻa. Loaʻa i kēlā me kēia poloka ka mea hana uaki ponoʻī a me ka mea hoʻoponopono laina I/O. Audio sampKākoʻo ʻia nā alapine ling a hiki i 192 kHz. Eia kekahi, hiki ke kākoʻo ʻia a hiki i ʻewalu mau microphones mahalo i kahi interface PDM i hoʻokomo ʻia. Hiki i ka SAI ke hana ma ka hoʻonohonoho haku a kauā. Hiki i nā sub-block leo ke loaʻa a i ʻole transmitter a hiki ke hana me ka synchronously a i ʻole asynchronously (e pili ana i kekahi). Hiki ke hoʻopili ʻia ka SAI me nā SAI ʻē aʻe e hana like.

3.34

SPDIF mea hoʻokipa hoʻokipa (SPDIFRX)
Hoʻolālā ʻia ka SPDIFRX no ka loaʻa ʻana o kahi kahe S/PDIF e pili ana me IEC-60958 a me IEC-61937. Kākoʻo kēia mau maʻamau i nā kahawai stereo maʻalahi a hiki i s kiʻekiʻeampka leo, a me ka leo hoʻopuni lehulehu-channel i hoʻopaʻa ʻia, e like me nā mea i wehewehe ʻia e Dolby a i ʻole DTS (a hiki i 5.1).
ʻO nā hiʻohiʻona nui o ka SPDIFRX penei: · Hiki i ʻehā mau hoʻokomo i loaʻa · ʻIke i ka helu hōʻailona maʻamau · Ka helu hōʻailona kiʻekiʻe: 12.288 MHz · Kākoʻo Stereo mai 32 a 192 kHz kākoʻo · Kākoʻo o ka leo IEC-60958 a me IEC-61937, nā noi mea kūʻai aku · Parity bit management · Ke kamaʻilio me ka hoʻohana ʻana i ka DMA no nā leo leo.amples · Kūkākūkā me ka hoʻohana ʻana i ka DMA no ka hoʻomalu a me ka ʻike channel mea hoʻohana · Hoʻopau i nā hiki
Hāʻawi ka SPDIFRX i nā hiʻohiʻona e pono ai e ʻike i ka helu hōʻailona, ​​​​a hoʻokaʻawale i ke kahawai ʻikepili komo. Hiki i ka mea hoʻohana ke koho i ka hoʻokomo SPDIF i makemake ʻia, a i ka wā e loaʻa ai kahi hōʻailona kūpono, hoʻi hou ka SPDIFRXampʻO ka hōʻailona e hiki mai ana, hoʻokaʻawale i ke kahawai Manchester, a ʻike i nā kiʻi, nā sub-frames a me nā mea poloka. Hāʻawi ka SPDIFRX i ka ʻikepili decoded CPU, a me nā hae kūlana pili.
Hāʻawi pū ka SPDIFRX i kahi hōʻailona i kapa ʻia ʻo spdif_frame_sync, e huli ana i ka S/PDIF sub-frame rate i hoʻohana ʻia e helu i nā s pololei.ample uku no ka uaki drift algorithms.

3.35

Hoʻopaʻa paʻa i nā mea hoʻokomo kikohoʻe a puka mai MultiMediaCard (SDMMC1, SDMMC2)
Hāʻawi ʻia ʻelua mau kikowaena kikohoʻe paʻa / puka MultiMediaCard (SDMMC) i kahi pilina ma waena o ka pahi AHB a me nā kāleka hoʻomanaʻo SD, nā kāleka SDIO a me nā mea hana MMC.
Aia nā hiʻohiʻona SDMMC penei: · Hoʻokō me ka Embedded MultiMediaCard System Specification Version 5.1
Kākoʻo kāleka no ʻekolu mau ʻano hana databus: 1-bit (paʻamau), 4-bit a me 8-bit

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(HS200 SDMMC_CK ka wikiwiki i kaupalena ʻia i ka ʻae ʻia ka wikiwiki I/O) (ʻAʻole kākoʻo ʻia ʻo HS400)
· Hoʻohālikelike piha me nā mana o mua o MultiMediaCards (hoʻohālikelike hope)
· Hoʻokō piha i nā kikoʻī kikoʻī kāleka hoʻomanaʻo SD version 4.1 (SDR104 SDMMC_CK wikiwiki i kaupalena ʻia i ka wikiwiki I/O i ʻae ʻia, ke ʻano SPI a me ke ʻano UHS-II ʻaʻole i kākoʻo ʻia)
· Ka hoʻokō piha ʻana me ka palapala kikoʻī kāleka SDIO mana 4.0 Kākoʻo kāleka no ʻelua mau ʻano databus ʻokoʻa: 1-bit (paʻamau) a me 4-bit (SDR104 SDMMC_CK wikiwiki i kaupalena ʻia i ka wikiwiki I/O i ʻae ʻia, SPI mode a me UHS-II mode ʻaʻole i kākoʻo ʻia)
· Hoʻoili ʻikepili a hiki i 208 Mbyte/s no ke ʻano 8-bit (ma muli o ka wikiwiki I/O i ʻae ʻia)
· ʻIkepili a me ka hoʻopuka kauoha e hiki ai i nā hōʻailona ke hoʻomalu i nā mea hoʻokele bidirectional waho
· Hoʻopili ʻia ka mea hoʻokele DMA i hoʻokomo ʻia i loko o ka SDMMC host interface, e ʻae ana i nā hoʻololi kiʻekiʻe ma waena o ka interface a me ka SRAM
· kākoʻo papa inoa pili IDMA
· Nā lako mana i hoʻolaʻa ʻia, VDDSD1 a me VDDSD2 no SDMMC1 a me SDMMC2 i kēlā me kēia, e wehe ana i ka pono no ka hoʻokomo pae-shifter ma ka pā kāleka SD ma ke ʻano UHS-I.
Loaʻa kekahi mau GPIO no SDMMC1 a me SDMMC2 ma kahi pine hāʻawi VDDSD1 a i ʻole VDDSD2. He ʻāpana ia o nā GPIO boot paʻamau no SDMMC1 a me SDMMC2 (SDMMC1: PC [12:8], PD [2], SDMMC2: PB [15,14,4,3], PE3, PG6). Hiki ke ʻike ʻia lākou ma ka papa hana ʻē aʻe e nā hōʻailona me kahi suffix "_VSD1" a i ʻole "_VSD2".
Hoʻohui ʻia kēlā me kēia SDMMC me kahi poloka lohi (DLYBSD) e ʻae i ke kākoʻo o kahi alapine ʻikepili waho ma luna o 100 MHz.
Loaʻa nā kikowaena SDMMC ʻelua i nā awa hoʻonohonoho paʻa.

3.36

Pūnaewele ʻāpana hoʻomalu (FDCAN1, FDCAN2)
Aia i loko o ka ʻōnaehana ʻāpana kikowaena (CAN) ʻelua mau modula CAN, kahi hoʻomanaʻo RAM memo me kahi ʻāpana calibration uaki.
ʻO nā modula CAN ʻelua (FDCAN1 a me FDCAN2) kūpono i ka ISO 11898-1 (CAN protocol specification version 2.0 part A, B) a me CAN FD protocol specification version 1.0.
He 10-Kbyte memo RAM e hoʻohana ana i nā kānana, loaʻa nā FIFO, loaʻa nā pale, hoʻouna i nā FIFO hanana hanana a hoʻouna i nā pale (me nā mea hoʻoulu no TTCAN). Hāʻawi ʻia kēia memo RAM ma waena o nā modula FDCAN1 a me FDCAN2.
ʻO ka ʻāpana calibration uaki maʻamau ke koho. Hiki ke hoʻohana ʻia e hana i ka uaki calibrated no ka FDCAN1 a me FDCAN2 mai ka HSI internal RC oscillator a me ka PLL, ma ka loiloi ʻana i nā memo CAN i loaʻa e ka FDCAN1.

DS13875 Hōʻike 5

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3.37

Kaʻa kaʻa holo kiʻekiʻe kiʻekiʻe (USBH)
Hoʻokomo nā mea hana i hoʻokahi USB kiʻekiʻe wikiwiki host (a hiki i 480 Mbit/s) me ʻelua mau awa kino. Kākoʻo ʻo USBH i nā hana haʻahaʻa haʻahaʻa piha (OHCI) a me ka wikiwiki kiʻekiʻe (EHCI) ma kēlā me kēia awa. Hoʻohui ia i nā transceivers ʻelua i hiki ke hoʻohana ʻia no ka wikiwiki haʻahaʻa (1.2 Mbit/s), piha holo wikiwiki (12 Mbit/s) a i ʻole ka hana kiʻekiʻe (480 Mbit/s). Hāʻawi ʻia ka lua o ka transceiver kiʻekiʻe me ka OTG kiʻekiʻe-wikiwiki.
Hoʻopili ka USBH me ka kikoʻī USB 2.0. Pono nā mea hoʻokele USBH i nā uaki i hoʻolaʻa ʻia e kahi PLL i loko o ka USB kiʻekiʻe PHY.

3.38

USB ma ka holo kiʻekiʻe (OTG)
Hoʻokomo nā mea hana i hoʻokahi USB OTG kiʻekiʻe (a hiki i 480 Mbit/s) mea hoʻokipa/host/OTG peripheral. Kākoʻo ʻo OTG i nā hana holoʻokoʻa a me ka wikiwiki. Hoʻokaʻawale ʻia ka transceiver no ka hana kiʻekiʻe (480 Mbit/s) me ka USB Host lua awa.
Hoʻopili ʻia ka USB OTG HS me ka kikoʻī USB 2.0 a me ka kikoʻī OTG 2.0. Loaʻa iā ia kahi hoʻonohonoho hoʻonohonoho hoʻonohonoho polokalamu-configurable a kākoʻo i ka hoʻokuʻu / hoʻomau. Pono nā mea hoʻokele USB OTG i ka uaki 48 MHz i hoʻolaʻa ʻia e kahi PLL i loko o RCC a i ʻole i loko o ka USB high-speed PHY.
ʻO nā hiʻohiʻona nui USB OTG HS i helu ʻia ma lalo nei: · Hui pū ʻia Rx a me Tx FIFO nui o 4 Kbyte me ka nui FIFO sizing · SRP (sesion request protocol) a me HNP (host negotiation protocol) kākoʻo · ʻEwalu bidirectional endpoints · 16 host channels me ke kākoʻo OUT periodic · Software configurable to OTG1.3 a me OTG mana hoʻokele. · Hoʻoponopono kikoʻī kikoʻī e hoʻouka ana i ka pākaukau 2.0 kākoʻo · Kākoʻo HS OTG PHY · DMA USB kūloko · HNP/SNP/IP i loko (ʻaʻohe pono no ka pale ʻana o waho) · No nā ʻano OTG/Host, pono ke hoʻololi mana inā loaʻa nā mea hoʻohana i ka pahi.
pili.
Hiki ke paʻa ke awa hoʻonohonoho USB OTG.

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3.39

Nā kikowaena MAC Gigabit Ethernet (ETH1, ETH2)
Hāʻawi nā mea hana i ʻelua IEEE-802.3-2002-compliant gigabit media access controllers (GMAC) no ka Ethernet LAN kamaʻilio ma o ka ʻoihana-standard medium-independent interface (MII), kahi pānaʻi kūʻokoʻa liʻiliʻi liʻiliʻi (RMII), a i ʻole kahi kikowaena gigabit medium-independent interface (RGMII).
Pono nā mea hana i kahi hāmeʻa pili kino waho (PHY) e hoʻopili i ka pahi LAN kino (twisted-pair, fiber, etc.). Hoʻopili ʻia ka PHY i ke awa hāmeʻa me ka hoʻohana ʻana i nā hōʻailona 17 no MII, nā hōʻailona 7 no RMII, a i ʻole 13 mau hōʻailona no RGMII, a hiki ke hoʻopaʻa ʻia me ka hoʻohana ʻana i ka 25 MHz (MII, RMII, RGMII) a i ʻole 125 MHz (RGMII) mai ka STM32MP133C/F a i ʻole PHY.
Aia nā mea hana i kēia mau hiʻohiʻona: · Nā ʻano hana a me nā pilina PHY
10-, 100-, a me 1000-Mbit/s nā helu hoʻoili ʻikepili Kākoʻo ʻana i nā hana piha-duplex a me ka hapalua-duplex Nā kikowaena MII, RMII a me RGMII PHY · Ka hoʻoponopono ʻana i nā kānana Packet Multi-layer: kānana MAC ma ke kumu (SA) a me ka huakaʻi (DA)
ʻōlelo me ka kānana kūpono a me ka hash, VLAN tag-ka kānana e pili ana me ka kānana maikaʻi a me ka hash, Layer 3 kānana ma ke kumu IP (SA) a i ʻole ka helu wahi (DA), Layer 4 kānana ma ke kumu (SP) a i ʻole kahi e hele ai (DP) awa Hana pālua VLAN: hoʻokomo i ʻelua VLAN tags ma ke ala hoʻouna, tag kānana ma ke ala loaʻa kākoʻo IEEE 1588-2008/PTPv2 Kākoʻo i nā ʻikepili pūnaewele me nā helu helu RMON/MIB (RFC2819/RFC2665) · Ka hoʻoili ʻana o nā lako paʻa i ka hoʻokomo ʻana a i ʻole ka holoi ʻana i ka Integrity checksum offload engine no ka nānā ʻana i ka IPP/ICMPCP/LCD. helu helu helu a me ka hoʻohālikelike ʻO ka pane noi ARP maʻamau me ka hāmeʻa MAC address TCP segmentation: hoʻokaʻawale ʻakomi o ka ʻeke TCP nui e hoʻouna i loko o nā ʻeke liʻiliʻi he nui · Ke ʻano haʻahaʻa haʻahaʻa Energy efficient Ethernet (IEEE 802.3az-2010 maʻamau) ʻO ka pahu hoʻāla mamao a me ka ʻike AMD Magic PacketTM
Hiki ke hoʻolālā ʻia ʻo ETH1 a me ETH2 e like me ka palekana. Ke paʻa, paʻa nā hana ma luna o ka interface AXI, a hiki ke hoʻololi wale ʻia nā papa inoa hoʻonohonoho e nā komo paʻa.

DS13875 Hōʻike 5

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STM32MP133C/F

3.40

Debug i nā ʻōnaehana
Hāʻawi nā mea hana i nā hiʻohiʻona debug a me ka trace e kākoʻo i ka hoʻomohala ʻana i nā polokalamu a me ka hoʻohui ʻana i nā ʻōnaehana: · Breakpoint debugging · Code execution tracing · Software instrumentation · JTAG awa debug · awa hoʻoheheʻe uea Serial · Hoʻokomo a me ka hoʻopuka ʻana · Wawa hōʻailona · Arm CoreSight debug a me nā ʻāpana
Hiki ke hoʻomalu ʻia ka debug ma o kahi JTAG/serial-wire debug access port, me ka hoʻohana ʻana i nā mea hana hoʻopiʻi maʻamau.
Hiki i kahi awa hōʻailona ke hopu i ka ʻikepili no ka hoʻopaʻa inoa ʻana a me ka nānā ʻana.
Hiki ke komo i ka debug i nā wahi palekana e nā hōʻailona hōʻoia i ka BSEC.

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Pinout, wehewehe pine a me nā hana ʻē aʻe

4

Pinout, wehewehe pine a me nā hana ʻē aʻe

Helu 5. STM32MP133C/F LFBGA289 balota

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

A

VSS

PA9

PD10

PB7

PE7

PD5

PE8

PG4

PH9

PH13

PC7

PB9

PB14

PG6

PD2

PC9

VSS

B

PD3

PF5

PD14

PE12

PE1

PE9

PH14

PE10

PF1

PF3

PC6

PB15

PB4

PC10

PC12

DDR_DQ4 DDR_DQ0

C

PB6

PH12

PE14

PE13

PD8

PD12

PD15

VSS

PG7

PB5

PB3

VDDSD1

PF0

PC11

DDR_DQ1

DDR_ DQS0N

DDR_ DQS0P

D

PB8

PD6

VSS

PE11

PD1

PE0

PG0

PE15

PB12

PB10

VDDSD2

VSS

PE3

PC8

DDR_ DQM0

DDR_DQ5 DDR_DQ3

E

PG9

PD11

PA12

PD0

VSS

PA15

PD4

PD9

PF2

PB13

PH10

VDDQ_ DDR

DDR_DQ2 DDR_DQ6 DDR_DQ7 DDR_A5

DDR_ RESETN

F

PG10

PG5

PG8

PH2

PH8

VDDCPU

VDD

VDDCPU VDDCPU

VDD

VDD

VDDQ_ DDR

VSS

DDR_A13

VSS

DDR_A9

DDR_A2

G

PF9

PF6

PF10

PG15

PF8

VDD

VSS

VSS

VSS

VSS

VSS

VDDQ_ DDR

DDR_BA2 DDR_A7

DDR_A3

DDR_A0 DDR_BA0

H

PH11

PI3

PH7

PB2

PE4

VDDCPU

VSS

VDDCORE VDDCORE VDDCORE

VSS

VDDQ_ DDR

DDR_WEN

VSS

DDR_ODT DDR_CSN

DDR_ RASN

J

PD13

VBAT

PI2

VSS_PLL VDD_PLL VDDCPU

VSS

VDDCORE

VSS

VDDCORE

VSS

VDDQ_ DDR

VDDCORE DDR_A10

DDR_ CASN

DDR_ CLKP

DDR_ CLKN

K

PC14OSC32_IN

PC15OSC32_
Iwaho

VSS

PC13

PI1

VDD

VSS

VDDCORE VDDCORE VDDCORE

VSS

VDDQ_ DDR

DDR_A11 DDR_CKE DDR_A1 DDR_A15 DDR_A12

L

PE2

PF4

PH6

PI0

PG3

VDD

VSS

VSS

VSS

VSS

VSS

VDDQ_ DDR

DDR_ATO

DDR_ DTO0

DDR_A8 DDR_BA1 DDR_A14

M

PF7

PA8

PG11

VDD_ANA VSS_ANA

VDD

VDD

VDD

VDD

VDD

VDD

VDDQ_ DDR

DDR_ VREF

DDR_A4

VSS

DDR_ DTO1

DDR_A6

N

PE6

PG1

PD7

VSS

PB11

PF13

VSSA

PA3

NJTRST

VSS_USB VDDA1V1_

HS

REG

VDDQ_ DDR

PWR_LP

DDR_ DQM1

DDR_ DQ10

DDR_DQ8 DDR_ZQ

P

PH0OSC_IN

PH1OSC_OUT

PA13

PF14

PA2

VREF-

VDDA

PG13

PG14

VDD3V3_ USBHS

VSS

PI5-BOOT1 VSS_PLL2 PWR_ON

DDR_ DQ11

DDR_ DQ13

DDR_DQ9

R

PG2

PH3

PWR_CPU _ON

PA1

VSS

VREF+

PC5

VSS

VDD

PF15

VDDA1V8_ REG

PI6-BOOT2

VDD_PLL2

PH5

DDR_ DQ12

DDR_ DQS1N

DDR_ DQS1P

T

PG12

PA11

PC0

PF12

PC3

PF11

PB1

PA6

PE5

PDR_ON USB_DP2

PA14

USB_DP1

BYPASS_ REG1V8

PH4

DDR_ DQ15

DDR_ DQ14

U

VSS

PA7

PA0

PA5

PA4

PC4

PB0

PC1

PC2

NRST

USB_DM2

USB_ RREF

USB_DM1 PI4-BOOT0

PA10

PI7

VSS

MSv65067V5

Hōʻike ka kiʻi ma luna i ka piko o ka pūʻolo view.

DS13875 Hōʻike 5

49/219
97

Pinout, wehewehe pine a me nā hana ʻē aʻe

STM32MP133C/F

Helu 6. STM32MP133C/F TFBGA289 balota

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

A

VSS

PD4

PE9

PG0

PD15

PE15

PB12

PF1

PC7

PC6

PF0

PB14

VDDSD2 VDDSD1 DDR_DQ4 DDR_DQ0

VSS

B

PE12

PD8

PE0

PD5

PD9

PH14

PF2

VSS

PF3

PB13

PB3

PE3

PC12

VSS

DDR_DQ1

DDR_ DQS0N

DDR_ DQS0P

C

PE13

PD1

PE1

PE7

VSS

VDD

PE10

PG7

PG4

PB9

PH10

PC11

PC8

DDR_DQ2

DDR_ DQM0

DDR_DQ3 DDR_DQ5

D

PF5

PA9

PD10

VDDCPU

PB7

VDDCPU

PD12

VDDCPU

PH9

VDD

PB15

VDD

VSS

VDDQ_ DDR

DDR_ RESETN

DDR_DQ7 DDR_DQ6

E

PD0

PE14

VSS

PE11

VDDCPU

VSS

PA15

VSS

PH13

VSS

PB4

VSS

VDDQ_ DDR

VSS

VDDQ_ DDR

VSS

DDR_A13

F

PH8

PA12

VDD

VDDCPU

VSS

VDDCORE

PD14

PE8

PB5

VDDCORE

PC10

VDDCORE

VSS

VDDQ_ DDR

DDR_A7

DDR_A5

DDR_A9

G

PD11

PH2

PB6

PB8

PG9

PD3

PH12

PG15

PD6

PB10

PD2

PC9

DDR_A2 DDR_BA2 DDR_A3

DDR_A0 DDR_ODT

H

PG5

PG10

PF8

VDDCPU

VSS

VDDCORE

PH11

PI3

PF9

PG6

BYPASS_ REG1V8

VDDCORE

VSS

VDDQ_ DDR

DDR_BA0 DDR_CSN DDR_WEN

J VDD_PLL VSS_PLL

PG8

PI2

VBAT

PH6

PF7

PA8

PF12

VDD

VDDA1V8_ REG

PA10

DDR_ VREF

DDR_ RASN

DDR_A10

VSS

DDR_ CASN

K

PE4

PF10

PB2

VDD

VSS

VDDCORE

PA13

PA1

PC4

NRST

VSS_PLL2 VDDCORE

VSS

VDDQ_ DDR

DDR_A15

DDR_ CLKP

DDR_ CLKN

L

PF6

VSS

PH7

VDD_ANA VSS_ANA

PG12

PA0

PF11

PE5

PF15

VDD_PLL2

PH5

DDR_CKE DDR_A12 DDR_A1 DDR_A11 DDR_A14

M

PC14OSC32_IN

PC15OSC32_
Iwaho

PC13

VDD

VSS

PB11

PA5

PB0

VDDCORE

USB_ RREF

PI6-BOOT2 VDDCORE

VSS

VDDQ_ DDR

DDR_A6

DDR_A8 DDR_BA1

N

PD13

VSS

PI0

PI1

PA11

VSS

PA4

PB1

VSS

VSS

PI5-BOOT1

VSS

VDDQ_ DDR

VSS

VDDQ_ DDR

VSS

DDR_ATO

P

PH0OSC_IN

PH1OSC_OUT

PF4

PG1

VSS

VDD

PC3

PC5

VDD

VDD

PI4-BOOT0

VDD

VSS

VDDQ_ DDR

DDR_A4 DDR_ZQ DDR_DQ8

R

PG11

PE6

PD7

PWR_ CPU_ON

PA2

PA7

PC1

PA6

PG13

NJTRST

PA14

VSS

PWR_ON

DDR_ DQM1

DDR_ DQ12

DDR_ DQ11

DDR_DQ9

T

PE2

PH3

PF13

PC0

VSSA

VREF-

PA3

PG14

USB_DP2

VSS

VSS_ USBHS

USB_DP1

PH4

DDR_ DQ13

DDR_ DQ14

DDR_ DQS1P

DDR_ DQS1N

U

VSS

PG3

PG2

PF14

VDDA

VREF+

PDR_ON

PC2

USB_DM2

VDDA1V1_ REG

VDD3V3_ USBHS

USB_DM1

PI7

Hōʻike ka kiʻi ma luna i ka piko o ka pūʻolo view.

PWR_LP

DDR_ DQ15

DDR_ DQ10

VSS

MSv67512V3

50/219

DS13875 Hōʻike 5

STM32MP133C/F

Pinout, wehewehe pine a me nā hana ʻē aʻe

Helu 7. STM32MP133C/F TFBGA320 balota
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

A

VSS

PA9

PE13 PE12

PD12

PG0

PE15

PG7

PH13

PF3

PB9

PF0

PC10 PC12

PC9

VSS

B

PD0

PE11

PF5

PA15

PD8

PE0

PE9

PH14

PE8

PG4

PF1

VSS

PB5

PC6

PB15 PB14

PE3

PC11

DDR_ DQ4

DDR_ DQ1

DDR_ DQ0

C

PB6

PD3

PE14 PD14

PD1

PB7

PD4

PD5

PD9

PE10 PB12

PH9

PC7

PB3

VDD SD2

PB4

PG6

PC8

PD2

DDR_ DDR_ DQS0P DQS0N

D

PB8

PD6

PH12

PD10

PE7

PF2

PB13

VSS

DDR_ DQ2

DDR_ DQ5

DDR_ DQM0

E

PH2

PH8

VSS

VSS

VDD CPU

PE1

PD15

VDD CPU

VSS

VDD

PB10

PH10

VDDQ_ DDR

VSS

VDD SD1

DDR_ DQ3

DDR_ DQ6

F

PF8

PG9

PD11 PA12

VSS

VSS

VSS

DDR_ DQ7

DDR_ A5

VSS

G

PF6

PG10

PG5

VDD CPU

H

PE4

PF10 PG15

PG8

J

PH7

PD13

PB2

PF9

VDD CPU

VSS

VDD

VDD CPU

VDD CORE

VSS

VDD

VSS

VDDQ_ DDR

VSS

VSS

VDD

VDD

VSS

VDD CORE

VSS

VDD

VDD CORE

VDDQ_ DDR

DDR_ A13

DDR_ A2

DDR_ A9

DDR_ RESET
N

DDR_ BA2

DDR_ A3

DDR_ A0

DDR_ A7

DDR_ BA0

DDR_ CSN

DDR_ ODT

K

VSS_ PLL

VDD_ PLL

PH11

VDD CPU

PC15-

L

VBAT OSC32 PI3

VSS

_WAKU

PC14-

M

VSS OSC32 PC13

_IN

VDD

N

PE2

PF4

PH6

PI2

VDD CPU
VDD CORE
VSS
VDD

VSS

VSS

VSS

VSS

VSS

VDD CORE

VSS

VSS

VDD CORE

VSS

VSS

VSS

VSS

VSS

VDD

VDD CORE

VSS

VDD

VDD CORE

VDDQ_ DDR
VSS
VDDQ_ DDR
VDD CORE

VDDQ_ DDR

DDR_ WEN

DDR_ RASN

VSS

VSS

DDR_ A10

DDR_ CASN

DDR_ CLKN

VDDQ_ DDR

DDR_ A12

DDR_ CLKP

DDR_ A15

DDR_ A11

DDR_ A14

DDR_ CKE

DDR_ A1

P

PA8

PF7

PI1

PI0

VSS

VSS

DDR_ DTO1

DDR_ ATO

DDR_ A8

DDR_ BA1

R

PG1

PG11

PH3

VDD

VDD

VSS

VDD

VDD CORE

VSS

VDD

VDD CORE

VSS

VDDQ_ DDR

VDDQ_ DDR

DDR_ A4

DDR_ ZQ

DDR_ A6

T

VSS

PE6

PH0OSC_IN

PA13

VSS

VSS

DDR_ VREF

DDR_ DQ10

DDR_ DQ8

VSS

U

PH1OSC_ OUT

VSS_ ANA

VSS

VSS

VDD

VDDA VSSA

PA6

VSS

VDD CORE

VSS

VDD VDDQ_ CORE DDR

VSS

PWR_ ON

DDR_ DQ13

DDR_ DQ9

V

PD7

VDD_ ANA

PG2

PA7

VREF-

NJ TRST

VDDA1 V1_ REG

VSS

PWR_ DDR_ DDR_ LP DQS1P DQS1N

W

PWR_

PG3

PG12 CPU_ PF13

PC0

ON

PC3 VREF+ PB0

PA3

PE5

VDD

USB_ RREF

PA14

VDD 3V3_ USBHS

VDDA1 V8_ REG

VSS

BYPAS S_REG
1V8

PH5

DDR_ DQ12

DDR_ DQ11

DDR_ DQM1

Y

PA11

PF14

PA0

PA2

PA5

PF11

PC4

PB1

PC1

PG14

NRST

PF15

USB_ VSS_

PI6-

USB_

PI4-

VDD_

DM2 USBHS BOOT2 DP1 BOOT0 PLL2

PH4

DDR_ DQ15

DDR_ DQ14

AA

VSS

PB11

PA1

PF12

PA4

PC5

PG13

PC2

PDR_ ON

USB_ DP2

PI5-

USB_

BOOT1 DM1

VSS_ PLL2

PA10

PI7

VSS

Hōʻike ka kiʻi ma luna i ka piko o ka pūʻolo view.

MSv65068V5

DS13875 Hōʻike 5

51/219
97

Pinout, wehewehe pine a me nā hana ʻē aʻe

STM32MP133C/F

Pakuhi 6. Kaao / pōkole i hoʻohana ʻia i ka pākaina pinout

inoa

Pōʻokoʻa

Wehewehe

inoa pine ʻAno pine
ʻO ke kūkulu I / ʻO
Notes Nā hana ʻokoʻa Nā hana hou

Inā ʻaʻole i kuhikuhi ʻia, ʻo ka hana pin i ka wā a ma hope o ka hoʻoponopono ʻana ua like ia me ka inoa pine maoli

S

Pin lako

I

Hoʻokomo wale i ka pine

O

Hoʻopuka wale i ka pine

I/O

Pin hookomo/puka

A

Analog a i ʻole pine pae kūikawā

FT(U/D/PD) 5 V hoʻomanawanui I/O (me ka huki paʻa i luna / huki-iho / hiki ke hoʻolālā ʻia i lalo)

DDR

1.5 V, 1.35 V a i ʻole 1.2 VI/O no DDR3, DDR3L, LPDDR2/LPDDR3 interface

A

hōʻailona analog

RST

E hoʻopaʻa hou i ka pine me ka pale huki huki nāwaliwali

_f(1) _a(2) _u(3) _h(4)

Koho no FT I/Os I2C FM+ koho Analog koho (i hoolakoia e VDDA no ka analog hapa o ka I/O) USB koho (hoolako ia e VDD3V3_USBxx no ka USB hapa o ka I/O) High-wikiwiki puka no 1.8V typ. VDD (no SPI, SDMMC, QUADSPI, TRACE)

_vh(5)

Loa-kiʻekiʻe-wikiwiki koho no 1.8V typ. VDD (no ETH, SPI, SDMMC, QUADSPI, TRACE)

Inā ʻaʻole i kuhikuhi ʻia e kahi memo, ua hoʻonohonoho ʻia nā I/O a pau ma ke ʻano he hoʻokomo lana i ka wā a ma hope o ka hoʻonohonoho hou ʻana

Nā hana i koho ʻia ma o nā papa inoa GPIOx_AFR

Ua koho pololei ʻia nā hana ma o nā papa inoa peripheral

1. ʻO nā hale I/O pili i ka Papa 7, ʻo ia: FT_f, FT_fh, FT_fvh 2. ʻO nā hale I/O pili i ka Papa 7: FT_a, FT_ha, FT_vha 3. ʻO nā hale I/O pili i ka Papa 7: FT_u 4. ʻO nā hale I/O pili i ka Papa _, FTh 7. FT_fvh, FT_vh, FT_ha, FT_vha 5. ʻO nā hale I/O pili i ka Papa 7: FT_vh, FT_vha, FT_fvh

52/219

DS13875 Hōʻike 5

STM32MP133C/F

Pinout, wehewehe pine a me nā hana ʻē aʻe

Helu Pin

Papa 7. STM32MP133C/F wehewehe kinipopo

Nā hana kinipōpō

inoa pine (hana ma hope
hana hou)

Nā hana ʻē aʻe

Nā hana hou aku

LFBGA289 TFBGA289 TFBGA320
Hoʻolālā I/O ʻano pine
Nā memo

K10 F6 U14 A2 D2 A2 A1 A1 T5 M6 F3 U7
D4 E4 B2
B2 D1 B3 B1 G6 C2
C3 E2 C3 F6 D4 E7 E4 E1 B1
C2 G7 D3
C1 G3 C1

VDDCORE S

–

PA9

I/O FT_h

VSS VDD

S

–

S

–

PE11

I/O FT_vh

PF5

I/O FT_h

PD3

I/O FT_f

PE14

I/O FT_h

VDDCPU

S

–

PD0

I/O FT

PH12

I/O FT_fh

PB6

I/O FT_h

–

–

TIM1_CH2, I2C3_SMBA,

–

DFSDM1_DATIN0, USART1_TX, UART4_TX,

FMC_NWAIT(kāpae)

–

–

–

–

TIM1_CH2,

USART2_CTS/USART2_NSS,

SAI1_D2,

–

SPI4_MOSI/I2S4_SDO, SAI1_FS_A, USART6_CK,

ETH2_MII_TX_ER,

ETH1_MII_TX_ER,

FMC_D8(boot)/FMC_AD8

–

TRACED12, DFSDM1_CKIN0, I2C1_SMBA, FMC_A5

TIM2_CH1,

–

USART2_CTS/USART2_NSS, DFSDM1_CKOUT, I2C1_SDA,

SAI1_D3, FMC_CLK

TIM1_BKIN, SAI1_D4,

UART8_RTS/UART8_DE,

–

QUADSPI_BK1_NCS,

QUADSPI_BK2_IO2,

FMC_D11(boot)/FMC_AD11

–

–

SAI1_MCLK_A, SAI1_CK1,

–

FDCAN1_RX,

FMC_D2(boot)/FMC_AD2

USART2_TX, TIM5_CH3,

DFSDM1_CKIN1, I2C3_SCL,

–

SPI5_MOSI, SAI1_SCK_A, QUADSPI_BK2_IO2,

SAI1_CK2, ETH1_MII_CRS,

FMC_A6

TRACED6, TIM16_CH1N,

TIM4_CH1, TIM8_CH1,

–

USART1_TX, SAI1_CK2, QUADSPI_BK1_NCS,

ETH2_MDIO, FMC_NE3,

HDP6

–
–
–
TAMP_IN6 –
–
–

DS13875 Hōʻike 5

53/219
97

Pinout, wehewehe pine a me nā hana ʻē aʻe

STM32MP133C/F

Helu Pin

Papa 7. STM32MP133C/F wehewehe kinipopo (hoʻomau)

Nā hana kinipōpō

inoa pine (hana ma hope
hana hou)

Nā hana ʻē aʻe

Nā hana hou aku

LFBGA289 TFBGA289 TFBGA320
Hoʻolālā I/O ʻano pine
Nā memo

A17 A17 T17 M7 – J13 D2 G9 D2 F5 F1 E3 D1 G4 D1
E3 F2 F4 F8 D6 E10 F4 G2 E2 C8 B8 T21 E2 G1 F3
E1 G5 F2 G5 H3 F1 M8 – M5

VSS VDD PD6 PH8 PB8
PA12 VDDCPU
PH2 VSS PD11
PG9 PF8 VDD

S

–

S

–

I/O FT

I/O FT_fh

I/O FT_f

I/O FT_h

S

–

I/O FT_h

S

–

I/O FT_h

I/O FT_f

I/O FT_h

S

–

–

–

–

–

–

TIM16_CH1N, SAI1_D1, SAI1_SD_A, UART4_TX(boot)

TRACED9, TIM5_ETR,

–

USART2_RX, I2C3_SDA,

FMC_A8, HDP2

TIM16_CH1, TIM4_CH3,

I2C1_SCL, I2C3_SCL,

–

DFSDM1_DATIN1,

UART4_RX, SAI1_D1,

FMC_D13(boot)/FMC_AD13

TIM1_ETR, SAI2_MCLK_A,

USART1_RTS/USART1_DE,

–

ETH2_MII_RX_DV/ETH2_

RGMII_RX_CTL/ETH2_RMII_

CRS_DV, FMC_A7

–

–

LPTIM1_IN2, UART7_TX,

QUADSPI_BK2_IO0(boot),

–

ETH2_MII_CRS,

ETH1_MII_CRS, FMC_NE4,

ETH2_RGMII_CLK125

–

–

LPTIM2_IN2, I2C4_SMBA,

USART3_CTS/USART3_NSS,

SPDIFRX_IN0,

–

QUADSPI_BK1_IO2,

ETH2_RGMII_CLK125,

FMC_CLE(boot)/FMC_A16,

UART7_RX

DBTRGO, I2C2_SDA,

–

USART6_RX, SPDIFRX_IN3, FDCAN1_RX, FMC_NE2,

FMC_NCE(kāpae)

TIM16_CH1N, TIM4_CH3,

–

TIM8_CH3, SAI1_SCK_B, USART6_TX, TIM13_CH1,

QUADSPI_BK1_IO0(boot)

–

–

–
–
WKUP1
–

54/219

DS13875 Hōʻike 5

STM32MP133C/F

Pinout, wehewehe pine a me nā hana ʻē aʻe

Helu Pin

Papa 7. STM32MP133C/F wehewehe kinipopo (hoʻomau)

Nā hana kinipōpō

inoa pine (hana ma hope
hana hou)

Nā hana ʻē aʻe

Nā hana hou aku

LFBGA289 TFBGA289 TFBGA320
Hoʻolālā I/O ʻano pine
Nā memo

F3 J3 H5
F9 D8 G5 F2 H1 G3 G4 G8 H4
F1 H2 G2 D3 B14 U5 G3 K2 H3 H8 F10 G2 L1 G1 D12 C5 U6 M9 K4 N7 G1 H9 J5

PG8

I/O FT_h

VDDCPU PG5

S

–

I/O FT_h

PG15

I/O FT_h

PG10

I/O FT_h

VSS

S

–

PF10

I/O FT_h

VDDCORE S

–

PF6

I/O FT_vh

VSS VDD

S

–

S

–

PF9

I/O FT_h

TIM2_CH1, TIM8_ETR,

SPI5_MISO, SAI1_MCLK_B,

USART3_RTS/USART3_DE,

–

SPDIFRX_IN2,

QUADSPI_BK2_IO2,

QUADSPI_BK1_IO3,

FMC_NE2, ETH2_CLK

–

–

–

TIM17_CH1, ETH2_MDC, FMC_A15

USART6_CTS/USART6_NSS,

–

UART7_CTS, QUADSPI_BK1_IO1,

ETH2_PHY_INTN

SPI5_SCK, SAI1_SD_B,

–

UART8_CTS, FDCAN1_TX, QUADSPI_BK2_IO1(boot),

FMC_NE3

–

–

TIM16_BKIN, SAI1_D3, TIM8_BKIN, SPI5_NSS, – USART6_RTS/USART6_DE, UART7_RTS/UART7_DE,
QUADSPI_CLK(kāpae)

–

–

TIM16_CH1, SPI5_NSS,

UART7_RX(boot),

–

QUADSPI_BK1_IO2, ETH2_MII_TX_EN/ETH2_

RGMII_TX_CTL/ETH2_RMII_

TX_EN

–

–

–

–

TIM17_CH1N, TIM1_CH1,

DFSDM1_CKIN3, SAI1_D4,

–

UART7_CTS, UART8_RX, TIM14_CH1,

QUADSPI_BK1_IO1(boot),

QUADSPI_BK2_IO3, FMC_A9

TAMP_IN4
–
TAMP_IN1 –

DS13875 Hōʻike 5

55/219
97

Pinout, wehewehe pine a me nā hana ʻē aʻe

STM32MP133C/F

Helu Pin

Papa 7. STM32MP133C/F wehewehe kinipopo (hoʻomau)

Nā hana kinipōpō

inoa pine (hana ma hope
hana hou)

Nā hana ʻē aʻe

Nā hana hou aku

LFBGA289 TFBGA289 TFBGA320
Hoʻolālā I/O ʻano pine
Nā memo

H5 K1 H2 H6 E5 G7 H4 K3 J3 E5 D13 U11 H3 L3 J1
H1 H7 K3
J1 N1 J2 J5 J1 K2 J4 J2 K1 H2 H8 L4 K4 M3 M3

PE4 VDDCPU
PB2 VSS PH7
PH11
PD13 VDD_PLL VSS_PLL
PI3 PC13

I/O FT_h

S

–

I/O FT_h

S

–

I/O FT_fh

I/O FT_fh

I/O FT_h

S

–

S

–

I/O FT

I/O FT

SPI5_MISO, SAI1_D2,

DFSDM1_DATIN3,

TIM15_CH1N, I2S_CKIN,

–

SAI1_FS_A, UART7_RTS/UART7_DE,

–

UART8_TX,

QUADSPI_BK2_NCS,

FMC_NCE2, FMC_A25

–

–

–

RTC_OUT2, SAI1_D1,

I2S_CKIN, SAI1_SD_A,

–

UART4_RX,

QUADSPI_BK1_NCS(boot),

ETH2_MDIO, FMC_A6

TAMP_IN7

–

–

–

SAI2_FS_B, I2C3_SDA,

SPI5_SCK,

–

QUADSPI_BK2_IO3, ETH2_MII_TX_CLK,

–

ETH1_MII_TX_CLK,

QUADSPI_BK1_IO3

SPI5_NSS, TIM5_CH2,

SAI2_SD_A,

SPI2_NSS/I2S2_WS,

–

I2C4_SCL, USART6_RX, QUADSPI_BK2_IO0,

–

ETH2_MII_RX_CLK/ETH2_

RGMII_RX_CLK/ETH2_RMII_

REF_CLK, FMC_A12

LPTIM2_ETR, TIM4_CH2,

TIM8_CH2, SAI1_CK1,

–

SAI1_MCLK_A, USART1_RX, QUADSPI_BK1_IO3,

–

QUADSPI_BK2_IO2,

FMC_A18

–

–

–

–

–

–

(1)

SPDIFRX_IN3,

TAMP_IN4/TAMP_

ETH1_MII_RX_ER

OUT5, WKUP2

RTC_OUT1/RTC_TS/

(1)

–

RTC_LSCO, TAMP_IN1/TAMP_

OUT2, WKUP3

56/219

DS13875 Hōʻike 5

STM32MP133C/F

Pinout, wehewehe pine a me nā hana ʻē aʻe

Helu Pin

Papa 7. STM32MP133C/F wehewehe kinipopo (hoʻomau)

Nā hana kinipōpō

inoa pine (hana ma hope
hana hou)

Nā hana ʻē aʻe

Nā hana hou aku

LFBGA289 TFBGA289 TFBGA320
Hoʻolālā I/O ʻano pine
Nā memo

J3 J4 N5

PI2

I/O FT

(1)

SPDIFRX_IN2

TAMP_IN3/TAMP_ OUT4, WKUP5

K5 N4 P4

PI1

I/O FT

(1)

SPDIFRX_IN1

RTC_OUT2/RTC_ LSCO,
TAMP_IN2/TAMP_ OUT3, WKUP4

F13 L2 U13

VSS

S

–

–

–

–

J2 J5 L2

VBAT

S

–

–

–

–

L4 N3 P5

PI0

I/O FT

(1)

SPDIFRX_IN0

TAMP_IN8/TAMP_ Iwaho1

K2 M2

L3

PC15OSC32_OUT

I/O

FT

(1)

–

OSC32_OUT

F15 N2 U16

VSS

S

–

–

–

–

K1 M1 M2

PC14OSC32_IN

I/O

FT

(1)

–

OSC32_IN

G7 E3 V16

VSS

S

–

–

–

–

H9 K6 N15 VDDCORE S

–

–

–

–

M10 M4 N9

VDD

S

–

–

–

–

G8 E6 W16

VSS

S

–

–

–

–

USART2_RX,

L2 P3 N2

PF4

I/O FT_h

–

ETH2_MII_RXD0/ETH2_ RGMII_RXD0/ETH2_RMII_

–

RXD0, FMC_A4

MCO1, SAI2_MCLK_A,

TIM8_BKIN2, I2C4_SDA,

SPI5_MISO, SAI2_CK1,

M2 J8 P2

PA8

I/O FT_fh –

USART1_CK, SPI2_MOSI/I2S2_SDO,

–

OTG_HS_SOF,

ETH2_MII_RXD3/ETH2_

RGMII_RXD3, FMC_A21

TRACECLK, TIM2_ETR,

I2C4_SCL, SPI5_MOSI,

SAI1_FS_B,

L1 T1 N1

PE2

I/O FT_fh

–

USART6_RTS/USART6_DE, SPDIFRX_IN1,

–

ETH2_MII_RXD1/ETH2_

RGMII_RXD1/ETH2_RMII_

RXD1, FMC_A23

DS13875 Hōʻike 5

57/219
97

Pinout, wehewehe pine a me nā hana ʻē aʻe

STM32MP133C/F

Helu Pin

Papa 7. STM32MP133C/F wehewehe kinipopo (hoʻomau)

Nā hana kinipōpō

inoa pine (hana ma hope
hana hou)

Nā hana ʻē aʻe

Nā hana hou aku

LFBGA289 TFBGA289 TFBGA320
Hoʻolālā I/O ʻano pine
Nā memo

M1 J7 P3

PF7

I/O FT_vh –

M3 R1 R2

PG11

I/O FT_vh –

L3 J6 N3

PH6

I/O FT_fh –

N2 P4 R1

PG1

I/O FT_vh –

M11 – N12

VDD

S

–

–

N1 R2 T2

PE6

I/O FT_vh –

P1 P1 T3 PH0-OSC_IN I/O FT

–

G9 U1 N11

VSS

S

–

–

P2 P2 U2 PH1-OSC_OUT I/O FT

–

R2 T2 R3

PH3

I/O FT_fh –

M5 L5 U3 VSS_ANA S

–

–

TIM17_CH1, UART7_TX(kāpae),
UART4_CTS, ETH1_RGMII_CLK125, ETH2_MII_TXD0/ETH2_ RGMII_TXD0/ETH2_RMII_
TXD0, FMC_A18
SAI2_D3, I2S2_MCK, USART3_TX, UART4_TX, ETH2_MII_TXD1/ETH2_ RGMII_TXD1/ETH2_RMII_
TXD1, FMC_A24
TIM12_CH1, USART2_CK, I2C5_SDA,
SPI2_SCK/I2S2_CK, QUADSPI_BK1_IO2,
ETH1_PHY_INTN, ETH1_MII_RX_ER, ETH2_MII_RXD2/ETH2_
RGMII_RXD2, QUADSPI_BK1_NCS
LPTIM1_ETR, TIM4_ETR, SAI2_FS_A, I2C2_SMBA,
SPI2_MISO/I2S2_SDI, SAI2_D2, FDCAN2_TX, ETH2_MII_TXD2/ETH2_ RGMII_TXD2, FMC_NBL0
–
MCO2, TIM1_BKIN2, SAI2_SCK_B, TIM15_CH2, I2C3_SMBA, SAI1_SCK_B, UART4_RTS/UART4_DE,
ETH2_MII_TXD3/ETH2_ RGMII_TXD3, FMC_A22
–
–
–
I2C3_SCL, SPI5_MOSI, QUADSPI_BK2_IO1, ETH1_MII_COL, ETH2_MII_COL, QUADSPI_BK1_IO0
–

–
–
–
OSC_IN OSC_OUT –

58/219

DS13875 Hōʻike 5

STM32MP133C/F

Pinout, wehewehe pine a me nā hana ʻē aʻe

Helu Pin

Papa 7. STM32MP133C/F wehewehe kinipopo (hoʻomau)

Nā hana kinipōpō

inoa pine (hana ma hope
hana hou)

Nā hana ʻē aʻe

Nā hana hou aku

LFBGA289 TFBGA289 TFBGA320
Hoʻolālā I/O ʻano pine
Nā memo

L5 U2 W1

PG3

I/O FT_fvh –

TIM8_BKIN2, I2C2_SDA, SAI2_SD_B, FDCAN2_RX, ETH2_RGMII_GTX_CLK,
ETH1_MDIO, FMC_A13

M4 L4 V2 VDD_ANA S

–

–

–

R1 U3 V3

PG2

I/O FT

–

MCO2, TIM8_BKIN, SAI2_MCLK_B, ETH1_MDC

T1 L6 W2

PG12

I/O FT

LPTIM1_IN1, SAI2_SCK_A,

SAI2_CK2,

USART6_RTS/USART6_DE,

USART3_CTS,

–

ETH2_PHY_INTN,

ETH1_PHY_INTN,

ETH2_MII_RX_DV/ETH2_

RGMII_RX_CTL/ETH2_RMII_

CRS_DV

F7 P6 R5

VDD

S

–

–

–

G10 E8 T1

VSS

S

–

–

–

N3 R3 V1

MCO1, USART2_CK,

I2C2_SCL, I2C3_SDA,

SPDIFRX_IN0,

PD7

I/O FT_fh

–

ETH1_MII_RX_CLK/ETH1_ RGMII_RX_CLK/ETH1_RMII_

REF_CLK,

QUADSPI_BK1_IO2,

FMC_NE1

P3 K7 T4

PA13

I/O FT

–

DBTRGO, DBTRGI, MCO1, UART4_TX

R3 R4 W3 PWR_CPU_ON O FT

–

–

T2 N5 Y1

PA11

I/O FT_f

TIM1_CH4, I2C5_SCL,

SPI2_NSS/I2S2_WS,

USART1_CTS/USART1_NSS,

–

ETH2_MII_RXD1/ETH2_

RGMII_RXD1/ETH2_RMII_

RXD1, ETH1_CLK,

ETH2_CLK

N5 M6 AA2

PB11

TIM2_CH4, LPTIM1_OUT,

I2C5_SMBA, USART3_RX,

I/O FT_vh –

ETH1_MII_TX_EN/ETH1_

RGMII_TX_CTL/ETH1_RMII_

TX_EN

–
–
–
BOOTFAILN –
–

DS13875 Hōʻike 5

59/219
97

Pinout, wehewehe pine a me nā hana ʻē aʻe

STM32MP133C/F

Helu Pin

Papa 7. STM32MP133C/F wehewehe kinipopo (hoʻomau)

Nā hana kinipōpō

inoa pine (hana ma hope
hana hou)

Nā hana ʻē aʻe

Nā hana hou aku

LFBGA289 TFBGA289 TFBGA320
Hoʻolālā I/O ʻano pine
Nā memo

P4 U4

Y2

PF14(JTCK/SW CLK)

I/O

FT

(2)

U3 L7 Y3

PA0

I/O FT_a –

JTCK/SWCLK
TIM2_CH1, TIM5_CH1, TIM8_ETR, TIM15_BKIN, SAI1_SD_B, UART5_TX,
ETH1_MII_CRS, ETH2_MII_CRS

N6 T3 W4

PF13

TIM2_ETR, SAI1_MCLK_B,

I/O FT_a –

DFSDM1_DATIN3,

USART2_TX, UART5_RX

G11 E10 P7

F10 –

–

R4 K8 AA3

P5 R5 Y4 U4 M7 Y5

VSS VDD PA1
PA2
PA5

S

–

S

–

I/O FT_a

I/O FT_a I/O FT_a

–

–

–

–

TIM2_CH2, TIM5_CH2, LPTIM3_OUT, TIM15_CH1N,
DFSDM1_CKIN0, – USART2_RTS/USART2_DE,
ETH1_MII_RX_CLK/ETH1_ RGMII_RX_CLK/ETH1_RMII_
REF_CLK

TIM2_CH3, TIM5_CH3, – LPTIM4_OUT, TIM15_CH1,
USART2_TX, ETH1_MDIO

TIM2_CH1/TIM2_ETR,

USART2_CK, TIM8_CH1N,

–

SAI1_D1, SPI1_NSS/I2S1_WS,

SAI1_SD_A, ETH1_PPS_OUT,

ETH2_PPS_OUT

T3 T4 W5

SAI1_SCK_A, SAI1_CK2,

PC0

I/O FT_ha –

I2S1_MCK, SPI1_MOSI/I2S1_SDO,

USART1_TX

T4 J9 AA4
R6 U6 W7 P7 U5 ​​U8 P6 T6 V8

PF12

I/O FT_vha –

VREF+

S

–

–

VDDA

S

–

–

VREF-

S

–

–

SPI1_NSS/I2S1_WS, SAI1_SD_A, UART4_TX,
ETH1_MII_TX_ER, ETH1_RGMII_CLK125
–
–
–

–
ADC1_INP7, ADC1_INN3, ADC2_INP7, ADC2_INN3 ADC1_INP11, ADC1_INN10, ADC2_INP11, ADC2_INN10
–
ADC1_INP3, ADC2_INP3
ADC1_INP1, ADC2_INP1
ADC1_INP2
ADC1_INP0, ADC1_INN1, ADC2_INP0, ADC2_INN1, TAMP_IN3
ADC1_INP6, ADC1_INN2
–

60/219

DS13875 Hōʻike 5

STM3

Palapala / Punawai

STMicroelectronics STM32MP133C F 32-bit Arm Cortex-A7 1GHz MPU [pdf] Ke alakaʻi hoʻohana STM32MP133C F 32-bit Arm Cortex-A7 1GHz MPU, STM32MP133C, F 32-bit Arm Cortex-A7 1GHz MPU, Arm Cortex-A7 1GHz MPU, 1GHz, MPU

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