STMicroelectronics STM32MP133C F 32-bit Arm Cortex-A7 1GHz MPU Jagoran mai amfani

Abubuwan da ke ciki boye

1 STMicroelectronics STM32MP133C F 32-bit Arm Cortex-A7 1GHz MPU

2 Ƙayyadaddun bayanai

3 Arm Cortex-A7 Subsystem

4 Tunawa

5 DDR Controller

6 FAQs

7 Takardu / Albarkatu

7.1 Magana

8 Labarai masu alaka

STMicroelectronics STM32MP133C F 32-bit Arm Cortex-A7 1GHz MPU

Ƙayyadaddun bayanai

Mai tushe: Arm Cortex-A7
Memories: SDRAM na waje, SRAM da aka haɗa

Bus Data: 16-bit parallel interface
Tsaro/Tsaro: Sake saitin da Gudanar da Wuta, LPLV-Stop2, Jiran aiki

Kunshin: LFBGA, TFBGA tare da farar min 0.5 mm
Gudanar da agogo

Gabaɗaya-Input/Fitarwa
Interconnect Matrix

4 Masu Kula da DMA
Abubuwan Sadarwa: Har zuwa 29

Analog Peripherals: 6
Masu ƙidayar lokaci: Har zuwa 24, Dogs: 2

Hanzarta Hardware
Yanayin gyara kuskure

Fuses: 3072-bit gami da ID na musamman da HUK don maɓallan AES 256
ECOPACK2 mai yarda

Arm Cortex-A7 Subsystem

Tsarin Arm Cortex-A7 na STM32MP133C/F yana ba da…

Tunawa

Na'urar ta haɗa da SDRAM na waje da SRAM ɗin da aka saka don ma'ajin bayanai…

DDR Controller

Mai sarrafa DDR3/DDR3L/LPDDR2/LPDDR3 yana sarrafa damar ƙwaƙwalwar ajiya…

Gudanarwar Samar da Wutar Lantarki
Tsarin samar da wutar lantarki da mai kulawa suna tabbatar da ingantaccen isar da wutar lantarki…

Gudanar da agogo
RCC tana sarrafa rarraba agogo da daidaitawa…

Gabaɗaya-Input/Fitarwa (GPIOs)
GPIOs suna ba da damar dubawa don na'urorin waje…

Mai Kula da Kariyar TrustZone
ETZPC tana haɓaka tsarin tsaro ta hanyar sarrafa haƙƙin shiga…

Bus-Interconnect Matrix
Matrix yana sauƙaƙe canja wurin bayanai tsakanin sassa daban-daban…

FAQs

Tambaya: Menene matsakaicin adadin hanyoyin sadarwa da ke da tallafi?
A: STM32MP133C/F yana goyan bayan hanyoyin sadarwa 29.

Tambaya: Nawa na'urorin analog nawa ne ake samu?
A: Na'urar tana ba da na'urorin analog guda 6 don ayyukan analog daban-daban.

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Saukewa: STM32MP133C

Arm® Cortex®-A7 har zuwa 1 GHz, 2× ETH, 2×CAN FD, 2× ADC, 24 masu ƙidayar lokaci, audio, crypto da adv. tsaro
Datasheet - bayanan samarwa

Siffofin
Ya haɗa da fasahar haƙƙin mallaka na zamani na ST
Core
32-bit Arm® Cortex®-A7 L1 32-Kbyte I / 32-Kbyte D 128-Kbyte haɗin kai matakin 2 cache Arm® NEONTM da Arm® TrustZone®

Tunawa
Ƙwaƙwalwar DDR ta waje har zuwa 1 Gbyte har zuwa LPDDR2/LPDDR3-1066 16-bit har zuwa DDR3/DDR3L-1066 16-bit
Kbytes 168 na SRAM na ciki: 128 Kbytes na AXI SYSRAM + 32 Kbytes na AHB SRAM da 8 Kbytes na SRAM a cikin yankin Ajiyayyen
* Dual Quad-SPI ƙwaƙwalwar ƙwaƙwalwar ajiya · Mai sarrafa ƙwaƙwalwar waje mai sassauƙa tare da har zuwa
Bus ɗin bayanan 16-bit: ƙirar layi ɗaya don haɗa ICs na waje da ƙwaƙwalwar SLC NAND tare da har zuwa 8-bit ECC
Tsaro/aminci
Amintaccen taya, TrustZone® na gefe, 12 xtamper fil gami da 5 x mai aiki tampers
· Zazzabi, voltage, mita da kuma 32 kHz saka idanu
Sake saitawa da ikon sarrafawa
1.71 V zuwa 3.6 VI/Os wadata (5 V-mai haƙuri I/Os) · POR, PDR, PVD da BOR · On-chip LDOs (USB 1.8 V, 1.1 V) · Mai sarrafa Ajiyayyen (~ 0.9 V) · Na'urori masu auna zafin jiki na ciki · Yanayin ƙarancin wuta: Barci, Stop-Stop
LPLV-Stop2 da jiran aiki

LFBGA

TFBGA

LFBGA289 (14 × 14mm) Fitar 0.8 mm

TFBGA289 (9 × 9 mm) TFBGA320 (11 × 11 mm)
tsawon 0.5 mm

Riƙewar DDR a yanayin jiran aiki · Sarrafa ga guntu abokin PMIC

Gudanar da agogo
Oscillators na ciki: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz LSI oscillator
Oscillators na waje: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator
· 4 × PLLs tare da yanayin juzu'i

Gabaɗaya-manufa shigarwa/fitarwa
Har zuwa 135 amintattun tashoshin I/O tare da iyawar katsewa
· Har zuwa 6 farkawa

Interconnect matrix
Matrix bas 2 64-bit Arm® AMBA® AXI haɗin kai, har zuwa 266 MHz 32-bit Arm® AMBA® AHB haɗin haɗin gwiwa, har zuwa 209 MHz

4 Masu sarrafa DMA don sauke CPU
· Tashoshi 56 na zahiri gabaɗaya
1 x babban maƙasudin babban manufa na gaba ɗaya mai sarrafa damar ƙwaƙwalwar ajiya kai tsaye (MDMA)
3 × DMAs dual-tashar jiragen ruwa tare da FIFO kuma suna buƙatar ikon na'ura mai ba da hanya tsakanin hanyoyin sadarwa don ingantacciyar gudanarwa ta gefe.

Satumba 2024
Wannan bayani ne akan samfur a cikin cikakken samarwa.

Saukewa: DS13875

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www.st.com

Saukewa: STM32MP133C/F

Har zuwa na'urorin sadarwa guda 29
5 × I2C FM+ (1 Mbit/s, SMBus/PMBusTM) · 4 x UART + 4 x USART (12.5Mbit/s,
ISO7816 dubawa, LIN, IrDA, SPI) · 5 × SPI (50 Mbit / s, gami da 4 tare da cikakken duplex).
Daidaitaccen aji na I2S ta hanyar sauti na ciki PLL ko agogon waje) (+2 QUADSPI + 4 tare da USART) · 2 × SAI (sautin sitiriyo: I2S, PDM, SPDIF Tx) · SPDIF Rx tare da abubuwan shigarwa 4 · 2 × SDMMC har zuwa 8 ragowa (SD/e·CAN · MMCTM/SDIO) · 2 × 2 × 2.0 FDco na sarrafa USB 1 Mai watsa shiri mai sauri ko 2.0 × USB XNUMX Mai watsa shiri mai sauri

+ 1 × USB 2.0 high-gudun OTG lokaci guda · 2 x Ethernet MAC/GMAC IEEE 1588v2 hardware, MII/RMII/RGII
6 na'urorin analog
2 × ADCs tare da max 12-bit. ƙuduri har zuwa 5 msps
· 1 x firikwensin zafin jiki · 1 x tace dijital don modulator na sigma-delta
(DFSDM) tare da tashoshi 4 da masu tacewa 2 · Ciki ko na waje ADC reference VREF+
Har zuwa masu ƙidayar lokaci 24 da masu sa ido 2
2 × 32-bit masu ƙidayar lokaci tare da har zuwa 4 IC/OC/PWM ko bugun bugun jini da shigarwar quadrature (ƙara)
2 × 16-bit masu ƙididdige ƙididdigewa · 10 × 16-bit masu ƙidayar manufa na gaba ɗaya (ciki har da
2 na asali masu ƙididdiga ba tare da PWM ba) · 5 × 16-bit ƙananan masu ƙidayar ƙarfi · Amintaccen RTC tare da daidaito na biyu
kalanda hardware · 4 Cortex®-A7 tsarin masu ƙidayar lokaci (aminci,
mara tsaro, kama-da-wane, hypervisor) · 2 × masu sa ido masu zaman kansu
Hanzarta Hardware
· AES 128, 192, 256 DES/TDES

2 (mai zaman kansa, amintaccen mai zaman kansa) 5 (2 amintaccen) 4 5 (3 amintattu)
4 + 4 (ciki har da 2 amintaccen USART), wasu na iya zama tushen taya
2 (har zuwa tashoshi masu jiwuwa 4), tare da maigidan I2S / bawa, shigarwar PCM, tashoshin jiragen ruwa na SPDIF-TX 2
HSPHY da aka haɗa tare da BCD Embedded HS PHY tare da BCD (mai aminci), na iya zama tushen taya
2 × HS an raba tsakanin Mai watsa shiri da shigarwar OTG 4

2 (1 × TTCAN), daidaitawar agogo, 10 Kbyte raba buffer 2 (8 + 8 ragowa) (mai aminci), e·MMC ko SD na iya zama tushen boot ɗin 2 na zaɓin ingantacciyar wutar lantarki don musayar katin SD
1 (dual-quad) (mai aminci), na iya zama tushen taya

–
–
Boot
–
Boot
Boot Boot
(1)

Daidaitaccen adireshin/bayanai 8/16-bit FMC Daidaitaccen AD-mux 8/16-bit
NAND 8/16-bit 10/100M/Gigabit Ethernet DMA Cryptography
Hash True bazuwar lamba janareta Fuses (wanda ake iya shirye-shiryen lokaci ɗaya)

4 × CS, har zuwa 4 × 64 Mbyte
Ee, 2 × CS, SLC, BCH4/8, na iya zama tushen taya 2 x (MII, RMI, RGMII) tare da PTP da EEE (mai aminci)
3 lokuta (1 amintaccen), 33-tashar MDMA PKA (tare da kariyar DPA), DES, TDES, AES (tare da kariyar DPA)
(duk mai tsaro) SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-3, HMAC
(amintaccen) Gaskiya-RNG (amintaccen) 3072 masu tasiri ragowa (amintacce, 1280 ragowa akwai ga mai amfani)

–
Boot -
–

16/219

Saukewa: DS13875

Saukewa: STM32MP133C/F

Bayani

Tebura 1. Siffofin STM32MP133C/F da ƙididdiga na gefe (ci gaba)

STM32MP133CAE STM32MP133FAE STM32MP133CAG STM32MP133FAG STM32MP133CAF STM32MP133FAF Daban-daban

Siffofin

LFBGA289

TFBGA289

TFBGA320

GPIOs tare da katsewa (jimlar ƙidayar)

135 (2)

Amintattun GPIOs Wakeup fil

Duka
6

Tamper fil (aiki tamper)

12 (5)

DFSDM Har zuwa 12-bit ADC mai aiki tare

Tashoshi 4 na shigarwa tare da tacewa 2

–

2 (3) (har zuwa 5 Msps akan 12-bit kowane) (amintaccen)

ADC1: Tashoshi 19 ciki har da 1x na ciki, tashoshi 18 akwai don

12-bit ADC tashoshi a duka(4)

mai amfani gami da bambancin 8x

–

ADC2: Tashoshi 18 ciki har da 6x na ciki, tashoshi 12 akwai don

mai amfani gami da bambancin 6x

ADC VREF VREF+ na ciki fil shigar

1.65V, 1.8V, 2.048V, 2.5V ko VREF+ shigar -
Ee

1. QUADSPI na iya yin taya ko dai daga GPIO da aka keɓe ko ta amfani da wasu FMC Nand8 boot GPIOs (PD4, PD1, PD5, PE9, PD11, PD15 (duba Table 7: STM32MP133C/F ma'anar ball).
2. Wannan jimlar GPIO ya ƙunshi J guda huɗuTAG GPIOs da BOOT GPIO guda uku tare da iyakancewar amfani (na iya yin karo da haɗin na'urar waje yayin duba iyaka ko taya).
3. Lokacin da aka yi amfani da duka ADCs, agogon kwaya ya kamata ya zama iri ɗaya don duka ADCs kuma ba za a iya amfani da na'urorin ADC da aka haɗa ba.
4. Bugu da ƙari, akwai kuma tashoshi na ciki: - ADC1 tashar ciki: VREFINT - ADC2 tashoshi na ciki: zafin jiki, vol na cikitage reference, VDDCORE, VDDCPU, VDDQ_DDR, VBAT / 4.

Saukewa: DS13875

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Bayanin 18/219

Saukewa: STM32MP133C/F

Hoto 1. STM32MP133C/F toshe zane

IC kayayyaki

@VDDA

Hsi

AXIM: Haɗin haɗin 64-bit AXI (266 MHz) T

@VDDCPU

GIC

Cortex-A7 CPU 650/1000 MHz + MMU + FPU + NEONT

32k D$

32k ku

CNT (lokacin lokaci) T

ETM

2561K2B8LK2B$L+2$SCU T
async

128 bits

CSI

LSI

Gyara lokaciamp

janareta TSGEN

DAP
(JTAG/SWD)

SYSRAM 128KB

ROM 128 KB

2 x ETH MAC
10/100/1000 (babu GMII)

FIFO

BKPSRAM 8KB

RNG

HASH

16b PHY

Bayanan Bayani na DRCTRL58
LPDDR2/3, DDR3/3L

async

CRYP

SAES

DDRMCE TZC T

Farashin DDRPHYC
T

DLY

8b QUADSPI (dual) T

16b

FMC

CRC

DLYBSD1

(SDMMC1 DLY iko)

DLYBSD2

(SDMMC2 DLY iko)

DLYBQS

(Ikon QUADSPI DLY)

Farashin FIFO

DLY DLY

14 8b SDMMC1 T 14 8b SDMMC2 T

PHY

USBH

(2xHS Mai watsa shiri)

PLLUSB

FIFO

PKA

FIFO

T MDMA 32 tashoshi

Farashin AXIMC TT

17 16b Trace tashar jiragen ruwa

Farashin ETZPC

Farashin IWDG1

@VBAT

BSEC

Farashin OTP

@VDDA

RTC/AWU

TAMP / Ajiyayyen T

@VBAT

LSE (32kHz XTAL)

Tsarin lokaci STGENC

tsara

STGENR

USBPHYC
(USB 2 x PHY iko)
Farashin IWDG2

@VBAT

@VDDA

VREFBUF

16b LPTIM2

16b LPTIM3

16b LPTIM4

16b LPTIM5

BOOT fil

SYSCFG

HDP

10 16b TIM1/PWM 10 16b TIM8/PWM

SAI1

SAI2

4ch DFSDM

Buffer 10KB CCU

FDCAN1

FDCAN2

Farashin FIFO
APB2 (100 MHz)

8KB FIFO
APB5 (100MHz)

APB3 (100 MHz)

Saukewa: APB4

Saukewa: AHB2APB

SRAM1 16KB T SRAM2 8KB T SRAM3 8KB T

Saukewa: AHB2APB

DMA1
8 rafuffuka
DMAMUX1
DMA2
8 rafuffuka

DMAMUX2

DMA3
8 rafuffuka

PMB (mai duba tsari)
DTS (dijital temp. firikwensin)

Voltage masu mulki

@VDDA

Kulawar samarwa

FIFO

2 × 2 Matrix
Saukewa: AHB2APB

64 bit AXI

64bits AXI master

32-bit AHB 32-bit AHB master

32 bit APB

T TrustZone kariyar tsaro

Saukewa: AHB2APB

APB2 (100 MHz)

APB1 (100 MHz)
FIFO FIFO FIFO FIFO

MLAHB: Arm 32-bit Multi-AHB bas matrix (209 MHz)
Saukewa: APB6
FIFO FIFO FIFO

@VBAT
T
FIFO

HSE (XTAL)

PLL1/2/3/4

RCC

Farashin PWR

KASHE

16 na gaba

176

USBO

(OTG HS)

PHY

12b ADC1

12b ADC2

GPIOA

16b

GPIOB

16b

GPIOC

16b

GPIOD

16b

GPIOE

16b

GPIOF

16b

GPIOG 16b 16

GPIOH

16b

GPIOI

16b

Saukewa: AHB2APB

USART1

Smartcard IrDA

USART2

Smartcard IrDA

SPI4/I2S4

Saukewa: SPI5

I2C3/SMBUS

I2C4/SMBUS

I2C5/SMBUS

Tace tace

TIM12

16b

TIM13

16b

TIM14

16b

TIM15

16b

TIM16

16b

TIM17

16b

TIM2 TIM3 TIM4

32b

16b

TIM5 TIM6 TIM7

32b

16b

LPTIM1 16b

USART3

Smartcard IrDA

Farashin 4

Farashin 5

Farashin 7

Farashin 8

Filin Tace

I2C1/SMBUS

I2C2/SMBUS

SPI2/I2S2

SPI3/I2S3

USART6

Smartcard IrDA

SPI1/I2S1

Farashin FIFO

MSv67509V2

Saukewa: DS13875

Saukewa: STM32MP133C/F

Aiki ya ƙareview

3.1
3.1.1
3.1.2

Arm Cortex-A7 subsystem
Siffofin
ARMv7-A gine-gine · 32-Kbyte L1 cache umarni · 32-Kbyte L1 data cache · 128-Kbyte level2 cache · Arm + Thumb®-2 wa'azi saitin · Arm TrustZone fasahar tsaro · Arm NEON ci-gaba SIMD · DSP da SIMD kari · VFPv4 floating-point Harshen goyan bayan Haɗaɗɗen mai sarrafa katsewa gabaɗaya (GIC) tare da katsewar yanki guda 160 · Integrated generic timer (CNT)
Ƙarsheview
Cortex-A7 na'ura mai sarrafa kayan aiki ne mai ƙarfi mai ƙarfi wanda aka ƙera don samar da kyakkyawan aiki a cikin manyan kayan sawa, da sauran ƙananan ƙarfin da aka saka da aikace-aikacen mabukaci. Yana ba da ƙarin aikin zare har zuwa 20% fiye da Cortex-A5 kuma yana ba da irin wannan aikin fiye da Cortex-A9.
Cortex-A7 ya haɗa da duk fasalulluka na manyan na'urori na Cortex-A15 da CortexA17, gami da tallafin haɓakawa a cikin hardware, NEON, da 128-bit AMBA 4 AXI bas dubawa.
Mai sarrafa Cortex-A7 yana ginawa akan 8-s mai ƙarfin kuzaritage bututun na Cortex-A5 processor. Hakanan yana fa'ida daga haɗaɗɗen cache na L2 wanda aka ƙera don ƙarancin ƙarfi, tare da ƙarancin latency na ma'amala da ingantaccen tallafin OS don kiyaye cache. A saman wannan, akwai ingantaccen tsinkayar reshe da ingantaccen tsarin aikin ƙwaƙwalwar ajiya, tare da hanyar 64-bit loadstore, 128-bit AMBA 4 AXI bas da haɓaka girman TLB (shigarwa 256, sama da shigarwar 128 don Cortex-A9 da Cortex-A5), haɓaka aiki don manyan ayyukan aiki kamar su. web lilo.
Thumb-2 fasaha
Yana ba da aikin kololuwar lambar hannu ta gargajiya yayin da kuma tana ba da ragi har zuwa 30% cikin buƙatun ƙwaƙwalwar ajiya don ajiyar umarni.
Fasahar TrustZone
Yana tabbatar da ingantaccen aiwatar da aikace-aikacen tsaro tun daga sarrafa haƙƙin dijital zuwa biyan kuɗi na lantarki. Babban tallafi daga fasaha da abokan masana'antu.

Saukewa: DS13875

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Aiki ya ƙareview

Saukewa: STM32MP133C/F

NEON
Fasahar NEON na iya haɓaka multimedia da algorithms masu sarrafa sigina irin su rikodin bidiyo / yanke hukunci, zane-zane na 2D / 3D, wasan kwaikwayo, sarrafa sauti da magana, sarrafa hoto, wayar tarho, da haɗin sauti. Cortex-A7 yana ba da injin da ke ba da duka ayyuka da ayyuka na ƙungiyar Cortex-A7 floating-point (FPU) da aiwatar da tsarin koyarwar SIMD na ci gaba na NEON da aka saita don ƙarin haɓaka hanyoyin watsa labarai da ayyukan sarrafa sigina. NEON ya ƙaddamar da Cortex-A7 processor FPU don samar da quad-MAC da ƙarin saitin rajista na 64-bit da 128-bit wanda ke goyan bayan fa'ida mai yawa na ayyukan SIMD akan 8-, 16- da 32-bit integer da 32-bit floating-point data yawa.
Haɓaka Hardware
Ingantacciyar goyon bayan kayan masarufi don sarrafa bayanai da sasantawa, ta yadda mahallin software da yawa da aikace-aikacensu ke samun damar samun damar tsarin lokaci guda. Wannan yana ba da damar gane na'urorin da suke da ƙarfi, tare da mahallin kama-da-wane waɗanda ke keɓe da juna.
Ingantattun caches na L1
Ayyuka da ingantattun caches na L1 sun haɗu da ƙananan dabarun jinkirin samun dama don haɓaka aiki da rage yawan amfani da wutar lantarki.
Hadakar mai sarrafa cache L2
Yana ba da ƙananan latency da babban bandwidth damar zuwa ƙwaƙwalwar ajiya mai girma, ko don rage amfani da wutar lantarki mai alaƙa da samun damar ƙwaƙwalwar ajiyar guntu.
Ƙungiyar Cortex-A7 (FPU)
FPU tana ba da ƙayyadaddun ayyuka guda ɗaya da madaidaicin umarni-madaidaicin madaidaicin madaidaicin Arm VFPv4 gine wanda ke da software mai dacewa da al'ummomin baya na Arm floating-point coprocessor.
Naúrar sarrafa Snoop (SCU)
SCU tana da alhakin sarrafa haɗin kai, sasantawa, sadarwa, cache zuwa cache da canja wurin ƙwaƙwalwar ajiyar tsarin, haɗin cache da sauran damar mai sarrafawa.
Wannan tsarin haɗin gwiwar kuma yana rage rikitar software da ke cikin kiyaye daidaituwar software a cikin kowane direban OS.
Mai sarrafa katsewa gabaɗaya (GIC)
Aiwatar da daidaitaccen mai sarrafa katsewa da tsararru, GIC yana ba da ingantacciyar hanya mai sauƙi da sauƙi don sadarwa tsakanin masu sarrafawa da sarrafawa da fifikon tsarin katsewa.
Taimakawa har zuwa 192 katsewa masu zaman kansu, ƙarƙashin sarrafa software, kayan aikin da aka ba da fifiko, da karkatar da su tsakanin tsarin aiki da Layer sarrafa software na TrustZone.
Wannan sassaucin ra'ayi da kuma goyan bayan ƙirƙira na katsewa cikin tsarin aiki, yana ba da ɗayan mahimman abubuwan da ake buƙata don haɓaka ƙarfin mafita ta amfani da hypervisor.

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Saukewa: DS13875

Saukewa: STM32MP133C/F

Aiki ya ƙareview

3.2
3.2.1
3.2.2

Tunawa
SDRAM na waje
Na'urorin STM32MP133C/F sun haɗa na'ura mai sarrafawa don SDRAM na waje wanda ke tallafawa masu zuwa: LPDDR2 ko LPDDR3, 16-bit data, har zuwa 1 Gbyte, zuwa agogon 533 MHz · DDR3 ko DDR3L, bayanan 16-bit, har zuwa 1 Gbyte, har zuwa 533 MHz .
Shigar da SRAM
Duk na'urorin suna da fasali: · SYSRAM: 128 Kbytes (tare da yankin tsaro mai girman shirye-shirye) · AHB SRAM: 32 Kbytes (amintaccen) · BKPSRAM (SRAM na baya): 8 Kbytes
Abubuwan da ke cikin wannan yanki an kiyaye su daga yuwuwar samun damar rubutu maras so, kuma ana iya kiyaye shi cikin yanayin jiran aiki ko VBAT. Ana iya siffanta BKPSRAM (a cikin ETZPC) azaman samun dama ta hanyar amintaccen software kawai.

3.3

DDR3/DDR3L/LPDDR2/LPDDR3 mai sarrafa (DDRCTRL)

DDRCTRL haɗe tare da DDRPHYC yana ba da cikakkiyar mafita ga ƙwaƙwalwar ƙwaƙwalwar ajiya don tsarin ƙwaƙwalwar ajiyar DDR. 64-bit AMBA 4 AXI Ports interface (XPI) · Agogon AXI daidai yake da mai sarrafawa · Injin ƙwaƙwalwar ƙwaƙwalwar ajiya na DDR (DDRMCE) wanda ke nuna AES-128 DDR akan-da-tashi
boye-boye/ karanta decryption. · Ma'auni masu goyan baya:
Bayanin JEDEC DDR3 SDRAM, JESD79-3E don DDR3/3L tare da ƙirar 16-bit
Bayanin JEDEC LPDDR2 SDRAM, JESD209-2E don LPDDR2 tare da ƙirar 16-bit
Bayanin JEDEC LPDDR3 SDRAM, JESD209-3B don LPDDR3 tare da ƙirar 16-bit
Advanced scheduler and SDRAM order generator · Programmable full data wide wide (16-bit) or half data wide (8-bit) · Advanced QoS support with three trafic class on read and two trafictures on write · Zabuka don gujewa yunwar karancin fifikon zirga-zirga · Tabbatar da daidaiton rubutu-bayan karanta (WAR) da karanta bayan-rubuta (RAW) akan
Tashar jiragen ruwa na AXI · Taimakon shirye-shirye don zaɓuɓɓukan tsayin fashe (4, 8, 16) · Rubuta hade don ba da damar yin rubutu da yawa zuwa adireshi iri ɗaya cikin
Rubutu ɗaya · Tsantsar daraja ɗaya

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· Taimakawa SDRAM ta atomatik shigarwa da fitarwa ta hanyar rashin isowar ma'amala don lokacin shirye-shirye
· Taimakawa tsayawar agogo ta atomatik (LPDDR2/3) shigarwa da fita wanda ya haifar da rashin isowar ciniki
· Taimakawa aikin yanayin ƙarancin wutar lantarki ta atomatik wanda ya haifar da rashin isowar ma'amala don lokacin shirye-shirye ta hanyar ƙirar ƙarancin wutar lantarki
· Manufofin rubutun da za a iya tsarawa · Taimakawa ta atomatik ko ƙarƙashin software don sabunta shigarwa da fitarwa · Taimakawa shigarwa da fitarwa mai zurfi a ƙarƙashin ikon software (LPDDR2 da
LPDDR3) · Goyan bayan sabunta rajistar yanayin SDRAM na zahiri a ƙarƙashin sarrafa software · Ma'anar taswirar adireshi mai sassauƙa don ba da damar takamaiman aikace-aikacen taswirar jere, shafi,
ɓangarorin banki · Zaɓuɓɓukan sarrafawa na wartsake da zaɓaɓɓen mai amfani · DDRPERFM toshe mai alaƙa don taimakawa don saka idanu da daidaitawa.
DDRCTRL da DDRPHYC za a iya ayyana su (a cikin ETZPC) azaman samun dama ta software mai aminci kawai.
DDRMCE (DDR memory cypher engine) manyan fasalulluka an jera su a ƙasa: · AXI system bus master/slave interfaces (64-bit) · In-line encryption (don rubutawa) da kuma ɓarna (don karantawa), dangane da shigar da tacewar zaɓi.
Shirye-shirye · Yanayin ɓoyewa guda biyu a kowane yanki (mafi girman yanki ɗaya): babu ɓoyewa (yanayin wucewa),
Yanayin toshewa · Farawa da ƙarshen yankuna da aka ayyana tare da 64-Kbyte granularity · Tsoffin tacewa (yanki 0): duk wani damar da aka bayar · Tace hanyar yanki: babu kowa.
Siffar toshe mai goyan bayan: AES Yanayin sarka mai goyan baya · Yanayin toshewa tare da AES cipher ya dace da yanayin ECB da aka kayyade a cikin NIST FIPS bugu na 197 ingantaccen ma'aunin ɓoyewa (AES), tare da aikin haɓaka maɓalli mai alaƙa dangane da Keccak-400 algorithm da aka buga akan https://keccak.team website. Saitin maɓalli ɗaya na rubuta-kawai da masu kullewa na maɓalli na maɓalli · tashar tashar ta AHB, mai gata

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3.4

TrustZone mai sarrafa sarari adreshin don DDR (TZC)

Ana amfani da TZC don tace karanta/rubuta damar shiga ga mai sarrafa DDR bisa ga haƙƙin TrustZone kuma bisa ga ƙwararrun ƙwararrun masani (NSAID) akan yankuna har zuwa guda tara masu shirye-shirye: · Tsarin da ke goyan bayan amintaccen software kawai · Sashin tacewa ɗaya · Yankuna tara:
Ana kunna yanki 0 koyaushe kuma yana rufe duk iyakar adireshi. Yankuna 1 zuwa 8 suna da adireshi-/karshen adireshin kuma ana iya sanya su
kowane daya ko biyu tace. Amintaccen izini da ba amintacce ba wanda aka tsara a kowane yanki · Abubuwan da ba amintacce ba da aka tace bisa ga NSAID · Yankunan da tacewa ɗaya ba dole ba ne su mamaye ba · Yanayin gazawa tare da kuskure da/ko katsewa · Ƙarfin yarda = 256 · Ƙofar mai tsaron ƙofar don kunna da kashe kowane tacewa · Hanyoyi masu ƙima

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3.5

Boot halaye

A lokacin farawa, tushen boot ɗin da ROM ɗin boot ɗin ciki ke amfani da shi ana zaɓin BOOT fil da OTP bytes.

Tebur 2. Hanyoyin takalma

BOOT2 BOOT1 BOOT0 Yanayin taya na farko

Sharhi

Jira haɗin mai shigowa:

UART da USB (1)

USART3/6 da UART4/5/7/8 akan tsoho fil

Na'urar USB mai sauri akan OTG_HS_DP/DM fil (2)

1 Serial NOR filasha (3) Serial KO filasha akan QUADSPI(5)

e·MMC(3)

e·MMC akan SDMMC2 (tsoho)(5)(6)

NAND flash (3)

SLC NAND flash akan FMC

Boot ɗin haɓakawa (babu boot ɗin ƙwaƙwalwar filashi)

Ana amfani da shi don samun damar gyara kuskure ba tare da taya daga ƙwaƙwalwar filasha ba(4)

Katin SD(3)

Katin SD akan SDMMC1 (tsoho)(5)(6)

Jira haɗin mai shigowa:

0 UART da USB (1) (3) USART3/6 da UART4/5/7/8 akan tsoho fil

Na'urar USB mai sauri akan OTG_HS_DP/DM fil (2)

1 Serial NAND flash(3) Serial NAND flash akan QUADSPI(5)

1. Za a iya kashe shi ta saitunan OTP. 2. USB yana buƙatar agogon HSE/crystal (duba AN5474 don mitoci masu goyan baya tare da kuma ba tare da saitunan OTP ba). 3. Za a iya canza tushen taya ta saitunan OTP (ga misaliampda farko taya akan katin SD, sannan e·MMC tare da saitunan OTP). 4. Cortex®-A7 core a cikin mara iyaka madauki toggling PA13. 5. OTP na iya canza tsoho fil. 6. A madadin, wani SDMMC interface fiye da wannan tsoho za a iya zaba ta OTP.

Kodayake ana yin ƙaramin matakin taya ta amfani da agogon ciki, ST ya ba da fakitin software da kuma manyan musaya na waje kamar DDR, USB (amma ba'a iyakance su ba) suna buƙatar kristal ko oscillator na waje don haɗa su akan fil ɗin HSE.
Dubi RM0475 “STM32MP13xx Advanced Arm® tushen 32-bit MPUs” ko AN5474 “Farawa tare da haɓaka kayan aikin layin STM32MP13xx” don ƙuntatawa da shawarwari game da haɗin filaye na HSE da mitoci masu goyan baya.

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3.6

Gudanar da samar da wutar lantarki

3.6.1
Tsanaki:

Makircin samar da wuta
VDD shine babban kayan aiki na I/Os kuma ana kiyaye ɓangaren ciki yayin yanayin jiran aiki. Voltage kewayon shine 1.71 V zuwa 3.6 V (1.8 V, 2.5 V, 3.0 V ko 3.3V nau'in.)
VDD_PLL da VDD_ANA dole ne su kasance masu haɗin tauraro zuwa VDD. VDDCPU shine Cortex-A7 CPU sadaukarwa voltage wadata, wanda darajarsa ta dogara da
mitar CPU da ake so. 1.22V zuwa 1.38V a cikin yanayin gudu. VDD dole ne ya kasance a gaban VDDCPU. VDDCORE shine babban voltage kuma yawanci yana kashewa yayin yanayin jiran aiki. Voltage kewayon shine 1.21 V zuwa 1.29 V a cikin yanayin gudu. VDD dole ne ya kasance a gaban VDDCORE. Ana iya haɗa fil ɗin VBAT zuwa baturin waje (1.6 V <VBAT <3.6 V). Idan ba a yi amfani da baturi na waje ba, dole ne a haɗa wannan fil zuwa VDD. VDDA shine analog (ADC/VREF), wadata voltage (1.62 zuwa 3.6V). Yin amfani da VREF + na ciki yana buƙatar VDDA daidai ko sama da VREF+ + 0.3 V. Ana kunna mai sarrafa VDDA1V8_REG na ciki ta tsohuwa kuma ana iya sarrafa shi ta software. Ana kashe shi koyaushe yayin yanayin jiran aiki.
Ba dole ba ne a taɓa barin takamaiman fil ɗin BYPASS_REG1V8 yana shawagi. Dole ne a haɗa shi ko dai zuwa VSS ko zuwa VDD don kunna ko kashe voltage regulator. Lokacin da VDD = 1.8 V, BYPASS_REG1V8 ya kamata a saita. · VDDA1V1_REG fil shine fitarwa na mai sarrafa na ciki, wanda aka haɗa ta ciki zuwa USB PHY. Ana kunna mai sarrafa VDDA1V1_REG na ciki ta tsohuwa kuma ana iya sarrafa shi ta software. Ana kashe shi koyaushe yayin yanayin jiran aiki.
· VDD3V3_USBHS shine kebul na USB mai sauri. VoltagMatsakaicin iyaka shine 3.07 V zuwa 3.6 V.
VDD3V3_USBHS kada ya kasance sai dai idan VDDA1V8_REG yana nan, in ba haka ba lalacewa ta dindindin na iya faruwa akan STM32MP133C/F. Dole ne a tabbatar da wannan ta hanyar tsarin martaba na PMIC ko tare da bangaren waje idan ana aiwatar da samar da wutar lantarki mai hankali.
VDDSD1 da VDDSD2 bi da bi SDMMC1 da SDMMC2 SD katin samar da wutar lantarki don tallafawa yanayin ultra-high-gudun.
VDDQ_DDR shine wadatar DDR IO. 1.425 V zuwa 1.575 V don haɗawa da ƙwaƙwalwar DDR3 (nau'in 1.5 V)
1.283 V zuwa 1.45 V don haɗawa da ƙwaƙwalwar DDR3L (nau'in 1.35 V)
1.14 V zuwa 1.3 V don haɗawa da ƙwaƙwalwar LPDDR2 ko LPDDR3 (nau'in 1.2 V)
A lokacin haɓakawar wutar lantarki da saukowa, dole ne a mutunta buƙatun jerin wutar lantarki masu zuwa:
Lokacin da VDD ke ƙasa da 1 V, sauran kayan wuta (VDDCORE, VDDCPU, VDDSD1, VDDSD2, VDDA, VDDA1V8_REG, VDDA1V1_REG, VDD3V3_USBHS, VDDQ_DDR) dole ne su kasance ƙasa da VDD + 300 mV.
Lokacin da VDD ta kasance sama da 1 V, duk kayan wutar lantarki masu zaman kansu ne.
A lokacin lokacin saukar wutar lantarki, VDD na iya zama ƙasa da ɗan lokaci fiye da sauran kayayyaki kawai idan makamashin da aka bayar ga STM32MP133C/F ya kasance ƙasa da 1 mJ. Wannan yana ba da damar fitar da capacitors na waje tare da maɓalli daban-daban na lokaci a lokacin tsaka mai ƙarfi.

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V 3.6
Farashin 0

Hoto 2. Power-up / saukar jerin

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VDDX (1) VDD

3.6.2
Lura: 26/219

0.3

Powerarfin wuta

Yanayin aiki

Powerarfin ƙasa

lokaci

Wurin wadata mara inganci

VDDX <VDD + 300mV

VDDX mai zaman kanta daga VDD

MSv47490V1

1. VDDX yana nufin duk wani wutar lantarki tsakanin VDDCORE, VDDCPU, VDDSD1, VDDSD2, VDDA, VDDA1V8_REG, VDDA1V1_REG, VDD3V3_USBHS, VDDQ_DDR.

Mai kula da samar da wutar lantarki

Na'urorin suna da haɗe-haɗe na sake saitin wutar lantarki (POR)/sake saitin saukar wuta (PDR) haɗe tare da na'urar sake saiti na Brownout (BOR):
Sake saitin wutar lantarki (POR)
Mai kula da POR yana saka idanu akan samar da wutar lantarki na VDD kuma yana kwatanta shi da ƙayyadaddun ƙofa. Na'urorin suna kasancewa cikin yanayin sake saiti lokacin da VDD ke ƙasa da wannan madaidaicin, · Sake saitin saukar da wuta (PDR)
Mai kula da PDR yana lura da samar da wutar lantarki na VDD. Ana haifar da sake saiti lokacin da VDD ta faɗo ƙasa da kafaffen madaidaici.
Sake saitin Brownout (BOR)
Mai kula da BOR yana lura da wutar lantarki ta VDD. Ana iya daidaita mashigin BOR guda uku (daga 2.1 zuwa 2.7 V) ta hanyar zaɓin bytes. Ana haifar da sake saiti lokacin da VDD ta faɗi ƙasa da wannan madaidaicin.
· Sake saitin wutar lantarki VDDCORE (POR_VDDCORE) Mai kula da POR_VDDCORE yana sa ido kan samar da wutar lantarki ta VDDCORE kuma yana kwatanta shi da kafaffen madaidaici. Yankin VDDCORE ya kasance cikin yanayin sake saiti lokacin da VDDCORE ke ƙasa da wannan madaidaicin.
Sake saitin saukar da wutar lantarki VDDCORE (PDR_VDDCORE) Mai kula da PDR_VDDCORE yana sa ido kan samar da wutar lantarki ta VDDCORE. Ana haifar da sake saitin yanki na VDDCORE lokacin da VDDCORE ya faɗo ƙasa ƙayyadaddun madaidaicin madaidaici.
VDDCPU-sake saitin wutar lantarki (POR_VDDCPU) Mai kula da POR_VDDCPU yana sa ido kan samar da wutar lantarki ta VDDCPU kuma yana kwatanta shi da kafaffen madaidaici. Yankin VDDCPU ya kasance a cikin yanayin sake saiti lokacin da VDDCORE ke ƙasa da wannan madaidaicin.
An tanada fil ɗin PDR_ON don gwaje-gwajen samarwa na STMicroelectronics kuma dole ne koyaushe a haɗa shi da VDD a cikin aikace-aikace.

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3.7

Dabarar ƙarancin ƙarfi

Akwai hanyoyi da yawa don rage amfani da wutar lantarki akan STM32MP133C/F: · Rage yawan amfani da wutar lantarki ta rage saurin agogon CPU da/ko
agogon matrix bas da/ko sarrafa agogon gefe guda ɗaya. · Ajiye amfani da wutar lantarki lokacin da CPU ke IDLE, ta zaɓi tsakanin ƙarancin da ake samu.
yanayin wutar lantarki bisa ga bukatun aikace-aikacen mai amfani. Wannan yana ba da damar mafi kyawun sasantawa tsakanin ɗan gajeren lokacin farawa, ƙarancin amfani da wutar lantarki, da kuma hanyoyin farkawa, da za a samu. · Yi amfani da DVFS (mai ƙarfi voltage da mitar sikelin) wuraren aiki waɗanda ke sarrafa mitar agogon CPU kai tsaye da kuma samar da fitarwa na VDDCPU.
Hanyoyin aiki suna ba da damar sarrafa rarraba agogo zuwa sassa daban-daban na tsarin da ikon tsarin. Yanayin aiki na tsarin yana gudana ta tsarin tsarin MPU.
An jera ƙananan tsarin tsarin MPU a ƙasa: · CSleep: Ana dakatar da agogon CPU kuma agogon gefe yana aiki kamar
wanda aka saita a baya a cikin RCC (sake saitin da mai kula da agogo). CStop: An dakatar da agogon gefe (s) na CPU. · CSJERIYA: VDDCPU KASHE
Yanayin ƙananan ƙarfin CSleep da CStop suna shigar da CPU yayin aiwatar da WFI (jiran katsewa) ko WFE (jira taron).
Hanyoyin aiki da tsarin da ake da su sune kamar haka: · Gudu (tsarin a cikakken aikinsa, VDDCORE, VDDCPU da agogon ON) · Tsaya (KASHIN KASHI) · LP-Tsaya (Agogon KASHE) · LPLV-Tsaya (Agogon KASHE, VDDCORE da VDDCPU matakin samar da matakin na iya ragewa) · LPLV-Stop2FFV (DD, VDD) Jiran aiki (VDDCPU, VDDCORE, da Agogon KASHE)

Table 3. Tsarin da yanayin wutar lantarki na CPU

Yanayin wutar lantarki

CPU

Yanayin aiki

Crun ko CSleep

Yanayin Tsaida Yanayin LP-Tsaya Yanayin LPLV-Tsaya Yanayin LPLV-Stop2
Yanayin jiran aiki

CStop ko CSTrandby CSTrandby

3.8

Sake saiti da mai sarrafa agogo (RCC)

Agogon da sake saiti mai sarrafawa yana kula da tsararru na duk agogo, da kuma agogon gating, da kuma kula da tsarin da kuma sake saiti. Bugu da ƙari, akan wasu abubuwan haɗin sadarwa waɗanda ke da ikon yin aiki da su

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3.8.1 3.8.2

yankuna biyu daban-daban na agogo daban-daban (ko dai agogon dubawar bas ko agogon kernel), ana iya canza mitar tsarin ba tare da canza baudrate ba.
Gudanar da agogo
Na'urorin sun haɗa oscillators na ciki huɗu, oscillators biyu tare da crystal na waje ko resonator, oscillators na ciki uku tare da lokacin farawa da sauri da PLL huɗu.
RCC tana karɓar abubuwan shigar agogo masu zuwa: · Oscillators na ciki:
Agogon HSI 64 MHz (daidaita 1%) 4 MHz agogon CSI agogon 32 kHz LSI Agogo · Oscillators na waje: 8-48 MHz agogon HSE agogo 32.768 kHz agogon LSE
RCC tana ba da PLLs guda huɗu: · PLL1 sadaukarwa ga CPU clocking · PLL2 tana ba da:
agogo don AXI-SS (gami da APB4, APB5, AHB5 da gadoji AHB6) agogo don dubawar DDR · PLL3 yana ba da: agogo don AHB da yawa da matrix bas na gefe (gami da APB1,
APB2, APB3, APB6, AHB1, AHB2, da AHB4) agogon kwaya don abubuwan da ke kewaye · PLL4 da aka keɓe don tsara agogon kwaya don sassa daban-daban
Tsarin yana farawa akan agogon HSI. Aikace-aikacen mai amfani zai iya zaɓar daidaitawar agogo.
Tushen sake saitin tsarin
Sake saitin wutar lantarki yana fara fara duk rajista sai dai don gyara kuskure, wani ɓangare na RCC, wani ɓangare na RTC da rikodin matsayi na mai sarrafa wuta, da kuma yankin ikon Ajiyayyen.
Ana samun sake saitin aikace-aikacen daga ɗayan waɗannan hanyoyin: · sake saiti daga pad na NRST · sake saiti daga POR da siginar PDR (wanda ake kira power-on reset) · sake saiti daga BOR (wanda ake kira brownout) · sake saiti daga mai tsaro mai zaman kanta kunnawa
Ana samar da sake saitin tsarin daga ɗayan hanyoyin masu zuwa: · sake saitin aikace-aikacen · sake saiti daga siginar POR_VDDCORE · fita daga yanayin jiran aiki zuwa yanayin Run.

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Ana samar da sake saitin processor na MPU daga ɗayan waɗannan hanyoyin: · sake saitin tsarin · duk lokacin da MPU ta fita CSstandby · Sake saitin MPU na software daga Cortex-A7 (CPU)

3.9

Gabaɗaya shigarwar shigarwa/fitarwa (GPIOs)

Ana iya daidaita kowane fil ɗin GPIO ta hanyar software azaman fitarwa (turawa ko buɗaɗɗen ruwa, tare da ko ba tare da cirewa ko cirewa ba), azaman shigarwa (tare da ko ba tare da cirewa ko ja da ƙasa ba) ko azaman madadin aiki na gefe. Yawancin fil ɗin GPIO ana raba su tare da na'urar dijital ko na'urar analog. Duk GPIOs suna da ƙarfin halin yanzu kuma suna da zaɓin sauri don sarrafa hayaniyar ciki, amfani da wutar lantarki da fitar da wutar lantarki.
Bayan sake saiti, duk GPIOs suna cikin yanayin analog don rage yawan wutar lantarki.
Ana iya kulle tsarin I/O idan an buƙata ta bin takamaiman jeri don guje wa rubutattun ɓoyayyiya zuwa rijistar I/Os.
Ana iya saita duk fil ɗin GPIO daidaiku a matsayin amintattu, wanda ke nufin cewa software tana isa ga waɗannan GPIOs da abubuwan da ke da alaƙa da aka ayyana amintacce an iyakance su don amintaccen software da ke aiki akan CPU.

3.10
Lura:

Mai sarrafa kariyar TrustZone (ETZPC)
Ana amfani da ETZPC don saita tsaro na TrustZone na mashahuran bas da bayi tare da halayen tsaro na shirye-shirye (abubuwa masu aminci). Misali: Ana iya tsara girman girman yanki na SYSRAM akan guntu. · AHB da APB na gefe za a iya sanya su amintacce ko maras tsaro. · AHB SRAM na iya zama amintacce ko mara tsaro.
Ta hanyar tsoho, an saita SYSRAM, AHB SRAMs da maɓalli masu aminci don samun damar shiga kawai, don haka, ba masu iyawa masu aminci kamar DMA1/DMA2 ke samun damar shiga ba.

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3.11

Matrix haɗin haɗin bas
Na'urorin sun ƙunshi matrix bas na AXI, babban matrix na AHB bas guda ɗaya da gadoji na bas waɗanda ke ba da izinin haɗin gwiwar manyan motocin bas da bayin bas (duba hoton da ke ƙasa, ɗigon yana wakiltar haɗin haɗin maigida/bayi da aka kunna).
Hoto 3. STM32MP133C/F matrix bas

MDMA

Bayanin SDMMC2

Bayanin SDMMC1

DBG Daga MLAHB haɗin haɗin USBH

CPU

Farashin ETH1

128-bit

AXIM

M1 M2

M11

S1 S2 S3 S4 S5 S6 S7 S8

Tsohuwar bawa AXIMC

NIC-400 AXI 64 bits 266 MHz - 10 masters / 10 bayi

Daga haɗin haɗin AXIM DMA1 DMA2 USBO DMA3

M1 M2

M3 M4

M6 M7

S4 S5 Interconnect AHB 32 bits 209 MHz - 8 masters / 6 bayi

DDRCTRL 533 MHz AHB gada zuwa AHB6 Zuwa MLAHB haɗin haɗin FMC/NAND QUADSPI SYSRAM 128 KB ROM 128 KB AHB gada zuwa gada AHB5 APB zuwa gadar APB5 APB zuwa DBG APB
AXI 64 synchronous master port AXI 64 synchronous bawa tashar jiragen ruwa AXI 64 asynchronous babban tashar jiragen ruwa AXI 64 asynchronous bawa tashar jiragen ruwa AHB 32 synchronous babban tashar jiragen ruwa AHB
Gada zuwa AHB2 SRAM1 SRAM2 SRAM3 Zuwa gadar haɗin AXIM zuwa AHB4
MSv67511V2

MLAHB

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3.12

Masu sarrafa DMA
Na'urorin sun ƙunshi nau'ikan DMA masu zuwa don sauke ayyukan CPU: · babban damar ƙwaƙwalwar ajiyar kai tsaye (MDMA)
MDMA babban mai sarrafa DMA ne mai sauri, wanda ke kula da kowane nau'in canja wurin ƙwaƙwalwar ajiya (na gefe-zuwa ƙwaƙwalwar ajiya, ƙwaƙwalwar ajiya-zuwa ƙwaƙwalwar ajiya, ƙwaƙwalwar ajiya-zuwa gefe), ba tare da wani aikin CPU ba. Yana fasalta babban AXI interface. MDMA tana iya yin mu'amala tare da sauran masu sarrafa DMA don tsawaita daidaitattun damar DMA, ko kuma tana iya sarrafa buƙatun DMA na gefe kai tsaye. Kowace tashoshi 32 na iya yin toshe canja wuri, maimaita jujjuyawar toshewar da haɗin lissafin da aka haɗa. Ana iya saita MDMA don yin amintaccen canja wuri zuwa amintattun ƙwaƙwalwar ajiya. · Masu kula da DMA guda uku (ba amintacce DMA1 da DMA2 ba, da DMA3 amintacce) Kowane mai sarrafawa yana da tashar jiragen ruwa guda biyu AHB, don jimlar 16 mara tsaro da tashoshi takwas masu aminci na DMA don aiwatar da bulogin tushen FIFO.
Raka'a DMAMUX guda biyu multix kuma suna bibiyar buƙatun DMA zuwa ga masu kula da DMA guda uku, tare da babban sassauci, suna haɓaka adadin buƙatun DMA waɗanda ke gudana a lokaci guda, da kuma samar da buƙatun DMA daga abubuwan fitarwa na gefe ko abubuwan DMA.
DMAMUX1 taswirorin DMA buƙatun daga wuraren da ba amintacce ba zuwa tashoshin DMA1 da DMA2. Taswirorin DMAMUX2 DMA buƙatun daga amintattun wurare zuwa tashoshin DMA3.

3.13

Extended katsewa da mai sarrafa taron (EXTI)
Tsawaita katsewa da mai sarrafa taron (EXTI) yana sarrafa CPU da farkawa ta tsarin ta hanyar daidaitawa da abubuwan shigar da taron kai tsaye. EXTI yana ba da buƙatun farkawa ga ikon iko, kuma yana haifar da buƙatun katsewa ga GIC, da abubuwan da suka faru zuwa shigar da taron CPU.
Buƙatun farkawa na EXTI suna ba da damar a farka da tsarin daga yanayin Tsaya, kuma za a tashe CPU daga yanayin CStop da CStandby.
Hakanan za'a iya amfani da buƙatar katsewa da ƙirar buƙatun taron a Yanayin Run.
EXTI kuma ya haɗa da zaɓin EXTI IOport.
Kowane katsewa ko taron ana iya saita shi azaman amintacce don taƙaita samun amintacciyar software kawai.

3.14

Unitungiyar ƙididdigar sake sake zagaye na Cyclic (CRC)
Ana amfani da naúrar ƙididdige CRC (binciken sake sakewa a cyclic) don samun lambar CRC ta amfani da nau'ikan nau'ikan tsari.
Daga cikin wasu aikace-aikacen, ana amfani da dabarun tushen CRC don tabbatar da watsa bayanai ko amincin ma'ajiya. A cikin iyakokin ma'aunin EN/IEC 60335-1, suna ba da hanyar tabbatar da amincin ƙwaƙwalwar walƙiya. Ƙungiyar lissafin CRC tana taimakawa wajen ƙididdige sa hannun software a lokacin aiki, don kwatanta shi da sa hannu na tunani da aka samar a lokacin haɗin kai kuma a adana shi a wurin da aka ba da ƙwaƙwalwar ajiya.

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3.15

Mai sarrafa ƙwaƙwalwar ajiya mai sassauƙa (FMC)
Babban fasalulluka masu sarrafa FMC sune kamar haka: · Interface tare da na'urorin da aka tsara taswirar ƙwaƙwalwar ajiya gami da:
NO flash memory Static ko pseudo-static random access memory (SRAM, PSRAM) NAND flash memory with 4-bit/8-bit BCH hardware ECC · 8-,16-bit data bas nisa · Independent guntu-zabi iko ga kowane bankin memori · Tsari mai zaman kansa ga kowane bankin ƙwaƙwalwar ajiya · Rubuta FIFO
Ana iya yin rajistar daidaitawar FMC amintacce.

3.16

Dual Quad-SPI memory interface (QUADSPI)
QUADSPI keɓantacciyar hanyar sadarwa ce ta keɓancewa guda, dual ko quad SPI memories. Yana iya aiki ta kowane ɗayan hanyoyi uku masu zuwa: · Yanayin kai tsaye: duk ayyukan ana yin su ta amfani da rajistar QUADSPI. Yanayin-polling: ana karantawa lokaci-lokaci rajistar halin ƙwaƙwalwar filasha ta waje kuma
ana iya haifar da katsewa idan akwai saitin tuta. Yanayin da aka yi taswirar ƙwaƙwalwar ajiya: ƙwaƙwalwar filasha ta waje tana taswira zuwa sararin adireshi
kuma tsarin yana gani kamar dai ƙwaƙwalwar ciki ce.
Dukansu kayan aiki da iya aiki za a iya ƙara ninki biyu ta amfani da yanayin filasha dual-flash, inda ake samun damar ƙwaƙwalwar walƙiya ta Quad-SPI guda biyu a lokaci guda.
An haɗe QUADSPI tare da toshewar jinkiri (DLYBQS) yana ba da damar goyan bayan mitar bayanan waje sama da 100 MHz.
Rijistar daidaitawar QUADSPI na iya zama amintacce, da kuma toshewar jinkiri.

3.17

Analog-zuwa-dijital masu juyawa (ADC1, ADC2)
Na'urorin sun haɗa na'urori biyu na analog-zuwa-dijital, waɗanda za a iya daidaita ƙudurin su zuwa 12-, 10-, 8- ko 6-bit. Kowane ADC yana raba har zuwa tashoshi na waje 18, yana yin juzu'i a cikin yanayin harbi ɗaya ko duba. A cikin yanayin dubawa, ana yin jujjuyawar atomatik akan zaɓin rukunin abubuwan shigar analog.
Dukansu ADCs suna da amintattun hanyoyin mu'amalar bas.
Kowane ADC na iya yin aiki da mai sarrafa DMA, don haka yana ba da damar canja wuri ta atomatik na ADC da aka canza dabi'u zuwa wurin da aka nufa ba tare da wani aikin software ba.
Bugu da kari, fasalin agogon analog na iya sa ido daidai da juzu'in juzu'itage na ɗaya, wasu ko duk tashoshin da aka zaɓa. Ana haifar da katsewa lokacin da juyi voltage yana waje da ƙofofin da aka tsara.
Domin daidaita jujjuyawar A/D da masu ƙidayar lokaci, ADCs na iya haifar da kowane na TIM1, TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, LPTIM1, LPTIM2 da LPTIM3 masu ƙidayar lokaci.

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3.18

firikwensin zafin jiki
Na'urorin sun haɗa firikwensin zafin jiki wanda ke haifar da voltage (VTS) wanda ya bambanta a layi tare da zafin jiki. Wannan firikwensin zafin jiki yana da haɗin ciki zuwa ADC2_INP12 kuma yana iya auna yanayin yanayin na'urar daga 40 zuwa +125 °C tare da madaidaicin ± 2 %.
Na'urar firikwensin zafin jiki yana da madaidaiciyar layi mai kyau, amma dole ne a daidaita shi don samun ingantaccen ma'aunin zafin jiki gabaɗaya. Kamar yadda saitin firikwensin zafin jiki ya bambanta daga guntu zuwa guntu saboda bambancin tsari, na'urar firikwensin zafin jiki mara kyau ya dace da aikace-aikacen da ke gano canjin zafin jiki kawai. Don inganta daidaiton ma'aunin firikwensin zafin jiki, kowace na'ura an daidaita masana'anta-daidaitacce ta ST. Ana adana bayanan ma'aunin firikwensin masana'anta ta ST a cikin yankin OTP, wanda ake iya samun dama ga yanayin karantawa kawai.

3.19

Dijital zazzabi firikwensin (DTS)
Na'urorin sun haɗa firikwensin zafin jiki na mitar. DTS tana ƙidayar mita bisa LSE ko PCLK don samar da bayanin zafin jiki.
Ana goyan bayan ayyuka masu zuwa: · Katse ƙirƙira ta hanyar zafin jiki · Ƙirƙirar siginar farkawa ta iyakar zafin jiki

3.20
Lura:

Farashin VBAT
Wurin wutar lantarki na VBAT yana ƙunshe da RTC, rijistar ajiyar ajiya da kuma SRAM ɗin ajiyar.
Domin inganta tsawon lokacin baturi, ana ba da wannan yankin wutar lantarki ta VDD lokacin da akwai ko ta voltage a yi amfani da fil ɗin VBAT (lokacin da ba a samar da VDD ba). Ana kunna wutar VBAT lokacin da PDR ta gano cewa VDD ya faɗi ƙasa da matakin PDR.
Voltage a kan fil ɗin VBAT ana iya ba da shi ta baturi na waje, babban capacitor ko kai tsaye ta VDD. A cikin yanayin baya, yanayin VBAT baya aiki.
Ana kunna aikin VBAT lokacin da babu VDD.
Babu ɗayan waɗannan abubuwan (katsewa na waje, TAMP taron, ko ƙararrawar RTC / abubuwan da suka faru) suna iya dawo da wadatar VDD kai tsaye da tilasta na'urar daga aikin VBAT. Duk da haka, TAMP Ana iya amfani da abubuwan da suka faru da ƙararrawar RTC / abubuwan da suka faru don samar da sigina zuwa na'ura na waje (yawanci PMIC) wanda zai iya mayar da kayan aiki na VDD.

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3.21

Voltage reference buffer (VREFBUF)
Na'urorin sun haɗa juzu'itage reference buffer wanda za a iya amfani dashi azaman voltage reference ga ADCs, da kuma kamar yadda voltage tunani don abubuwan haɗin waje ta hanyar VREF+ fil. VREFBUF na iya zama amintacce. VREFBUF na ciki yana goyan bayan voltages: · 1.65V · 1.8V · 2.048V · 2.5V Volume na wajetagAna iya ba da tunani ta hanyar VREF + fil lokacin da VREFBUF na ciki ke kashe.
Hoto 4. Voltage reference buffer

VREFINT

–

VREF+

VSSA

MSv64430V1

3.22

Tace na dijital don sigma-delta modulator (DFSDM)
Na'urorin sun haɗa DFSDM ɗaya tare da goyan bayan samfuran matattara na dijital guda biyu da tashoshi na shigarwa na waje guda huɗu (masu ɗaukar nauyi) ko madadin abubuwan shigar guda huɗu na layi ɗaya.
DFSDM tana mu'amala da masu daidaitawa na waje zuwa na'urar kuma tana yin tace dijital na rafukan bayanan da aka karɓa. Ana amfani da masu daidaitawa don canza siginar analog zuwa rafukan dijital-serial waɗanda suka ƙunshi abubuwan shigar da DFSDM.
DFSDM kuma na iya yin mu'amala da makirufo na PDM (yawanci-yawanci) makirufo da yin PDM zuwa juzu'in PCM da tacewa (hardware accelerated). DFSDM tana fasalta bayanan zaɓi na zaɓi daidaitattun bayanai daga ADCs ko daga ƙwaƙwalwar na'urar (ta hanyar DMA/CPU ana canjawa wuri zuwa DFSDM).
Masu watsawa na DFSDM suna goyan bayan nau'ikan mu'amala da siriyal da yawa (don tallafawa masu daidaitawa daban-daban). Na'urorin tace dijital na DFSDM suna yin aiki na dijital bisa ƙayyadaddun ma'aunin tace mai amfani tare da ƙudurin ADC na ƙarshe na 24-bit.

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Ƙarshen DFSDM yana goyan bayan: · Tashoshi na siriyal na dijital da aka haɗa da yawa:
configurable SPI dubawa don haɗa nau'ikan modulators masu daidaitawa Manchester codeed 1-wire interface PDM (modulation-density modulation) shigar da makirufo matsakaicin mitar agogon shigarwa har zuwa 20 MHz (10 MHz don Manchester coding) fitowar agogo don masu daidaitawa (0 zuwa 20 MHz) · Madadin bayanai daga mahaɗin dijital guda huɗu na layi ɗaya): Maɓuɓɓugan bayanai na ciki ko tashoshi na ciki: Maɓuɓɓuka na ciki Rafukan ruwa (DMA) · Na'urori masu tacewa na dijital guda biyu tare da daidaitawar siginar dijital mai daidaitawa: Sincx filter: odar tacewa/nau'i (16 zuwa 1), oversampling rabo (1 zuwa 1024) mai haɗawa: oversampling ratio (1 zuwa 256) · Har zuwa 24-bit fitarwa data ƙuduri, sa hannu fitarwa data format · Atomatik data diyya gyara (offset adana a cikin rajista ta mai amfani) · Ci gaba ko guda juzu'i haifar da: software fararwa ciki masu kididdige al'amurran da suka shafi na waje fara-of-conversion synchronously tare da farko digital data module (DFSDM) · Analog-value: low-value watchdogue Rijista ƙwararrun matattarar dijital ta Sincx (oda = 1 zuwa 3,
oversampling ratio = 1 zuwa 32) shigarwa daga bayanan fitarwa na ƙarshe ko daga zaɓin tashoshi na dijital da aka zaɓa ci gaba da sa ido ba tare da daidaitaccen juzu'i ba · Mai gano gajeriyar kewayawa don gano madaidaitan ƙimar shigarwar analog (ƙasa da saman kewayon): har zuwa 8-bit counter don gano 1 zuwa 256 a jere 0's ko 1's akan serial data rafi saka idanu akan tashar tashar analog ta ci gaba da ci gaba da kallon siginar da'irar da'irar ko wace tsarawar abun ciki. Lamarin ganowa · Matsanancin ganowa: adana mafi ƙanƙanta da matsakaicin ƙimar bayanan juzu'i na ƙarshe da aka sabunta ta software · DMA iyawar karanta bayanan jujjuyawa na ƙarshe · Katsewa: ƙarshen jujjuyawa, wuce gona da iri, agogon analog, gajeriyar kewayawa, rashi serial tashoshi agogon agogo · “na yau da kullun” ko “injected” jujjuyawar: “na yau da kullun” ana iya neman canjin canji a kowane lokaci ko ma a cikin yanayin ci gaba.
ba tare da samun wani tasiri a kan lokacin "injected" juzu'ai "injected" juzu'ai don daidaitaccen lokaci kuma tare da babban fifikon juyawa.

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3.23

Gaskiya bazuwar lamba janareta (RNG)
Na'urorin sun haɗa RNG guda ɗaya wanda ke ba da lambobi bazuwar 32-bit da aka samar ta haɗaɗɗiyar da'irar analog.
Ana iya siffanta RNG (a cikin ETZPC) azaman samun dama ta software mai aminci kawai.
RNG na gaskiya yana haɗawa zuwa amintattun AES da PKA ta hanyar bas ɗin da aka keɓe (wanda ba CPU ɗin zai iya karantawa ba).

3.24

Na'urori masu sarrafa bayanai da zanta (CRYP, SAES, PKA da HASH)
Na'urorin sun haɗa na'ura mai sarrafa sikirin guda ɗaya wanda ke goyan bayan ci-gaban algorithms cryptographic yawanci ana buƙata don tabbatar da sirri, tantancewa, amincin bayanai da rashin karɓuwa yayin musayar saƙo tare da takwarorinsu.
Har ila yau, na'urorin sun haɗa keɓaɓɓen keɓaɓɓen DPA mai tsaro AES 128- da 256-bit key (SAES) da PKA kayan aikin ɓoyayyen ɓoyayyen ɓoyayyen abu, tare da keɓaɓɓen bas ɗin kayan aikin bas ɗin da CPU ba zai samu ba.
Babban fasalulluka na CRYP: · DES/TDES (misali ɓoyayyen bayanai/madaidaicin ɓoyayyen bayanai sau uku): ECB (lantarki)
codebook) da CBC (cipher block sarkar) sarkar algorithms, 64-, 128- ko 192-bit key · AES (ci gaban boye-boye misali): ECB, CBC, GCM, CCM, da kuma CTR (yanayin counter) sarkar algorithms, 128-, 192- ko 256-bit key.
Babban fasali na HASH na duniya: · SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-3 (amintacce HASH algorithms) · HMAC
Mai hanzarin sirri yana goyan bayan ƙirƙira buƙatar DMA.
Ana iya bayyana CRYP, SAES, PKA da HASH (a cikin ETZPC) azaman samun dama ta hanyar amintaccen software kawai.

3.25

Boot da tsaro da OTP iko (BSEC)
BSEC (boot da tsaro da kuma kula da OTP) an yi niyya don sarrafa akwatin fuse OTP (mai shirye-shirye na lokaci ɗaya), wanda aka yi amfani da shi don ajiya mara ƙarfi don daidaitawar na'urar da sigogin tsaro. Dole ne a saita wasu ɓangaren BSEC azaman mai isa ga ta amintaccen software kawai.
BSEC na iya amfani da kalmomin OTP don ajiyar HWKEY 256-bit don SAES (amintaccen AES).

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3.26

Lokaci da masu tsaro
Na'urorin sun haɗa da na'urori masu sarrafawa guda biyu, masu ƙididdige ƙididdiga na gaba ɗaya guda goma (wanda bakwai ke da tsaro), ƙididdiga na asali guda biyu, masu ƙidayar ƙarancin ƙarfi biyar, masu sa ido biyu, da masu ƙidayar tsarin huɗu a cikin kowane Cortex-A7.
Ana iya daskarar da duk masu ƙidayar ƙidayar lokaci a cikin yanayin gyara kuskure.
Teburin da ke ƙasa yana kwatanta fasalulluka na ci-gaba-iko, manufa-manufa, asali da ƙananan masu ƙidayar lokaci.

Nau'in lokaci

Mai ƙidayar lokaci

Tebur 4. Kwatanta fasalin fasalin lokaci

Counter resolu-
tion

Nau'in Counter

Fatar Prescaler

Buƙatun DMA

Ɗauki/ kwatanta tashoshi

Ƙaddamarwa fitarwa

Max dubawa
agogo (MHz)

Max
mai lokaci
agogo (MHz) (1)

Advanced TIM1, -control TIM8

16-bit

Sama, Kowane lamba ƙasa, tsakanin 1 sama/ƙasa da 65536

TIM2 TIM5

32-bit

Sama, Kowane lamba ƙasa, tsakanin 1 sama/ƙasa da 65536

TIM3 TIM4

16-bit

Sama, Kowane lamba ƙasa, tsakanin 1 sama/ƙasa da 65536

Kowane lamba

TIM12(2) 16-bit

Sama tsakanin 1

A'a

Gabaɗaya

kuma 65536

manufa

TIM13(2) TIM14(2)

16-bit

Kowane lamba sama tsakanin 1
kuma 65536

A'a

Kowane lamba

TIM15(2) 16-bit

Sama tsakanin 1

kuma 65536

TIM16(2) TIM17(2)

16-bit

Kowane lamba sama tsakanin 1
kuma 65536

Na asali

TIM6, TIM7

16-bit

Kowane lamba sama tsakanin 1
kuma 65536

LPTIM1,

Ƙarfin ƙarfi

LPTIM2(2), LPTIM3(2),
LPTIM4,

16-bit

1, 2, 4, 8, Sama 16, 32, 64,
128

A'a

LPTIM5

104.5

209

A'a

104.5

209

A'a

104.5

209

A'a

104.5

209

A'a

104.5

209

104.5

209

104.5

209

A'a

104.5

209

1 (3)

A'a

104.5 104.5

1. Matsakaicin agogo mai ƙidayar lokaci yana zuwa 209 MHz dangane da bit TIMGxPRE a cikin RCC. 2. Amintaccen mai ƙidayar lokaci. 3. Babu tashar kamawa akan LPTIM.

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3.26.1 3.26.2 3.26.3

Ƙididdiga masu ƙarfi (TIM1, TIM8)
Ana iya ganin masu ƙididdige ƙididdiga na ci-gaba (TIM1, TIM8) azaman janareta na PWM mai hawa uku wanda aka ninka akan tashoshi 6. Suna da ƙarin fitowar PWM tare da shigar da lokutan matattu masu shirye-shirye. Hakanan ana iya ɗaukar su azaman cikakken maƙasudin maƙasudin maƙasudi. Za a iya amfani da tashoshi huɗu masu zaman kansu don: · shigar da shigarwa · kwatanta fitarwa · Ƙirƙirar PWM (yanayin gefe- ko tsakiyar-daidaitacce) · fitowar yanayin bugun jini ɗaya.
Idan an saita su azaman daidaitattun masu ƙidayar lokaci 16-bit, suna da fasali iri ɗaya da masu ƙidayar manufa ta gaba ɗaya. Idan an saita su azaman 16-bit PWM janareta, suna da cikakken ikon daidaitawa (0-100%).
Mai ƙididdige ƙididdiga na ci gaba na iya aiki tare tare da masu ƙididdige ƙididdiga na gaba ɗaya ta hanyar hanyar haɗin lokacin don aiki tare ko sarkar taron.
TIM1 da TIM8 suna goyan bayan samar da buƙatun DMA masu zaman kansu.
Ƙididdiga na gaba ɗaya (TIM2, TIM3, TIM4, TIM5, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17)
Akwai maƙallan maƙasudin maƙasudin gabaɗaya guda goma guda goma waɗanda aka saka a cikin na'urorin STM32MP133C/F (duba Table 4 don bambance-bambance). · TIM2, TIM3, TIM4, TIM5
TIM 2 da TIM5 sun dogara ne a kan 32-bit auto-reload up/down counter da 16-bit prescaler, yayin da TIM3 da TIM4 sun dogara ne akan 16-bit auto-reload up/downcounter da 16-bit prescaler. Duk masu ƙidayar lokaci suna da tashoshi huɗu masu zaman kansu don kwatanta kamawa/fitarwa, PWM ko yanayin fitowar bugun jini ɗaya. Wannan yana ba da kwatancen shigarwa/fitarwa har 16/PWMs akan manyan fakiti. Waɗannan masu ƙidayar maƙasudin gabaɗaya na iya aiki tare, ko tare da sauran masu ƙididdige ƙididdiga na gaba ɗaya da masu ƙidayar sarrafawa TIM1 da TIM8, ta hanyar hanyar haɗin ƙididdiga don aiki tare ko sarkar taron. Ana iya amfani da kowane ɗayan waɗannan maƙallan maƙasudin gabaɗaya don samar da abubuwan PWM. TIM2, TIM3, TIM4, TIM5 duk suna da tsararrun buƙatun DMA masu zaman kansu. Suna da ikon sarrafa siginonin ɓoyayyiyar ƙididdiga (ƙari) da abubuwan dijital daga firikwensin tasirin zaure ɗaya zuwa huɗu. · TIM12, TIM13, TIM14, TIM15, TIM16, TIM17 Waɗannan masu ƙidayar lokaci suna dogara ne akan na'ura mai ɗaukar nauyi mai 16-bit ta atomatik da na'urar tantancewa mai 16-bit. TIM13, TIM14, TIM16 da TIM17 suna da tashoshi ɗaya mai zaman kanta, yayin da TIM12 da TIM15 suna da tashoshi masu zaman kansu guda biyu don kwatancen shigar da fitarwa, PWM ko fitarwa yanayin bugun jini ɗaya. Ana iya daidaita su tare da TIM2, TIM3, TIM4, TIM5 cikakken maƙasudin maƙasudin maƙasudi na gabaɗaya ko amfani da su azaman madaidaicin lokaci. Ana iya siffanta kowane ɗayan waɗannan masu ƙidayar lokaci (a cikin ETZPC) azaman samun dama ta hanyar amintaccen software kawai.
Ma'auni na asali (TIM6 da TIM7)
Ana amfani da waɗannan masu ƙidayar lokaci azaman tushen lokaci na 16-bit.
TIM6 da TIM7 suna goyan bayan samar da buƙatun DMA masu zaman kansu.

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3.26.4
3.26.5 3.26.6

Ƙididdiga masu ƙarancin ƙarfi (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5)
Kowane mai ƙaramar ƙidayar lokaci yana da agogo mai zaman kansa kuma yana aiki kuma a yanayin Tsaya idan LSE, LSI ko agogon waje ya rufe shi. LPTIMx yana iya tayar da na'urar daga Yanayin Tsaya.
Waɗannan masu ƙididdige ƙima suna goyan bayan waɗannan fasalulluka: · 16-bit up counter with 16-bit autoreload rejista · 16-bit kwatanta rajista · Ƙaddamar da fitarwa: pulse, PWM · Ci gaba / yanayin harbi daya · Zaɓuɓɓukan shigar da software/hardware mai faɗakarwa · Zaɓaɓɓen tushen agogo:
Tushen agogo na ciki: LSE, LSI, HSI ko APB tushen agogo na waje akan shigarwar LPTIM (aiki koda ba tare da agogon ciki ba.
Gudun tushen tushen, wanda aikace-aikacen bugun bugun jini ke amfani da shi) · Fitar glitch na dijital mai shirye-shirye · Yanayin Encoder
Ana iya siffanta LPTIM2 da LPTIM3 (a cikin ETZPC) azaman samun dama ta software mai aminci kawai.
Masu sa ido masu zaman kansu (IWDG1, IWDG2)
Wani mai sa ido mai zaman kansa ya dogara ne akan 12-bit downcounter da 8-bit prescaler. An rufe shi daga RC na ciki mai zaman kansa 32 kHz (LSI) kuma, yayin da yake aiki da kansa daga babban agogo, yana iya aiki a yanayin Tsayawa da Jiran aiki. Ana iya amfani da IWDG azaman mai sa ido don sake saita na'urar lokacin da matsala ta faru. Hardware- ko software ana iya daidaita shi ta hanyar zaɓin bytes.
Ana iya siffanta IWDG1 (a cikin ETZPC) azaman mai isa ga ta amintaccen software kawai.
Masu ƙidayar lokaci (Cortex-A7 CNT)
Cortex-A7 jeneriki masu ƙidayar lokaci da aka saka a cikin Cortex-A7 ana ciyar da su ta ƙimar ƙima daga tsara lokaci (STGEN).
Cortex-A7 processor yana samar da masu ƙidayar lokaci: · ƙidayar lokaci ta jiki don amfani a cikin amintattun yanayi da mara tsaro.
Ana yin rijistar masu ƙidayar lokaci ta zahiri don samar da amintattun kwafi marasa aminci. · Mai ƙidayar ƙidayar lokaci don amfani a cikin hanyoyin da ba amintacce ba · mai ƙidayar lokaci don amfani a yanayin hypervisor
Masu ƙidayar lokaci ba ƙayyadaddun taswirar ƙwaƙwalwar ajiya ba ne sannan ana samun dama ta musamman ta takamaiman umarnin coprocessor Cortex-A7 (cp15).

3.27

Ƙirƙirar ƙidayar lokaci (STGEN)
Tsarin lokaci na tsarin (STGEN) yana haifar da ƙimar ƙidayar lokaci wanda ke ba da daidaito view lokaci don duk masu ƙidayar lokaci na Cortex-A7.

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Tsarin lokaci na tsarin yana da waɗannan mahimman abubuwan: · Faɗin 64-bit don guje wa al'amurran da suka shafi juyewa · Fara daga sifili ko ƙimar shirye-shirye · Control APB interface (STGENC) wanda ke ba da damar adana lokaci da dawo da shi.
a duk abubuwan da suka faru na kashe wutar lantarki · Karatu-kawai APB interface (STGENR) wanda ke ba da damar ƙimar lokacin karanta ta wanda ba-
amintacce software da kayan aikin cire matsala · Ƙimar ƙima tana ƙaruwa wanda za'a iya dakatar da shi yayin cire buguwar tsarin
Ana iya siffanta STGENC (a cikin ETZPC) azaman mai isa ga ta amintaccen software kawai.

3.28

Lokaci-lokaci na gaske (RTC)
RTC yana ba da farkawa ta atomatik don sarrafa duk yanayin ƙarancin ƙarfi.RTC mai ƙidayar ƙidayar lokaci/ƙirar BCD ce mai zaman kanta kuma tana ba da agogon rana / kalanda tare da katsewar ƙararrawa na shirye-shirye.
RTC ya haɗa da tutar farkawa na lokaci-lokaci tare da iyawar katsewa.
Rijistar 32-bit guda biyu sun ƙunshi daƙiƙa, mintuna, sa'o'i (tsarar sa'o'i 12 ko 24), rana (ranar mako), kwanan wata (ranar wata), wata, da shekara, waɗanda aka bayyana a cikin tsarin ƙima na binary codeed (BCD). Hakanan ana samun ƙimar ƙananan daƙiƙai a sigar binary.
Ana goyan bayan yanayin binary don sauƙaƙe sarrafa direban software.
Ana biyan diyya na 28-, 29- (shekarar tsalle), 30-, da watanni 31 ta atomatik. Hakanan ana iya yin diyya na lokacin adana hasken rana.
Ƙarin rijistar 32-bit sun ƙunshi ƙararrawa da za a iya yin shiri a cikin dakika kaɗan, daƙiƙa, mintuna, sa'o'i, rana, da kwanan wata.
Akwai fasalin daidaitawa na dijital don rama kowane sabani cikin daidaiton oscillator crystal.
Bayan sake saitin yanki na Ajiyayyen, duk rajistar RTC ana kiyaye su daga yuwuwar shigar da rubutacciyar parasitic kuma ana kiyaye su ta amintaccen shiga.
Matukar samar da voltage ya kasance a cikin kewayon aiki, RTC baya tsayawa, ba tare da la'akari da matsayin na'urar ba (Yanayin Run, yanayin ƙarancin ƙarfi ko ƙarƙashin sake saiti).
Babban fasalulluka na RTC sune kamar haka: · Kalanda tare da ƙananan dakika, daƙiƙa, mintuna, sa'o'i (tsara 12 ko 24), ranar (ranar da za a yi nasara).
mako), kwanan wata (ranar wata), wata, da shekara · Rarraba ceton hasken rana wanda aka tsara ta software · Ƙararrawa mai shirye-shirye tare da aikin katsewa. Ana iya kunna ƙararrawa ta kowane
hade da filayen kalanda. Naúrar farkawa ta atomatik tana haifar da tuta na lokaci-lokaci wanda ke haifar da farkawa ta atomatik
Katsewa · Gano agogon magana: ƙarin madaidaicin agogo na biyu (50 ko 60 Hz) na iya zama
amfani da su don haɓaka daidaitattun kalanda. Daidaitaccen aiki tare da agogo na waje ta amfani da fasalin motsi na biyu · Da'irar daidaitawa na dijital (gyaran ƙididdiga na lokaci): 0.95 ppm daidaito, samu a cikin
taga daidaitawa na daƙiƙa da yawa

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· Lokaciamp aiki don ceton taron · Adana SWKEY a cikin rijistar madadin RTC tare da samun damar bas kai tsaye zuwa SAE (ba
CPU wanda za'a iya karantawa) · Matsaloli / abubuwan da za a iya rufe su:
Ƙararrawa A Ƙararrawa B Wakeup yana katse lokaciamp Goyan bayan TrustZone: RTC cikakke ƙararrawa A, ƙararrawa B, mai ƙidayar tashi da lokaciamp mutum amintacce ko mara tsaro
daidaitawar daidaitawar RTC da aka yi a cikin tsaro akan tsari mara tsaro

3.29

Tamper da madadin rajista (TAMP)
32 x 32-bit rajistan rajista ana kiyaye su a cikin duk yanayin ƙarancin ƙarfi kuma a cikin yanayin VBAT. Ana iya amfani da su don adana mahimman bayanai kamar yadda abun cikin su ke samun kariya ta aampda'irar ganowa.
Bakwai tamper shigar fil da biyar tamper fitarwa fil suna samuwa don anti-tampganowa. Na waje tamper fil za a iya saita don gano gefen, gefe da matakin, matakin ganowa tare da tacewa, ko aiki tamper wanda ke ƙara matakin tsaro ta atomatik bincika cewa tamper fil ba a buɗe ko gajarta a waje.
TAMP manyan fasalulluka · 32 rijistar ajiya (TAMP_BKPxR) wanda aka aiwatar a cikin yankin RTC wanda ya rage
kunnawa ta VBAT lokacin da aka kashe wutar VDD · 12 tamper fil samuwa (masu shigarwa bakwai da fitarwa biyar) · Kowane tampGanowa zai iya haifar da lokacin RTCamp taron. · Wani tampganowa er yana share rijistar madadin. Tallafin TrustZone:
Tampamintacce ko mara tsaro saitin Ajiyayyen Ajiyayyen saitin rajista a cikin yankuna uku masu daidaitawa:
. wuri mai tsaro guda karanta/rubutu . daya rubuta amintacce/ karanta yankin mara tsaro. wurin karantawa/rubutu ɗaya wanda ba amintacce ba · Maƙallan monotonic

3.30

Matsalolin da'ira mai haɗin kai (I2C1, I2C2, I2C3, I2C4, I2C5)
Na'urorin sun haɗa mu'amalar I2C guda biyar.
Motar motar bas ta I2C tana sarrafa sadarwa tsakanin STM32MP133C/F da serial I2C bas. Yana sarrafa duk takamaiman jerin bas na I2C, yarjejeniya, sasantawa da lokaci.

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Gefen I2C yana goyan bayan: · Ƙayyadaddun I2C-bas da mai amfani da littafin rev. 5 dacewa:
Yanayin Bayi da Jagora, Matsayin Multimaster Standard-mode (Sm), tare da bitrate har zuwa 100 kbit/s Fast-mode (Fm), tare da bitrate har zuwa 400 kbit/s Fast-mode Plus (Fm +), tare da bitrate har zuwa 1 Mbit / s da 20 mA fitarwa drive I / Os 7-bit adireshin adireshin bawa da yawa, da adireshin bawa da yawa 10. Riƙe lokutan Zaɓar agogo na zaɓi · Bas ɗin sarrafa tsarin (SMBus) ƙayyadaddun dacewa rev 7: Hardware PEC (duba kuskuren fakiti) ƙira da tabbaci tare da ACK
Control Address Resolution Protocol (ARP) goyon bayan SMBus faɗakarwa · Power tsarin management yarjejeniya (PMBusTM) ƙayyadaddun rev 1.1 dacewa · Agogo mai zaman kanta: zaɓi na tushen agogo mai zaman kansa yana ba da damar saurin sadarwa na I2C ya zama mai zaman kansa daga tsarin PCLK · Farkawa daga Yanayin Tsaya akan wasan adireshi · Ana iya yin shirye-shirye tare da iyawar sauti na dijital da DMA.
Ana iya ayyana I2C3, I2C4 da I2C5 (a cikin ETZPC) azaman samun dama ta software mai aminci kawai.

3.31

Mai watsa mai karɓar asynchronous gama gari (USART1, USART2, USART3, USART6 da UART4, UART5, UART7, UART8)
Na'urorin suna da na'urori masu karɓa guda huɗu masu haɗawa da haɗin kai na duniya (USART1, USART2, USART3 da USART6) da masu karɓar mai karɓar asynchronous guda huɗu (UART4, UART5, UART7 da UART8). Koma zuwa teburin da ke ƙasa don taƙaita abubuwan USARTx da UARTx.
Waɗannan musaya suna ba da sadarwar asynchronous, goyan bayan IrDA SIR ENDEC, yanayin sadarwa da yawa, yanayin sadarwa mai rabi-waya guda ɗaya kuma suna da ikon LIN master/bayi. Suna ba da sarrafa kayan aiki na siginar CTS da RTS, da RS485 Direba Enable. Suna iya sadarwa a cikin sauri har zuwa 13 Mbit/s.
USART1, USART2, USART3 da USART6 suma suna ba da yanayin Smartcard (ISO 7816 mai yarda) da damar sadarwa kamar SPI.
Duk USART suna da yankin agogo mai zaman kansa daga agogon CPU, yana barin USARTx ta farka da STM32MP133C/F daga Yanayin Tsayawa ta amfani da baudrates har zuwa 200 Kbaud. Abubuwan farkawa daga Yanayin Tsayawa suna shirye-shirye kuma suna iya zama:
· fara gano bit
· kowane firam ɗin bayanai da aka karɓa
· takamaiman tsarin bayanai

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Duk abubuwan musaya na USART na iya yin aiki ta mai sarrafa DMA.

Table 5. USART/UART fasali

Hanyoyin USART/fasali(1)

USART1/2/3/6

UART4/5/7/8

Gudanar da kwararar kayan aiki don modem

Cigaba da sadarwa ta amfani da DMA

Hanyar sadarwa da yawa

Yanayin SPI mai aiki tare (maigida/bawa)

–

Yanayin Smartcard

–

Single-waya rabin-duplex sadarwa IrDA SIR ENDEC block

Yanayin LIN

Yankin agogo biyu da farkawa daga yanayin ƙarancin wuta

Lokacin ƙarewar mai karɓa ya katse sadarwar Modbus

Auto baud kudi gano

Kunna Direba

USART tsawon bayanan

7, 8 da 9 bits

1. X = goyon baya.

USART1 da USART2 ana iya siffanta su (a cikin ETZPC) azaman samun dama ta software mai aminci kawai.

3.32

Serial musaya (SPI1, SPI2, SPI3, SPI4, SPI5) haɗakar sauti musaya (I2S1, I2S2, I2S3, I2S4)
Na'urorin sun ƙunshi har zuwa SPI guda biyar (SPI2S1, SPI2S2, SPI2S3, SPI2S4, da SPI5) waɗanda ke ba da damar sadarwa har zuwa 50 Mbit/s a cikin yanayin master da bawa, a cikin rabin-duplex, cikakken duplex da yanayin simplex. Prescaler na 3-bit yana ba da mitoci guda takwas kuma ana iya daidaita firam ɗin daga 4 zuwa 16 ragowa. Dukkan musaya na SPI suna goyan bayan yanayin bugun jini na NSS, yanayin TI, lissafin CRC hardware da ninka Rx da Tx FIFOs 8-bit tare da iyawar DMA.
I2S1, I2S2, I2S3, da I2S4 suna da yawa tare da SPI1, SPI2, SPI3 da SPI4. Ana iya sarrafa su a yanayin master ko bawa, a cikin cikakken tsarin sadarwa na duplex da rabi-duplex, kuma ana iya daidaita su don aiki tare da ƙudurin 16- ko 32-bit azaman tashar shigarwa ko fitarwa. Audio sampAna goyan bayan mitoci daga 8 kHz har zuwa 192 kHz. Duk musaya na I2S suna goyan bayan ninka 8-bit na Rx da Tx FIFOs tare da iyawar DMA.
Ana iya siffanta SPI4 da SPI5 (a cikin ETZPC) azaman samun dama ta software mai aminci kawai.

3.33

Serial audio musaya (SAI1, SAI2)
Na'urorin sun haɗa SAI guda biyu waɗanda ke ba da izinin ƙira yawancin ka'idojin sauti na sitiriyo ko mono mono

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kamar I2S, LSB ko MSB-justified, PCM/DSP, TDM ko AC'97. Ana samun fitowar SPDIF lokacin da aka saita toshe mai jiwuwa azaman mai watsawa. Don kawo wannan matakin sassauci da sake daidaitawa, kowane SAI yana ƙunshe da ƙananan tubalan sauti masu zaman kansu guda biyu. Kowane toshe yana da nasa janareta na agogo da mai kula da layin I/O. Audio sampAna goyan bayan mitoci har zuwa 192 kHz. Bugu da ƙari, ana iya tallafawa har zuwa makirufo takwas godiya ga abin da aka haɗa PDM. SAI na iya aiki a cikin tsari na master ko bawa. Ƙananan tubalan odiyo na iya zama ko dai mai karɓa ko mai watsawa kuma suna iya aiki tare ko asynchronously (dangane da ɗayan). Ana iya haɗa SAI tare da sauran SAI don yin aiki tare.

3.34

SPDIFRX (SPDIFRX)
An ƙera SPDIFRX don karɓar madaidaicin kwararar S/PDIF tare da IEC-60958 da IEC-61937. Waɗannan ƙa'idodi suna tallafawa sauƙaƙan rafukan sitiriyo har zuwa manyan sample rate, da kuma matsar da Multi-tashar kewaye sauti, kamar waɗanda Dolby ko DTS ayyana (har zuwa 5.1).
Babban fasalulluka na SPDIFRX sune kamar haka: · Har zuwa abubuwan shigarwa guda huɗu akwai · Gano ƙimar alamar atomatik · Matsakaicin ƙimar alama: 12.288 MHz · Rafi na sitiriyo daga 32 zuwa 192 kHz yana goyan bayan audio IEC-60958 da IEC-61937, aikace-aikacen mabukaci · Gudanar da Parity bit · Sadarwa ta amfani da DMA don sarrafa sauti.amp· Sadarwa ta amfani da DMA don sarrafawa da bayanin tashar mai amfani · Katse iyawar
Mai karɓar SPDIFRX yana ba da duk abubuwan da suka wajaba don gano ƙimar alamar, da kuma yanke bayanan rafi mai shigowa. Mai amfani zai iya zaɓar shigarwar SPDIF da ake so, kuma idan akwai ingantacciyar sigina, sake SPDIFXampba da siginar mai shigowa, yana yanke rafin Manchester, kuma yana gane firam, ƙananan firam ɗin da toshe abubuwa. SPDIFRX yana isar da bayanan da aka yanke na CPU, da alamun matsayi masu alaƙa.
SPDIFRX kuma tana ba da sigina mai suna spdif_frame_sync, wanda ke jujjuyawa a ƙimar ƙaramin yanki na S/PDIF wanda ake amfani da shi don ƙididdige ainihin s.ampAlgorithms na yau da kullun don karkatar da agogo.

3.35

Amintaccen shigar da dijital / fitarwa MultiMediaCard musaya (SDMMC1, SDMMC2)
Amintattun shigarwar dijital/fitarwa guda biyu MultiMediaCard musaya (SDMMC) suna ba da haɗin kai tsakanin bas ɗin AHB da katunan ƙwaƙwalwar SD, katunan SDIO da na'urorin MMC.
Siffofin SDMMC sun haɗa da masu zuwa: · Yarda da Ƙaƙwalwar Tsarin Kayyade Katin MultiMediaCard 5.1
Tallafin kati don hanyoyin bas guda uku daban-daban: 1-bit (tsoho), 4-bit da 8-bit

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(HS200 SDMMC_CK gudun iyaka zuwa iyakar I/O da aka yarda da shi) (HS400 ba ta da tallafi)
Cikakken dacewa tare da nau'ikan MultiMediaCards na baya (daidaituwar baya)
Cikakken yarda da ƙayyadaddun ƙayyadaddun katin ƙwaƙwalwar ajiyar SD nau'in 4.1 (SDR104 SDMMC_CK gudun iyaka ga iyakar I/O da aka yarda, yanayin SPI da yanayin UHS-II ba a goyan baya)
Cikakken yarda da sigar ƙayyadaddun katin SDIO 4.0 Tallafin katin don nau'ikan databus daban-daban: 1-bit (tsoho) da 4-bit (SDR104 SDMMC_CK gudun iyaka zuwa matsakaicin izinin I/O gudun, yanayin SPI da yanayin UHS-II ba a goyan baya)
Canja wurin bayanai har zuwa 208 Mbyte/s don yanayin 8-bit (dangane da matsakaicin izinin I/O gudun)
Bayanan bayanai da fitarwar umarni suna ba da damar sigina don sarrafa direbobin da ke waje
Mai sarrafa DMA mai sadaukarwa wanda aka saka a cikin SDMMC mai masaukin baki, yana ba da damar canja wuri mai sauri tsakanin mai dubawa da SRAM.
· Tallafin lissafin haɗin IDMA
· Ƙaddamar da kayan wuta, VDDSD1 da VDDSD2 don SDMMC1 da SDMMC2 bi da bi, cire buƙatar shigar da matakin-shifter akan ƙirar katin SD a cikin yanayin UHS-I.
Wasu GPIO kawai don SDMMC1 da SDMMC2 suna samuwa akan keɓaɓɓen fil ɗin wadata VDDSD1 ko VDDSD2. Waɗannan su ne ɓangare na tsoho GPIOs na SDMMC1 da SDMMC2 (SDMMC1: PC[12:8], PD [2], SDMMC2: PB[15,14,4,3], PE3, PG6). Ana iya gano su a madadin tebur ɗin aiki ta sigina tare da kari na "_VSD1" ko "_VSD2".
Kowane SDMMC yana haɗe tare da toshewar jinkiri (DLYBSD) yana ba da damar goyan bayan mitar bayanan waje sama da 100 MHz.
Dukkan musaya na SDMMC suna da amintattun tashoshin jiragen ruwa.

3.36

Cibiyar sadarwar yankin mai sarrafawa (FDCAN1, FDCAN2)
Tsarin yanki na cibiyar sadarwa (CAN) ya ƙunshi nau'ikan CAN guda biyu, ƙwaƙwalwar RAM ɗin saƙon da aka raba da sashin daidaita agogo.
Dukansu nau'ikan CAN (FDCAN1 da FDCAN2) sun dace da ISO 11898-1 (CAN 2.0 sigar ƙayyadaddun ƙayyadaddun ka'ida A, B) da sigar ƙayyadaddun ƙa'idar CAN FD 1.0.
Ƙwaƙwalwar ajiyar saƙon 10-Kbyte RAM tana aiwatar da matattara, karɓar FIFOs, karɓar buffers, watsa taron FIFOs da watsa buffers (da abubuwan da ke haifar da TTCAN). Ana raba wannan saƙon RAM tsakanin nau'ikan FDCAN1 da FDCAN2 guda biyu.
Naúrar daidaita agogo gama gari zaɓi ne. Ana iya amfani da shi don samar da agogo mai ƙima don duka FDCAN1 da FDCAN2 daga HSI na ciki RC oscillator da PLL, ta hanyar kimanta saƙonnin CAN da FDCAN1 ta karɓa.

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3.37

Mai watsa shirye-shiryen bas na duniya (USBH)
Na'urorin sun haɗa babban tashar USB guda ɗaya (har zuwa 480 Mbit/s) tare da tashar jiragen ruwa na zahiri guda biyu. USBH yana goyan bayan duka ƙananan, cikakken-gudun (OHCI) da kuma ayyuka masu sauri (EHCI) da kansa akan kowace tashar jiragen ruwa. Yana haɗa nau'ikan transceivers guda biyu waɗanda za a iya amfani da su don ko dai ƙananan sauri (1.2 Mbit / s), cikakken sauri (12 Mbit / s) ko aiki mai sauri (480 Mbit / s). Ana raba transceiver mai sauri na biyu tare da babban saurin OTG.
USBH ya dace da ƙayyadaddun kebul na 2.0. Masu kula da USBH suna buƙatar keɓaɓɓun agogo waɗanda PLL ke samarwa a cikin PHY na USB mai sauri.

3.38

Kebul on-the-go high-gudun (OTG)
Na'urorin sun haɗa babban gudun USB OTG guda ɗaya (har zuwa 480 Mbit/s) na'urar / mai watsa shiri / OTG na gefe. OTG yana goyan bayan duka ayyuka masu cikakken sauri da sauri. Ana raba transceiver don aiki mai sauri (480 Mbit/s) tare da tashar USB Mai watsa shiri ta biyu.
Kebul na OTG HS ya dace da ƙayyadaddun kebul na 2.0 kuma tare da ƙayyadaddun OTG 2.0. Yana da saitin ƙarshen saitin software mai daidaitawa kuma yana goyan bayan dakatarwa/ci gaba. Masu kula da OTG na USB suna buƙatar keɓaɓɓen agogon 48 MHz wanda PLL ke samarwa a cikin RCC ko a cikin PHY na USB mai sauri.
An jera manyan fasalulluka na USB OTG HS a ƙasa: · Haɗewar Rx da Tx FIFO girman 4 Kbyte tare da ƙimar FIFO mai ƙarfi · SRP (ka'idar buƙatun zama) da HNP ( yarjejeniya yarjejeniya) tallafi · Maƙasudin ƙarshen bidi'a takwas · Tashoshi 16 mai masaukin baki tare da goyan bayan OUT na lokaci-lokaci · OTGurable Software zuwa yanayin OUT.1.3. 2.0 LPM (gudanar da wutar lantarki) goyon bayan · Ƙimar cajin baturi 2.0 goyon baya · HS OTG PHY goyon bayan · USB DMA na ciki · HNP/SNP/IP ciki (babu bukatar wani waje resistor) · Domin OTG/Mai watsa shiri yanayin, ana buƙatar canjin wuta idan akwai na'urori masu ƙarfin bas.
hade.
USB OTG tashar jiragen ruwa na iya zama amintacce.

46/219

Saukewa: DS13875

Saukewa: STM32MP133C/F

Aiki ya ƙareview

3.39

Gigabit Ethernet MAC musaya (ETH1, ETH2)
Na'urorin suna ba da IEEE-802.3-2002-mai yarda da masu ba da damar samun damar watsa labarai na gigabit guda biyu (GMAC) don sadarwar Ethernet LAN ta hanyar madaidaicin matsakaicin matsakaicin zaman kanta na masana'antu (MII), matsakaicin matsakaici mai zaman kanta (RMII), ko rage girman gigabit matsakaici mai zaman kansa (RGMII).
Na'urorin suna buƙatar na'urar mu'amala ta zahiri ta waje (PHY) don haɗawa zuwa bas ɗin LAN na zahiri (karkatattu-biyu, fiber, da sauransu). An haɗa PHY zuwa tashar na'urar ta amfani da sigina 17 don MII, sigina 7 don RMII, ko sigina 13 don RGMII, kuma ana iya rufe ta ta amfani da 25 MHz (MII, RMII, RGMII) ko 125 MHz (RGMII) daga STM32MP133C/F ko daga PHY.
Na'urorin sun haɗa da abubuwa masu zuwa: · Yanayin aiki da mu'amalar PHY
10-, 100-, da 1000-Mbit/s data canja wurin rates Taimako na duka-duplex da rabi-duplex ayyuka MII, RMII da RGMII PHY musaya · Gudanar da Multi-Layer Fakitin tacewa: MAC tacewa a kan tushen (SA) da manufa (DA)
adireshin tare da cikakke kuma tace zanta, VLAN tagTace mai tushe tare da cikakkiyar tacewa da zanta, tacewa Layer 3 akan tushen IP (SA) ko adireshin (DA) adireshin, Layer 4 tacewa akan tushen (SP) ko makoma (DP) tashar jiragen ruwa Biyu VLAN aiki: shigar da har zuwa VLAN guda biyu. tags a cikin hanyar watsawa, tag Tacewa a hanyar karɓar hanyar IEEE 1588-2008/PTPv2 Tallafin Yana goyan bayan ƙididdiga na cibiyar sadarwa tare da ƙididdigar RMON/MIB (RFC2819/RFC2665) lissafin checksum da kwatanta Amsar buƙatun ARP ta atomatik tare da na'urar MAC adireshin TCP yanki: tsaga ta atomatik na manyan fakiti TCP masu watsawa cikin ƙananan fakiti masu yawa · Yanayin ƙarancin ƙarfi Ƙarfin ƙarfin Ethernet (misali IEEE 802.3az-2010) fakitin farkawa mai nisa da gano AMD Magic PacketTM ganowa
Dukansu ETH1 da ETH2 ana iya tsara su azaman amintattu. Lokacin amintacce, ma'amaloli akan mu'amalar AXI suna da amintattu, kuma ana iya canza rijistar saitin ta hanyar shiga cikin aminci kawai.

Saukewa: DS13875

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48

Aiki ya ƙareview

Saukewa: STM32MP133C/F

3.40

Gyara abubuwan more rayuwa
Na'urorin suna ba da fasali masu ɗorewa da abubuwan ganowa don tallafawa haɓaka software da haɗin tsarin: · Maɓallin Breakpoint · Binciko kisa · Kayan aikin software · J.TAG Port debug Port · Serial-wire debug Port · Mai haifar da shigarwa da fitarwa · Tashar jirgin ruwa · Arm CoreSight debug da abubuwan ganowa
Ana iya sarrafa gyara kuskuren ta hanyar JTAG/ serial-wire debug access port, ta yin amfani da daidaitattun kayan aikin gyara na masana'antu.
Tashar jiragen ruwa tana ba da damar ɗaukar bayanai don shiga da bincike.
Ana kunna damar cire kuskure zuwa wurare masu aminci ta hanyar siginar tantancewa a cikin BSEC.

48/219

Saukewa: DS13875

Saukewa: STM32MP133C/F

Pinout, bayanin fil da madadin ayyuka

Hoto 5. STM32MP133C/F LFBGA289 jefa kuri'a

VSS

PA9

Farashin PD10

Saukewa: PB7

Farashin PE7

Farashin PD5

Farashin PE8

Saukewa: PG4

Saukewa: PH9

Saukewa: PH13

PC7

Saukewa: PB9

Saukewa: PB14

Saukewa: PG6

Farashin PD2

PC9

VSS

Farashin PD3

Farashin PF5

Farashin PD14

Farashin PE12

Farashin PE1

Farashin PE9

Saukewa: PH14

Farashin PE10

Farashin PF1

Farashin PF3

PC6

Saukewa: PB15

Saukewa: PB4

PC10

PC12

DDR_DQ4 DDR_DQ0

Saukewa: PB6

Saukewa: PH12

Farashin PE14

Farashin PE13

Farashin PD8

Farashin PD12

Farashin PD15

VSS

Saukewa: PG7

Saukewa: PB5

Saukewa: PB3

VDDSD1

Farashin PF0

PC11

DDR_DQ1

DDR_DQS0N

DDR_DQS0P

Saukewa: PB8

Farashin PD6

VSS

Farashin PE11

Farashin PD1

Farashin PE0

Saukewa: PG0

Farashin PE15

Saukewa: PB12

Saukewa: PB10

VDDSD2

VSS

Farashin PE3

PC8

DDR_DQM0

DDR_DQ5 DDR_DQ3

Saukewa: PG9

Farashin PD11

PA12

Farashin PD0

VSS

PA15

Farashin PD4

Farashin PD9

Farashin PF2

Saukewa: PB13

Saukewa: PH10

VDDQ_DDR

DDR_DQ2 DDR_DQ6 DDR_DQ7 DDR_A5

DDR_ SAKEWA

Saukewa: PG10

Saukewa: PG5

Saukewa: PG8

Saukewa: PH2

Saukewa: PH8

VDDCPU

VDD

Farashin VDDCPU

VDD

VDDQ_DDR

VSS

DDR_A13

VSS

DDR_A9

DDR_A2

Farashin PF9

Farashin PF6

Farashin PF10

Saukewa: PG15

Farashin PF8

VDD

VSS

VDDQ_DDR

DDR_BA2 DDR_A7

DDR_A3

DDR_A0 DDR_BA0

Saukewa: PH11

PI3

Saukewa: PH7

Saukewa: PB2

Farashin PE4

VDDCPU

VSS

VDDCORE VDDCORE VDDCORE

VSS

VDDQ_DDR

DDR_WEN

VSS

DDR_ODT DDR_CSN

DDR_ RASN

Farashin PD13

VBAT

PI2

VSS_PLL VDD_PLL VDDCPU

VSS

VDDCORE

VSS

VDDCORE

VSS

VDDQ_DDR

VDDCORE DDR_A10

DDR_ CASN

DDR_ CLKP

DDR_ CLKN

PC14OSC32_IN

PC15OSC32_
FITA

VSS

PC13

PI1

VDD

VSS

VDDCORE VDDCORE VDDCORE

VSS

VDDQ_DDR

DDR_A11 DDR_CKE DDR_A1 DDR_A15 DDR_A12

Farashin PE2

Farashin PF4

Saukewa: PH6

PI0

Saukewa: PG3

VDD

VSS

VDDQ_DDR

DDR_ATO

DDR_DTO0

DDR_A8 DDR_BA1 DDR_A14

Farashin PF7

PA8

Saukewa: PG11

VDD_ANA VSS_ANA

VDD

VDDQ_DDR

DDR_VREF

DDR_A4

VSS

DDR_DTO1

DDR_A6

Farashin PE6

Saukewa: PG1

Farashin PD7

VSS

Saukewa: PB11

Farashin PF13

VSSA

PA3

NJTRST

VSS_USB VDDA1V1_

REG

VDDQ_DDR

PWR_LP

DDR_DQM1

DDR_DQ10

DDR_DQ8 DDR_ZQ

PH0OSC_IN

PH1OSC_OUT

PA13

Farashin PF14

PA2

VREF-

VDDA

Saukewa: PG13

Saukewa: PG14

VDD3V3_USBHS

VSS

PI5-BOOT1 VSS_PLL2 PWR_ON

DDR_DQ11

DDR_DQ13

DDR_DQ9

Saukewa: PG2

Saukewa: PH3

PWR_CPU _ON

PA1

VSS

VREF+

PC5

VSS

VDD

Farashin PF15

VDDA1V8_ REG

PI6-BOOT2

VDD_PLL2

Saukewa: PH5

DDR_DQ12

DDR_DQS1N

DDR_DQS1P

Saukewa: PG12

PA11

PC0

Farashin PF12

PC3

Farashin PF11

Saukewa: PB1

PA6

Farashin PE5

PDR_ON USB_DP2

PA14

USB_DP1

BYPASS_ REG1V8

Saukewa: PH4

DDR_DQ15

DDR_DQ14

VSS

PA7

PA0

PA5

PA4

PC4

Saukewa: PB0

PC1

PC2

NRST

USB_DM2

USB_ RREF

USB_DM1 PI4-BOOT0

PA10

PI7

VSS

MSv65067V5

Hoton da ke sama yana nuna saman kunshin view.

Saukewa: DS13875

49/219
97

Pinout, bayanin fil da madadin ayyuka

Saukewa: STM32MP133C/F

Hoto 6. STM32MP133C/F TFBGA289 jefa kuri'a

VSS

Farashin PD4

Farashin PE9

Saukewa: PG0

Farashin PD15

Farashin PE15

Saukewa: PB12

Farashin PF1

PC7

PC6

Farashin PF0

Saukewa: PB14

VDDSD2 VDDSD1 DDR_DQ4 DDR_DQ0

VSS

Farashin PE12

Farashin PD8

Farashin PE0

Farashin PD5

Farashin PD9

Saukewa: PH14

Farashin PF2

VSS

Farashin PF3

Saukewa: PB13

Saukewa: PB3

Farashin PE3

PC12

VSS

DDR_DQ1

DDR_DQS0N

DDR_DQS0P

Farashin PE13

Farashin PD1

Farashin PE1

Farashin PE7

VSS

VDD

Farashin PE10

Saukewa: PG7

Saukewa: PG4

Saukewa: PB9

Saukewa: PH10

PC11

PC8

DDR_DQ2

DDR_DQM0

DDR_DQ3 DDR_DQ5

Farashin PF5

PA9

Farashin PD10

VDDCPU

Saukewa: PB7

VDDCPU

Farashin PD12

VDDCPU

Saukewa: PH9

VDD

Saukewa: PB15

VDD

VSS

VDDQ_DDR

DDR_ SAKEWA

DDR_DQ7 DDR_DQ6

Farashin PD0

Farashin PE14

VSS

Farashin PE11

VDDCPU

VSS

PA15

VSS

Saukewa: PH13

VSS

Saukewa: PB4

VSS

VDDQ_DDR

VSS

VDDQ_DDR

VSS

DDR_A13

Saukewa: PH8

PA12

VDD

VDDCPU

VSS

VDDCORE

Farashin PD14

Farashin PE8

Saukewa: PB5

VDDCORE

PC10

VDDCORE

VSS

VDDQ_DDR

DDR_A7

DDR_A5

DDR_A9

Farashin PD11

Saukewa: PH2

Saukewa: PB6

Saukewa: PB8

Saukewa: PG9

Farashin PD3

Saukewa: PH12

Saukewa: PG15

Farashin PD6

Saukewa: PB10

Farashin PD2

PC9

DDR_A2 DDR_BA2 DDR_A3

DDR_A0 DDR_ODT

Saukewa: PG5

Saukewa: PG10

Farashin PF8

VDDCPU

VSS

VDDCORE

Saukewa: PH11

PI3

Farashin PF9

Saukewa: PG6

BYPASS_ REG1V8

VDDCORE

VSS

VDDQ_DDR

DDR_BA0 DDR_CSN DDR_WEN

J VDD_PLL VSS_PLL

Saukewa: PG8

PI2

VBAT

Saukewa: PH6

Farashin PF7

PA8

Farashin PF12

VDD

VDDA1V8_ REG

PA10

DDR_VREF

DDR_ RASN

DDR_A10

VSS

DDR_ CASN

Farashin PE4

Farashin PF10

Saukewa: PB2

VDD

VSS

VDDCORE

PA13

PA1

PC4

NRST

VSS_PLL2 VDDCORE

VSS

VDDQ_DDR

DDR_A15

DDR_ CLKP

DDR_ CLKN

Farashin PF6

VSS

Saukewa: PH7

VDD_ANA VSS_ANA

Saukewa: PG12

PA0

Farashin PF11

Farashin PE5

Farashin PF15

VDD_PLL2

Saukewa: PH5

DDR_CKE DDR_A12 DDR_A1 DDR_A11 DDR_A14

PC14OSC32_IN

PC15OSC32_
FITA

PC13

VDD

VSS

Saukewa: PB11

PA5

Saukewa: PB0

VDDCORE

USB_ RREF

PI6-BOOT2 VDDCORE

VSS

VDDQ_DDR

DDR_A6

DDR_A8 DDR_BA1

Farashin PD13

VSS

PI0

PI1

PA11

VSS

PA4

Saukewa: PB1

VSS

PI5-BOOT1

VSS

VDDQ_DDR

VSS

VDDQ_DDR

VSS

DDR_ATO

PH0OSC_IN

PH1OSC_OUT

Farashin PF4

Saukewa: PG1

VSS

VDD

PC3

PC5

VDD

PI4-BOOT0

VDD

VSS

VDDQ_DDR

DDR_A4 DDR_ZQ DDR_DQ8

Saukewa: PG11

Farashin PE6

Farashin PD7

PWR_ CPU_ON

PA2

PA7

PC1

PA6

Saukewa: PG13

NJTRST

PA14

VSS

PWR_ON

DDR_DQM1

DDR_DQ12

DDR_DQ11

DDR_DQ9

Farashin PE2

Saukewa: PH3

Farashin PF13

PC0

VSSA

VREF-

PA3

Saukewa: PG14

USB_DP2

VSS

VSS_USBHS

USB_DP1

Saukewa: PH4

DDR_DQ13

DDR_DQ14

DDR_DQS1P

DDR_DQS1N

VSS

Saukewa: PG3

Saukewa: PG2

Farashin PF14

VDDA

VREF+

PDR_ON

PC2

USB_DM2

VDDA1V1_ REG

VDD3V3_USBHS

USB_DM1

PI7

Hoton da ke sama yana nuna saman kunshin view.

PWR_LP

DDR_DQ15

DDR_DQ10

VSS

MSv67512V3

50/219

Saukewa: DS13875

Saukewa: STM32MP133C/F

Pinout, bayanin fil da madadin ayyuka

Hoto 7. STM32MP133C/F TFBGA320 jefa kuri'a
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

VSS

PA9

Farashin PE13PE12

Farashin PD12

Saukewa: PG0

Farashin PE15

Saukewa: PG7

Saukewa: PH13

Farashin PF3

Saukewa: PB9

Farashin PF0

Saukewa: PC10PC12

PC9

VSS

Farashin PD0

Farashin PE11

Farashin PF5

PA15

Farashin PD8

Farashin PE0

Farashin PE9

Saukewa: PH14

Farashin PE8

Saukewa: PG4

Farashin PF1

VSS

Saukewa: PB5

PC6

Saukewa: PB15PB14

Farashin PE3

PC11

DDR_DQ4

DDR_DQ1

DDR_DQ0

Saukewa: PB6

Farashin PD3

Saukewa: PE14PD14

Farashin PD1

Saukewa: PB7

Farashin PD4

Farashin PD5

Farashin PD9

Farashin PE10PB12

Saukewa: PH9

PC7

Saukewa: PB3

VDD SD2

Saukewa: PB4

Saukewa: PG6

PC8

Farashin PD2

DDR_DQS0P DQS0N

Saukewa: PB8

Farashin PD6

Saukewa: PH12

Farashin PD10

Farashin PE7

Farashin PF2

Saukewa: PB13

VSS

DDR_DQ2

DDR_DQ5

DDR_DQM0

Saukewa: PH2

Saukewa: PH8

VSS

VDD CPU

Farashin PE1

Farashin PD15

VDD CPU

VSS

VDD

Saukewa: PB10

Saukewa: PH10

VDDQ_DDR

VSS

VDD SD1

DDR_DQ3

DDR_DQ6

Farashin PF8

Saukewa: PG9

Saukewa: PD11PA12

VSS

DDR_DQ7

DDR_A5

VSS

Farashin PF6

Saukewa: PG10

Saukewa: PG5

VDD CPU

Farashin PE4

Saukewa: PF10PG15

Saukewa: PG8

Saukewa: PH7

Farashin PD13

Saukewa: PB2

Farashin PF9

VDD CPU

VSS

VDD

VDD CPU

VDD CORE

VSS

VDD

VSS

VDDQ_DDR

VSS

VDD

VSS

VDD CORE

VSS

VDD

VDD CORE

VDDQ_DDR

DDR_A13

DDR_A2

DDR_A9

DDR_ SAKESA
N

DDR_ BA2

DDR_A3

DDR_A0

DDR_A7

DDR_ BA0

DDR_ CSN

DDR_ ODT

VSS_ PLL

VDD_ PLL

Saukewa: PH11

VDD CPU

PC15-

VBAT OSC32 PI3

VSS

_FITA

PC14-

VSS OSC32 PC13

_IN

VDD

Farashin PE2

Farashin PF4

Saukewa: PH6

PI2

VDD CPU
VDD CORE
VSS
VDD

VSS

VDD CORE

VSS

VDD CORE

VSS

VDD

VDD CORE

VSS

VDD

VDD CORE

VDDQ_DDR
VSS
VDDQ_DDR
VDD CORE

VDDQ_DDR

DDR_ WEN

DDR_ RASN

VSS

DDR_A10

DDR_ CASN

DDR_ CLKN

VDDQ_DDR

DDR_A12

DDR_ CLKP

DDR_A15

DDR_A11

DDR_A14

DDR_ CKE

DDR_A1

PA8

Farashin PF7

PI1

PI0

VSS

DDR_DTO1

DDR_ ATO

DDR_A8

DDR_ BA1

Saukewa: PG1

Saukewa: PG11

Saukewa: PH3

VDD

VSS

VDD

VDD CORE

VSS

VDD

VDD CORE

VSS

VDDQ_DDR

DDR_A4

DDR_ZQ

DDR_A6

VSS

Farashin PE6

PH0OSC_IN

PA13

VSS

DDR_VREF

DDR_DQ10

DDR_DQ8

VSS

PH1OSC_ FITA

VSS_ ANA

VSS

VDD

VDDA VSSA

PA6

VSS

VDD CORE

VSS

VDD VDDQ_ CORE DDR

VSS

PWR_ ON

DDR_DQ13

DDR_DQ9

Farashin PD7

VDD_ ANA

Saukewa: PG2

PA7

VREF-

NJ TRST

VDDA1 V1_ REG

VSS

PWR_ DDR_ DDR_ LP DQS1P DQS1N

PWR_

Saukewa: PG3

PG12 CPU_PF13

PC0

PC3 VREF+ PB0

PA3

Farashin PE5

VDD

USB_ RREF

PA14

VDD 3V3_ USBHS

VDDA1 V8_ REG

VSS

BYPAS S_REG
1V8

Saukewa: PH5

DDR_DQ12

DDR_DQ11

DDR_DQM1

PA11

Farashin PF14

PA0

PA2

PA5

Farashin PF11

PC4

Saukewa: PB1

PC1

Saukewa: PG14

NRST

Farashin PF15

USB_VSS_

PI6-

USB_

PI4-

VDD_

DM2 USBHS BOOT2 DP1 BOOT0 PLL2

Saukewa: PH4

DDR_DQ15

DDR_DQ14

VSS

Saukewa: PB11

PA1

Farashin PF12

PA4

PC5

Saukewa: PG13

PC2

PDR_ ON

USB_DP2

PI5-

USB_

BOOT1 DM1

VSS_PLL2

PA10

PI7

VSS

Hoton da ke sama yana nuna saman kunshin view.

MSv65068V5

Saukewa: DS13875

51/219
97

Pinout, bayanin fil da madadin ayyuka

Saukewa: STM32MP133C/F

Tebur 6. An yi amfani da almara / gajerun kalmomi a cikin tebur

Suna

Gajarta

Ma'anarsa

Nau'in fil ɗin suna
Tsarin I / O
Bayanan kula Madadin ayyuka Ƙarin ayyuka

Sai dai in an bayyana shi, aikin fil yayin da bayan sake saiti iri ɗaya ne da ainihin sunan fil

fil ɗin bayarwa

Fin ɗin shigarwa kawai

Fitar kawai fil

I/O

Fin ɗin shigarwa/fitarwa

Analog ko pin na musamman

FT (U/D/PD) 5V I/O mai jurewa (tare da ƙayyadaddun ja-up / ja-saukar / shirye-shiryen cirewa)

DDR

1.5V, 1.35V ko 1.2 VI/O don DDR3, DDR3L, LPDDR2/LPDDR3 dubawa

Analog siginar

RST

Sake saitin fil tare da mai juye mai rauni mai rauni

_f (1) _a (2) _u (3) _h (4)

Zaɓi don FT I/Os I2C FM+ zaɓi Analog zaɓi (wanda VDDA ke bayarwa don ɓangaren analog na I/O) zaɓi na USB (wanda aka kawo ta VDD3V3_USBxx don ɓangaren USB na I/O) Fitowar sauri don nau'in 1.8V. VDD (na SPI, SDMMC, QUADSPI, TRACE)

_na (5)

Zaɓin babban-sauri don nau'in 1.8V. VDD (na ETH, SPI, SDMMC, QUADSPI, TRACE)

Sai dai in an bayyana shi ta hanyar bayanin kula, duk I/Os an saita su azaman abubuwan shigar da ke iyo yayin da bayan sake saiti

Ayyukan da aka zaɓa ta hanyar rajistar GPIOx_AFR

Zaɓuɓɓuka kai tsaye/an kunna ayyuka ta wurin rajista na gefe

1. Tsarin I / O masu alaƙa a cikin Table 7 sune: FT_f, FT_fh, FT_fvh 2. Tsarin I / O masu alaƙa a cikin Tebur 7 sune: FT_a, FT_ha, FT_vha 3. Tsarin I / O masu alaƙa a cikin Tebur 7 sune: FT_u 4. Tsarin I / O mai alaƙa a cikin Tebur_h FT_fvh, FT_vh, FT_ha, FT_vha 7. Abubuwan da suka danganci I/O a cikin Tebura 5 sune: FT_vh, FT_vha, FT_fvh

52/219

Saukewa: DS13875

Saukewa: STM32MP133C/F

Pinout, bayanin fil da madadin ayyuka

Lambar Pin

Table 7. STM32MP133C/F ma'anar ball

Ayyukan ball

Sunan fil (aiki bayan
sake saiti)

Madadin ayyuka

Ƙarin ayyuka

LFBGA289 TFBGA289 TFBGA320
Tsarin nau'in fil I/O
Bayanan kula

K10 F6 U14 A2 D2 A2 A1 A1 T5 M6 F3 U7
Saukewa: D4E4B2
B2 D1 B3 B1 G6 C2
C3 E2 C3 F6 D4 E7 E4 E1 B1
C2 G7D3
C1 G3 C1

VDDCORE S

–

PA9

I/O FT_h

VSS VDD

–

Farashin PE11

I/O FT_vh

Farashin PF5

I/O FT_h

Farashin PD3

I/O FT_f

Farashin PE14

I/O FT_h

VDDCPU

–

Farashin PD0

I/O FT

Saukewa: PH12

I/O FT_fh

Saukewa: PB6

I/O FT_h

–

TIM1_CH2, I2C3_SMBA,

–

DFSDM1_DATIN0, USART1_TX, UART4_TX,

FMC_NWAIT(boot)

–

TIM1_CH2,

USART2_CTS/USART2_NSS,

SAI1_D2,

–

SPI4_MOSI/I2S4_SDO, SAI1_FS_A, USART6_CK,

ETH2_MII_TX_ER,

ETH1_MII_TX_ER,

FMC_D8(Bot)/FMC_AD8

–

TRAACED12, DFSDM1_CKIN0, I2C1_SMBA, FMC_A5

TIM2_CH1,

–

USART2_CTS/USART2_NSS, DFSDM1_CKOUT, I2C1_SDA,

SAI1_D3, FMC_CLK

TIM1_BKIN, SAI1_D4,

UART8_RTS/UART8_DE,

–

QUADSPI_BK1_NCS,

QUADSPI_BK2_IO2,

FMC_D11(Bot)/FMC_AD11

–

SAI1_MCLK_A, SAI1_CK1,

–

FDCAN1_RX,

FMC_D2(Bot)/FMC_AD2

USART2_TX, TIM5_CH3,

DFSDM1_CKIN1, I2C3_SCL,

–

SPI5_MOSI, SAI1_SCK_A, QUADSPI_BK2_IO2,

SAI1_CK2, ETH1_MII_CRS,

FMC_A6

TRAACED6, TIM16_CH1N,

TIM4_CH1, TIM8_CH1,

–

USART1_TX, SAI1_CK2, QUADSPI_BK1_NCS,

ETH2_MDIO, FMC_NE3,

HDP6

–
–
–
TAMP_IN6-
–
–

Saukewa: DS13875

53/219
97

Pinout, bayanin fil da madadin ayyuka

Saukewa: STM32MP133C/F

Lambar Pin

Tebur 7. STM32MP133C/F ma'anar ball (ci gaba)

Ayyukan ball

Sunan fil (aiki bayan
sake saiti)

Madadin ayyuka

Ƙarin ayyuka

LFBGA289 TFBGA289 TFBGA320
Tsarin nau'in fil I/O
Bayanan kula

A17 A17 T17 M7 – J13 D2 G9 D2 F5 F1 E3 D1 G4 D1
E3 F2 F4 F8 D6 E10 F4 G2 E2 C8 B8 T21 E2 G1 F3
E1 G5 F2 G5 H3 F1 M8 - M5

VSS VDD PD6 PH8 PB8
Saukewa: PA12 VDDCPU
Saukewa: PH2 VSS PD11
PG9 PF8 VDD

–

I/O FT

I/O FT_fh

I/O FT_f

I/O FT_h

–

I/O FT_h

–

I/O FT_h

I/O FT_f

I/O FT_h

–

TIM16_CH1N, SAI1_D1, SAI1_SD_A, UART4_TX(boot)

TRAACED9, TIM5_ETR,

–

USART2_RX, I2C3_SDA,

FMC_A8, HDP2

TIM16_CH1, TIM4_CH3,

I2C1_SCL, I2C3_SCL,

–

DFSDM1_DATIN1,

UART4_RX, SAI1_D1,

FMC_D13(Bot)/FMC_AD13

TIM1_ETR, SAI2_MCLK_A,

USART1_RTS/USART1_DE,

–

ETH2_MII_RX_DV/ETH2_

RGMII_RX_CTL/ETH2_RMII_

CRS_DV, FMC_A7

–

LPTIM1_IN2, UART7_TX,

QUADSPI_BK2_IO0(boot),

–

ETH2_MII_CRS,

ETH1_MII_CRS, FMC_NE4,

ETH2_RGII_CLK125

–

LPTIM2_IN2, I2C4_SMBA,

USART3_CTS/USART3_NSS,

SPDIFRX_IN0,

–

QUADSPI_BK1_IO2,

ETH2_RGII_CLK125,

FMC_CLE(boot)/FMC_A16,

UART7_RX

DBTRGO, I2C2_SDA,

–

USART6_RX, SPIFRX_IN3, FDCAN1_RX, FMC_NE2,

FMC_NCE(boot)

TIM16_CH1N, TIM4_CH3,

–

TIM8_CH3, SAI1_SCK_B, USART6_TX, TIM13_CH1,

QUADSPI_BK1_IO0 (boot)

–

–
–
WMUP1
–

54/219

Saukewa: DS13875

Saukewa: STM32MP133C/F

Pinout, bayanin fil da madadin ayyuka

Lambar Pin

Tebur 7. STM32MP133C/F ma'anar ball (ci gaba)

Ayyukan ball

Sunan fil (aiki bayan
sake saiti)

Madadin ayyuka

Ƙarin ayyuka

LFBGA289 TFBGA289 TFBGA320
Tsarin nau'in fil I/O
Bayanan kula

Saukewa: F3J3H5
F9 D8 G5 F2 H1 G3 G4 G8 H4
F1 H2 G2 D3 B14 U5 G3 K2 H3 H8 F10 G2 L1 G1 D12 C5 U6 M9 K4 N7 G1 H9 J5

Saukewa: PG8

I/O FT_h

Bayani na PG5

–

I/O FT_h

Saukewa: PG15

I/O FT_h

Saukewa: PG10

I/O FT_h

VSS

–

Farashin PF10

I/O FT_h

VDDCORE S

–

Farashin PF6

I/O FT_vh

VSS VDD

–

Farashin PF9

I/O FT_h

TIM2_CH1, TIM8_ETR,

SPI5_MISO, SAI1_MCLK_B,

USART3_RTS/USART3_DE,

–

SPDIFRX_IN2,

QUADSPI_BK2_IO2,

QUADSPI_BK1_IO3,

FMC_NE2, ETH2_CLK

–

TIM17_CH1, ETH2_MDC, FMC_A15

USART6_CTS/USART6_NSS,

–

UART7_CTS, QUADSPI_BK1_IO1,

ETH2_PHY_INTN

SPI5_SCK, SAI1_SD_B,

–

UART8_CTS, FDCAN1_TX, QUADSPI_BK2_IO1(boot),

FMC_NE3

–

TIM16_BKIN, SAI1_D3, TIM8_BKIN, SPI5_NSS, - USART6_RTS/USART6_DE, UART7_RTS/UART7_DE,
QUADSPI_CLK(boot)

–

TIM16_CH1, SPI5_NSS,

UART7_RX(boot),

–

QUADSPI_BK1_IO2, ETH2_MII_TX_EN/ETH2_

RGMII_TX_CTL/ETH2_RMII_

TX_EN

–

TIM17_CH1N, TIM1_CH1,

DFSDM1_CKIN3, SAI1_D4,

–

UART7_CTS, UART8_RX, TIM14_CH1,

QUADSPI_BK1_IO1(boot),

QUADSPI_BK2_IO3, FMC_A9

TAMP_IN4
–
TAMP_IN1-

Saukewa: DS13875

55/219
97

Pinout, bayanin fil da madadin ayyuka

Saukewa: STM32MP133C/F

Lambar Pin

Tebur 7. STM32MP133C/F ma'anar ball (ci gaba)

Ayyukan ball

Sunan fil (aiki bayan
sake saiti)

Madadin ayyuka

Ƙarin ayyuka

LFBGA289 TFBGA289 TFBGA320
Tsarin nau'in fil I/O
Bayanan kula

H5 K1 H2 H6 E5 G7 H4 K3 J3 E5 D13 U11 H3 L3 J1
Saukewa: H1H7K3
J1 N1 J2 J5 J1 K2 J4 J2 K1 H2 H8 L4 K4 M3 M3

PE4 VDDCPU
Bayani na PB2 VSS PH7
Saukewa: PH11
PD13 VDD_PLL VSS_PLL
Saukewa: PI3 PC13

I/O FT_h

–

I/O FT_h

–

I/O FT_fh

I/O FT_h

–

I/O FT

SPI5_MISO, SAI1_D2,

DFSDM1_DATIN3,

TIM15_CH1N, I2S_CKIN,

–

SAI1_FS_A, UART7_RTS/UART7_DE,

–

UART8_TX,

QUADSPI_BK2_NCS,

FMC_NCE2, FMC_A25

–

RTC_OUT2, SAI1_D1,

I2S_CKIN, SAI1_SD_A,

–

UART4_RX,

QUADSPI_BK1_NCS(boot),

ETH2_MDIO, FMC_A6

TAMP_IN7

–

SAI2_FS_B, I2C3_SDA,

SPI5_SCK,

–

QUADSPI_BK2_IO3, ETH2_MII_TX_CLK,

–

ETH1_MII_TX_CLK,

QUADSPI_BK1_IO3

SPI5_NSS, TIM5_CH2,

SAI2_SD_A,

SPI2_NSS/I2S2_WS,

–

I2C4_SCL, USART6_RX, QUADSPI_BK2_IO0,

–

ETH2_MII_RX_CLK/ETH2_

RGMII_RX_CLK/ETH2_RMII_

REF_CLK, FMC_A12

LPTIM2_ETR, TIM4_CH2,

TIM8_CH2, SAI1_CK1,

–

SAI1_MCLK_A, USART1_RX, QUADSPI_BK1_IO3,

–

QUADSPI_BK2_IO2,

FMC_A18

–

(1)

SPDIFRX_IN3,

TAMP_IN4/TAMP_

ETH1_MII_RX_ER

OUT5, WKUP2

RTC_OUT1/RTC_TS/

(1)

–

RTC_LSCO, TAMP_IN1/TAMP_

OUT2, WKUP3

56/219

Saukewa: DS13875

Saukewa: STM32MP133C/F

Pinout, bayanin fil da madadin ayyuka

Lambar Pin

Tebur 7. STM32MP133C/F ma'anar ball (ci gaba)

Ayyukan ball

Sunan fil (aiki bayan
sake saiti)

Madadin ayyuka

Ƙarin ayyuka

LFBGA289 TFBGA289 TFBGA320
Tsarin nau'in fil I/O
Bayanan kula

J3 J4 N5

PI2

I/O FT

(1)

SPDIFRX_IN2

TAMP_IN3/TAMP_ OUT4, WKUP5

K5 N4 P4

PI1

I/O FT

(1)

SPDIFRX_IN1

RTC_OUT2/RTC_ LSCO,
TAMP_IN2/TAMP_ OUT3, WKUP4

F13 L2 U13

VSS

–

J2 J5 L2

VBAT

–

L4 N3 P5

PI0

I/O FT

(1)

SPDIFRX_IN0

TAMP_IN8/TAMP_ FITA1

K2 M2

PC15OSC32_OUT

I/O

(1)

–

OSC32_OUT

F15 N2 U16

VSS

–

K1 M1 M2

PC14OSC32_IN

I/O

(1)

–

OSC32_IN

G7 E3 V16

VSS

–

H9 K6 N15 VDDCORE S

–

M10 M4 N9

VDD

–

G8 E6 W16

VSS

–

USART2_RX,

L2 P3 N2

Farashin PF4

I/O FT_h

–

ETH2_MII_RXD0/ETH2_ RGMII_RXD0/ETH2_RMII_

–

RXD0, FMC_A4

MCO1, SAI2_MCLK_A,

TIM8_BKIN2, I2C4_SDA,

SPI5_MISO, SAI2_CK1,

Farashin M2J8P2

PA8

I/O FT_fh -

USART1_CK, SPI2_MOSI/I2S2_SDO,

–

OTG_HS_SOF,

ETH2_MII_RXD3/ETH2_

RGMII_RXD3, FMC_A21

TRACECLK, TIM2_ETR,

I2C4_SCL, SPI5_MOSI,

SAI1_FS_B,

L1T1 N1

Farashin PE2

I/O FT_fh

–

USART6_RTS/USART6_DE, SPIFRX_IN1,

–

ETH2_MII_RXD1/ETH2_

RGMII_RXD1/ETH2_RMII_

RXD1, FMC_A23

Saukewa: DS13875

57/219
97

Pinout, bayanin fil da madadin ayyuka

Saukewa: STM32MP133C/F

Lambar Pin

Tebur 7. STM32MP133C/F ma'anar ball (ci gaba)

Ayyukan ball

Sunan fil (aiki bayan
sake saiti)

Madadin ayyuka

Ƙarin ayyuka

LFBGA289 TFBGA289 TFBGA320
Tsarin nau'in fil I/O
Bayanan kula

Farashin M1J7P3

Farashin PF7

I/O FT_vh -

Saukewa: M3R1R2

Saukewa: PG11

I/O FT_vh -

L3 J6 N3

Saukewa: PH6

I/O FT_fh -

N2 P4 R1

Saukewa: PG1

I/O FT_vh -

M11 - N12

VDD

–

N1 R2 T2

Farashin PE6

I/O FT_vh -

P1 P1 T3 PH0-OSC_IN I/O FT

–

G9 U1 N11

VSS

–

P2 P2 U2 PH1-OSC_OUT I/O FT

–

Saukewa: R2T2R3

Saukewa: PH3

I/O FT_fh -

M5 L5 U3 VSS_ANA S

–

TIM17_CH1, UART7_TX(boot),
UART4_CTS, ETH1_RGMII_CLK125, ETH2_MII_TXD0/ETH2_ RGMII_TXD0/ETH2_RMII_
TXD0, FMC_A18
SAI2_D3, I2S2_MCK, USART3_TX, UART4_TX, ETH2_MII_TXD1/ETH2_ RGMII_TXD1/ETH2_RMII_
TXD1, FMC_A24
TIM12_CH1, USART2_CK, I2C5_SDA,
SPI2_SCK/I2S2_CK, QUADSPI_BK1_IO2,
ETH1_PHY_INTN, ETH1_MII_RX_ER, ETH2_MII_RXD2/ETH2_
RGMII_RXD2, QUADSPI_BK1_NCS
LPTIM1_ETR, TIM4_ETR, SAI2_FS_A, I2C2_SMBA,
SPI2_MISO/I2S2_SDI, SAI2_D2, FDCAN2_TX, ETH2_MII_TXD2/ETH2_ RGMII_TXD2, FMC_NBL0
–
MCO2, TIM1_BKIN2, SAI2_SCK_B, TIM15_CH2, I2C3_SMBA, SAI1_SCK_B, UART4_RTS/UART4_DE,
ETH2_MII_TXD3/ETH2_ RGMII_TXD3, FMC_A22
–
–
–
I2C3_SCL, SPI5_MOSI, QUADSPI_BK2_IO1, ETH1_MII_COL, ETH2_MII_COL, QUADSPI_BK1_IO0
–

–
–
–
OSC_IN OSC_OUT -

58/219

Saukewa: DS13875

Saukewa: STM32MP133C/F

Pinout, bayanin fil da madadin ayyuka

Lambar Pin

Tebur 7. STM32MP133C/F ma'anar ball (ci gaba)

Ayyukan ball

Sunan fil (aiki bayan
sake saiti)

Madadin ayyuka

Ƙarin ayyuka

LFBGA289 TFBGA289 TFBGA320
Tsarin nau'in fil I/O
Bayanan kula

Bayani na L5U2W1

Saukewa: PG3

I/O FT_fvh -

TIM8_BKIN2, I2C2_SDA, SAI2_SD_B, FDCAN2_RX, ETH2_RGMII_GTX_CLK,
ETH1_MDIO, FMC_A13

M4 L4 V2 VDD_ANA S

–

R1 U3 V3

Saukewa: PG2

I/O FT

–

MCO2, TIM8_BKIN, SAI2_MCLK_B, ETH1_MDC

Saukewa: T1L6W2

Saukewa: PG12

I/O FT

LPTIM1_IN1, SAI2_SCK_A,

SAI2_CK2,

USART6_RTS/USART6_DE,

USART3_CTS,

–

ETH2_PHY_INTN,

ETH1_PHY_INTN,

ETH2_MII_RX_DV/ETH2_

RGMII_RX_CTL/ETH2_RMII_

CRS_DV

F7 P6 R5

VDD

–

Saukewa: G10E8T1

VSS

–

N3 R3 V1

MCO1, USART2_CK,

I2C2_SCL, I2C3_SDA,

SPDIFRX_IN0,

Farashin PD7

I/O FT_fh

–

ETH1_MII_RX_CLK/ETH1_ RGMII_RX_CLK/ETH1_RMII_

REF_CLK,

QUADSPI_BK1_IO2,

FMC_NE1

Bayani na P3K7T4

PA13

I/O FT

–

DBTRGO, DBTRGI, MCO1, UART4_TX

R3 R4 W3 PWR_CPU_ON O FT

–

T2 N5 Y1

PA11

I/O FT_f

TIM1_CH4, I2C5_SCL,

SPI2_NSS/I2S2_WS,

USART1_CTS/USART1_NSS,

–

ETH2_MII_RXD1/ETH2_

RGMII_RXD1/ETH2_RMII_

RXD1, ETH1_CLK,

ETH2_CLK

N5 M6 AA2

Saukewa: PB11

TIM2_CH4, LPTIM1_OUT,

I2C5_SMBA, USART3_RX,

I/O FT_vh -

ETH1_MII_TX_EN/ETH1_

RGMII_TX_CTL/ETH1_RMII_

TX_EN

–
–
–
BOOTFAILN -
–

Saukewa: DS13875

59/219
97

Pinout, bayanin fil da madadin ayyuka

Saukewa: STM32MP133C/F

Lambar Pin

Tebur 7. STM32MP133C/F ma'anar ball (ci gaba)

Ayyukan ball

Sunan fil (aiki bayan
sake saiti)

Madadin ayyuka

Ƙarin ayyuka

LFBGA289 TFBGA289 TFBGA320
Tsarin nau'in fil I/O
Bayanan kula

P4 U4

PF14(JTCK/SW CLK)

I/O

(2)

U3 L7 Y3

PA0

I/O FT_a -

JTCK/SWCLK
TIM2_CH1, TIM5_CH1, TIM8_ETR, TIM15_BKIN, SAI1_SD_B, UART5_TX,
ETH1_MII_CRS, ETH2_MII_CRS

N6 T3 W4

Farashin PF13

TIM2_ETR, SAI1_MCLK_B,

I/O FT_a -

DFSDM1_DATIN3,

USART2_TX, UART5_RX

Saukewa: G11E10

F10-

–

R4K8 AA3

P5 R5 Y4 U4 M7 Y5

VSS VDD PA1
PA2
PA5

–

I/O FT_a

I/O FT_a I/O FT_a

–

TIM2_CH2, TIM5_CH2, LPTIM3_OUT, TIM15_CH1N,
DFSDM1_CKIN0, – USART2_RTS/USART2_DE,
ETH1_MII_RX_CLK/ETH1_ RGMII_RX_CLK/ETH1_RMII_
REF_CLK

TIM2_CH3, TIM5_CH3, - LPTIM4_OUT, TIM15_CH1,
USART2_TX, ETH1_MDIO

TIM2_CH1/TIM2_ETR,

USART2_CK, TIM8_CH1N,

–

SAI1_D1, SPI1_NSS/I2S1_WS,

SAI1_SD_A, ETH1_PPS_OUT,

ETH2_PPS_OUT

Saukewa: T3T4W5

SAI1_SCK_A, SAI1_CK2,

PC0

I/O FT_ha -

I2S1_MCK, SPI1_MOSI/I2S1_SDO,

USART1_TX

T4 J9 AA4
R6 U6 W7 P7 U5 U8 P6 T6 V8

Farashin PF12

I/O FT_vha -

VREF+

–

VDDA

–

VREF-

–

SPI1_NSS/I2S1_WS, SAI1_SD_A, UART4_TX,
ETH1_MII_TX_ER, ETH1_RGMII_CLK125
–
–
–

–
ADC1_INP7, ADC1_INN3, ADC2_INP7, ADC2_INN3 ADC1_INP11, ADC1_INN10, ADC2_INP11, ADC2_INN10
–
ADC1_INP3, ADC2_INP3
ADC1_INP1, ADC2_INP1
ADC1_INP2
ADC1_INP0, ADC1_INN1, ADC2_INP0, ADC2_INN1, TAMP_IN3
ADC1_INP6, ADC1_INN2
–

60/219

Saukewa: DS13875

Saukewa: STM3

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STM32MP133C F 32-bit Arm Cortex-A7 1GHz MPU, STM32MP133C, F 32-bit Arm Cortex-A7 1GHz MPU, Arm Cortex-A7 1GHz MPU, 1GHz, MPU

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STMicroelectronics STM32MP133C F 32-bit Arm Cortex-A7 1GHz MPU

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Arm Cortex-A7 Subsystem

Tunawa

DDR Controller

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