STMicroelectronics STM32MP133C F 32-bita Arm Cortex-A7 1GHz MPU Uzantogvidilo

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1 STMicroelectronics STM32MP133C F 32-bit Arm Cortex-A7 1GHz MPU

2 Specifoj

3 Arm Cortex-A7 Subsystem

STMicroelectronics STM32MP133C F 32-bit Arm Cortex-A7 1GHz MPU

Specifoj

Core: Arm Cortex-A7
Memories: External SDRAM, Embedded SRAM

Data Bus: 16-bit parallel interface
Security/Safety: Reset and Power Management, LPLV-Stop2, Standby

Package: LFBGA, TFBGA with min pitch 0.5 mm
Administrado de Horloĝo

General-purpose Input/Outputs
Interkonekta Matrico

4 DMA Controllers
Communications Peripherals: Up to 29

Analog Peripherals: 6
Timers: Up to 24, Watchdogs: 2

Hardware Acceleration
Sencimiga Reĝimo

Fuses: 3072-bit including unique ID and HUK for AES 256 keys
ECOPACK2 compliant

Arm Cortex-A7 Subsystem

The Arm Cortex-A7 subsystem of the STM32MP133C/F provides…

Memoroj

The device includes External SDRAM and Embedded SRAM for data storage…

DDR-regilo

The DDR3/DDR3L/LPDDR2/LPDDR3 controller manages memory access…

Power Supply Management
The power supply scheme and supervisor ensure stable power delivery…

Administrado de Horloĝo
The RCC handles clock distribution and configurations…

General-purpose Input/Outputs (GPIOs)
The GPIOs provide interface capabilities for external devices…

TrustZone Protection Controller
The ETZPC enhances system security by managing access rights…

Bus-Interconnect Matrix
The matrix facilitates data transfer between different modules…

Oftaj Demandoj

Q: What is the maximum number of communication peripherals supported?
A: The STM32MP133C/F supports up to 29 communication peripherals.

Q: How many analog peripherals are available?
A: The device offers 6 analog peripherals for various analog functions.

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STM32MP133C STM32MP133F

Arm® Cortex®-A7 up to 1 GHz, 2×ETH, 2×CAN FD, 2×ADC, 24 timers, audio, crypto and adv. security
Datenfolio - produktadaj datumoj

Karakterizaĵoj
Inkluzivas ST-pintnivelan patentitan teknologion
Kerno
· 32-bit Arm® Cortex®-A7 L1 32-Kbyte I / 32-Kbyte D 128-Kbyte unified level 2 cache Arm® NEONTM and Arm® TrustZone®

Memoroj
· External DDR memory up to 1 Gbyte up to LPDDR2/LPDDR3-1066 16-bit up to DDR3/DDR3L-1066 16-bit
· 168 Kbytes of internal SRAM: 128 Kbytes of AXI SYSRAM + 32 Kbytes of AHB SRAM and 8 Kbytes of SRAM in Backup domain
· Dual Quad-SPI memory interface · Flexible external memory controller with up to
16-bit data bus: parallel interface to connect external ICs and SLC NAND memories with up to 8-bit ECC
Security/safety
· Secure boot, TrustZone® peripherals, 12 x tamper pins including 5 x active tampers
· Temperature, voltage, frequency and 32 kHz monitoring
Restarigo kaj administrado de potenco
· 1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os) · POR, PDR, PVD and BOR · On-chip LDOs (USB 1.8 V, 1.1 V) · Backup regulator (~0.9 V) · Internal temperature sensors · Low-power modes: Sleep, Stop, LPLV-Stop,
LPLV-Stop2 and Standby

LFBGA

TFBGA

LFBGA289 (14 × 14mm) Pitch 0.8 mm

TFBGA289 (9 × 9 mm) TFBGA320 (11 × 11 mm)
min pitch 0.5 mm

· DDR retention in Standby mode · Controls for PMIC companion chip

Horloĝadministrado
· Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz LSI oscillator
· External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator
· 4 × PLLs with fractional mode

Ĝenerala celo enigo/produktaĵoj
· Up to 135 secure I/O ports with interrupt capability
· Up to 6 wakeup

Interconnect matrix
· 2 bus matrices 64-bit Arm® AMBA® AXI interconnect, up to 266 MHz 32-bit Arm® AMBA® AHB interconnect, up to 209 MHz

4 DMA controllers to unload the CPU
· 56 physical channels in total
· 1 x high-speed general-purpose master direct memory access controller (MDMA)
· 3 × dual-port DMAs with FIFO and request router capabilities for optimal peripheral management

septembro 2024
Ĉi tio estas informo pri produkto en plena produktado.

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www.st.com

STM32MP133C/F

Ĝis 29 komunikadaj ekstercentraj
· 5 × I2C FM+ (1 Mbit/s, SMBus/PMBusTM) · 4 x UART + 4 x USART (12.5 Mbit/s,
ISO7816 interface, LIN, IrDA, SPI) · 5 × SPI (50 Mbit/s, including 4 with full-duplex
I2S audio class accuracy via internal audio PLL or external clock)(+2 QUADSPI + 4 with USART) · 2 × SAI (stereo audio: I2S, PDM, SPDIF Tx) · SPDIF Rx with 4 inputs · 2 × SDMMC up to 8 bits (SD/e·MMCTM/SDIO) · 2 × CAN controllers supporting CAN FD protocol · 2 × USB 2.0 high-speed Host or 1 × USB 2.0 high-speed Host

+ 1 × USB 2.0 high-speed OTG simultaneously · 2 x Ethernet MAC/GMAC IEEE 1588v2 hardware, MII/RMII/RGMII
6 analog peripherals
· 2 × ADCs with 12-bit max. resolution up to 5 Msps
· 1 x temperature sensor · 1 x digital filter for sigma-delta modulator
(DFSDM) with 4 channels and 2 filters · Internal or external ADC reference VREF+
Ĝis 24 tempigiloj kaj 2 gardohundoj
· 2 × 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
· 2 × 16-bit advanced timers · 10 × 16-bit general-purpose timers (including
2 basic timers without PWM) · 5 × 16-bit low-power timers · Secure RTC with sub-second accuracy and
hardware calendar · 4 Cortex®-A7 system timers (secure,
non-secure, virtual, hypervisor) · 2 × independent watchdogs
Akcelado de aparataro
· AES 128, 192, 256 DES/TDES

2 (independent, independent secure) 5 (2 securable) 4 5 (3 securable)
4 + 4 (including 2 securable USART), some can be a boot source
2 (up to 4 audio channels), with I2S master/slave, PCM input, SPDIF-TX 2 ports
Embedded HSPHY with BCD Embedded HS PHY with BCD (securable), can be a boot source
2 × HS shared between Host and OTG 4 inputs

2 (1 × TTCAN), clock calibration, 10 Kbyte shared buffer 2 (8 + 8 bits) (securable), e·MMC or SD can be a boot source 2 optional independant power supplies for SD card interfaces
1 (dual-quad) (securable), can be a boot source

–
–
Boto
–
Boto
Boot Boot
(1)

Parallel address/data 8/16-bit FMC Parallel AD-mux 8/16-bit
NAND 8/16-bit 10/100M/Gigabit Ethernet DMA Cryptography
Hash True random number generator Fuses (one-time programmable)

4 × CS, up to 4 × 64 Mbyte
Yes, 2× CS, SLC, BCH4/8, can be a boot source 2 x (MII, RMI, RGMII) with PTP and EEE (securable)
3 instances (1 secure), 33-channel MDMA PKA (with DPA protection), DES, TDES, AES (with DPA protection)
(all securable) SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-3, HMAC
(securable) True-RNG (securable) 3072 effective bits (secure, 1280 bits available for the user)

–
Boot –
–

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Priskribo

Table 1. STM32MP133C/F features and peripheral counts (continued)

STM32MP133CAE STM32MP133FAE STM32MP133CAG STM32MP133FAG STM32MP133CAF STM32MP133FAF Miscellaneous

Karakterizaĵoj

LFBGA289

TFBGA289

TFBGA320

GPIOs with interrupt (total count)

135 (2)

Securable GPIOs Wakeup pins

Ĉiuj
6

Tamper pins (active tampe)

12 (5)

DFSDM Up to 12-bit synchronized ADC

4 input channels with 2 filters

–

2(3) (up to 5 Msps on 12-bit each) (securable)

ADC1: 19 channels including 1x internal, 18 channels available for

12-bit ADC channels in total(4)

user including 8x differential

–

ADC2: 18 channels including 6x internal, 12 channels available for

user including 6x differential

Internal ADC VREF VREF+ input pin

1.65 V, 1.8 V, 2.048 V, 2.5 V or VREF+ input –
Jes

1. QUADSPI may boot either from dedicated GPIOs or using some FMC Nand8 boot GPIOs (PD4, PD1, PD5, PE9, PD11, PD15 (see Table 7: STM32MP133C/F ball definitions).
2. This total GPIO count includes four JTAG GPIOs and three BOOT GPIOs with limited usage (may conflict with external device connection during boundary scan or boot).
3. When both ADCs are used, the kernel clock should be the same for both ADCs and the embedded ADC prescalers cannot be used.
4. In addition, there are also internal channels: – ADC1 internal channel: VREFINT – ADC2 internal channels: temperature, internal voltage reference, VDDCORE, VDDCPU, VDDQ_DDR, VBAT / 4.

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Figure 1. STM32MP133C/F block diagram

IC supplies

@VDDA

HSI

AXIM: Arm 64-bit AXI interconnect (266 MHz) T

@VDDCPU

GIC

Cortex-A7 CPU 650/1000 MHz + MMU + FPU + NEONT

32K D$

32K I$

CNT (timer) T

ETM

2561K2B8LK2B$L+2$SCU T
async

128 bitoj

CSI

LSI

Debug timestamp

generator TSGEN

DAP
(JTAG/SWD)

SYSRAM 128KB

ROM 128KB

2 x ETH MAC
10/100/1000(no GMII)

FIFO

BKPSRAM 8KB

RNG

HASH

16b PHY

DDRCTRL 58
LPDDR2/3, DDR3/3L

async

CRYP

SAES

DDRMCE T TZC T

DDRPHYC
T

DLY

8b QUADSPI (dual) T

16b

FMC

CRC

DLYBSD1

(SDMMC1 DLY control)

DLYBSD2

(SDMMC2 DLY control)

DLYBQS

(QUADSPI DLY control)

FIFO FIFO

DLY DLY

14 8b SDMMC1 T 14 8b SDMMC2 T

PHY

USBH

(2xHS Host)

PLLUSB

FIFO

PKA

FIFO

T MDMA 32 channels

AXIMC T T

17 16b Trace port

ETZPC

IWDG1

@VBAT

BSEC

OTP Fuses

@VDDA

RTC / AWU

TAMP / Backup regs T

@VBAT

LSE (32kHz XTAL)

System timing STGENC

generacio

STGENR

USBPHYC
(USB 2 x PHY control)
IWDG2

@VBAT

@VDDA

VREFBUF

16b LPTIM2

16b LPTIM3

16b LPTIM4

16b LPTIM5

BOOT pins

SYSCFG

HDP

10 16b TIM1/PWM 10 16b TIM8/PWM

SAI1

SAI2

4ch DFSDM

Buffer 10KB CCU

FDCAN1

FDCAN2

FIFO FIFO
APB2 (100 MHz)

8KB FIFO
APB5 (100MHz)

APB3 (100 MHz)

APB4

async AHB2APB

SRAM1 16KB T SRAM2 8KB T SRAM3 8KB T

AHB2APB

DMA1
8 riveretoj
DMAMUX1
DMA2
8 riveretoj

DMAMUX2

DMA3
8 riveretoj

PMB (process monitor)
DTS (digital temp. sensor)

Voltage reguligistoj

@VDDA

Supply supervision

FIFO

2×2 Matrico
AHB2APB

64 bits AXI

64bits AXI master

32 bits AHB 32 bits AHB master

32 bits APB

T TrustZone security protection

AHB2APB

APB2 (100 MHz)

APB1 (100 MHz)
FIFO FIFO FIFO FIFO FIFO

MLAHB: Arm 32-bit multi-AHB bus matrix (209 MHz)
APB6
FIFO FIFO FIFO FIFO

@VBAT
T
FIFO

HSE (XTAL)

PLL1/2/3/4

RCC

T PWR

EXTI

16ext

176

USBO

(OTG HS)

PHY

12b ADC1

12b ADC2

GPIOA

16b

GPIOB

16b

GPIOC

16b

GPIOD

16b

GPIOE

16b

GPIOF

16b

GPIOG 16b 16

GPIOH

16b

GPIOI

16b

AHB2APB

USART1

Smartcard IrDA

USART2

Smartcard IrDA

SPI4/I2S4

SPI5

I2C3/SMBUS

I2C4/SMBUS

I2C5/SMBUS

Filter Filter Filter

TIM12

16b

TIM13

16b

TIM14

16b

TIM15

16b

TIM16

16b

TIM17

16b

TIM2 TIM3 TIM4

32b

16b

TIM5 TIM6 TIM7

32b

16b

LPTIM1 16b

USART3

Smartcard IrDA

UART4

UART5

UART7

UART8

Filtrilo Filtrilo

I2C1/SMBUS

I2C2/SMBUS

SPI2/I2S2

SPI3/I2S3

USART6

Smartcard IrDA

SPI1/I2S1

FIFO FIFO

MSv67509V2

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3.1
3.1.1
3.1.2

Arm Cortex-A7 subsystem
Karakterizaĵoj
· ARMv7-A architecture · 32-Kbyte L1 instruction cache · 32-Kbyte L1 data cache · 128-Kbyte level2 cache · Arm + Thumb®-2 instruction set · Arm TrustZone security technology · Arm NEON advanced SIMD · DSP and SIMD extensions · VFPv4 floating-point · Hardware virtualization support · Embedded trace module (ETM) · Integrated generic interrupt controller (GIC) with 160 shared peripheral interrupts · Integrated generic timer (CNT)
Finiteview
The Cortex-A7 processor is a very energy-efficient applications processor designed to provide rich performance in high-end wearables, and other low-power embedded and consumer applications. It provides up to 20 % more single thread performance than the Cortex-A5 and provides similar performance than the Cortex-A9.
The Cortex-A7 incorporates all features of the high-performance Cortex-A15 and CortexA17 processors, including virtualization support in hardware, NEON, and 128-bit AMBA 4 AXI bus interface.
The Cortex-A7 processor builds on the energy-efficient 8-stage pipeline of the Cortex-A5 processor. It also benefits from an integrated L2 cache designed for low-power, with lower transaction latencies and improved OS support for cache maintenance. On top of this, there is improved branch prediction and improved memory system performance, with 64-bit loadstore path, 128-bit AMBA 4 AXI buses and increased TLB size (256 entry, up from 128 entry for Cortex-A9 and Cortex-A5), increasing performance for large workloads such as web foliumante.
Thumb-2 technology
Delivers the peak performance of traditional Arm code while also providing up to a 30 % reduction in memory requirement for instructions storage.
TrustZone technology
Ensures reliable implementation of security applications ranging from digital rights management to electronic payment. Broad support from technology and industry partners.

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NEONO
NEON technology can accelerate multimedia and signal processing algorithms such as video encode/decode, 2D/3D graphics, gaming, audio and speech processing, image processing, telephony, and sound synthesis. The Cortex-A7 provides an engine that offers both the performance and functionality of the Cortex-A7 floating-point unit (FPU) and an implementation of the NEON advanced SIMD instruction set for further acceleration of media and signal processing functions. The NEON extends the Cortex-A7 processor FPU to provide a quad-MAC and additional 64-bit and 128-bit register set supporting a rich set of SIMD operations over 8-, 16- and 32-bit integer and 32-bit floating-point data quantities.
Hardware virtualization
Highly efficient hardware support for data management and arbitration, whereby multiple software environments and their applications are able to simultaneously access the system capabilities. This enables the realization of devices that are robust, with virtual environments that are well isolated from each other.
Optimized L1 caches
Performance and power optimized L1 caches combine minimal access latency techniques to maximize performance and minimize power consumption.
Integrated L2 cache controller
Provides low-latency and high-bandwidth access to cached memory in high-frequency, or to reduce the power consumption associated with off-chip memory access.
Cortex-A7 floating-point unit (FPU)
The FPU provides high-performance single and double precision floating-point instructions compatible with the Arm VFPv4 architecture that is software compatible with previous generations of Arm floating-point coprocessor.
Snoop control unit (SCU)
The SCU is responsible for managing the interconnect, arbitration, communication, cache to cache and system memory transfers, cache coherence and other capabilities for the processor.
This system coherence also reduces software complexity involved in maintaining software coherence within each OS driver.
Generic interrupt controller (GIC)
Implementing the standardized and architected interrupt controller, the GIC provides a rich and flexible approach to inter-processor communication and the routing and prioritization of system interrupts.
Supporting up to 192 independent interrupts, under software control, hardware prioritized, and routed between the operating system and TrustZone software management layer.
This routing flexibility and the support for virtualization of interrupts into the operating system, provides one of the key features required to enhance the capabilities of a solution utilizing a hypervisor.

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3.2
3.2.1
3.2.2

Memoroj
Ekstera SDRAM
The STM32MP133C/F devices embed a controller for external SDRAM that supports the following: · LPDDR2 or LPDDR3, 16-bit data, up to 1 Gbyte, up to 533 MHz clock · DDR3 or DDR3L, 16-bit data, up to 1 Gbyte, up to 533 MHz clock
Enigita SRAM
All devices feature: · SYSRAM: 128 Kbytes (with programmable size secure zone) · AHB SRAM: 32 Kbytes (securable) · BKPSRAM (backup SRAM): 8 Kbytes
The content of this area is protected against possible unwanted write accesses, and can be retained in Standby or VBAT mode. BKPSRAM can be defined (in ETZPC) as accessible by secure software only.

3.3

DDR3/DDR3L/LPDDR2/LPDDR3 controller (DDRCTRL)

DDRCTRL combined with DDRPHYC provides a complete memory interface solution for DDR memory subsystem. · One 64-bit AMBA 4 AXI ports interface (XPI) · AXI clock asynchronous to the controller · DDR memory cypher engine (DDRMCE) featuring AES-128 DDR on-the-fly write
encryption/read decryption. · Supported standards:
JEDEC DDR3 SDRAM specification, JESD79-3E for DDR3/3L with 16-bit interface
JEDEC LPDDR2 SDRAM specification, JESD209-2E for LPDDR2 with 16-bit interface
JEDEC LPDDR3 SDRAM specification, JESD209-3B for LPDDR3 with 16-bit interface
· Advanced scheduler and SDRAM command generator · Programmable full data width (16-bit) or half data width (8-bit) · Advanced QoS support with three traffic class on read and two traffic classes on write · Options to avoid starvation of lower priority traffic · Guaranteed coherency for write-after-read (WAR) and read-after-write (RAW) on
AXI ports · Programmable support for burst length options (4, 8, 16) · Write combine to allow multiple writes to the same address to be combined into a
single write · Single rank configuration

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· Support of automatic SDRAM power-down entry and exit caused by lack of transaction arrival for programmable time
· Support of automatic clock stop (LPDDR2/3) entry and exit caused by lack of transaction arrival
· Support of automatic low-power mode operation caused by lack of transaction arrival for programmable time via hardware low-power interface
· Programmable paging policy · Support of automatic or under software control self-refresh entry and exit · Support of deep power-down entry and exit under software control (LPDDR2 and
LPDDR3) · Support of explicit SDRAM mode register updates under software control · Flexible address mapper logic to allow application specific mapping of row, column,
bank bits · User-selectable refresh control options · DDRPERFM associated block to help for performance monitoring and tuning
DDRCTRL and DDRPHYC can be defined (in ETZPC) as accessible by secure software only.
The DDRMCE (DDR memory cypher engine) main features are listed below: · AXI system bus master/slave interfaces (64-bit) · In-line encryption (for writes) and decryption (for reads), based on embedded firewall
programming · Two encryption mode per region (maximum one region): no encryption (bypass mode),
block cipher mode · Start and end of regions defined with 64-Kbyte granularity · Default filtering (region 0): any access granted · Region access filtering: none
Supported block cipher: AES Supported chaining mode · Block mode with AES cipher is compatible with ECB mode specified in NIST FIPS publication 197 advanced encryption standard (AES), with an associated key derivation function based on Keccak-400 algorithm published on https://keccak.team website. · One set of write-only and lockable master key registers · AHB configuration port, privileged aware

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3.4

TrustZone address space controller for DDR (TZC)

TZC is used to filter read/write accesses to DDR controller according to TrustZone rights and according to non-secure master (NSAID) on up to nine programmable regions: · Configuration supported by trusted software only · One filter unit · Nine regions:
Region 0 is always enabled and covers the whole address range. Regions 1 to 8 have programmable base-/end-address and can be assigned to
any one or both filters. · Secure and non-secure access permissions programmed per region · Non-secure accesses filtered according to NSAID · Regions controlled by same filter must not overlap · Fail modes with error and/or interrupt · Acceptance capability = 256 · Gate keeper logic to enable and disable of each filter · Speculative accesses

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3.5

Boot-reĝimoj

At startup, the boot source used by the internal boot ROM is selected by the BOOT pin and OTP bytes.

Table 2. Boot modes

BOOT2 BOOT1 BOOT0 Initial boot mode

Komentoj

Wait incoming connection on:

UART and USB(1)

USART3/6 and UART4/5/7/8 on default pins

USB high-speed device on OTG_HS_DP/DM pins(2)

1 Serial NOR flash(3) Serial NOR flash on QUADSPI(5)

e·MMC(3)

e·MMC on SDMMC2 (default)(5)(6)

NAND flash(3)

SLC NAND flash on FMC

Development boot (no flash memory boot)

Used to get debug access without boot from flash memory(4)

SD card(3)

SD card on SDMMC1 (default)(5)(6)

Wait incoming connection on:

0 UART and USB(1)(3) USART3/6 and UART4/5/7/8 on default pins

USB high-speed device on OTG_HS_DP/DM pins(2)

1 Serial NAND flash(3) Serial NAND flash on QUADSPI(5)

1. Can be disabled by OTP settings. 2. USB requires HSE clock/crystal (see AN5474 for supported frequencies with and without OTP settings). 3. Boot source can be changed by OTP settings (for example initial boot on SD card, then e·MMC with OTP settings). 4. Cortex®-A7 core in infinite loop toggling PA13. 5. Default pins can be altered by OTP. 6. Alternatively, another SDMMC interface than this default can be selected by OTP.

Although low level boot is done using internal clocks, ST supplied software packages as well as major external interfaces such as DDR, USB (but not limited to) require a crystal or an external oscillator to be connected on HSE pins.
See RM0475 “STM32MP13xx advanced Arm®-based 32-bit MPUs” or AN5474 “Getting started with STM32MP13xx lines hardware development” for constraints and recommendations regarding HSE pins connection and supported frequencies.

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3.6

Administrado de elektroprovizo

3.6.1
Atentu:

Elektroproviza skemo
· VDD is the main supply for I/Os and internal part kept powered during Standby mode. Useful voltage range is 1.71 V to 3.6 V (1.8 V, 2.5 V, 3.0 V or 3.3 V typ.)
VDD_PLL and VDD_ANA must be star-connected to VDD. · VDDCPU is the Cortex-A7 CPU dedicated voltage supply, whose value depends on the
desired CPU frequency. 1.22 V to 1.38 V in run mode. VDD must be present before VDDCPU. · VDDCORE is the main digital voltage and is usually shutdown during Standby mode. Voltage range is 1.21 V to 1.29 V in run mode. VDD must be present before VDDCORE. · The VBAT pin can be connected to the external battery (1.6 V < VBAT < 3.6 V). If no external battery is used, this pin must be connected to VDD. · VDDA is the analog (ADC/VREF), supply voltage (1.62 V to 3.6 V). Using the internal VREF+ requires VDDA equal to or higher than VREF+ + 0.3 V. · The VDDA1V8_REG pin is the output of the internal regulator, connected internally to USB PHY and USB PLL. The internal VDDA1V8_REG regulator is enabled by default and can be controlled by software. It is always shut down during Standby mode.
The specific BYPASS_REG1V8 pin must never be left floating. It must be connected either to VSS or to VDD to activate or deactivate the voltage regulator. When VDD = 1.8 V, BYPASS_REG1V8 should be set. · VDDA1V1_REG pin is the output of the internal regulator, connected internally to USB PHY. The internal VDDA1V1_REG regulator is enabled by default and can be controlled by software. It is always shut down during Standby mode.
· VDD3V3_USBHS is the USB high-speed supply. VoltagLa gamo estas 3.07 V ĝis 3.6 V.
VDD3V3_USBHS must not be present unless VDDA1V8_REG is present, otherwise permanent damage may occur on the STM32MP133C/F. This must be ensured by PMIC ranking order or with external component in case of discrete component power supply implementation.
· VDDSD1 and VDDSD2 are respectively SDMMC1 and SDMMC2 SD card power supplies to support ultra-high-speed mode.
· VDDQ_DDR is the DDR IO supply. 1.425 V to 1.575 V for interfacing DDR3 memories (1.5 V typ.)
1.283 V to 1.45 V for interfacing DDR3L memories (1.35 V typ.)
1.14 V to 1.3 V for interfacing LPDDR2 or LPDDR3 memories (1.2 V typ.)
Dum ŝalti kaj malŝalti fazojn, la sekvaj potencsekvencaj postuloj devas esti respektitaj:
· When VDD is below 1 V, other power supplies (VDDCORE, VDDCPU, VDDSD1, VDDSD2, VDDA, VDDA1V8_REG, VDDA1V1_REG, VDD3V3_USBHS, VDDQ_DDR) must remain below VDD + 300 mV.
· Kiam VDD estas super 1 V, ĉiuj elektrofontoj estas sendependaj.
During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided to the STM32MP133C/F remains below 1 mJ. This allows external decoupling capacitors to be discharged with different time constants during the power- down transient phase.

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V 3.6
VBOR0 1

Figure 2. Power-up/down sequence

STM32MP133C/F

VDDX(1) VDD

3.6.2
Note: 26/219

0.3

Ŝalti

Funkcia reĝimo

Potenco-malfunkcio

tempo

Nevalida provizoregiono

VDDX < VDD + 300 mV

VDDX sendependa de VDD

MSv47490V1

1. VDDX refers to any power supply among VDDCORE, VDDCPU, VDDSD1, VDDSD2, VDDA, VDDA1V8_REG, VDDA1V1_REG, VDD3V3_USBHS, VDDQ_DDR.

Kontrolisto de elektroprovizo

The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry:
· Power-on reset (POR)
The POR supervisor monitors VDD power supply and compares it to a fixed threshold. The devices remain in reset mode when VDD is below this threshold, · Power-down reset (PDR)
The PDR supervisor monitors VDD power supply. A reset is generated when VDD drops below a fixed threshold.
· Brownout reset (BOR)
The BOR supervisor monitors VDD power supply. Three BOR thresholds (from 2.1 to 2.7 V) can be configured through option bytes. A reset is generated when VDD drops below this threshold.
· Power-on reset VDDCORE (POR_VDDCORE) The POR_VDDCORE supervisor monitors VDDCORE power supply and compares it to a fixed threshold. The VDDCORE domain remains in reset mode when VDDCORE is below this threshold.
· Power-down reset VDDCORE (PDR_VDDCORE) The PDR_VDDCORE supervisor monitors VDDCORE power supply. A VDDCORE domain reset is generated when VDDCORE drops below a fixed threshold.
· Power-on-reset VDDCPU (POR_VDDCPU) The POR_VDDCPU supervisor monitors VDDCPU power supply and compares it to a fixed threshold. The VDDCPU domain remains in reset mode when VDDCORE is below this threshold.
The PDR_ON pin is reserved for STMicroelectronics production tests and must always be connected to VDD in an application.

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3.7

Low-power strategy

There are several ways to reduce power consumption on STM32MP133C/F: · Decrease dynamic power consumption by slowing down the CPU clocks and/or the
bus matrix clocks and/or controlling individual peripheral clocks. · Save power consumption when the CPU is IDLE, by selecting among the available low-
power modes according to the user application needs. This allows the best compromise between short startup time, low-power consumption, as well as available wakeup sources, to be achieved. · Use the DVFS (dynamic voltage and frequency scaling) operating points that directly controls the CPU clock frequency as well as the VDDCPU output supply.
The operating modes allow the control of the clock distribution to the different system parts and the power of the system. The system operation mode is driven by the MPU sub-system.
The MPU sub-system low-power modes are listed below: · CSleep: The CPU clocks are stopped and the peripheral(s) clock operates as
previously set in the RCC (reset and clock controller). · CStop: The CPU peripheral(s) clocks are stopped. · CStandby: VDDCPU OFF
CSleep and CStop low-power modes are entered by the CPU when executing the WFI (wait for interrupt) or WFE (wait for event) instructions.
The system operating modes available are the followings: · Run (system at its full performance, VDDCORE, VDDCPU and clocks ON) · Stop (clocks OFF) · LP-Stop (clocks OFF) · LPLV-Stop (clocks OFF, VDDCORE and VDDCPU supply level may be lowered) · LPLV-Stop2 (VDDCPU OFF, VDDCORE lowered, and clocks OFF) · Standby (VDDCPU, VDDCORE, and clocks OFF)

Table 3. System versus CPU power mode

System power mode

CPU

Kura reĝimo

CRun or CSleep

Stop mode LP-Stop mode LPLV-Stop mode LPLV-Stop2 mode
Standby-reĝimo

CStop or CStandby CStandby

3.8

Restarigi kaj horloĝregilo (RCC)

The clock and reset controller manages the generation of all the clocks, as well as the clock gating, and the control of the system and peripheral resets.RCC provides a high flexibility in the choice of clock sources and allows application of clock ratios to improve the power consumption. In addition, on some communication peripherals that are capable to work with

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3.8.1 3.8.2

two different clock domains (either a bus interface clock or a kernel peripheral clock), the system frequency can be changed without modifying the baudrate.
Horloĝadministrado
The devices embed four internal oscillators, two oscillators with external crystal or resonator, three internal oscillators with fast startup time and four PLLs.
The RCC receives the following clock source inputs: · Internal oscillators:
64 MHz HSI clock (1 % accuracy) 4 MHz CSI clock 32 kHz LSI clock · External oscillators: 8-48 MHz HSE clock 32.768 kHz LSE clock
The RCC provides four PLLs: · PLL1 dedicated to the CPU clocking · PLL2 providing:
clocks for the AXI-SS (including APB4, APB5, AHB5 and AHB6 bridges) clocks for the DDR interface · PLL3 providing: clocks for the multi-Layer AHB and peripheral bus matrix (including the APB1,
APB2, APB3, APB6, AHB1, AHB2, and AHB4) kernel clocks for peripherals · PLL4 dedicated to the generation of the kernel clocks for various peripherals
The system starts on the HSI clock. The user application can then select the clock configuration.
System reset sources
The power-on reset initializes all registers except for the debug, a part of the RCC, a part of the RTC and power controller status registers, as well as the Backup power domain.
An application reset is generated from one of the following sources: · a reset from NRST pad · a reset from POR and PDR signal (generally called power-on reset) · a reset from BOR (generally called brownout) · a reset from the independent watchdog 1 · a reset from the independent watchdog 2 · a software system reset from the Cortex-A7 (CPU) · a failure on HSE, when the clock security system feature is activated
A system reset is generated from one of the following sources: · an application reset · a reset from POR_VDDCORE signal · an exit from Standby mode to Run mode

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A MPU processor reset is generated from one of the following sources: · a system reset · every time the MPU exits CStandby · a software MPU reset from the Cortex-A7 (CPU)

3.9

General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission.
After reset, all GPIOs are in analog mode to reduce power consumption.
The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers.
All GPIO pins can be individually set as secure, which means that software accesses to these GPIOs and associated peripherals defined as secure are restricted to secure software running on the CPU.

3.10
Notu:

TrustZone protection controller (ETZPC)
ETZPC is used to configure TrustZone security of bus masters and slaves with programmable-security attributes (securable resources). For instance: · On-chip SYSRAM secure region size can be programmed. · AHB and APB peripherals can be made secure or non-secure. · AHB SRAM can be made secure or non-secure.
By default, SYSRAM, AHB SRAMs and securable peripherals are set to secure access only, so, not accessible by non-secure masters such as DMA1/DMA2.

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3.11

Bus-interconnect matrix
The devices feature an AXI bus matrix, one main AHB bus matrix and bus bridges that allow bus masters to be interconnected with bus slaves (see the figure below, the dots represent the enabled master/slave connections).
Figure 3. STM32MP133C/F bus matrix

MDMA

SDMMC2

SDMMC1

DBG From MLAHB interconnect USBH

CPU

ETH1 ETH2

128-bita

AXIM

M1 M2

M11

S1 S2 S3 S4 S5 S6 S7 S8 S9

Default slave AXIMC

NIC-400 AXI 64 bits 266 MHz – 10 masters / 10 slaves

From AXIM interconnect DMA1 DMA2 USBO DMA3

M1 M2

M3 M4

M6 M7

S4 S5 Interconnect AHB 32 bits 209 MHz – 8 masters / 6 slaves

DDRCTRL 533 MHz AHB bridge to AHB6 To MLAHB interconnect FMC/NAND QUADSPI SYSRAM 128 KB ROM 128 KB AHB bridge to AHB5 APB bridge to APB5 APB bridge to DBG APB
AXI 64 synchronous master port AXI 64 synchronous slave port AXI 64 asynchronous master port AXI 64 asynchronous slave port AHB 32 synchronous master port AHB 32 synchronous slave port AHB 32 asynchronous master port AHB 32 asynchronous slave port
Bridge to AHB2 SRAM1 SRAM2 SRAM3 To AXIM interconnect Bridge to AHB4
MSv67511V2

MLAHB

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3.12

DMA-regiloj
The devices feature the following DMA modules to unload CPU activity: · a master direct memory access (MDMA)
The MDMA is a high-speed DMA controller, that is in charge of all types of memory transfers (peripheral-to-memory, memory-to-memory, memory-to-peripheral), without any CPU action. It features a master AXI interface. The MDMA is able to interface with the other DMA controllers to extend the standard DMA capabilities, or can manage peripheral DMA requests directly. Each of the 32 channels can perform block transfers, repeated block transfers and linked list transfers. The MDMA can be set to make secure transfers to secured memories. · three DMA controllers (not secure DMA1 and DMA2, plus secure DMA3) Each controller has a dual-port AHB, for a total of 16 non-secure and eight secure DMA channels to perform FIFO-based block transfers.
Two DMAMUX units multiplex and route the DMA peripheral requests to the three DMA controllers, with high flexibility, maximizing the number of DMA requests that run concurrently, as well as generating DMA requests from peripheral output triggers or DMA events.
DMAMUX1 maps DMA requests from non-secure peripherals to DMA1 and DMA2 channels. DMAMUX2 maps DMA requests from secure peripherals to DMA3 channels.

3.13

Extended interrupt and event controller (EXTI)
The extended interrupt and event controller (EXTI) manages the CPU and system wakeup through configurable and direct event inputs. EXTI provides wakeup requests to the power control, and generates an interrupt request to the GIC, and events to the CPU event input.
The EXTI wakeup requests allow the system to be woken up from Stop mode, and the CPU to be woken up from CStop and CStandby modes.
The interrupt request and event request generation can also be used in Run mode.
The EXTI also includes the EXTI IOport selection.
Each interrupt or event can be set as secure in order to restrict access to secure software only.

3.14

Cikla redundanca kontrola kalkulunuo (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a programmable polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the flash memory integrity. The CRC calculation unit helps computing a signature of the software during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location.

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3.15

Flexible memory controller (FMC)
The FMC controller main features are the following: · Interface with static-memory mapped devices including:
NOR flash memory Static or pseudo-static random access memory (SRAM, PSRAM) NAND flash memory with 4-bit/8-bit BCH hardware ECC · 8-,16-bit data bus width · Independent chip-select control for each memory bank · Independent configuration for each memory bank · Write FIFO
The FMC configuration registers can be made secure.

3.16

Dual Quad-SPI memory interface (QUADSPI)
The QUADSPI is a specialized communication interface targeting single, dual or quad SPI flash memories. It can operate in any of the three following modes: · Indirect mode: all the operations are performed using the QUADSPI registers. · Status-polling mode: the external flash memory status register is periodically read and
an interrupt can be generated in case of flag setting. · Memory-mapped mode: the external flash memory is mapped to the address space
and is seen by the system as if it was an internal memory.
Both throughput and capacity can be increased two-fold using dual-flash mode, where two Quad-SPI flash memories are accessed simultaneously.
QUADSPI is coupled with a delay block (DLYBQS) allowing the support of external data frequency above 100 MHz.
The QUADSPI configuration registers can be secure, as well as its delay block.

3.17

Analog-to-digital converters (ADC1, ADC2)
The devices embed two analog-to-digital converters, whose resolution can be configured to 12-, 10-, 8- or 6-bit. Each ADC shares up to 18 external channels, performing conversions in the single-shot or scan mode. In scan mode, the automatic conversion is performed on a selected group of analog inputs.
Both ADCs have securable bus interfaces.
Each ADC can be served by a DMA controller, thus allowing the automatic transfer of ADC converted values to a destination location without any software action.
In addition, an analog watchdog feature can accurately monitor the converted voltage de unu, iuj aŭ ĉiuj elektitaj kanaloj. Interrompo estas generita kiam la transformita voltage estas ekster la planitaj sojloj.
In order to synchronize A/D conversion and timers, the ADCs can be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, LPTIM1, LPTIM2 and LPTIM3 timers.

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3.18

Sensilo de temperaturo
The devices embed a temperature sensor that generates a voltage (VTS) that varies linearly with the temperature. This temperature sensor is internally connected to ADC2_INP12 and can measure the device ambient temperature ranging from 40 to +125 °C with a precision of ±2 %.
The temperature sensor has a good linearity, but it has to be calibrated to obtain a good overall accuracy of the temperature measurement. As the temperature sensor offset varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the OTP area, that is accessible in read-only mode.

3.19

Digital temperature sensor (DTS)
The devices embed a frequency output temperature sensor. DTS counts the frequency based on the LSE or PCLK to provide the temperature information.
Following functions are supported: · interrupt generation by temperature threshold · wakeup signal generation by temperature threshold

3.20
Notu:

VBAT operacio
The VBAT power domain contains the RTC, the backup registers and the backup SRAM.
In order to optimize battery duration, this power domain is supplied by VDD when available or by the voltage applied on VBAT pin (when VDD supply is not present). VBAT power is switched when the PDR detects that VDD has dropped below the PDR level.
La voltage on the VBAT pin can be provided by an external battery, a supercapacitor or directly by VDD. In the later case, VBAT mode is not functional.
VBAT operation is activated when VDD is not present.
None of these events (external interrupts, TAMP event, or RTC alarm/events) are able to directly restore the VDD supply and force the device out of the VBAT operation. Nevertheless, TAMP events and RTC alarm/events can be used to generate a signal to an external circuitry (typically a PMIC) that can restore the VDD supply.

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3.21

Voltage reference buffer (VREFBUF)
The devices embed a voltage reference buffer that can be used as voltage reference for the ADCs, and also as voltage reference for external components through the VREF+ pin. VREFBUF can be secure. The internal VREFBUF supports four voltages: · 1.65 V · 1.8 V · 2.048 V · 2.5 V An external voltage reference can be provided through the VREF+ pin when the internal VREFBUF is off.
Figuro 4. Voltage referenca bufro

VREFINT

–

VREF+

VSSA

MSv64430V1

3.22

Digital filter for sigma-delta modulator (DFSDM)
The devices embed one DFSDM with support for two digital filters modules and four external input serial channels (transceivers) or alternately four internal parallel inputs.
The DFSDM interfaces external modulators to the device and performs digital filtering of the received data streams. modulators are used to convert analog signals into digital-serial streams that constitute the inputs of the DFSDM.
The DFSDM can also interface PDM (pulse-density modulation) microphones and perform the PDM to PCM conversion and filtering (hardware accelerated). The DFSDM features optional parallel data stream inputs from the ADCs or from the device memory (through DMA/CPU transfers into DFSDM).
The DFSDM transceivers support several serial-interface formats (to support various modulators). DFSDM digital filter modules perform digital processing according user-defined filter parameters with up to 24-bit final ADC resolution.

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The DFSDM peripheral supports: · Four multiplexed input digital serial channels:
configurable SPI interface to connect various modulators configurable Manchester coded 1-wire interface PDM (pulse-density modulation) microphone input maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding) clock output for modulators (0 to 20 MHz) · Alternative inputs from four internal digital parallel channels (up to 16-bit input resolution): internal sources: ADC data or memory data streams (DMA) · Two digital filter modules with adjustable digital signal processing: Sincx filter: filter order/type (1 to 5), oversampling ratio (1 to 1024) integrator: oversampling ratio (1 to 256) · Up to 24-bit output data resolution, signed output data format · Automatic data offset correction (offset stored in register by user) · Continuous or single conversion · Start-of-conversion triggered by: software trigger internal timers external events start-of-conversion synchronously with first digital filter module (DFSDM) · Analog watchdog featuring: low-value and high-value data threshold registers dedicated configurable Sincx digital filter (order = 1 to 3,
oversampling ratio = 1 to 32) input from final output data or from selected input digital serial channels continuous monitoring independently from standard conversion · Short-circuit detector to detect saturated analog input values (bottom and top range): up to 8-bit counter to detect 1 to 256 consecutive 0’s or 1’s on serial data stream monitoring continuously each input serial channel · Break signal generation on analog watchdog event or on short-circuit detector event · Extremes detector: storage of minimum and maximum values of final conversion data refreshed by software · DMA capability to read the final conversion data · Interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial channel clock absence · “Regular” or “injected” conversions: “regular” conversions can be requested at any time or even in continuous mode
without having any impact on the timing of “injected” conversions “injected” conversions for precise timing and with high conversion priority

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3.23

Vera hazarda nombrogeneratoro (RNG)
The devices embed one RNG that delivers 32-bit random numbers generated by an integrated analog circuit.
The RNG can be defined (in ETZPC) as accessible by secure software only.
The true RNG connects to the secured AES and PKA peripherals via a dedicated bus (not readable by the CPU).

3.24

Cryptographic and hash processors (CRYP, SAES, PKA and HASH)
The devices embed one cryptographic processor that supports the advanced cryptographic algorithms usually required to ensure confidentiality, authentication, data integrity and nonrepudiation when exchanging messages with a peer.
The devices also embed a dedicated DPA resistant secure AES 128- and 256-bit key (SAES) and PKA hardware encryption/decryption accelerator, with dedicated hardware bus not accessible by the CPU.
CRYP main features: · DES/TDES (data encryption standard/triple data encryption standard): ECB (electronic
codebook) and CBC (cipher block chaining) chaining algorithms, 64-, 128- or 192-bit key · AES (advanced encryption standard): ECB, CBC, GCM, CCM, and CTR (counter mode) chaining algorithms, 128-, 192- or 256-bit key
Universal HASH main features: · SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-3 (secure HASH algorithms) · HMAC
The cryptographic accelerator supports DMA request generation.
CRYP, SAES, PKA and HASH can be defined (in ETZPC) as accessible by secure software only.

3.25

Boot and security and OTP control (BSEC)
The BSEC (boot and security and OTP control) is intended to control an OTP (one-time programmable) fuse box, used for embedded non-volatile storage for device configuration and security parameters. Some part of BSEC must be configured as accessible by secure software only.
The BSEC can use OTP words for storage of HWKEY 256-bit for SAES (secure AES).

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3.26

Tempigiloj kaj gardohundoj
The devices include two advanced-control timers, ten general-purpose timers (out of which seven are secured), two basic timers, five low-power timers, two watchdogs, and four system timers in each Cortex-A7.
All timer counters can be frozen in debug mode.
The table below compares the features of the advanced-control, general-purpose, basic and low-power timers.

Temporizilo tipo

Temporizilo

Tabelo 4. Tempa komparo

Counter resolu-
tion

Nombrilo tipo

Prescaler factor

DMA request generation

Capture/ compare channels

Complementary output

Max interface
clock (MHz)

Maks
tempigilo
clock (MHz)(1)

Advanced TIM1, -control TIM8

16-bita

Up, Any integer down, between 1 up/down and 65536

Jes

TIM2 TIM5

32-bita

Up, Any integer down, between 1 up/down and 65536

Jes

TIM3 TIM4

16-bita

Up, Any integer down, between 1 up/down and 65536

Jes

Ajna entjero

TIM12(2) 16-bit

Up between 1

Generalo

kaj 65536

celo

TIM13(2) TIM14(2)

16-bita

Any integer Up between 1
kaj 65536

Ajna entjero

TIM15(2) 16-bit

Up between 1

Jes

kaj 65536

TIM16(2) TIM17(2)

16-bita

Any integer Up between 1
kaj 65536

Jes

Baza

TIM6, TIM7

16-bita

Any integer Up between 1
kaj 65536

Jes

LPTIM1,

Lowpower

LPTIM2(2), LPTIM3(2),
LPTIM4,

16-bita

1, 2, 4, 8, Up 16, 32, 64,
128

LPTIM5

104.5

209

104.5

209

104.5

209

104.5

209

104.5

209

104.5

209

104.5

209

104.5

209

1 (3)

104.5 104.5

1. The maximum timer clock is up to 209 MHz depending on TIMGxPRE bit in the RCC. 2. Securable timer. 3. No capture channel on LPTIM.

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3.26.1 3.26.2 3.26.3

Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their four independent channels can be used for: · input capture · output compare · PWM generation (edge- or center-aligned modes) · one-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose timers. If configured as 16-bit PWM generators, they have full modulation capability (0-100 %).
The advanced-control timer can work together with the general-purpose timers via the timer link feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17)
There are ten synchronizable general-purpose timers embedded in the STM32MP133C/F devices (see Table 4 for differences). · TIM2, TIM3, TIM4, TIM5
TIM 2 and TIM5 are based on a 32-bit auto-reload up/down counter and a 16-bit prescaler, while TIM3 and TIM4 are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. All timers feature four independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. These general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8, via the timer link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from one to four hall-effect sensors. · TIM12, TIM13, TIM14, TIM15, TIM16, TIM17 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM13, TIM14, TIM16 and TIM17 feature one independent channel, whereas TIM12 and TIM15 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers or used as simple timebases. Each of these timers can be defined (in ETZPC) as accessible by secure software only.
Basic timers (TIM6 and TIM7)
These timers are mainly used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.

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3.26.4
3.26.5 3.26.6

Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5)
Each low-power timer has an independent clock and runs also in Stop mode if it is clocked by LSE, LSI or an external clock. An LPTIMx is able to wake up the device from Stop mode.
These low-power timers support the following features: · 16-bit up counter with 16-bit autoreload register · 16-bit compare register · Configurable output: pulse, PWM · Continuous/one-shot mode · Selectable software/hardware input trigger · Selectable clock source:
internal clock source: LSE, LSI, HSI or APB clock external clock source over LPTIM input (working even with no internal clock
source running, used by the pulse counter application) · Programmable digital glitch filter · Encoder mode
LPTIM2 and LPTIM3 can be defined (in ETZPC) as accessible by secure software only.
Independent watchdogs (IWDG1, IWDG2)
An independent watchdog is based on a 12-bit downcounter and a 8-bit prescaler. It is clocked from an independent 32 kHz internal RC (LSI) and, as it operates independently from the main clock, it can operate in Stop and Standby modes. IWDG can be used as a watchdog to reset the device when a problem occurs. It is hardware- or softwareconfigurable through the option bytes.
IWDG1 can be defined (in ETZPC) as accessible by secure software only.
Generic timers (Cortex-A7 CNT)
Cortex-A7 generic timers embedded inside Cortex-A7 are fed by value from system timing generation (STGEN).
The Cortex-A7 processor provides the following timers: · physical timer for use in secure and non-secure modes
The registers for the physical timer are banked to provide secure and non-secure copies. · virtual timer for use in non-secure modes · physical timer for use in hypervisor mode
Generic timers are not memory mapped peripherals and are then accessible only by specific Cortex-A7 coprocessor instructions (cp15).

3.27

System timer generation (STGEN)
The system timing generation (STGEN) generates a time-count value that provides a consistent view of time for all Cortex-A7 generic timers.

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The system timing generation has the following key features: · 64-bit wide to avoid roll-over issues · Start from zero or a programmable value · Control APB interface (STGENC) that enables the timer to be saved and restored
across powerdown events · Read-only APB interface (STGENR) that enables the timer value to be read by non-
secure software and debug tools · Timer value incrementing that can be stopped during system debug
STGENC can be defined (in ETZPC) as accessible by secure software only.

3.28

Realtempa horloĝo (RTC)
The RTC provides an automatic wakeup to manage all low-power modes.RTC is an independent BCD timer/counter and provides a time-of-day clock/calendar with programmable alarm interrupts.
The RTC includes also a periodic programmable wakeup flag with interrupt capability.
Two 32-bit registers contain the seconds, minutes, hours (12- or 24-hour format), day (day of week), date (day of month), month, and year, expressed in binary coded decimal format (BCD). The sub-seconds value is also available in binary format.
Binary mode is supported to ease software driver management.
Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed automatically. Daylight saving time compensation can also be performed.
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date.
A digital calibration feature is available to compensate for any deviation in crystal oscillator accuracy.
After Backup domain reset, all RTC registers are protected against possible parasitic write accesses and protected by secured access.
As long as the supply voltage remains in the operating range, the RTC never stops, regardless of the device status (Run mode, low-power mode or under reset).
The RTC main features are the following: · Calendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of
week), date (day of month), month, and year · Daylight saving compensation programmable by software · Programmable alarm with interrupt function. The alarm can be triggered by any
combination of the calendar fields. · Automatic wakeup unit generating a periodic flag that triggers an automatic wakeup
interrupt · Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision. · Accurate synchronization with an external clock using the sub-second shift feature · Digital calibration circuit (periodic counter correction): 0.95 ppm accuracy, obtained in a
calibration window of several seconds

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· Timestamp function for event saving · Storage of SWKEY in RTC backup registers with direct bus access to SAE (not
readable by the CPU) · Maskable interrupts/events:
Alarm A Alarm B Wakeup interrupt Timestamp · TrustZone support: RTC fully securable Alarm A, alarm B, wakeup timer and timestamp individual secure or non-secure
configuration RTC calibration done in secure on non-secure configuration

3.29

Tamper kaj rezervaj registroj (TAMP)
32 x 32-bit backup registers are retained in all low-power modes and also in VBAT mode. They can be used to store sensitive data as their content is protected by a tamper detection circuit.
Seven tamper input pins and five tamper output pins are available for anti-tamper detection. The external tamper pins can be configured for edge detection, edge and level, level detection with filtering, or active tamper that increases the security level by auto checking that the tamper pins are not externally opened or shorted.
TAMP main features · 32 backup registers (TAMP_BKPxR) implemented in the RTC domain that remains
powered-on by VBAT when the VDD power is switched off · 12 tamper pins available (seven inputs and five outputs) · Any tamper detection can generate a RTC timestamp event. · Any tamper detection erases the backup registers. · TrustZone support:
Tamper secure or non-secure configuration Backup registers configuration in three configurable-size areas:
. one read/write secure area . one write secure/read non-secure area . one read/write non-secure area · Monotonic counter

3.30

Inter-integrated circuit interfaces (I2C1, I2C2, I2C3, I2C4, I2C5)
The devices embed five I2C interfaces.
The I2C bus interface handles communications between the STM32MP133C/F and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.

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The I2C peripheral supports: · I2C-bus specification and user manual rev. 5 compatibility:
Slave and master modes, multimaster capability Standard-mode (Sm), with a bitrate up to 100 kbit/s Fast-mode (Fm), with a bitrate up to 400 kbit/s Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses Programmable setup and hold times Optional clock stretching · System management bus (SMBus) specification rev 2.0 compatibility: Hardware PEC (packet error checking) generation and verification with ACK
control Address resolution protocol (ARP) support SMBus alert · Power system management protocol (PMBusTM) specification rev 1.1 compatibility · Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming · Wakeup from Stop mode on address match · Programmable analog and digital noise filters · 1-byte buffer with DMA capability
I2C3, I2C4 and I2C5 can be defined (in ETZPC) as accessible by secure software only.

3.31

Universal synchronous asynchronous receiver transmitter (USART1, USART2, USART3, USART6 and UART4, UART5, UART7, UART8)
The devices have four embedded universal synchronous receiver transmitters (USART1, USART2, USART3 and USART6) and four universal asynchronous receiver transmitters (UART4, UART5, UART7 and UART8). Refer to the table below for a summary of USARTx and UARTx features.
These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN master/slave capability. They provide hardware management of the CTS and RTS signals, and RS485 Driver Enable. They are able to communicate at speeds of up to 13 Mbit/s.
USART1, USART2, USART3 and USART6 also provide Smartcard mode (ISO 7816 compliant) and SPI-like communication capability.
All USART have a clock domain independent from the CPU clock, allowing the USARTx to wake up the STM32MP133C/F from Stop mode using baudrates up to 200 Kbaud.The wakeup events from Stop mode are programmable and can be:
· start bit detection
· any received data frame
· a specific programmed data frame

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Ĉiuj USART-interfacoj povas esti servataj de la DMA-regilo.

Table 5. USART/UART features

USART modes/features(1)

USART1/2/3/6

UART4/5/7/8

Aparatara fluokontrolo por modemo

Kontinua komunikado per DMA

Plurprocesora komunikado

Synchronous SPI mode (master/slave)

–

Reĝimo de inteligenta karto

–

Single-wire half-duplex communication IrDA SIR ENDEC block

LIN-reĝimo

Dual clock domain and wakeup from low power mode

Receiver timeout interrupt Modbus communication

Aŭtomata baud-indika detekto

Ŝoforo Ebligi

USART data length

7, 8 and 9 bits

1. X = supported.

USART1 and USART2 can be defined (in ETZPC) as accessible by secure software only.

3.32

Serial peripheral interfaces (SPI1, SPI2, SPI3, SPI4, SPI5) inter- integrated sound interfaces (I2S1, I2S2, I2S3, I2S4)
The devices feature up to five SPIs (SPI2S1, SPI2S2, SPI2S3, SPI2S4, and SPI5) that allow communication at up to 50 Mbit/s in master and slave modes, in half-duplex, fullduplex and simplex modes. The 3-bit prescaler gives eight master mode frequencies and the frame is configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI mode, hardware CRC calculation and multiply of 8-bit embedded Rx and Tx FIFOs with DMA capability.
I2S1, I2S2, I2S3, and I2S4 are multiplexed with SPI1, SPI2, SPI3 and SPI4. They can be operated in master or slave mode, in full-duplex and half-duplex communication modes, and can be configured to operate with a 16- or 32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. All I2S interfaces support multiply of 8-bit embedded Rx and Tx FIFOs with DMA capability.
SPI4 and SPI5 can be defined (in ETZPC) as accessible by secure software only.

3.33

Serial audio interfaces (SAI1, SAI2)
The devices embed two SAIs that allow the design of many stereo or mono audio protocols

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such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An SPDIF output is available when the audio block is configured as a transmitter. To bring this level of flexibility and reconfigurability, each SAI contains two independent audio sub-blocks. Each block has it own clock generator and I/O line controller. Audio sampling frequencies up to 192 kHz are supported. In addition, up to eight microphones can be supported thanks to an embedded PDM interface. The SAI can work in master or slave configuration. The audio sub-blocks can be either receiver or transmitter and can work synchronously or asynchronously (with respect to the other one). The SAI can be connected with other SAIs to work synchronously.

3.34

SPDIF receiver interface (SPDIFRX)
The SPDIFRX is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. These standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up to 5.1).
The SPDIFRX main features are the following: · Up to four inputs available · Automatic symbol rate detection · Maximum symbol rate: 12.288 MHz · Stereo stream from 32 to 192 kHz supported · Support of audio IEC-60958 and IEC-61937, consumer applications · Parity bit management · Communication using DMA for audio samples · Communication using DMA for control and user channel information · Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and decode the incoming data stream. The user can select the wanted SPDIF input, and when a valid signal is available, the SPDIFRX re-samples the incoming signal, decodes the Manchester stream, and recognizes frames, sub-frames and blocks elements. The SPDIFRX delivers to the CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, that toggles at the S/PDIF sub-frame rate that is used to compute the exact sample rate for clock drift algorithms.

3.35

Secure digital input/output MultiMediaCard interfaces (SDMMC1, SDMMC2)
Two secure digital input/output MultiMediaCard interfaces (SDMMC) provide an interface between the AHB bus and SD memory cards, SDIO cards and MMC devices.
The SDMMC features include the following: · Compliance with Embedded MultiMediaCard System Specification Version 5.1
Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit

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(HS200 SDMMC_CK speed limited to maximum allowed I/O speed)(HS400 is not supported)
· Full compatibility with previous versions of MultiMediaCards (backward compatibility)
· Full compliance with SD memory card specifications version 4.1 (SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and UHS-II mode not supported)
· Full compliance with SDIO card specification version 4.0 Card support for two different databus modes: 1-bit (default) and 4-bit (SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and UHS-II mode not supported)
· Data transfer up to 208 Mbyte/s for the 8-bit mode (depending maximum allowed I/O speed)
· Data and command output enable signals to control external bidirectional drivers
· Dedicated DMA controller embedded in the SDMMC host interface, allowing high-speed transfers between the interface and the SRAM
· IDMA linked list support
· Dedicated power supplies, VDDSD1 and VDDSD2 for SDMMC1 and SDMMC2 respectively, removing the need for level-shifter insertion on the SD card interface in UHS-I mode
Only some GPIOs for SDMMC1 and SDMMC2 are available on a dedicated VDDSD1 or VDDSD2 supply pin. Those are part of the default boot GPIOs for SDMMC1 and SDMMC2 (SDMMC1: PC[12:8], PD[2], SDMMC2: PB[15,14,4,3], PE3, PG6). They can be identified in the alternate function table by signals with a “_VSD1” or “_VSD2” suffix.
Each SDMMC is coupled with a delay block (DLYBSD) allowing support of an external data frequency above 100 MHz.
Both SDMMC interfaces have securable configuration ports.

3.36

Controller area network (FDCAN1, FDCAN2)
The controller area network (CAN) subsystem consists of two CAN modules, a shared message RAM memory and a clock calibration unit.
Both CAN modules (FDCAN1 and FDCAN2) are compliant with ISO 11898-1 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.
A 10-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers, transmit event FIFOs and transmit buffers (plus triggers for TTCAN). This message RAM is shared between the two FDCAN1 and FDCAN2 modules.
The common clock calibration unit is optional. It can be used to generate a calibrated clock for both FDCAN1 and FDCAN2 from the HSI internal RC oscillator and the PLL, by evaluating CAN messages received by the FDCAN1.

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3.37

Universal serial bus high-speed host (USBH)
The devices embed one USB high-speed host (up to 480 Mbit/s) with two physical ports. USBH supports both low, full-speed (OHCI) as well as high-speed (EHCI) operations independently on each port. It integrates two transceivers that can be used for either low-speed (1.2 Mbit/s), full-speed (12 Mbit/s) or high-speed operation (480 Mbit/s). The second high-speed transceiver is shared with OTG high-speed.
The USBH is compliant with the USB 2.0 specification. The USBH controllers require dedicated clocks that are generated by a PLL inside the USB high-speed PHY.

3.38

USB on-the-go high-speed (OTG)
The devices embed one USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral. OTG supports both full-speed and high-speed operations. The transceiver for high-speed operation (480 Mbit/s) is shared with the USB Host second port.
The USB OTG HS is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controllers require a dedicated 48 MHz clock that is generated by a PLL inside RCC or inside the USB high-speed PHY.
The USB OTG HS main features are listed below: · Combined Rx and Tx FIFO size of 4 Kbyte with dynamic FIFO sizing · SRP (session request protocol) and HNP (host negotiation protocol) support · Eight bidirectional endpoints · 16 host channels with periodic OUT support · Software configurable to OTG1.3 and OTG2.0 modes of operation · USB 2.0 LPM (link power management) support · Battery charging specification revision 1.2 support · HS OTG PHY support · Internal USB DMA · HNP/SNP/IP inside (no need for any external resistor) · For OTG/Host modes, a power switch is needed in case bus-powered devices are
konektita.
The USB OTG configuration port can be secure.

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3.39

Gigabit Ethernet MAC interfaces (ETH1, ETH2)
The devices provide two IEEE-802.3-2002-compliant gigabit media access controllers (GMAC) for Ethernet LAN communications through an industry-standard medium-independent interface (MII), a reduced medium-independent interface (RMII), or a reduced gigabit medium-independent interface (RGMII).
The devices require an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is connected to the device port using 17 signals for MII, 7 signals for RMII, or 13 signals for RGMII, and can be clocked using the 25 MHz (MII, RMII, RGMII) or 125 MHz (RGMII) from the STM32MP133C/F or from the PHY.
The devices include the following features: · Operation modes and PHY interfaces
10-, 100-, and 1000-Mbit/s data transfer rates Support of both full-duplex and half-duplex operations MII, RMII and RGMII PHY interfaces · Processing control Multi-layer Packet filtering: MAC filtering on source (SA) and destination (DA)
address with perfect and hash filter, VLAN tag-based filtering with perfect and hash filter, Layer 3 filtering on IP source (SA) or destination (DA) address, Layer 4 filtering on source (SP) or destination (DP) port Double VLAN processing: insertion of up to two VLAN tags in transmit path, tag filtering in receive path IEEE 1588-2008/PTPv2 support Supports network statistics with RMON/MIB counters (RFC2819/RFC2665) · Hardware offload processing Preamble and start-of-frame data (SFD) insertion or deletion Integrity checksum offload engine for IP header and TCP/UDP/ICMP payload: transmit checksum calculation and insertion, receive checksum calculation and comparison Automatic ARP request response with the device MAC address TCP segmentation: automatic split of large transmit TCP packet into multiple small packets · Low-power mode Energy efficient Ethernet (standard IEEE 802.3az-2010) Remote wakeup packet and AMD Magic PacketTM detection
Both ETH1 and ETH2 can be programmed as secure. When secure, transactions over the AXI interface are secure, and the configuration registers can only be modified by secure accesses.

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3.40

Debug infrastructure
The devices offer the following debug and trace features to support software development and system integration: · Breakpoint debugging · Code execution tracing · Software instrumentation · JTAG debug port · Serial-wire debug port · Trigger input and output · Trace port · Arm CoreSight debug and trace components
The debug can be controlled via a JTAG/serial-wire debug access port, using industry standard debugging tools.
A trace port allows data to be captured for logging and analysis.
A debug access to secure areas is enabled by the authentication signals in the BSEC.

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Pinout, pin description and alternate functions

Figure 5. STM32MP133C/F LFBGA289 ballout

VSS

PA9

PD10

PB7

PE7

PD5

PE8

PG4

PH9

PH13

PC7

PB9

PB14

PG6

PD2

PC9

VSS

PD3

PF5

PD14

PE12

PE1

PE9

PH14

PE10

PF1

PF3

PC6

PB15

PB4

PC10

PC12

DDR_DQ4 DDR_DQ0

PB6

PH12

PE14

PE13

PD8

PD12

PD15

VSS

PG7

PB5

PB3

VDDSD1

PF0

PC11

DDR_DQ1

DDR_ DQS0N

DDR_ DQS0P

PB8

PD6

VSS

PE11

PD1

PE0

PG0

PE15

PB12

PB10

VDDSD2

VSS

PE3

PC8

DDR_ DQM0

DDR_DQ5 DDR_DQ3

PG9

PD11

PA12

PD0

VSS

PA15

PD4

PD9

PF2

PB13

PH10

VDDQ_ DDR

DDR_DQ2 DDR_DQ6 DDR_DQ7 DDR_A5

DDR_ RESETN

PG10

PG5

PG8

PH2

PH8

VDDCPU

VDD

VDDCPU VDDCPU

VDD

VDDQ_ DDR

VSS

DDR_A13

VSS

DDR_A9

DDR_A2

PF9

PF6

PF10

PG15

PF8

VDD

VSS

VDDQ_ DDR

DDR_BA2 DDR_A7

DDR_A3

DDR_A0 DDR_BA0

PH11

PI3

PH7

PB2

PE4

VDDCPU

VSS

VDDCORE VDDCORE VDDCORE

VSS

VDDQ_ DDR

DDR_WEN

VSS

DDR_ODT DDR_CSN

DDR_ RASN

PD13

VBAT

PI2

VSS_PLL VDD_PLL VDDCPU

VSS

VDDCORE

VSS

VDDCORE

VSS

VDDQ_ DDR

VDDCORE DDR_A10

DDR_ CASN

DDR_ CLKP

DDR_ CLKN

PC14OSC32_IN

PC15OSC32_
EKSTER

VSS

PC13

PI1

VDD

VSS

VDDCORE VDDCORE VDDCORE

VSS

VDDQ_ DDR

DDR_A11 DDR_CKE DDR_A1 DDR_A15 DDR_A12

PE2

PF4

PH6

PI0

PG3

VDD

VSS

VDDQ_ DDR

DDR_ATO

DDR_ DTO0

DDR_A8 DDR_BA1 DDR_A14

PF7

PA8

PG11

VDD_ANA VSS_ANA

VDD

VDDQ_ DDR

DDR_ VREF

DDR_A4

VSS

DDR_ DTO1

DDR_A6

PE6

PG1

PD7

VSS

PB11

PF13

VSSA

PA3

NJTRST

VSS_USB VDDA1V1_

REG

VDDQ_ DDR

PWR_LP

DDR_ DQM1

DDR_ DQ10

DDR_DQ8 DDR_ZQ

PH0OSC_IN

PH1OSC_OUT

PA13

PF14

PA2

VREF-

VDDA

PG13

PG14

VDD3V3_ USBHS

VSS

PI5-BOOT1 VSS_PLL2 PWR_ON

DDR_ DQ11

DDR_ DQ13

DDR_DQ9

PG2

PH3

PWR_CPU _ON

PA1

VSS

VREF+

PC5

VSS

VDD

PF15

VDDA1V8_ REG

PI6-BOOT2

VDD_PLL2

PH5

DDR_ DQ12

DDR_ DQS1N

DDR_ DQS1P

PG12

PA11

PC0

PF12

PC3

PF11

PB1

PA6

PE5

PDR_ON USB_DP2

PA14

USB_DP1

BYPASS_ REG1V8

PH4

DDR_ DQ15

DDR_ DQ14

VSS

PA7

PA0

PA5

PA4

PC4

PB0

PC1

PC2

NRST

USB_DM2

USB_ RREF

USB_DM1 PI4-BOOT0

PA10

PI7

VSS

MSv65067V5

The above figure shows the package top view.

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STM32MP133C/F

Figure 6. STM32MP133C/F TFBGA289 ballout

VSS

PD4

PE9

PG0

PD15

PE15

PB12

PF1

PC7

PC6

PF0

PB14

VDDSD2 VDDSD1 DDR_DQ4 DDR_DQ0

VSS

PE12

PD8

PE0

PD5

PD9

PH14

PF2

VSS

PF3

PB13

PB3

PE3

PC12

VSS

DDR_DQ1

DDR_ DQS0N

DDR_ DQS0P

PE13

PD1

PE1

PE7

VSS

VDD

PE10

PG7

PG4

PB9

PH10

PC11

PC8

DDR_DQ2

DDR_ DQM0

DDR_DQ3 DDR_DQ5

PF5

PA9

PD10

VDDCPU

PB7

VDDCPU

PD12

VDDCPU

PH9

VDD

PB15

VDD

VSS

VDDQ_ DDR

DDR_ RESETN

DDR_DQ7 DDR_DQ6

PD0

PE14

VSS

PE11

VDDCPU

VSS

PA15

VSS

PH13

VSS

PB4

VSS

VDDQ_ DDR

VSS

VDDQ_ DDR

VSS

DDR_A13

PH8

PA12

VDD

VDDCPU

VSS

VDDCORE

PD14

PE8

PB5

VDDCORE

PC10

VDDCORE

VSS

VDDQ_ DDR

DDR_A7

DDR_A5

DDR_A9

PD11

PH2

PB6

PB8

PG9

PD3

PH12

PG15

PD6

PB10

PD2

PC9

DDR_A2 DDR_BA2 DDR_A3

DDR_A0 DDR_ODT

PG5

PG10

PF8

VDDCPU

VSS

VDDCORE

PH11

PI3

PF9

PG6

BYPASS_ REG1V8

VDDCORE

VSS

VDDQ_ DDR

DDR_BA0 DDR_CSN DDR_WEN

J VDD_PLL VSS_PLL

PG8

PI2

VBAT

PH6

PF7

PA8

PF12

VDD

VDDA1V8_ REG

PA10

DDR_ VREF

DDR_ RASN

DDR_A10

VSS

DDR_ CASN

PE4

PF10

PB2

VDD

VSS

VDDCORE

PA13

PA1

PC4

NRST

VSS_PLL2 VDDCORE

VSS

VDDQ_ DDR

DDR_A15

DDR_ CLKP

DDR_ CLKN

PF6

VSS

PH7

VDD_ANA VSS_ANA

PG12

PA0

PF11

PE5

PF15

VDD_PLL2

PH5

DDR_CKE DDR_A12 DDR_A1 DDR_A11 DDR_A14

PC14OSC32_IN

PC15OSC32_
EKSTER

PC13

VDD

VSS

PB11

PA5

PB0

VDDCORE

USB_ RREF

PI6-BOOT2 VDDCORE

VSS

VDDQ_ DDR

DDR_A6

DDR_A8 DDR_BA1

PD13

VSS

PI0

PI1

PA11

VSS

PA4

PB1

VSS

PI5-BOOT1

VSS

VDDQ_ DDR

VSS

VDDQ_ DDR

VSS

DDR_ATO

PH0OSC_IN

PH1OSC_OUT

PF4

PG1

VSS

VDD

PC3

PC5

VDD

PI4-BOOT0

VDD

VSS

VDDQ_ DDR

DDR_A4 DDR_ZQ DDR_DQ8

PG11

PE6

PD7

PWR_ CPU_ON

PA2

PA7

PC1

PA6

PG13

NJTRST

PA14

VSS

PWR_ON

DDR_ DQM1

DDR_ DQ12

DDR_ DQ11

DDR_DQ9

PE2

PH3

PF13

PC0

VSSA

VREF-

PA3

PG14

USB_DP2

VSS

VSS_ USBHS

USB_DP1

PH4

DDR_ DQ13

DDR_ DQ14

DDR_ DQS1P

DDR_ DQS1N

VSS

PG3

PG2

PF14

VDDA

VREF+

PDR_ON

PC2

USB_DM2

VDDA1V1_ REG

VDD3V3_ USBHS

USB_DM1

PI7

The above figure shows the package top view.

PWR_LP

DDR_ DQ15

DDR_ DQ10

VSS

MSv67512V3

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Figure 7. STM32MP133C/F TFBGA320 ballout
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

VSS

PA9

PE13 PE12

PD12

PG0

PE15

PG7

PH13

PF3

PB9

PF0

PC10 PC12

PC9

VSS

PD0

PE11

PF5

PA15

PD8

PE0

PE9

PH14

PE8

PG4

PF1

VSS

PB5

PC6

PB15 PB14

PE3

PC11

DDR_ DQ4

DDR_ DQ1

DDR_ DQ0

PB6

PD3

PE14 PD14

PD1

PB7

PD4

PD5

PD9

PE10 PB12

PH9

PC7

PB3

VDD SD2

PB4

PG6

PC8

PD2

DDR_ DDR_ DQS0P DQS0N

PB8

PD6

PH12

PD10

PE7

PF2

PB13

VSS

DDR_ DQ2

DDR_ DQ5

DDR_ DQM0

PH2

PH8

VSS

VDD CPU

PE1

PD15

VDD CPU

VSS

VDD

PB10

PH10

VDDQ_ DDR

VSS

VDD SD1

DDR_ DQ3

DDR_ DQ6

PF8

PG9

PD11 PA12

VSS

DDR_ DQ7

DDR_ A5

VSS

PF6

PG10

PG5

VDD CPU

PE4

PF10 PG15

PG8

PH7

PD13

PB2

PF9

VDD CPU

VSS

VDD

VDD CPU

VDD CORE

VSS

VDD

VSS

VDDQ_ DDR

VSS

VDD

VSS

VDD CORE

VSS

VDD

VDD CORE

VDDQ_ DDR

DDR_ A13

DDR_ A2

DDR_ A9

DDR_ RESET
N

DDR_ BA2

DDR_ A3

DDR_ A0

DDR_ A7

DDR_ BA0

DDR_ CSN

DDR_ ODT

VSS_ PLL

VDD_ PLL

PH11

VDD CPU

PC15-

VBAT OSC32 PI3

VSS

_EKSTER

PC14-

VSS OSC32 PC13

_EN

VDD

PE2

PF4

PH6

PI2

VDD CPU
VDD CORE
VSS
VDD

VSS

VDD CORE

VSS

VDD CORE

VSS

VDD

VDD CORE

VSS

VDD

VDD CORE

VDDQ_ DDR
VSS
VDDQ_ DDR
VDD CORE

VDDQ_ DDR

DDR_ WEN

DDR_ RASN

VSS

DDR_ A10

DDR_ CASN

DDR_ CLKN

VDDQ_ DDR

DDR_ A12

DDR_ CLKP

DDR_ A15

DDR_ A11

DDR_ A14

DDR_ CKE

DDR_ A1

PA8

PF7

PI1

PI0

VSS

DDR_ DTO1

DDR_ ATO

DDR_ A8

DDR_ BA1

PG1

PG11

PH3

VDD

VSS

VDD

VDD CORE

VSS

VDD

VDD CORE

VSS

VDDQ_ DDR

DDR_ A4

DDR_ ZQ

DDR_ A6

VSS

PE6

PH0OSC_IN

PA13

VSS

DDR_ VREF

DDR_ DQ10

DDR_ DQ8

VSS

PH1OSC_ OUT

VSS_ ANA

VSS

VDD

VDDA VSSA

PA6

VSS

VDD CORE

VSS

VDD VDDQ_ CORE DDR

VSS

PWR_ ON

DDR_ DQ13

DDR_ DQ9

PD7

VDD_ ANA

PG2

PA7

VREF-

NJ TRST

VDDA1 V1_ REG

VSS

PWR_ DDR_ DDR_ LP DQS1P DQS1N

PWR_

PG3

PG12 CPU_ PF13

PC0

PC3 VREF+ PB0

PA3

PE5

VDD

USB_ RREF

PA14

VDD 3V3_ USBHS

VDDA1 V8_ REG

VSS

BYPAS S_REG
1V8

PH5

DDR_ DQ12

DDR_ DQ11

DDR_ DQM1

PA11

PF14

PA0

PA2

PA5

PF11

PC4

PB1

PC1

PG14

NRST

PF15

USB_ VSS_

PI6-

USB_

PI4-

VDD_

DM2 USBHS BOOT2 DP1 BOOT0 PLL2

PH4

DDR_ DQ15

DDR_ DQ14

VSS

PB11

PA1

PF12

PA4

PC5

PG13

PC2

PDR_ ON

USB_ DP2

PI5-

USB_

BOOT1 DM1

VSS_ PLL2

PA10

PI7

VSS

The above figure shows the package top view.

MSv65068V5

DS13875 Rev 5

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97

Pinout, pin description and alternate functions

STM32MP133C/F

Tabelo 6. Legendo / mallongigoj uzataj en la aldona tabelo

Nomo

Mallongigo

Difino

Pin name Pin type
I / O-strukturo
Notes Alternate functions Additional functions

Unless otherwise specified, the pin function during and after reset is the same as the actual pin name

Proviza pinglo

Enigu nur pinglo

Eligo nur pinglo

I/O

Eniga/eliga pinglo

Analog or special level pin

FT(U/D/PD) 5 V tolerant I/O (with fixed pull-up / pull-down / programmable pull-down)

DDR

1.5 V, 1.35 V or 1.2 V I/O for DDR3, DDR3L, LPDDR2/LPDDR3 interface

Analoga signalo

RST

Reset pin with weak pull-up resistor

_f(1) _a(2) _u(3) _h(4)

Option for FT I/Os I2C FM+ option Analog option (supplied by VDDA for the analog part of the I/O) USB option (supplied by VDD3V3_USBxx for the USB part of the I/O) High-speed output for 1.8V typ. VDD (for SPI, SDMMC, QUADSPI, TRACE)

_vh(5)

Very-high-speed option for 1.8V typ. VDD (for ETH, SPI, SDMMC, QUADSPI, TRACE)

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset

Functions selected through GPIOx_AFR registers

Functions directly selected/enabled through peripheral registers

1. The related I/O structures in Table 7 are: FT_f, FT_fh, FT_fvh 2. The related I/O structures in Table 7 are: FT_a, FT_ha, FT_vha 3. The related I/O structures in Table 7 are: FT_u 4. The related I/O structures in Table 7 are: FT_h, FT_fh, FT_fvh, FT_vh, FT_ha, FT_vha 5. The related I/O structures in Table 7 are: FT_vh, FT_vha, FT_fvh

52/219

DS13875 Rev 5

STM32MP133C/F

Pinout, pin description and alternate functions

Pinnumero

Table 7. STM32MP133C/F ball definitions

Ball functions

Pin name (function after
restarigi)

Alternaj funkcioj

Pliaj funkcioj

LFBGA289 TFBGA289 TFBGA320
Pin type I/O structure
Notoj

K10 F6 U14 A2 D2 A2 A1 A1 T5 M6 F3 U7
D4 E4 B2
B2 D1 B3 B1 G6 C2
C3 E2 C3 F6 D4 E7 E4 E1 B1
C2 G7 D3
C1 G3 C1

VDDCORE S

–

PA9

I/O FT_h

VSS VDD

–

PE11

I/O FT_vh

PF5

I/O FT_h

PD3

I/O FT_f

PE14

I/O FT_h

VDDCPU

–

PD0

I/O FT

PH12

I/O FT_fh

PB6

I/O FT_h

–

TIM1_CH2, I2C3_SMBA,

–

DFSDM1_DATIN0, USART1_TX, UART4_TX,

FMC_NWAIT(boot)

–

TIM1_CH2,

USART2_CTS/USART2_NSS,

SAI1_D2,

–

SPI4_MOSI/I2S4_SDO, SAI1_FS_A, USART6_CK,

ETH2_MII_TX_ER,

ETH1_MII_TX_ER,

FMC_D8(boot)/FMC_AD8

–

TRACED12, DFSDM1_CKIN0, I2C1_SMBA, FMC_A5

TIM2_CH1,

–

USART2_CTS/USART2_NSS, DFSDM1_CKOUT, I2C1_SDA,

SAI1_D3, FMC_CLK

TIM1_BKIN, SAI1_D4,

UART8_RTS/UART8_DE,

–

QUADSPI_BK1_NCS,

QUADSPI_BK2_IO2,

FMC_D11(boot)/FMC_AD11

–

SAI1_MCLK_A, SAI1_CK1,

–

FDCAN1_RX,

FMC_D2(boot)/FMC_AD2

USART2_TX, TIM5_CH3,

DFSDM1_CKIN1, I2C3_SCL,

–

SPI5_MOSI, SAI1_SCK_A, QUADSPI_BK2_IO2,

SAI1_CK2, ETH1_MII_CRS,

FMC_A6

TRACED6, TIM16_CH1N,

TIM4_CH1, TIM8_CH1,

–

USART1_TX, SAI1_CK2, QUADSPI_BK1_NCS,

ETH2_MDIO, FMC_NE3,

HDP6

–
–
–
TAMP_IN6 –
–
–

DS13875 Rev 5

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97

Pinout, pin description and alternate functions

STM32MP133C/F

Pinnumero

Table 7. STM32MP133C/F ball definitions (continued)

Ball functions

Pin name (function after
restarigi)

Alternaj funkcioj

Pliaj funkcioj

LFBGA289 TFBGA289 TFBGA320
Pin type I/O structure
Notoj

A17 A17 T17 M7 – J13 D2 G9 D2 F5 F1 E3 D1 G4 D1
E3 F2 F4 F8 D6 E10 F4 G2 E2 C8 B8 T21 E2 G1 F3
E1 G5 F2 G5 H3 F1 M8 – M5

VSS VDD PD6 PH8 PB8
PA12 VDDCPU
PH2 VSS PD11
PG9 PF8 VDD

–

I/O FT

I/O FT_fh

I/O FT_f

I/O FT_h

–

I/O FT_h

–

I/O FT_h

I/O FT_f

I/O FT_h

–

TIM16_CH1N, SAI1_D1, SAI1_SD_A, UART4_TX(boot)

TRACED9, TIM5_ETR,

–

USART2_RX, I2C3_SDA,

FMC_A8, HDP2

TIM16_CH1, TIM4_CH3,

I2C1_SCL, I2C3_SCL,

–

DFSDM1_DATIN1,

UART4_RX, SAI1_D1,

FMC_D13(boot)/FMC_AD13

TIM1_ETR, SAI2_MCLK_A,

USART1_RTS/USART1_DE,

–

ETH2_MII_RX_DV/ETH2_

RGMII_RX_CTL/ETH2_RMII_

CRS_DV, FMC_A7

–

LPTIM1_IN2, UART7_TX,

QUADSPI_BK2_IO0(boot),

–

ETH2_MII_CRS,

ETH1_MII_CRS, FMC_NE4,

ETH2_RGMII_CLK125

–

LPTIM2_IN2, I2C4_SMBA,

USART3_CTS/USART3_NSS,

SPDIFRX_IN0,

–

QUADSPI_BK1_IO2,

ETH2_RGMII_CLK125,

FMC_CLE(boot)/FMC_A16,

UART7_RX

DBTRGO, I2C2_SDA,

–

USART6_RX, SPDIFRX_IN3, FDCAN1_RX, FMC_NE2,

FMC_NCE(boot)

TIM16_CH1N, TIM4_CH3,

–

TIM8_CH3, SAI1_SCK_B, USART6_TX, TIM13_CH1,

QUADSPI_BK1_IO0(boot)

–

–
–
WKUP1
–

54/219

DS13875 Rev 5

STM32MP133C/F

Pinout, pin description and alternate functions

Pinnumero

Table 7. STM32MP133C/F ball definitions (continued)

Ball functions

Pin name (function after
restarigi)

Alternaj funkcioj

Pliaj funkcioj

LFBGA289 TFBGA289 TFBGA320
Pin type I/O structure
Notoj

F3 J3 H5
F9 D8 G5 F2 H1 G3 G4 G8 H4
F1 H2 G2 D3 B14 U5 G3 K2 H3 H8 F10 G2 L1 G1 D12 C5 U6 M9 K4 N7 G1 H9 J5

PG8

I/O FT_h

VDDCPU PG5

–

I/O FT_h

PG15

I/O FT_h

PG10

I/O FT_h

VSS

–

PF10

I/O FT_h

VDDCORE S

–

PF6

I/O FT_vh

VSS VDD

–

PF9

I/O FT_h

TIM2_CH1, TIM8_ETR,

SPI5_MISO, SAI1_MCLK_B,

USART3_RTS/USART3_DE,

–

SPDIFRX_IN2,

QUADSPI_BK2_IO2,

QUADSPI_BK1_IO3,

FMC_NE2, ETH2_CLK

–

TIM17_CH1, ETH2_MDC, FMC_A15

USART6_CTS/USART6_NSS,

–

UART7_CTS, QUADSPI_BK1_IO1,

ETH2_PHY_INTN

SPI5_SCK, SAI1_SD_B,

–

UART8_CTS, FDCAN1_TX, QUADSPI_BK2_IO1(boot),

FMC_NE3

–

TIM16_BKIN, SAI1_D3, TIM8_BKIN, SPI5_NSS, – USART6_RTS/USART6_DE, UART7_RTS/UART7_DE,
QUADSPI_CLK(boot)

–

TIM16_CH1, SPI5_NSS,

UART7_RX(boot),

–

QUADSPI_BK1_IO2, ETH2_MII_TX_EN/ETH2_

RGMII_TX_CTL/ETH2_RMII_

TX_EN

–

TIM17_CH1N, TIM1_CH1,

DFSDM1_CKIN3, SAI1_D4,

–

UART7_CTS, UART8_RX, TIM14_CH1,

QUADSPI_BK1_IO1(boot),

QUADSPI_BK2_IO3, FMC_A9

TAMP_IN4
–
TAMP_IN1 –

DS13875 Rev 5

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97

Pinout, pin description and alternate functions

STM32MP133C/F

Pinnumero

Table 7. STM32MP133C/F ball definitions (continued)

Ball functions

Pin name (function after
restarigi)

Alternaj funkcioj

Pliaj funkcioj

LFBGA289 TFBGA289 TFBGA320
Pin type I/O structure
Notoj

H5 K1 H2 H6 E5 G7 H4 K3 J3 E5 D13 U11 H3 L3 J1
H1 H7 K3
J1 N1 J2 J5 J1 K2 J4 J2 K1 H2 H8 L4 K4 M3 M3

PE4 VDDCPU
PB2 VSS PH7
PH11
PD13 VDD_PLL VSS_PLL
PI3 PC13

I/O FT_h

–

I/O FT_h

–

I/O FT_fh

I/O FT_h

–

I/O FT

SPI5_MISO, SAI1_D2,

DFSDM1_DATIN3,

TIM15_CH1N, I2S_CKIN,

–

SAI1_FS_A, UART7_RTS/UART7_DE,

–

UART8_TX,

QUADSPI_BK2_NCS,

FMC_NCE2, FMC_A25

–

RTC_OUT2, SAI1_D1,

I2S_CKIN, SAI1_SD_A,

–

UART4_RX,

QUADSPI_BK1_NCS(boot),

ETH2_MDIO, FMC_A6

TAMP_IN7

–

SAI2_FS_B, I2C3_SDA,

SPI5_SCK,

–

QUADSPI_BK2_IO3, ETH2_MII_TX_CLK,

–

ETH1_MII_TX_CLK,

QUADSPI_BK1_IO3

SPI5_NSS, TIM5_CH2,

SAI2_SD_A,

SPI2_NSS/I2S2_WS,

–

I2C4_SCL, USART6_RX, QUADSPI_BK2_IO0,

–

ETH2_MII_RX_CLK/ETH2_

RGMII_RX_CLK/ETH2_RMII_

REF_CLK, FMC_A12

LPTIM2_ETR, TIM4_CH2,

TIM8_CH2, SAI1_CK1,

–

SAI1_MCLK_A, USART1_RX, QUADSPI_BK1_IO3,

–

QUADSPI_BK2_IO2,

FMC_A18

–

(1)

SPDIFRX_IN3,

TAMP_IN4/TAMP_

ETH1_MII_RX_ER

OUT5, WKUP2

RTC_OUT1/RTC_TS/

(1)

–

RTC_LSCO, TAMP_IN1/TAMP_

OUT2, WKUP3

56/219

DS13875 Rev 5

STM32MP133C/F

Pinout, pin description and alternate functions

Pinnumero

Table 7. STM32MP133C/F ball definitions (continued)

Ball functions

Pin name (function after
restarigi)

Alternaj funkcioj

Pliaj funkcioj

LFBGA289 TFBGA289 TFBGA320
Pin type I/O structure
Notoj

J3 J4 N5

PI2

I/O FT

(1)

SPDIFRX_IN2

TAMP_IN3/TAMP_ OUT4, WKUP5

K5 N4 P4

PI1

I/O FT

(1)

SPDIFRX_IN1

RTC_OUT2/RTC_ LSCO,
TAMP_IN2/TAMP_ OUT3, WKUP4

F13 L2 U13

VSS

–

J2 J5 L2

VBAT

–

L4 N3 P5

PI0

I/O FT

(1)

SPDIFRX_IN0

TAMP_IN8/TAMP_ OUT1

K2 M2

PC15OSC32_OUT

I/O

(1)

–

OSC32_OUT

F15 N2 U16

VSS

–

K1 M1 M2

PC14OSC32_IN

I/O

(1)

–

OSC32_IN

G7 E3 V16

VSS

–

H9 K6 N15 VDDCORE S

–

M10 M4 N9

VDD

–

G8 E6 W16

VSS

–

USART2_RX,

L2 P3 N2

PF4

I/O FT_h

–

ETH2_MII_RXD0/ETH2_ RGMII_RXD0/ETH2_RMII_

–

RXD0, FMC_A4

MCO1, SAI2_MCLK_A,

TIM8_BKIN2, I2C4_SDA,

SPI5_MISO, SAI2_CK1,

M2 J8 P2

PA8

I/O FT_fh –

USART1_CK, SPI2_MOSI/I2S2_SDO,

–

OTG_HS_SOF,

ETH2_MII_RXD3/ETH2_

RGMII_RXD3, FMC_A21

TRACECLK, TIM2_ETR,

I2C4_SCL, SPI5_MOSI,

SAI1_FS_B,

L1 T1 N1

PE2

I/O FT_fh

–

USART6_RTS/USART6_DE, SPDIFRX_IN1,

–

ETH2_MII_RXD1/ETH2_

RGMII_RXD1/ETH2_RMII_

RXD1, FMC_A23

DS13875 Rev 5

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97

Pinout, pin description and alternate functions

STM32MP133C/F

Pinnumero

Table 7. STM32MP133C/F ball definitions (continued)

Ball functions

Pin name (function after
restarigi)

Alternaj funkcioj

Pliaj funkcioj

LFBGA289 TFBGA289 TFBGA320
Pin type I/O structure
Notoj

M1 J7 P3

PF7

I/O FT_vh –

M3 R1 R2

PG11

I/O FT_vh –

L3 J6 N3

PH6

I/O FT_fh –

N2 P4 R1

PG1

I/O FT_vh –

M11 – N12

VDD

–

N1 R2 T2

PE6

I/O FT_vh –

P1 P1 T3 PH0-OSC_IN I/O FT

–

G9 U1 N11

VSS

–

P2 P2 U2 PH1-OSC_OUT I/O FT

–

R2 T2 R3

PH3

I/O FT_fh –

M5 L5 U3 VSS_ANA S

–

TIM17_CH1, UART7_TX(boot),
UART4_CTS, ETH1_RGMII_CLK125, ETH2_MII_TXD0/ETH2_ RGMII_TXD0/ETH2_RMII_
TXD0, FMC_A18
SAI2_D3, I2S2_MCK, USART3_TX, UART4_TX, ETH2_MII_TXD1/ETH2_ RGMII_TXD1/ETH2_RMII_
TXD1, FMC_A24
TIM12_CH1, USART2_CK, I2C5_SDA,
SPI2_SCK/I2S2_CK, QUADSPI_BK1_IO2,
ETH1_PHY_INTN, ETH1_MII_RX_ER, ETH2_MII_RXD2/ETH2_
RGMII_RXD2, QUADSPI_BK1_NCS
LPTIM1_ETR, TIM4_ETR, SAI2_FS_A, I2C2_SMBA,
SPI2_MISO/I2S2_SDI, SAI2_D2, FDCAN2_TX, ETH2_MII_TXD2/ETH2_ RGMII_TXD2, FMC_NBL0
–
MCO2, TIM1_BKIN2, SAI2_SCK_B, TIM15_CH2, I2C3_SMBA, SAI1_SCK_B, UART4_RTS/UART4_DE,
ETH2_MII_TXD3/ETH2_ RGMII_TXD3, FMC_A22
–
–
–
I2C3_SCL, SPI5_MOSI, QUADSPI_BK2_IO1, ETH1_MII_COL, ETH2_MII_COL, QUADSPI_BK1_IO0
–

–
–
–
OSC_IN OSC_OUT –

58/219

DS13875 Rev 5

STM32MP133C/F

Pinout, pin description and alternate functions

Pinnumero

Table 7. STM32MP133C/F ball definitions (continued)

Ball functions

Pin name (function after
restarigi)

Alternaj funkcioj

Pliaj funkcioj

LFBGA289 TFBGA289 TFBGA320
Pin type I/O structure
Notoj

L5 U2 W1

PG3

I/O FT_fvh –

TIM8_BKIN2, I2C2_SDA, SAI2_SD_B, FDCAN2_RX, ETH2_RGMII_GTX_CLK,
ETH1_MDIO, FMC_A13

M4 L4 V2 VDD_ANA S

–

R1 U3 V3

PG2

I/O FT

–

MCO2, TIM8_BKIN, SAI2_MCLK_B, ETH1_MDC

T1 L6 W2

PG12

I/O FT

LPTIM1_IN1, SAI2_SCK_A,

SAI2_CK2,

USART6_RTS/USART6_DE,

USART3_CTS,

–

ETH2_PHY_INTN,

ETH1_PHY_INTN,

ETH2_MII_RX_DV/ETH2_

RGMII_RX_CTL/ETH2_RMII_

CRS_DV

F7 P6 R5

VDD

–

G10 E8 T1

VSS

–

N3 R3 V1

MCO1, USART2_CK,

I2C2_SCL, I2C3_SDA,

SPDIFRX_IN0,

PD7

I/O FT_fh

–

ETH1_MII_RX_CLK/ETH1_ RGMII_RX_CLK/ETH1_RMII_

REF_CLK,

QUADSPI_BK1_IO2,

FMC_NE1

P3 K7 T4

PA13

I/O FT

–

DBTRGO, DBTRGI, MCO1, UART4_TX

R3 R4 W3 PWR_CPU_ON O FT

–

T2 N5 Y1

PA11

I/O FT_f

TIM1_CH4, I2C5_SCL,

SPI2_NSS/I2S2_WS,

USART1_CTS/USART1_NSS,

–

ETH2_MII_RXD1/ETH2_

RGMII_RXD1/ETH2_RMII_

RXD1, ETH1_CLK,

ETH2_CLK

N5 M6 AA2

PB11

TIM2_CH4, LPTIM1_OUT,

I2C5_SMBA, USART3_RX,

I/O FT_vh –

ETH1_MII_TX_EN/ETH1_

RGMII_TX_CTL/ETH1_RMII_

TX_EN

–
–
–
BOOTFAILN –
–

DS13875 Rev 5

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97

Pinout, pin description and alternate functions

STM32MP133C/F

Pinnumero

Table 7. STM32MP133C/F ball definitions (continued)

Ball functions

Pin name (function after
restarigi)

Alternaj funkcioj

Pliaj funkcioj

LFBGA289 TFBGA289 TFBGA320
Pin type I/O structure
Notoj

P4 U4

PF14(JTCK/SW CLK)

I/O

(2)

U3 L7 Y3

PA0

I/O FT_a –

JTCK/SWCLK
TIM2_CH1, TIM5_CH1, TIM8_ETR, TIM15_BKIN, SAI1_SD_B, UART5_TX,
ETH1_MII_CRS, ETH2_MII_CRS

N6 T3 W4

PF13

TIM2_ETR, SAI1_MCLK_B,

I/O FT_a –

DFSDM1_DATIN3,

USART2_TX, UART5_RX

G11 E10 P7

F10 -

–

R4 K8 AA3

P5 R5 Y4 U4 M7 Y5

VSS VDD PA1
PA2
PA5

–

I/O FT_a

I/O FT_a I/O FT_a

–

TIM2_CH2, TIM5_CH2, LPTIM3_OUT, TIM15_CH1N,
DFSDM1_CKIN0, – USART2_RTS/USART2_DE,
ETH1_MII_RX_CLK/ETH1_ RGMII_RX_CLK/ETH1_RMII_
REF_CLK

TIM2_CH3, TIM5_CH3, – LPTIM4_OUT, TIM15_CH1,
USART2_TX, ETH1_MDIO

TIM2_CH1/TIM2_ETR,

USART2_CK, TIM8_CH1N,

–

SAI1_D1, SPI1_NSS/I2S1_WS,

SAI1_SD_A, ETH1_PPS_OUT,

ETH2_PPS_OUT

T3 T4 W5

SAI1_SCK_A, SAI1_CK2,

PC0

I/O FT_ha –

I2S1_MCK, SPI1_MOSI/I2S1_SDO,

USART1_TX

T4 J9 AA4
R6 U6 W7 P7 U5 U8 P6 T6 V8

PF12

I/O FT_vha –

VREF+

–

VDDA

–

VREF-

–

SPI1_NSS/I2S1_WS, SAI1_SD_A, UART4_TX,
ETH1_MII_TX_ER, ETH1_RGMII_CLK125
–
–
–

–
ADC1_INP7, ADC1_INN3, ADC2_INP7, ADC2_INN3 ADC1_INP11, ADC1_INN10, ADC2_INP11, ADC2_INN10
–
ADC1_INP3, ADC2_INP3
ADC1_INP1, ADC2_INP1
ADC1_INP2
ADC1_INP0, ADC1_INN1, ADC2_INP0, ADC2_INN1, TAMP_IN3
ADC1_INP6, ADC1_INN2
–

60/219

DS13875 Rev 5

STM3

Dokumentoj/Rimedoj

STMicroelectronics STM32MP133C F 32-bit Arm Cortex-A7 1GHz MPU [pdf] Uzantogvidilo
STM32MP133C F 32-bit Arm Cortex-A7 1GHz MPU, STM32MP133C, F 32-bit Arm Cortex-A7 1GHz MPU, Arm Cortex-A7 1GHz MPU, 1GHz, MPU

Referencoj

Uzanto Manlibro

STMicroelectronics STM32MP133C F 32-bit Arm Cortex-A7 1GHz MPU

Specifoj

Arm Cortex-A7 Subsystem

Memoroj

DDR-regilo

Oftaj Demandoj

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