MICROCHIP PolarFire FPGA High Definition Multimedia Interface HDMI olugba
Ifaara (Beere ibeere kan)
Olugba IP Olugba-Definition Multimedia Interface (HDMI) ti Microchip ṣe atilẹyin data fidio ati gbigba data soso ohun ohun ti a sapejuwe ninu sipesifikesonu boṣewa HDMI. HDMI RX IP jẹ apẹrẹ pataki fun PolarFire® FPGA ati Eto PolarFire lori Chip (SoC) awọn ẹrọ FPGA ti n ṣe atilẹyin HDMI 2.0 fun awọn ipinnu to 1920 × 1080 ni 60 Hz ni ipo ẹbun kan ati titi di 3840 × 2160 ni 60 Hz ni ipo ẹbun mẹrin. RX IP ṣe atilẹyin Hot Plug Detect (HPD) fun mimojuto agbara tan tabi pa ati yọọ tabi pulọọgi awọn iṣẹlẹ lati tọka ibaraẹnisọrọ laarin orisun HDMI ati HDMI ifọwọ.
Orisun HDMI nlo ikanni Data Ifihan (DDC) lati ka Data Idanimọ Ifihan Afikun ti rii (EDID) lati ṣawari iṣeto ti Sink ati/tabi awọn agbara. HDMI RX IP ni EDID ti a ti ṣe tẹlẹ, eyiti orisun HDMI le ka nipasẹ ikanni I2C boṣewa kan. PolarFire FPGA ati PolarFire SoC FPGA ẹrọ transceivers ti wa ni lilo pẹlu RX IP lati deserialize data ni tẹlentẹle sinu 10-bit data. Awọn ikanni data ni HDMI gba ọ laaye lati ni akude skew laarin wọn. HDMI RX IP yọkuro skew laarin awọn ikanni data nipa lilo First-Ni First-Out (FIFOs). IP yii ṣe iyipada data Iyipada Iyatọ Iyatọ Iyatọ (TMDS) ti a gba lati orisun HDMI nipasẹ transceiver sinu data piksẹli 24-bit RGB, data ohun ohun 24-bit ati awọn ifihan agbara iṣakoso. Awọn ami iṣakoso boṣewa mẹrin ti a sọ pato ni Ilana HDMI ni a lo lati ṣe deede data data lakoko isọdọtun.
Lakotan
Tabili ti o tẹle n pese akopọ ti awọn abuda IP HDMI RX.
Table 1. HDMI RX IP Abuda
| Ẹya mojuto | Itọsọna olumulo yii ṣe atilẹyin HDMI RX IP v5.4. |
| Awọn idile Ẹrọ atilẹyin |
|
| Ti ṣe atilẹyin Sisan Irinṣẹ | Nilo Libero® SoC v12.0 tabi awọn idasilẹ nigbamii. |
| Awọn atọkun atilẹyin | Awọn atọkun atilẹyin nipasẹ HDMI RX IP jẹ:
|
| Iwe-aṣẹ | HDMI RX IP ti pese pẹlu awọn aṣayan iwe-aṣẹ meji wọnyi:
|
Awọn ẹya ara ẹrọ
HDMI RX IP ni awọn ẹya wọnyi:
- Ibamu fun HDMI 2.0
- Ṣe atilẹyin 8, 10, 12 ati 16 Bits Ijinle Awọ
- Ṣe atilẹyin Awọn ọna kika Awọ bii RGB, YUV 4: 2: 2 ati YUV 4: 4: 4
- Ṣe atilẹyin Awọn piksẹli Ọkan tabi Mẹrin Fun titẹ sii aago kan
- Ṣe atilẹyin Awọn ipinnu titi di 1920✕ 1080 ni 60 Hz ni Ipo Pixel Kan ati titi di 3840✕ 2160 ni 60 Hz ni ipo Pixel Mẹrin.
- Ṣe awari Gbona-Plug
- Ṣe atilẹyin Eto Iyipada koodu – TMDS
- Ṣe atilẹyin Input DVI
- Ṣe atilẹyin ikanni Data Ifihan (DDC) ati Imudara ikanni Data Ifihan (E-DDC)
- Ṣe atilẹyin Ilu abinibi ati Atọka Fidio ṣiṣan AXI4 fun Gbigbe Data Fidio
- Ṣe atilẹyin Ilu abinibi ati AXI4 Stream Audio Interface fun Gbigbe Data Audio
Awọn ẹya ara ẹrọ ti ko ni atilẹyin
Atẹle ni awọn ẹya ti ko ni atilẹyin ti HDMI RX IP:
- 4: 2: 0 awọ kika ko ni atilẹyin.
- Ibiti Yiyi to gaju (HDR) ati Idaabobo Akoonu oni-bandwidth giga (HDCP) ko ni atilẹyin.
- Oṣuwọn Isọdọtun Ayipada (VRR) ati Ipo Irẹlẹ Aifọwọyi Aifọwọyi (ALLM) ko ni atilẹyin.
- Awọn paramita akoko petele eyiti ko pin si mẹrin ni ipo Pixel Mẹrin ko ni atilẹyin.
Awọn ilana fifi sori ẹrọ
Ipilẹ ipilẹ gbọdọ wa ni fi sori ẹrọ si Katalogi IP ti sọfitiwia Libero® SoC laifọwọyi nipasẹ iṣẹ imudojuiwọn Katalogi IP ni sọfitiwia SoC Libero, tabi o ti ṣe igbasilẹ pẹlu ọwọ lati inu katalogi naa. Ni kete ti ipilẹ IP ti fi sori ẹrọ ni Labero SoC sọfitiwia IP Catalog, o ti tunto, ti ipilẹṣẹ ati lẹsẹkẹsẹ laarin Apẹrẹ Smart fun ifisi ninu iṣẹ akanṣe Libero.
Awọn Ẹrọ Orisun Idanwo (Beere ibeere kan)
Tabili ti o tẹle ṣe atokọ awọn ẹrọ orisun idanwo.
Table 1-1. Idanwo Awọn ẹrọ Awọn orisun
| Awọn ẹrọ | Ipo Pixel | Awọn ipinnu Idanwo | Ijinle Awọ (Bit) | Ipo Awọ | Ohun |
| quantumdata™ M41h HDMI Oluyanju | 1 | 720P 30 FPS, 720P 60 FPS ati 1080P 60 FPS | 8 | RGB, YUV444 ati YUV422 | Bẹẹni |
| 1080P 30 FPS | 8, 10, 12 ati 16 | ||||
| 4 | 720P 30 FPS, 1080P 30 FPS ati 4K 60 FPS | 8 | |||
| 1080P 60 FPS | 8, 12 ati 16 | ||||
| 4K 30 FPS | 8, 10, 12 ati 16 | ||||
| Lenovo™ 20U1A007IG | 1 | 1080P 60 FPS | 8 | RGB | Bẹẹni |
| 4 | 1080P 60 FPS ati 4K 30 FPS | ||||
| Dell Latitude 3420 | 1 | 1080P 60 FPS | 8 | RGB | Bẹẹni |
| 4 | 4K 30 FPS ati 4K 60 FPS | ||||
| Astro VA-1844A HDMI® igbeyewo | 1 | 720P 30 FPS, 720P 60 FPS ati 1080P 60 FPS | 8 | RGB, YUV444 ati YUV422 | Bẹẹni |
| 1080P 30 FPS | 8, 10, 12 ati 16 | ||||
| 4 | 720P 30 FPS, 1080P 30 FPS ati 4K 30 FPS | 8 | |||
| 1080P 30 FPS | 8, 12 ati 16 | ||||
| NVIDIA® Jetson AGX Orin 32GB H01 Kit | 1 | 1080P 30 FPS | 8 | RGB | Rara |
| 4 | 4K 60 FPS |
HDMI RX IP iṣeto ni (Beere ibeere kan)
Yi apakan pese ohun loriview ti HDMI RX IP Configurator ni wiwo ati awọn oniwe-irinše. HDMI RX IP Configurator n pese wiwo ayaworan lati ṣeto ipilẹ HDMI RX. Oluṣeto yii n gba olumulo laaye lati yan awọn aye bii Nọmba ti Pixels, Nọmba awọn ikanni ohun, Atọka fidio, Interface Audio, SCRAMBLER, Ijinle Awọ, Ọna kika Awọ, Testbench ati Iwe-aṣẹ. Ni wiwo Configurator pẹlu awọn akojọ aṣayan silẹ ati awọn aṣayan lati ṣe akanṣe awọn eto. Awọn atunto bọtini jẹ apejuwe ninu Table 4-1. Nọmba ti o tẹle n pese alaye kan view ti HDMI RX IP Configurator ni wiwo.
olusin 2-1. HDMI RX IP Configurator
Ni wiwo tun pẹlu O dara ati awọn bọtini Fagilee lati jẹrisi tabi sọ awọn atunto naa silẹ.
Imuse Hardware (Beere ibeere kan)
Awọn isiro wọnyi ṣe apejuwe wiwo HDMI RX IP pẹlu transceiver (XCVR).
olusin 3-1. HDMI RX Block aworan atọka
olusin 3-2. Aworan atọka Àkọsílẹ Alaye Olugba
HDMI RX oriširiši meta stages:
- Apejọ alakoso ṣe deede data ti o jọra pẹlu ọwọ si iṣakoso awọn aala ami nipa lilo isokuso bit transceiver.
- Iyipada koodu TMDS ṣe iyipada data koodu 10-bit sinu data piksẹli fidio 8-bit, data apo ohun 4-bit ati awọn ifihan agbara iṣakoso 2-bit.
- Awọn FIFO yọkuro skew laarin awọn aago ti awọn ọna R, G ati B.
Aligner Alakoso (Beere ibeere kan)
Awọn data afiwera 10-bit lati XCVR ko nigbagbogbo ni ibamu pẹlu ọwọ si awọn aala ọrọ ti a fi koodu TMDS. Awọn data ti o jọra nilo lati yipada diẹ ati ni ibamu lati le pinnu data naa. Apejọ alakoso ṣe deede data afiwera ti nwọle si awọn aala ọrọ nipa lilo ẹya-ara isokuso ni XCVR. XCVR ni Per-Monitor DPI Awareness (PMA) mode faye gba bit-isokuso ẹya-ara, ibi ti o ti satunṣe awọn titete ti 10-bit deserialized ọrọ nipa 1-bit. Ni akoko kọọkan, lẹhin titunṣe ọrọ 10-bit nipasẹ ipo isokuso 1 bit, o ṣe afiwe pẹlu eyikeyi ọkan ninu awọn ami iṣakoso mẹrin ti Ilana HDMI lati tii ipo naa lakoko akoko iṣakoso. Ọrọ 10-bit ti wa ni deede deede ati pe o wulo fun awọn s atẹletages. Ikanni awọ kọọkan ni olutọpa alakoso tirẹ, decoder TMDS bẹrẹ iyipada nikan nigbati gbogbo awọn alabaṣe alakoso ti wa ni titiipa lati ṣatunṣe awọn aala ọrọ.
Oluyipada TMDS (Beere ibeere kan)
TMDS decoder ṣe iyipada 10-bit deserialized lati transceiver sinu data piksẹli 8-bit lakoko akoko fidio. HSYNC, VSYNC ati PACKET HEADER ti wa ni ipilẹṣẹ lakoko akoko iṣakoso lati data ikanni buluu 10-bit. Awọn data apo-iwe ohun jẹ iyipada si ikanni R ati G ọkọọkan pẹlu awọn die-die mẹrin. Oluyipada TMDS ti ikanni kọọkan n ṣiṣẹ lori aago tirẹ. Nitorinaa, o le ni skew kan laarin awọn ikanni.
Ikanni si ikanni De-Skew (Beere ibeere kan)
A FIFO orisun de-skew kannaa ti lo lati yọ skew laarin awọn ikanni. Ikanni kọọkan gba ifihan agbara ti o wulo lati awọn apa titete alakoso lati tọka boya data 10-bit ti nwọle lati alapin alakoso jẹ wulo. Ti gbogbo awọn ikanni ba wulo (ti ṣaṣeyọri titete alakoso), module FIFO bẹrẹ lati kọja data nipasẹ module FIFO nipa lilo awọn ifihan agbara kika ati kọ (tẹsiwaju kikọ sinu ati kika jade). Nigbati a ba rii ami iṣakoso kan ni eyikeyi awọn abajade FIFO, ṣiṣan ka jade ti daduro, ati ami ami ti a rii ni ipilẹṣẹ lati tọka dide ti ami ami kan pato ninu ṣiṣan fidio. Ṣiṣan kika jade bẹrẹ nikan nigbati aami yii ti de lori gbogbo awọn ikanni mẹta naa. Bi abajade, skew ti o yẹ ti yọ kuro. Awọn FIFO-aago meji ṣiṣẹpọ gbogbo awọn ṣiṣan data mẹta si aago ikanni buluu lati yọ skew ti o yẹ kuro. Nọmba ti o tẹle ṣe apejuwe ikanni si ilana de-skew ikanni.
olusin 3-3. Ikanni to ikanni De-Skew
DDC (Beere ibeere kan)
DDC jẹ ikanni ibaraẹnisọrọ ti o da lori sipesifikesonu ọkọ akero I2C. Orisun naa nlo awọn aṣẹ I2C lati ka alaye lati E-EDID kan rii pẹlu adirẹsi ẹrú. HDMI RX IP nlo EDID ti a ti sọ tẹlẹ pẹlu ipinnu ipinnu pupọ ṣe atilẹyin awọn ipinnu to 1920 ✕ 1080 ni 60 Hz ni Ipo Pixel Kan ati pe o to 3840✕ 2160 ni 60 Hz ni ipo Pixel Mẹrin.
EDID duro fun orukọ ifihan bi Microchip HDMI àpapọ.
Awọn paramita HDMI RX ati Awọn ifihan agbara Ni wiwo (Beere ibeere kan)
Yi apakan ti jiroro awọn paramita ni HDMI RX GUI configurator ati I/O awọn ifihan agbara.
Awọn Ilana Iṣeto (Beere Ibeere kan)
Tabili ti o tẹle ṣe atokọ awọn aye atunto ni HDMI RX IP.
tabili 4-1. Awọn paramita iṣeto ni
| Orukọ paramita | Apejuwe |
| Awọ kika | Awọn asọye aaye awọ. Ṣe atilẹyin awọn ọna kika awọ wọnyi:
|
| Ijinle Awọ | Pato nọmba ti awọn die-die fun paati awọ. Atilẹyin 8, 10, 12 ati 16 die-die fun paati. |
| Nọmba ti awọn piksẹli | Tọkasi nọmba awọn piksẹli fun titẹ sii aago:
|
| SCRAMBLER | Atilẹyin fun ipinnu 4K ni awọn fireemu 60 fun iṣẹju kan:
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| Nọmba awọn ikanni ohun | Ṣe atilẹyin nọmba awọn ikanni ohun:
|
| Atọka fidio | Ilu abinibi ati ṣiṣan AXI |
| Olohun Interface | Ilu abinibi ati ṣiṣan AXI |
| Idanwo ibujoko | Laaye yiyan ti agbegbe ibujoko idanwo. Ṣe atilẹyin awọn aṣayan ibujoko idanwo atẹle:
|
| Iwe-aṣẹ | Ni pato iru iwe-aṣẹ. Pese awọn aṣayan iwe-aṣẹ meji wọnyi:
|
Awọn ibudo (Beere ibeere kan)
Tabili ti o tẹle ṣe atokọ igbewọle ati awọn ebute oko oju omi ti HDMI RX IP fun wiwo Ilu abinibi nigbati Ọna Awọ jẹ RGB.
Table 4-2. Input and Output for Abin Interface
| Orukọ ifihan agbara | Itọsọna | Ìbú (Bits) | Apejuwe |
| RESET_N_I | Iṣawọle | 1 | Ifihan agbara atunto asynchronous kekere ti nṣiṣe lọwọ |
| R_RX_CLK_I | Iṣawọle | 1 | Aago ti o jọra fun ikanni “R” lati XCVR |
| G_RX_CLK_I | Iṣawọle | 1 | Aago ti o jọra fun ikanni “G” lati XCVR |
| B_RX_CLK_I | Iṣawọle | 1 | Aago ti o jọra fun ikanni “B” lati XCVR |
| EDID_RESET_N_I | Iṣawọle | 1 | Ifihan agbara atunto asynchronous kekere ti nṣiṣe lọwọ |
| R_RX_VALID_I | Iṣawọle | 1 | Ifihan agbara to wulo lati XCVR fun data afiwe ikanni “R”. |
| G_RX_VALID_I | Iṣawọle | 1 | Ifihan agbara lati XCVR fun data afiwe ikanni “G”. |
| B_RX_VALID_I | Iṣawọle | 1 | Ifihan agbara ti o wulo lati XCVR fun data afiwe ikanni “B”. |
| Orukọ ifihan agbara | Itọsọna | Ìbú (Bits) | Apejuwe |
| DATA_R_I | Iṣawọle | NOMBA PIXELS ✕ 10 die-die | Ti gba data ibajọra ikanni “R” lati XCVR |
| DATA_G_I | Iṣawọle | NOMBA PIXELS ✕ 10 die-die | Ti gba data afiwe ikanni “G” lati XCVR |
| DATA_B_I | Iṣawọle | NOMBA PIXELS ✕ 10 die-die | Ti gba data ibajọra ikanni “B” lati XCVR |
| SCL_I | Iṣawọle | 1 | I2C ni tẹlentẹle aago igbewọle fun DDC |
| HPD_I | Iṣawọle | 1 | Pulọọgi gbigbona ṣawari ifihan agbara titẹ sii. Orisun ti sopọ si ifọwọ ifihan agbara HPD yẹ ki o ga. |
| SDA_I | Iṣawọle | 1 | I2C ni tẹlentẹle data igbewọle fun DDC |
| EDID_CLK_I | Iṣawọle | 1 | Aago eto fun I2C module |
| BIT_SLIP_R_O | Abajade | 1 | Bit isokuso ifihan agbara to "R" ikanni ti transceiver |
| BIT_SLIP_G_O | Abajade | 1 | Bit isokuso ifihan agbara si "G" ikanni ti transceiver |
| BIT_SLIP_B_O | Abajade | 1 | Bit isokuso ifihan agbara to "B" ikanni ti transceiver |
| VIDEO_DATA_VALID_O | Abajade | 1 | Fidio data wu wulo |
| AUDIO_DATA_VALID_O | Abajade | 1 | Ohùn data wu wulo |
| H_SYNC_O | Abajade | 1 | Petele ìsiṣẹpọ polusi |
| V_SYNC_O | Abajade | 1 | Polusi amuṣiṣẹpọ inaro ti nṣiṣe lọwọ |
| R_O | Abajade | NOMBA PIXELS ✕ Ijinle Awọ | Decoded "R" data |
| G_O | Abajade | NOMBA PIXELS ✕ Ijinle Awọ | Decoded "G" data |
| B_O | Abajade | NOMBA PIXELS ✕ Ijinle Awọ | Decoded "B" data |
| SDA_O | Abajade | 1 | I2C ni tẹlentẹle data wu fun DDC |
| HPD_O | Abajade | 1 | Gbona plug iwari o wu ifihan agbara |
| ACR_CTS_O | Abajade | 20 | Ohun Aago Atunse ọmọ Timestamp iye |
| ACR_N_O | Abajade | 20 | Iwọn Aago Olooru (N) paramita |
| ACR_VALID_O | Abajade | 1 | Audio Aago Isọdọtun wulo ifihan agbara |
| AUDIO_SAMPLE_CH1_O | Abajade | 24 | ikanni 1 ohun sample data |
| AUDIO_SAMPLE_CH2_O | Abajade | 24 | ikanni 2 ohun sample data |
| AUDIO_SAMPLE_CH3_O | Abajade | 24 | ikanni 3 ohun sample data |
| AUDIO_SAMPLE_CH4_O | Abajade | 24 | ikanni 4 ohun sample data |
| AUDIO_SAMPLE_CH5_O | Abajade | 24 | ikanni 5 ohun sample data |
| AUDIO_SAMPLE_CH6_O | Abajade | 24 | ikanni 6 ohun sample data |
| AUDIO_SAMPLE_CH7_O | Abajade | 24 | ikanni 7 ohun sample data |
| AUDIO_SAMPLE_CH8_O | Abajade | 24 | ikanni 8 ohun sample data |
| HDMI_DVI_MODE_O | Abajade | 1 | Awọn wọnyi ni awọn ọna meji:
|
Tabili ti o tẹle n ṣapejuwe igbewọle ati awọn ebute oko oju omi ti HDMI RX IP fun Atọka Fidio ṣiṣan AXI4.
Table 4-3. Awọn ebute oko oju omi ti nwọle ati ti njade fun AXI4 Stream Video Interface
| Orukọ Port | Itọsọna | Ìbú (Bits) | Apejuwe |
| TDATA_O | Abajade | NUMBER TI PIXELS ✕ Ijinle Awọ ✕ 3 bits | Data fidio ti o jade [R, G, B] |
| TVALID_O | Abajade | 1 | Fidio ti njade wulo |
| Orukọ Port | Itọsọna | Ìbú (Bits) | Apejuwe |
| TLAST_O | Abajade | 1 | O wu fireemu opin ifihan agbara |
| TUSER_O | Abajade | 3 |
|
| TSTRB_O | Abajade | 3 | O wu fidio data strobe |
| TKEEP_O | Abajade | 3 | O wu fidio data pa |
Tabili ti o tẹle n ṣapejuwe igbewọle ati awọn ebute agbejade ti HDMI RX IP fun Interface Audio ṣiṣanwọle AXI4.
Table 4-4. Awọn ebute oko oju omi ti nwọle ati ti njade fun AXI4 Stream Audio Interface
| Orukọ Port | Itọsọna | Ìbú (Bits) | Apejuwe |
| AUDIO_TDATA_O | Abajade | 24 | Ojade iwe data |
| AUDIO_TID_O | Abajade | 3 | Ikanni ohun afetigbọ |
| AUDIO_TVALID_O | Abajade | 1 | O wu iwe ohun ifihan agbara |
Tabili ti o tẹle ṣe atokọ awọn igbewọle ati awọn ebute oko oju omi ti o wu ti HDMI RX IP fun wiwo Ilu abinibi nigbati Ọna Awọ jẹ YUV444.
Table 4-5. Input and Output for Abin Interface
| Orukọ Port | Itọsọna | Ìbú (Bits) | Apejuwe |
| RESET_N_I | Iṣawọle | 1 | Ifihan agbara atunto asynchronous kekere ti nṣiṣe lọwọ |
| LANE3_RX_CLK_I | Iṣawọle | 1 | Aago ti o jọra fun ikanni Lane 3 lati XCVR |
| LANE2_RX_CLK_I | Iṣawọle | 1 | Aago ti o jọra fun ikanni Lane 2 lati XCVR |
| LANE1_RX_CLK_I | Iṣawọle | 1 | Aago ti o jọra fun ikanni Lane 1 lati XCVR |
| EDID_RESET_N_I | Iṣawọle | 1 | Ifihan agbara atunto asynchronous kekere ti nṣiṣe lọwọ |
| LANE3_RX_VALID_I | Iṣawọle | 1 | Ifihan agbara lati XCVR fun Lane 3 data ti o jọra |
| LANE2_RX_VALID_I | Iṣawọle | 1 | Ifihan agbara lati XCVR fun Lane 2 data ti o jọra |
| LANE1_RX_VALID_I | Iṣawọle | 1 | Ifihan agbara lati XCVR fun Lane 1 data ti o jọra |
| DATA_LANE3_I | Iṣawọle | NOMBA PIXELS ✕ 10 die-die | Ti gba Lane 3 data afiwera lati XCVR |
| DATA_LANE2_I | Iṣawọle | NOMBA PIXELS ✕ 10 die-die | Ti gba Lane 2 data afiwera lati XCVR |
| DATA_LANE1_I | Iṣawọle | NOMBA PIXELS ✕ 10 die-die | Ti gba Lane 1 data afiwera lati XCVR |
| SCL_I | Iṣawọle | 1 | I2C ni tẹlentẹle aago igbewọle fun DDC |
| HPD_I | Iṣawọle | 1 | Pulọọgi gbigbona ṣawari ifihan agbara titẹ sii. Orisun ti sopọ si ifọwọ ifihan agbara HPD yẹ ki o ga. |
| SDA_I | Iṣawọle | 1 | I2C ni tẹlentẹle data igbewọle fun DDC |
| EDID_CLK_I | Iṣawọle | 1 | Aago eto fun I2C module |
| BIT_SLIP_LANE3_O | Abajade | 1 | Bit isokuso ifihan agbara to Lane 3 ti transceiver |
| BIT_SLIP_LANE2_O | Abajade | 1 | Bit isokuso ifihan agbara to Lane 2 ti transceiver |
| BIT_SLIP_LANE1_O | Abajade | 1 | Bit isokuso ifihan agbara to Lane 1 ti transceiver |
| VIDEO_DATA_VALID_O | Abajade | 1 | Fidio data wu wulo |
| AUDIO_DATA_VALID_O | Abajade | 1 | Ohùn data wu wulo |
| H_SYNC_O | Abajade | 1 | Petele ìsiṣẹpọ polusi |
| V_SYNC_O | Abajade | 1 | Polusi amuṣiṣẹpọ inaro ti nṣiṣe lọwọ |
| Orukọ Port | Itọsọna | Ìbú (Bits) | Apejuwe |
| Y_O | Abajade | NOMBA PIXELS ✕ Ijinle Awọ | Ti ṣe iyipada data “Y”. |
| Cb_O | Abajade | NOMBA PIXELS ✕ Ijinle Awọ | Decoded "Cb" data |
| Cr_O | Abajade | NOMBA PIXELS ✕ Ijinle Awọ | Decoded "Cr" data |
| SDA_O | Abajade | 1 | I2C ni tẹlentẹle data wu fun DDC |
| HPD_O | Abajade | 1 | Gbona plug iwari o wu ifihan agbara |
| ACR_CTS_O | Abajade | 20 | Ohun Aago Atunṣe Yiyipo igbaamp iye |
| ACR_N_O | Abajade | 20 | Iwọn Aago Olooru (N) paramita |
| ACR_VALID_O | Abajade | 1 | Audio Aago Isọdọtun wulo ifihan agbara |
| AUDIO_SAMPLE_CH1_O | Abajade | 24 | ikanni 1 ohun sample data |
| AUDIO_SAMPLE_CH2_O | Abajade | 24 | ikanni 2 ohun sample data |
| AUDIO_SAMPLE_CH3_O | Abajade | 24 | ikanni 3 ohun sample data |
| AUDIO_SAMPLE_CH4_O | Abajade | 24 | ikanni 4 ohun sample data |
| AUDIO_SAMPLE_CH5_O | Abajade | 24 | ikanni 5 ohun sample data |
| AUDIO_SAMPLE_CH6_O | Abajade | 24 | ikanni 6 ohun sample data |
| AUDIO_SAMPLE_CH7_O | Abajade | 24 | ikanni 7 ohun sample data |
| AUDIO_SAMPLE_CH8_O | Abajade | 24 | ikanni 8 ohun sample data |
Tabili ti o tẹle ṣe atokọ awọn igbewọle ati awọn ebute oko oju omi ti o wu ti HDMI RX IP fun wiwo Ilu abinibi nigbati Ọna Awọ jẹ YUV422.
Table 4-6. Input and Output for Abin Interface
| Orukọ Port | Itọsọna | Ìbú (Bits) | Apejuwe |
| RESET_N_I | Iṣawọle | 1 | Ifihan agbara atunto asynchronous kekere ti nṣiṣe lọwọ |
| LANE3_RX_CLK_I | Iṣawọle | 1 | Aago ti o jọra fun ikanni Lane 3 lati XCVR |
| LANE2_RX_CLK_I | Iṣawọle | 1 | Aago ti o jọra fun ikanni Lane 2 lati XCVR |
| LANE1_RX_CLK_I | Iṣawọle | 1 | Aago ti o jọra fun ikanni Lane 1 lati XCVR |
| EDID_RESET_N_I | Iṣawọle | 1 | Ifihan agbara atunto asynchronous kekere ti nṣiṣe lọwọ |
| LANE3_RX_VALID_I | Iṣawọle | 1 | Ifihan agbara lati XCVR fun Lane 3 data ti o jọra |
| LANE2_RX_VALID_I | Iṣawọle | 1 | Ifihan agbara lati XCVR fun Lane 2 data ti o jọra |
| LANE1_RX_VALID_I | Iṣawọle | 1 | Ifihan agbara lati XCVR fun Lane 1 data ti o jọra |
| DATA_LANE3_I | Iṣawọle | NOMBA PIXELS ✕ 10 die-die | Ti gba Lane 3 data afiwera lati XCVR |
| DATA_LANE2_I | Iṣawọle | NOMBA PIXELS ✕ 10 die-die | Ti gba Lane 2 data afiwera lati XCVR |
| DATA_LANE1_I | Iṣawọle | NOMBA PIXELS ✕ 10 die-die | Ti gba Lane 1 data afiwera lati XCVR |
| SCL_I | Iṣawọle | 1 | I2C ni tẹlentẹle aago igbewọle fun DDC |
| HPD_I | Iṣawọle | 1 | Pulọọgi gbigbona ṣawari ifihan agbara titẹ sii. Orisun ti sopọ si ifọwọ ifihan agbara HPD yẹ ki o ga. |
| SDA_I | Iṣawọle | 1 | I2C ni tẹlentẹle data igbewọle fun DDC |
| EDID_CLK_I | Iṣawọle | 1 | Aago eto fun I2C module |
| BIT_SLIP_LANE3_O | Abajade | 1 | Bit isokuso ifihan agbara to Lane 3 ti transceiver |
| BIT_SLIP_LANE2_O | Abajade | 1 | Bit isokuso ifihan agbara to Lane 2 ti transceiver |
| BIT_SLIP_LANE1_O | Abajade | 1 | Bit isokuso ifihan agbara to Lane 1 ti transceiver |
| VIDEO_DATA_VALID_O | Abajade | 1 | Fidio data wu wulo |
| Orukọ Port | Itọsọna | Ìbú (Bits) | Apejuwe |
| AUDIO_DATA_VALID_O | Abajade | 1 | Ohùn data wu wulo |
| H_SYNC_O | Abajade | 1 | Petele ìsiṣẹpọ polusi |
| V_SYNC_O | Abajade | 1 | Polusi amuṣiṣẹpọ inaro ti nṣiṣe lọwọ |
| Y_O | Abajade | NOMBA PIXELS ✕ Ijinle Awọ | Ti ṣe iyipada data “Y”. |
| C_O | Abajade | NOMBA PIXELS ✕ Ijinle Awọ | Decoded "C" data |
| SDA_O | Abajade | 1 | I2C ni tẹlentẹle data wu fun DDC |
| HPD_O | Abajade | 1 | Gbona plug iwari o wu ifihan agbara |
| ACR_CTS_O | Abajade | 20 | Ohun Aago Atunṣe Yiyipo igbaamp iye |
| ACR_N_O | Abajade | 20 | Iwọn Aago Olooru (N) paramita |
| ACR_VALID_O | Abajade | 1 | Audio Aago Isọdọtun wulo ifihan agbara |
| AUDIO_SAMPLE_CH1_O | Abajade | 24 | ikanni 1 ohun sample data |
| AUDIO_SAMPLE_CH2_O | Abajade | 24 | ikanni 2 ohun sample data |
| AUDIO_SAMPLE_CH3_O | Abajade | 24 | ikanni 3 ohun sample data |
| AUDIO_SAMPLE_CH4_O | Abajade | 24 | ikanni 4 ohun sample data |
| AUDIO_SAMPLE_CH5_O | Abajade | 24 | ikanni 5 ohun sample data |
| AUDIO_SAMPLE_CH6_O | Abajade | 24 | ikanni 6 ohun sample data |
| AUDIO_SAMPLE_CH7_O | Abajade | 24 | ikanni 7 ohun sample data |
| AUDIO_SAMPLE_CH8_O | Abajade | 24 | ikanni 8 ohun sample data |
Tabili ti o tẹle ṣe atokọ awọn igbewọle ati awọn ebute agbejade ti HDMI RX IP fun wiwo Ilu abinibi nigbati SCRAMBLER ti ṣiṣẹ.
Table 4-7. Input and Output for Abin Interface
| Orukọ Port | Itọsọna | Ìbú (Bits) | Apejuwe |
| RESET_N_I | Iṣawọle | 1 | Ifihan agbara atunto asynchronous kekere ti nṣiṣe lọwọ |
| R_RX_CLK_I | Iṣawọle | 1 | Aago ti o jọra fun ikanni “R” lati XCVR |
| G_RX_CLK_I | Iṣawọle | 1 | Aago ti o jọra fun ikanni “G” lati XCVR |
| B_RX_CLK_I | Iṣawọle | 1 | Aago ti o jọra fun ikanni “B” lati XCVR |
| EDID_RESET_N_I | Iṣawọle | 1 | Ifihan agbara atunto asynchronous kekere ti nṣiṣe lọwọ |
| HDMI_CABLE_CLK_I | Iṣawọle | 1 | Aago USB lati orisun HDMI |
| R_RX_VALID_I | Iṣawọle | 1 | Ifihan agbara to wulo lati XCVR fun data afiwe ikanni “R”. |
| G_RX_VALID_I | Iṣawọle | 1 | Ifihan agbara lati XCVR fun data afiwe ikanni “G”. |
| B_RX_VALID_I | Iṣawọle | 1 | Ifihan agbara ti o wulo lati XCVR fun data afiwe ikanni “B”. |
| DATA_R_I | Iṣawọle | NOMBA PIXELS ✕ 10 die-die | Ti gba data ibajọra ikanni “R” lati XCVR |
| DATA_G_I | Iṣawọle | NOMBA PIXELS ✕ 10 die-die | Ti gba data afiwe ikanni “G” lati XCVR |
| DATA_B_I | Iṣawọle | NOMBA PIXELS ✕ 10 die-die | Ti gba data ibajọra ikanni “B” lati XCVR |
| SCL_I | Iṣawọle | 1 | I2C ni tẹlentẹle aago igbewọle fun DDC |
| HPD_I | Iṣawọle | 1 | Pulọọgi gbigbona ṣawari ifihan agbara titẹ sii. Orisun ti sopọ si ifọwọ, ati ifihan HPD yẹ ki o ga. |
| SDA_I | Iṣawọle | 1 | I2C ni tẹlentẹle data igbewọle fun DDC |
| EDID_CLK_I | Iṣawọle | 1 | Aago eto fun I2C module |
| BIT_SLIP_R_O | Abajade | 1 | Bit isokuso ifihan agbara to "R" ikanni ti transceiver |
| BIT_SLIP_G_O | Abajade | 1 | Bit isokuso ifihan agbara si "G" ikanni ti transceiver |
| Orukọ Port | Itọsọna | Ìbú (Bits) | Apejuwe |
| BIT_SLIP_B_O | Abajade | 1 | Bit isokuso ifihan agbara to "B" ikanni ti transceiver |
| VIDEO_DATA_VALID_O | Abajade | 1 | Fidio data wu wulo |
| AUDIO_DATA_VALID_O | Ijade1 | 1 | Ohùn data wu wulo |
| H_SYNC_O | Abajade | 1 | Petele ìsiṣẹpọ polusi |
| V_SYNC_O | Abajade | 1 | Polusi amuṣiṣẹpọ inaro ti nṣiṣe lọwọ |
| DATA_ RATE_O | Abajade | 16 | Oṣuwọn data Rx. Awọn wọnyi ni awọn iye oṣuwọn data:
|
| R_O | Abajade | NOMBA PIXELS ✕ Ijinle Awọ | Decoded "R" data |
| G_O | Abajade | NOMBA PIXELS ✕ Ijinle Awọ | Decoded "G" data |
| B_O | Abajade | NOMBA PIXELS ✕ Ijinle Awọ | Decoded "B" data |
| SDA_O | Abajade | 1 | I2C ni tẹlentẹle data wu fun DDC |
| HPD_O | Abajade | 1 | Gbona plug iwari o wu ifihan agbara |
| ACR_CTS_O | Abajade | 20 | Ohun Aago Atunṣe Yiyipo igbaamp iye |
| ACR_N_O | Abajade | 20 | Iwọn Aago Olooru (N) paramita |
| ACR_VALID_O | Abajade | 1 | Audio Aago Isọdọtun wulo ifihan agbara |
| AUDIO_SAMPLE_CH1_O | Abajade | 24 | ikanni 1 ohun sample data |
| AUDIO_SAMPLE_CH2_O | Abajade | 24 | ikanni 2 ohun sample data |
| AUDIO_SAMPLE_CH3_O | Abajade | 24 | ikanni 3 ohun sample data |
| AUDIO_SAMPLE_CH4_O | Abajade | 24 | ikanni 4 ohun sample data |
| AUDIO_SAMPLE_CH5_O | Abajade | 24 | ikanni 5 ohun sample data |
| AUDIO_SAMPLE_CH6_O | Abajade | 24 | ikanni 6 ohun sample data |
| AUDIO_SAMPLE_CH7_O | Abajade | 24 | ikanni 7 ohun sample data |
| AUDIO_SAMPLE_CH8_O | Abajade | 24 | ikanni 8 ohun sample data |
Testbench Simulation (Beere ibeere kan)
A pese Testbench lati ṣayẹwo iṣẹ ṣiṣe ti HDMI RX mojuto. Testbench ṣiṣẹ nikan ni Atọwọọlu abinibi nigbati nọmba awọn piksẹli jẹ ọkan.
Lati ṣe afarawe mojuto nipa lilo testbench, ṣe awọn igbesẹ wọnyi:
- Ni awọn Design Flow window, faagun Ṣẹda Design.
- Tẹ-ọtun Ṣẹda SmartDesign Testbench, ati lẹhinna tẹ Ṣiṣe, bi o ṣe han ninu nọmba atẹle.
olusin 5-1. Ṣiṣẹda SmartDesign Testbench
- Tẹ orukọ sii fun SmartDesign testbench, ati lẹhinna tẹ O DARA.
olusin 5-2. Loruko SmartDesign Testbench
SmartDesign testbench ti ṣẹda, ati kanfasi kan han si ọtun ti PAN Flow Design. - Lilö kiri si Libero® SoC Catalog, yan View > Windows > Katalogi IP, ati lẹhinna faagun awọn Solusan-Fidio. Tẹ HDMI RX IP lẹẹmeji (v5.4.0) ati lẹhinna tẹ O DARA.
- Yan gbogbo awọn ebute oko oju omi, tẹ-ọtun ko si yan Igbega si Ipele oke.
- Lori ọpa irinṣẹ SmartDesign, tẹ Ṣẹda paati.
- Lori taabu Stimulus Hierarchy, tẹ-ọtun HDMI_RX_TB testbench file, ati ki o si tẹ Simulate Pre-Synth Design> Ṣii Interactively.
Ohun elo ModelSim® ṣii pẹlu testbench, bi o ṣe han ninu nọmba atẹle.
olusin 5-3. Ọpa ModelSim pẹlu HDMI RX Testbench File
Pataki: If kikopa ti wa ni Idilọwọ nitori awọn run akoko iye to pato ninu awọn DO file, lo run -all pipaṣẹ lati pari kikopa.
Iwe-aṣẹ (Beere ibeere kan)
HDMI RX IP ti pese pẹlu awọn aṣayan iwe-aṣẹ meji wọnyi:
- Ti paroko: Pari koodu RTL ti paroko ti pese fun mojuto. O wa fun ọfẹ pẹlu eyikeyi iwe-aṣẹ Libero, ti o fun laaye ni mojuto lati wa ni ese pẹlu SmartDesign. O le ṣe Simulation, Synthesis, Layout, ati ṣeto ohun alumọni FPGA nipa lilo suite apẹrẹ Libero.
- RTL: koodu orisun RTL pipe ti wa ni titiipa iwe-aṣẹ, eyiti o nilo lati ra lọtọ.
Awọn abajade Simulation (Beere ibeere kan)
Aworan akoko atẹle fun HDMI RX IP ṣe afihan data fidio ati awọn akoko data iṣakoso.
olusin 6-1. Video Data
Aworan atọka atẹle n ṣe afihan hsync ati awọn abajade vsync fun awọn igbewọle data iṣakoso ti o baamu.
olusin 6-2. Amuṣiṣẹpọ petele ati Awọn ifihan agbara amuṣiṣẹpọ inaro
Aworan atẹle yii fihan apakan EDID.
olusin 6-3. Awọn ifihan agbara EDID
Lilo orisun (Beere ibeere kan)
HDMI RX IP ti wa ni imuse ni PolarFire® FPGA (MPF300T - 1FCG1152I Package). Tabili ti o tẹle yii ṣe atokọ awọn orisun ti a lo nigbati Nọmba ti Pixels = 1 pixels.
tabili 7-1. Lilo orisun fun Ipo Pixel 1
| Awọ kika | Ijinle Awọ | SCRAMBLER | Aṣọ 4LUT | Aṣọ DFF | Ni wiwo 4LUT | Ni wiwo DFF | uSRAM (64×12) | LSRAM (20k) |
| RGB | 8 | Pa a | 987 | 1867 | 360 | 360 | 0 | 10 |
| 10 | Pa a | 1585 | 1325 | 456 | 456 | 11 | 9 | |
| 12 | Pa a | 1544 | 1323 | 456 | 456 | 11 | 9 | |
| 16 | Pa a | 1599 | 1331 | 492 | 492 | 14 | 9 | |
| YCbCr422 | 8 | Pa a | 1136 | 758 | 360 | 360 | 3 | 9 |
| YCbCr444 | 8 | Pa a | 1105 | 782 | 360 | 360 | 3 | 9 |
| 10 | Pa a | 1574 | 1321 | 456 | 456 | 11 | 9 | |
| 12 | Pa a | 1517 | 1319 | 456 | 456 | 11 | 9 | |
| 16 | Pa a | 1585 | 1327 | 492 | 492 | 14 | 9 |
Tabili ti o tẹle yii ṣe atokọ awọn orisun ti a lo nigbati Nọmba ti Pixels = 4 pixels.
tabili 7-2. Lilo orisun fun Ipo Pixel 4
| Awọ kika | Ijinle Awọ | SCRAMBLER | Aṣọ 4LUT | Aṣọ DFF | Ni wiwo 4LUT | Ni wiwo DFF | uSRAM (64×12) | LSRAM (20k) |
| RGB | 8 | Pa a | 1559 | 1631 | 1080 | 1080 | 9 | 27 |
| 12 | Pa a | 1975 | 2191 | 1344 | 1344 | 31 | 27 | |
| 16 | Pa a | 1880 | 2462 | 1428 | 1428 | 38 | 27 | |
| RGB | 10 | Mu ṣiṣẹ | 4231 | 3306 | 1008 | 1008 | 3 | 27 |
| 12 | Mu ṣiṣẹ | 4253 | 3302 | 1008 | 1008 | 3 | 27 | |
| 16 | Mu ṣiṣẹ | 3764 | 3374 | 1416 | 1416 | 37 | 27 | |
| YCbCr422 | 8 | Pa a | 1485 | 1433 | 912 | 912 | 7 | 23 |
| YCbCr444 | 8 | Pa a | 1513 | 1694 | 1080 | 1080 | 9 | 27 |
| 12 | Pa a | 2001 | 2099 | 1344 | 1344 | 31 | 27 | |
| 16 | Pa a | 1988 | 2555 | 1437 | 1437 | 38 | 27 |
Tabili atẹle yii ṣe atokọ awọn orisun ti a lo nigbati Nọmba ti Pixels = 4 pixel ati SCRAMBLER ṣiṣẹ.
tabili 7-3. Lilo awọn orisun fun Ipo Pixel 4 ati SCRAMBLER ti ṣiṣẹ
| Awọ kika | Ijinle Awọ | SCRAMBLER | Aṣọ 4LUT | Aṣọ DFF | Ni wiwo 4LUT | Ni wiwo DFF | uSRAM (64×12) | LSRAM (20k) |
| RGB | 8 | Mu ṣiṣẹ | 5029 | 5243 | 1126 | 1126 | 9 | 28 |
| YCbCr422 | 8 | Mu ṣiṣẹ | 4566 | 3625 | 1128 | 1128 | 13 | 27 |
| YCbCr444 | 8 | Mu ṣiṣẹ | 4762 | 3844 | 1176 | 1176 | 17 | 27 |
Isopọpọ eto (Beere ibeere kan)
Abala yii fihan bi o ṣe le ṣepọ IP sinu apẹrẹ Libero.
Tabili ti o tẹle ṣe atokọ awọn atunto ti PF XCVR, PF TX PLL ati PF CCC ti o nilo fun awọn ipinnu oriṣiriṣi ati awọn iwọn iwọn.
Table 8-1. PF XCVR, PF TX PLL ati PF CCC Awọn atunto
| Ipinnu | Iwọn Bit | Iṣeto ni PF XCVR | CDR REF Aago paadi | PF CCC iṣeto ni | |||
| Oṣuwọn data RX | RX CDR Ref Aago Igbohunsafẹfẹ | RX PCS Fabric Iwọn | Igbohunsafẹfẹ Input | Igbohunsafẹfẹ Ijade | |||
| 1 PXL (1080p60) | 8 | 1485 | 148.5 | 10 | AE27, AE28 | NA | NA |
| 1 PXL (1080p30) | 10 | 1485 | 148.5 | 10 | AE27, AE28 | 92.5 | 74 |
| 12 | 1485 | 148.5 | 10 | AE27, AE28 | 74.25 | 111.375 | |
| 16 | 1485 | 148.5 | 10 | AE27, AE28 | 74.25 | 148.5 | |
| 4 PXL (1080p60) | 8 | 1485 | 148.5 | 40 | AE27, AE28 | NA | NA |
| 12 | 1485 | 148.5 | 40 | AE27, AE28 | 55.725 | 37.15 | |
| 16 | 1485 | 148.5 | 40 | AE27, AE28 | 74.25 | 37.125 | |
| 4 PXL (4kp30) | 8 | 1485 | 148.5 | 40 | AE27, AE28 | NA | NA |
| 10 | 3712.5 | 148.5 | 40 | AE29, AE30 | 92.81 | 74.248 | |
| 12 | 4455 | 148.5 | 40 | AE29, AE30 | 111.375 | 74.25 | |
| 16 | 5940 | 148.5 | 40 | AE29, AE30 | 148.5 | 74.25 | |
| 4 PXL (4Kp60) | 8 | 5940 | 148.5 | 40 | AE29, AE30 | NA | NA |
HDMI RX SampApẹrẹ 1: Nigbati a ba tunto ni Ijinle Awọ = 8-bit ati Nọmba ti Awọn piksẹli = Ipo Pixel 1, yoo han ni nọmba atẹle.
olusin 8-1. HDMI RX Sample Apẹrẹ 1
Fun example, ni awọn atunto 8-bit, awọn paati atẹle jẹ apakan ti apẹrẹ:
- PF_XCVR_ERM (PF_XCVR_ERM_C0_0) ti wa ni tunto fun TX ati RX ni kikun ile oloke meji mode. Oṣuwọn data RX ti 1485 Mbps ni ipo PMA, pẹlu iwọn data tunto bi 10 bit fun ipo 1 PXL ati aago itọkasi 148.5 MHz CDR. Oṣuwọn data TX ti 1485 Mbps ni ipo PMA, pẹlu iwọn data ti a tunto bi 10 bit pẹlu ifosiwewe pipin aago 4.
- LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK ati LANE3_CDR_REF_CLK wa ni wiwakọ lati PF_XCVR_REF_CLK pẹlu AE27, AE28 paadi pinni.
- PIN EDID CLK_I yẹ ki o wakọ pẹlu aago 150 MHz pẹlu CCC.
- R_RX_CLK_I, G_RX_CLK_I ati B_RX_CLK_I ti wa ni idari nipasẹ LANE3_TX_CLK_R, LANE2_TX_CLK_R ati LANE1_TX_CLK_R, lẹsẹsẹ.
- R_RX_VALID_I, G_RX_VALID_I ati B_RX_VALID_I ti wa ni idari nipasẹ LANE3_RX_VAL, LANE2_RX_VAL ati LANE1_RX_VAL, lẹsẹsẹ.
- DATA_R_I, DATA_G_I ati DATA_B_I ti wa ni idari nipasẹ LANE3_RX_DATA, LANE2_RX_DATA ati LANE1_RX_DATA, lẹsẹsẹ.
HDMI RX SampApẹrẹ 2: Nigbati a ba tunto ni Ijinle Awọ = 8-bit ati Nọmba ti Awọn piksẹli = Ipo Pixel 4, yoo han ni nọmba atẹle.
olusin 8-2. HDMI RX Sample Apẹrẹ 2
Fun example, ni awọn atunto 8-bit, awọn paati atẹle jẹ apakan ti apẹrẹ:
- PF_XCVR_ERM (PF_XCVR_ERM_C0_0) ti wa ni tunto fun TX ati RX ni kikun ile oloke meji mode. Oṣuwọn data RX ti 1485 Mbps ni ipo PMA, pẹlu iwọn data tunto bi 40 bit fun ipo 4 PXL ati aago itọkasi 148.5 MHz CDR. Oṣuwọn data TX ti 1485 Mbps ni ipo PMA, pẹlu iwọn data ti a tunto bi 40 bit pẹlu ifosiwewe pipin aago 4.
- LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK ati LANE3_CDR_REF_CLK wa ni wiwakọ lati PF_XCVR_REF_CLK pẹlu AE27, AE28 paadi pinni.
- PIN EDID CLK_I yẹ ki o wakọ pẹlu aago 150 MHz pẹlu CCC.
- R_RX_CLK_I, G_RX_CLK_I ati B_RX_CLK_I ti wa ni idari nipasẹ LANE3_TX_CLK_R, LANE2_TX_CLK_R ati LANE1_TX_CLK_R, lẹsẹsẹ.
- R_RX_VALID_I, G_RX_VALID_I ati B_RX_VALID_I ti wa ni idari nipasẹ LANE3_RX_VAL, LANE2_RX_VAL ati LANE1_RX_VAL, lẹsẹsẹ.
- DATA_R_I, DATA_G_I ati DATA_B_I ti wa ni idari nipasẹ LANE3_RX_DATA, LANE2_RX_DATA ati LANE1_RX_DATA, lẹsẹsẹ.
HDMI RX SampApẹrẹ 3: Nigbati o ba tunto ni Ijinle Awọ = 8-bit ati Nọmba ti Awọn piksẹli = Ipo Pixel 4 ati SCRAMBLER = Ṣiṣẹ, yoo han ni nọmba atẹle.
olusin 8-3. HDMI RX Sample Apẹrẹ 3
Fun example, ni awọn atunto 8-bit, awọn paati atẹle jẹ apakan ti apẹrẹ:
- PF_XCVR_ERM (PF_XCVR_ERM_C0_0) ti wa ni tunto fun TX ati RX Independent mode. Oṣuwọn data RX ti 5940 Mbps ni ipo PMA, pẹlu iwọn data tunto bi 40 bit fun ipo 4 PXL ati aago itọkasi 148.5 MHz CDR. Oṣuwọn data TX ti 5940 Mbps ni ipo PMA, pẹlu iwọn data ti a tunto bi 40 bit pẹlu ifosiwewe pipin aago 4.
- LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK ati LANE3_CDR_REF_CLK ti wa ni iwakọ lati PF_XCVR_REF_CLK pẹlu AF29, AF30 paadi pinni.
- PIN EDID CLK_I yẹ ki o wakọ pẹlu aago 150 MHz pẹlu CCC.
- R_RX_CLK_I, G_RX_CLK_I ati B_RX_CLK_I ti wa ni idari nipasẹ LANE3_TX_CLK_R, LANE2_TX_CLK_R ati LANE1_TX_CLK_R, lẹsẹsẹ.
- R_RX_VALID_I, G_RX_VALID_I ati B_RX_VALID_I ti wa ni idari nipasẹ LANE3_RX_VAL, LANE2_RX_VAL ati LANE1_RX_VAL, lẹsẹsẹ.
- DATA_R_I, DATA_G_I ati DATA_B_I ti wa ni idari nipasẹ LANE3_RX_DATA, LANE2_RX_DATA ati LANE1_RX_DATA, lẹsẹsẹ.
HDMI RX SampApẹrẹ 4: Nigbati o ba tunto ni Ijinle Awọ = 12-bit ati Nọmba ti Awọn piksẹli = Ipo Pixel 4 ati SCRAMBLER = Ṣiṣẹ, yoo han ni nọmba atẹle.
olusin 8-4. HDMI RX Sample Apẹrẹ 4
Fun example, ni awọn atunto 12-bit, awọn paati atẹle jẹ apakan ti apẹrẹ:
- PF_XCVR_ERM (PF_XCVR_ERM_C0_0) jẹ atunto fun ipo RX Nikan. Oṣuwọn data RX ti 4455 Mbps ni ipo PMA, pẹlu iwọn data tunto bi 40 bit fun ipo 4 PXL ati aago itọkasi 148.5 MHz CDR.
- LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK ati LANE3_CDR_REF_CLK ti wa ni iwakọ lati PF_XCVR_REF_CLK pẹlu AF29, AF30 paadi pinni.
- PIN EDID CLK_I yẹ ki o wakọ pẹlu aago 150 MHz pẹlu CCC.
- R_RX_CLK_I, G_RX_CLK_I ati B_RX_CLK_I ti wa ni idari nipasẹ LANE3_TX_CLK_R, LANE2_TX_CLK_R ati LANE1_TX_CLK_R, lẹsẹsẹ.
- R_RX_VALID_I, G_RX_VALID_I ati B_RX_VALID_I ti wa ni idari nipasẹ LANE3_RX_VAL, LANE2_RX_VAL ati LANE1_RX_VAL, lẹsẹsẹ.
- DATA_R_I, DATA_G_I ati DATA_B_I ti wa ni idari nipasẹ LANE3_RX_DATA, LANE2_RX_DATA ati LANE1_RX_DATA, lẹsẹsẹ.
- Module PF_CCC_C0 n ṣe agbejade aago kan ti a npè ni OUT0_FABCLK_0 pẹlu igbohunsafẹfẹ ti 74.25 MHz, ti o wa lati aago titẹ sii ti 111.375 MHz, eyiti LANE1_RX_CLK_R wa ni idari.
HDMI RX SampApẹrẹ 5: Nigbati o ba tunto ni Ijinle Awọ = 8-bit, Nọmba ti Awọn piksẹli = Ipo Pixel 4 ati SCRAMBLER = Ṣiṣẹ ni afihan ni nọmba atẹle. Apẹrẹ yii jẹ oṣuwọn data ti o ni agbara pẹlu DRI.
olusin 8-5. HDMI RX Sample Apẹrẹ 5
Fun example, ni awọn atunto 8-bit, awọn paati atẹle jẹ apakan ti apẹrẹ:
- PF_XCVR_ERM (PF_XCVR_ERM_C0_0) ni tunto fun ipo RX Nikan pẹlu wiwo atunto atunto ti o mu ṣiṣẹ. Oṣuwọn data RX ti 5940 Mbps ni ipo PMA, pẹlu iwọn data tunto bi 40 bit fun ipo 4 PXL ati aago itọkasi 148.5 MHz CDR.
- LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK ati LANE3_CDR_REF_CLK ti wa ni iwakọ lati PF_XCVR_REF_CLK pẹlu AF29, AF30 paadi pinni.
- PIN EDID CLK_I yẹ ki o wakọ pẹlu aago 150 MHz pẹlu CCC.
- R_RX_CLK_I, G_RX_CLK_I ati B_RX_CLK_I ti wa ni idari nipasẹ LANE3_TX_CLK_R, LANE2_TX_CLK_R ati LANE1_TX_CLK_R, lẹsẹsẹ.
- R_RX_VALID_I, G_RX_VALID_I ati B_RX_VALID_I ti wa ni idari nipasẹ LANE3_RX_VAL, LANE2_RX_VAL ati LANE1_RX_VAL, lẹsẹsẹ.
- DATA_R_I, DATA_G_I ati DATA_B_I ti wa ni idari nipasẹ LANE3_RX_DATA, LANE2_RX_DATA ati LANE1_RX_DATA, lẹsẹsẹ.
Itan Atunyẹwo (Beere ibeere kan)
Itan atunyẹwo ṣe apejuwe awọn iyipada ti a ṣe imuse ninu iwe-ipamọ naa. Awọn iyipada ti wa ni atokọ nipasẹ atunyẹwo, bẹrẹ pẹlu atẹjade lọwọlọwọ julọ.
Table 9-1. Àtúnyẹwò History
| Àtúnyẹwò | Ọjọ | Apejuwe |
| D | 02/2025 | Atẹle ni atokọ ti awọn ayipada ti a ṣe ni atunyẹwo C ti iwe naa:
|
| C | 02/2023 | Atẹle ni atokọ ti awọn ayipada ti a ṣe ni atunyẹwo C ti iwe naa:
|
| B | 09/2022 | Atẹle ni atokọ ti awọn ayipada ti a ṣe ni atunyẹwo B ti iwe naa:
|
| A | 04/2022 | Atẹle ni atokọ ti awọn ayipada ninu atunyẹwo A ti iwe naa:
|
| 2.0 | — | Awọn atẹle jẹ akopọ ti awọn ayipada ti a ṣe ninu atunyẹwo yii.
|
| 1.0 | 08/2021 | Atunyẹwo akọkọ. |
Microchip FPGA Support
Ẹgbẹ awọn ọja Microchip FPGA ṣe atilẹyin awọn ọja rẹ pẹlu ọpọlọpọ awọn iṣẹ atilẹyin, pẹlu Iṣẹ alabara, Ile-iṣẹ Atilẹyin Imọ-ẹrọ Onibara, a webojula, ati ni agbaye tita ifiweranṣẹ. A daba awọn alabara lati ṣabẹwo si awọn orisun ori ayelujara Microchip ṣaaju kikan si atilẹyin nitori o ṣee ṣe pupọ pe awọn ibeere wọn ti ni idahun tẹlẹ. Kan si Technical Support Center nipasẹ awọn webojula ni www.microchip.com/support. Darukọ nọmba Apakan Ẹrọ FPGA, yan ẹka ọran ti o yẹ, ati apẹrẹ ikojọpọ files nigba ti ṣiṣẹda a imọ support irú. Kan si Iṣẹ Onibara fun atilẹyin ọja ti kii ṣe imọ-ẹrọ, gẹgẹbi idiyele ọja, awọn iṣagbega ọja, alaye imudojuiwọn, ipo aṣẹ, ati aṣẹ.
- Lati North America, pe 800.262.1060
- Lati iyoku agbaye, pe 650.318.4460
- Faksi, lati nibikibi ninu aye, 650.318.8044
Microchip Alaye
Awọn aami-išowo
Orukọ “Microchip” ati aami, aami “M”, ati awọn orukọ miiran, awọn aami, ati awọn ami iyasọtọ ti forukọsilẹ ati awọn aami-išowo ti ko forukọsilẹ ti Microchip Technology Incorporated tabi awọn alafaramo ati/tabi awọn ẹka ni Amẹrika ati/tabi awọn orilẹ-ede miiran (“Microchip). Awọn aami-išowo"). Alaye nipa Awọn aami-išowo Microchip le rii ni https://www.microchip.com/en-us/about/legal-information/microchip-trademarks.
ISBN: 979-8-3371-0744-8
Ofin Akiyesi
Atẹjade yii ati alaye ti o wa ninu rẹ le ṣee lo pẹlu awọn ọja Microchip nikan, pẹlu lati ṣe apẹrẹ, idanwo, ati ṣepọ awọn ọja Microchip pẹlu ohun elo rẹ. Lilo alaye yii ni ọna miiran ti o lodi si awọn ofin wọnyi. Alaye nipa awọn ohun elo ẹrọ ti pese fun irọrun rẹ nikan ati pe o le rọpo nipasẹ awọn imudojuiwọn. O jẹ ojuṣe rẹ lati rii daju pe ohun elo rẹ ni ibamu pẹlu awọn pato rẹ. Kan si ọfiisi tita Microchip agbegbe rẹ fun atilẹyin afikun tabi, gba atilẹyin afikun ni www.microchip.com/en-us/support/design-help/client-support-services.
ALAYE YI NI MICROCHIP “BI O SE WA”. MICROCHIP KO SE Aṣoju TABI ATILẸYIN ỌJA TI IRU KANKAN BOYA KIAKIA TABI TỌRỌ, KỌ TABI ẹnu, Ilana tabi Bibẹkọkọ, ti o jọmọ ALAYE NAA SUGBON KO NI LOPIN SI KANKAN, LATI IKILỌ ỌRỌ, ÀTI IFỌRỌWỌRỌ FUN IDI PATAKI, TABI ATILẸYIN ỌJA TO JEmọ MAJEMU, Didara, TABI Iṣe Rẹ.
LAISI iṣẹlẹ ti yoo ṣe oniduro fun eyikeyi aiṣedeede, PATAKI, ijiya, ijamba, tabi ipadanu, bibajẹ, iye owo, tabi inawo ti eyikeyi iru ohunkohun ti o jọmọ si awọn alaye tabi ti o ti gba, ti o ba ti lo, Ti a gbaniyanju nipa Seese TABI awọn bibajẹ ni o wa tẹlẹ. SI AWỌN NIPA NIPA NIPA TI OFIN, LAPAPA LAPAPO MICROCHIP LORI Gbogbo awọn ẹtọ ni eyikeyi ọna ti o jọmọ ALAYE TABI LILO RE KO NI JU OPO ỌWỌ, TI O BA KAN, PE O TI ṢAN NIPA TODAJU SIROMỌ.
Lilo awọn ẹrọ Microchip ni atilẹyin igbesi aye ati/tabi awọn ohun elo aabo jẹ patapata ni ewu olura, ati pe olura gba lati daabobo, ṣe idalẹbi ati dimu Microchip ti ko lewu lati eyikeyi ati gbogbo awọn bibajẹ, awọn ẹtọ, awọn ipele, tabi awọn inawo ti o waye lati iru lilo. Ko si awọn iwe-aṣẹ ti a gbe lọ, laisọtọ tabi bibẹẹkọ, labẹ eyikeyi awọn ẹtọ ohun-ini imọ Microchip ayafi bibẹẹkọ ti sọ.
Ẹya Idaabobo koodu Awọn ẹrọ Microchip
Ṣe akiyesi awọn alaye atẹle ti ẹya aabo koodu lori awọn ọja Microchip:
- Awọn ọja Microchip pade awọn pato ti o wa ninu Iwe Data Microchip pato wọn.
- Microchip gbagbọ pe ẹbi ti awọn ọja wa ni aabo nigba lilo ni ọna ti a pinnu, laarin awọn pato iṣẹ, ati labẹ awọn ipo deede.
- Awọn iye Microchip ati ibinu ṣe aabo awọn ẹtọ ohun-ini ọgbọn rẹ. Awọn igbiyanju lati irufin awọn ẹya aabo koodu ti awọn ọja Microchip jẹ eewọ muna ati pe o le rú Ofin Aṣẹ-lori Ẹgbẹrun Ọdun Digital.
- Bẹni Microchip tabi eyikeyi olupese semikondokito miiran le ṣe iṣeduro aabo koodu rẹ. Idaabobo koodu ko tumọ si pe a n ṣe iṣeduro ọja naa jẹ “aibikita”. Idaabobo koodu ti wa ni idagbasoke nigbagbogbo. Microchip ti pinnu lati ni ilọsiwaju nigbagbogbo awọn ẹya aabo koodu ti awọn ọja wa.
© 2025 Microchip Technology Inc. ati awọn ẹka rẹ
FAQ
- Q: Bawo ni MO ṣe ṣe imudojuiwọn HDMI RX IP mojuto?
A: IP mojuto le ṣe imudojuiwọn nipasẹ sọfitiwia Libero SoC tabi ṣe igbasilẹ pẹlu ọwọ lati katalogi naa. Ni kete ti o ti fi sii ni Labero SoC sọfitiwia IP Catalog, o le tunto, ipilẹṣẹ, ati lẹsẹkẹsẹ laarin SmartDesign fun ifisi ninu iṣẹ akanṣe naa.
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