MICROCHIP PolarFire FPGA High Definition Multimedia Interface HDMI Mai karɓa
Gabatarwa (Tambaya Tambaya)
Mai karɓa na IP na Microchip's High-Definition Multimedia Interface (HDMI) yana goyan bayan bayanan bidiyo da liyafar fakitin bayanan mai jiwuwa da aka bayyana a cikin ƙayyadaddun ma'auni na HDMI. HDMI RX IP an tsara shi musamman don PolarFire® FPGA da Tsarin PolarFire akan Chip (SoC) na'urorin FPGA masu goyan bayan HDMI 2.0 don ƙuduri har zuwa 1920 × 1080 a 60 Hz a cikin yanayin pixel ɗaya kuma har zuwa 3840 × 2160 a 60 Hz a cikin yanayin pixel huɗu. RX IP yana goyan bayan Hot Plug Detect (HPD) don saka idanu akan kunnawa ko kashewa da cirewa ko toshe abubuwan da suka faru don nuna sadarwa tsakanin tushen HDMI da nutsewar HDMI.
Tushen HDMI yana amfani da tashar Bayanin Nuni (DDC) don karanta bayanan Fahimtar Nuni na Nuni (EDID) don gano daidaitawar Sink da/ko iyawa. HDMI RX IP yana da EDID da aka riga aka tsara, wanda tushen HDMI zai iya karantawa ta hanyar daidaitaccen tashar I2C. PolarFire FPGA da PolarFire SoC FPGA masu watsa na'ura ana amfani da su tare da RX IP don lalata bayanan serial cikin bayanan 10-bit. Ana ba da izinin tashoshin bayanai a cikin HDMI su sami babban skew a tsakanin su. HDMI RX IP yana cire skew tsakanin tashoshin bayanai ta amfani da Farko-A Farko (FIFOs). Wannan IP tana jujjuya bayanan Canjin Canjin Siginar Rarraba (TMDS) da aka karɓa daga tushen HDMI ta hanyar transceiver zuwa bayanan pixel 24-bit RGB, bayanan sauti na 24-bit da siginar sarrafawa. Ana amfani da ƙayyadaddun alamun sarrafawa guda huɗu da aka ƙayyade a cikin ka'idar HDMI don daidaita bayanan lokaci yayin ɓarna.
Takaitawa
Tebur mai zuwa yana ba da taƙaitaccen halayen HDMI RX IP.
Table 1. HDMI RX IP Halayen
| Sigar Core | Wannan jagorar mai amfani yana goyan bayan HDMI RX IP v5.4. |
| Iyalan Na'ura masu Goyan baya |
|
| Gudun Kayan Aikin Goyon baya | Yana buƙatar Libero® SoC v12.0 ko daga baya sakewa. |
| Hanyoyin sadarwa masu goyan baya | Hanyoyi masu goyan bayan HDMI RX IP sune:
|
| Yin lasisi | Ana samar da HDMI RX IP tare da zaɓuɓɓukan lasisi guda biyu masu zuwa:
|
Siffofin
HDMI RX IP yana da fasali masu zuwa:
- Mai jituwa don HDMI 2.0
- Yana goyan bayan zurfin launi na 8, 10, 12 da 16 Bits
- Yana goyan bayan Tsarin Launi kamar RGB, YUV 4: 2: 2 da YUV 4: 4: 4
- Yana goyan bayan Pixels ɗaya ko huɗu kowace shigarwar agogo
- Yana goyan bayan Sharuɗɗa har zuwa 1920 ✕ 1080 a 60 Hz a cikin Yanayin Pixel guda ɗaya kuma har zuwa 3840 ✕ 2160 a 60 Hz a cikin yanayin Pixel huɗu.
- Yana Gano Hot-Plug
- Yana goyan bayan Tsarin Yankewa – TMDS
- Yana goyan bayan shigarwar DVI
- Yana goyan bayan Tashoshin Bayanai na Nuni (DDC) da Ingantacciyar Tashar Bayanan Bayanai (E-DDC)
- Yana goyan bayan Interface Bidiyo na Yan ƙasa da AXI4 don Canja wurin Bayanan Bidiyo
- Yana goyan bayan Interface Audio na Ƙasa da AXI4 Rafi don Canja wurin Bayanan Sauti
Siffofin da ba su da tallafi
Wadannan su ne abubuwan da ba su da tallafi na HDMI RX IP:
- 4: 2: 0 tsarin launi ba a tallafawa.
- Babban Rage Tsayi (HDR) da Kariyar abun ciki na Dijital mai girma-bandwidth (HDCP) ba su da tallafi.
- Ba'a goyan bayan Rate Refresh Rate (VRR) da Yanayin Lantarki ta atomatik (ALLM).
- Matsakaicin lokaci na kwance waɗanda ba za a raba su da huɗu a cikin yanayin Pixel huɗu ba.
Umarnin Shigarwa
Dole ne a shigar da ainihin IP ɗin zuwa Kas ɗin IP na software na Libero® SoC ta atomatik ta aikin sabunta Catalog na IP a cikin software na Libero SoC, ko kuma an zazzage shi da hannu daga kundin. Da zarar an shigar da ainihin IP a cikin software na Libero SoC IP Catalog, an saita shi, ƙirƙira kuma a nan take a cikin Smart Design don haɗawa cikin aikin Libero.
Na'urorin Tushen Gwaji (Tambaya Tambaya)
Tebur mai zuwa yana lissafin na'urorin tushen da aka gwada.
Tebur 1-1. Na'urorin Tushen da aka gwada
| Na'urori | Yanayin Pixel | An gwada ƙuduri | Zurfin Launi (Bit) | Yanayin launi | Audio |
| Quantumdata™ M41h HDMI Analyzer | 1 | 720P 30 FPS, 720P 60 FPS da 1080P 60 FPS | 8 | RGB, YUV444 da YUV422 | Ee |
| 1080P 30 FPS | 8, 10, 12 da 16 | ||||
| 4 | 720P 30 FPS, 1080P 30 FPS da 4K 60 FPS | 8 | |||
| 1080P 60 FPS | 8, 12 da 16 | ||||
| 4K 30 FPS | 8, 10, 12 da 16 | ||||
| Lenovo™ 20U1A007IG | 1 | 1080P 60 FPS | 8 | RGB | Ee |
| 4 | 1080P 60 FPS da 4K 30 FPS | ||||
| Dell Latitude 3420 | 1 | 1080P 60 FPS | 8 | RGB | Ee |
| 4 | 4K 30 FPS da 4K 60 FPS | ||||
| Astro VA-1844A HDMI® Gwajin | 1 | 720P 30 FPS, 720P 60 FPS da 1080P 60 FPS | 8 | RGB, YUV444 da YUV422 | Ee |
| 1080P 30 FPS | 8, 10, 12 da 16 | ||||
| 4 | 720P 30 FPS, 1080P 30 FPS da 4K 30 FPS | 8 | |||
| 1080P 30 FPS | 8, 12 da 16 | ||||
| NVIDIA® Jetson AGX Orin 32GB H01 Kit | 1 | 1080P 30 FPS | 8 | RGB | A'a |
| 4 | 4K 60 FPS |
HDMI RX Kanfigareshan IP (Tambaya Tambaya)
Wannan sashe yana ba da ƙarewaview na HDMI RX IP Configurator interface da abubuwan da aka haɗa. HDMI RX IP Configurator yana ba da ƙirar hoto don saita ainihin HDMI RX. Wannan mai daidaitawa yana bawa mai amfani damar zaɓar sigogi kamar Adadin Pixels, Adadin tashoshin sauti, Interface Video, Interface Audio, SCRAMBLER, Zurfin Launi, Tsarin Launi, Testbench da Lasisi. Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙaddamarwa ya yi ya haɗa da menus masu saukewa da zaɓuɓɓuka don tsara saitunan. An kwatanta maɓalli na maɓalli a cikin Tebur 4-1. Hoto na gaba yana ba da daki-daki view na HDMI RX IP Configurator interface.
Hoto na 2-1. HDMI RX IP Configurator
Maballin ya haɗa da OK da maɓallan soke don tabbatarwa ko watsar da saitunan.
Aiwatar Hardware (Tambaya Tambaya)
Alkaluman da ke biyowa sun bayyana haɗin haɗin IP na HDMI RX tare da transceiver (XCVR).
Hoto na 3-1. HDMI RX Block zane
Hoto na 3-2. Cikakkun Hoton Toshe Mai karɓa
HDMI RX ya ƙunshi s guda ukutage:
- Madaidaicin lokaci yana daidaita bayanan layi ɗaya dangane da sarrafa iyakokin alamar ta amfani da zamewar bit transceiver.
- Mai ƙididdigewa na TMDS yana juyar da bayanan 10-bit ɗin zuwa bayanan pixel na bidiyo 8-bit, bayanan fakitin odiyo 4-bit da siginar sarrafawa 2-bit.
- FIFOs suna cire skew tsakanin agogon hanyoyin R, G da B.
Daidaita Mataki (Tambaya Tambaya)
Bayanan layi na 10-bit daga XCVR ba koyaushe yana daidaitawa dangane da iyakokin kalmomin da aka sanya na TMDS ba. Ana buƙatar daidaita bayanan layi ɗaya da daidaita su don yanke bayanan. Madaidaicin lokaci yana daidaita bayanai masu shigowa daidai gwargwado zuwa iyakokin kalmomi ta amfani da fasalin zamewar bit a cikin XCVR. XCVR a cikin Per-Monitor DPI Awareness (PMA) yanayin yana ba da damar fasalin zamewa, inda yake daidaita daidaita kalmar 10-bit ta 1-bit. Kowane lokaci, bayan daidaita kalmar 10-bit ta wurin 1 bit zamewa, ana kwatanta shi da kowane ɗayan alamomin sarrafawa huɗu na ka'idar HDMI don kulle matsayi yayin lokacin sarrafawa. Kalmar 10-bit tana daidaita daidai kuma ana ganin tana aiki don s na gabatage. Kowane tashoshi launi yana da nasa aligner na zamani, TMDS decoder yana fara yanke hukunci kawai lokacin da aka kulle duk masu daidaita lokaci don gyara iyakokin kalmar.
Dikoda TMDS (Tambaya Tambaya)
TMDS mai ƙididdigewa yana ƙaddamar da 10-bit da aka ware daga mai aikawa zuwa bayanan pixel 8-bit yayin lokacin bidiyo. Ana samar da HSYNC, VSYNC da PACKET HEADER yayin lokacin sarrafawa daga bayanan tashar shuɗi na 10-bit. Ana yanke bayanan fakitin odiyo zuwa tashar R da G kowanne tare da rago hudu. Mai gyara TMDS na kowane tashoshi yana aiki akan agogon kansa. Don haka, yana iya samun ɗan karkata tsakanin tashoshi.
Tashar zuwa tashar De-Skew (Tambaya Tambaya)
Ana amfani da dabarar de-skew na tushen FIFO don cire skew tsakanin tashoshi. Kowane tashoshi yana karɓar ingantacciyar sigina daga raka'o'in daidaita lokaci don nuna idan bayanan 10-bit mai shigowa daga daidaitawar lokaci suna da inganci. Idan duk tashoshi suna aiki (sun sami daidaitawar lokaci), tsarin FIFO yana fara wucewa bayanai ta hanyar FIFO ta amfani da karantawa da rubuta siginar kunnawa (ci gaba da rubutawa da karantawa). Lokacin da aka gano alamar sarrafawa a cikin kowane fitowar FIFO, an dakatar da kwararar da aka karanta, kuma ana samar da siginar da aka gano don nuna isowar wata alama ta musamman a cikin rafin bidiyo. Matsalolin da aka karanta suna dawowa ne kawai lokacin da wannan alamar ta iso kan dukkan tashoshi uku. A sakamakon haka, an cire skew mai dacewa. FIFOs na agogo biyu suna aiki tare da duk rafukan bayanai guda uku zuwa agogon tashar shuɗi don cire skew mai dacewa. Hoto mai zuwa yana kwatanta tashar zuwa fasahar de-skew.
Hoto na 3-3. Tashar zuwa Channel De-Skew
DDC (Tambaya Tambaya)
DDC tashar sadarwa ce bisa ƙayyadaddun bas ɗin I2C. Tushen yana amfani da umarnin I2C don karanta bayanai daga E-EDID na nutse tare da adireshin bawa. HDMI RX IP yana amfani da EDID da aka riga aka ƙayyade tare da ƙuduri da yawa yana goyan bayan ƙuduri har zuwa 1920 ✕ 1080 a 60 Hz a cikin Yanayin Pixel guda ɗaya kuma har zuwa 3840 ✕ 2160 a 60 Hz a cikin yanayin Pixel Hudu.
EDID yana wakiltar sunan nuni azaman nunin Microchip HDMI.
HDMI RX Parameters da Interface Signals (Tambaya Tambaya)
Wannan sashe yana tattauna sigogi a cikin HDMI RX GUI mai daidaitawa da sigina na I/O.
Ma'aunin Kanfigareshan (Tambaya Tambaya)
Tebur mai zuwa yana lissafin sigogin daidaitawa a cikin HDMI RX IP.
Tebur 4-1. Ma'aunin Kanfigareshan
| Sunan Siga | Bayani |
| Tsarin launi | Yana bayyana sararin launi. Yana goyan bayan tsarin launi masu zuwa:
|
| Zurfin Launi | Yana ƙayyade adadin ragowa a kowane ɓangaren launi. Yana goyan bayan 8, 10, 12 da 16 ragowa kowane bangare. |
| Adadin Pixels | Yana nuna adadin pixels a kowace shigarwar agogo:
|
| SCRAMBLER | Taimako don ƙudurin 4K a firam 60 a sakan daya:
|
| Yawan tashoshin sauti | Yana goyan bayan adadin tashoshin sauti:
|
| Siffar Bidiyo | Na asali da AXI rafi |
| Interface Audio | Na asali da AXI rafi |
| Gwajin benci | Yana ba da damar zaɓin yanayin benci na gwaji. Yana goyan bayan zaɓuɓɓukan benci na gwaji masu zuwa:
|
| Lasisi | Yana ƙayyade nau'in lasisi. Yana ba da zaɓuɓɓukan lasisi guda biyu masu zuwa:
|
Tashoshin ruwa (Tambaya Tambaya)
Tebur mai zuwa yana lissafin shigarwar da tashoshin fitarwa na HDMI RX IP don ƙirar ƙasa lokacin da Tsarin Launi shine RGB.
Table 4-2. Shigarwa da Fitarwa don Interface na Ƙasar
| Sunan siginar | Hanyar | Nisa (Bits) | Bayani |
| SAKETA_N_I | Shigarwa | 1 | Siginar sake saitin asynchronous mara ƙarancin aiki |
| R_RX_CLK_I | Shigarwa | 1 | Agogon layi daya don tashar "R" daga XCVR |
| G_RX_CLK_I | Shigarwa | 1 | Agogon layi daya don tashar "G" daga XCVR |
| B_RX_CLK_I | Shigarwa | 1 | Agogon layi daya don tashar "B" daga XCVR |
| EDID_RESET_N_I | Shigarwa | 1 | Siginar sake saitin saitin edita mai ƙarancin aiki |
| R_RX_VALID_I | Shigarwa | 1 | Ingantacciyar sigina daga XCVR don bayanan tashar “R” daidai gwargwado |
| G_RX_VALID_I | Shigarwa | 1 | Ingantacciyar sigina daga XCVR don bayanan tashar “G” daidai gwargwado |
| B_RX_VALID_I | Shigarwa | 1 | Ingantacciyar sigina daga XCVR don bayanan tashar “B” daidai gwargwado |
| Sunan siginar | Hanyar | Nisa (Bits) | Bayani |
| DATA_R_I | Shigarwa | YAWAN PIXELS ✕ 10 bits | An karɓi bayanan tashar "R" daidaitattun bayanai daga XCVR |
| DATA_G_I | Shigarwa | YAWAN PIXELS ✕ 10 bits | An karɓi bayanan tashar "G" daidaitattun bayanai daga XCVR |
| DATA_B_I | Shigarwa | YAWAN PIXELS ✕ 10 bits | An karɓi bayanan tashar "B" daidaitattun bayanai daga XCVR |
| SCL_I | Shigarwa | 1 | I2C shigarwar agogon serial don DDC |
| HPD_I | Shigarwa | 1 | Filogi mai zafi gano siginar shigarwa. An haɗa tushen tushe don nutsewar siginar HPD ya kamata ya zama babba. |
| SDA_I | Shigarwa | 1 | I2C shigarwar bayanan serial don DDC |
| EDID_CLK_I | Shigarwa | 1 | Agogon tsarin don module I2C |
| BIT_SLIP_R_O | Fitowa | 1 | Siginar zamewa Bit zuwa tashar "R" na transceiver |
| BIT_SLIP_G_O | Fitowa | 1 | Siginar zamewa Bit zuwa tashar "G" na transceiver |
| BIT_SLIP_B_O | Fitowa | 1 | Siginar zamewa Bit zuwa tashar "B" na transceiver |
| VIDEO_DATA_VALID_O | Fitowa | 1 | Bayanan bidiyo ingantacce fitarwa |
| AUDIO_DATA_VALID_O | Fitowa | 1 | Bayanan odiyo ingantaccen fitarwa |
| H_SYNC_O | Fitowa | 1 | A tsaye bugun bugun jini |
| V_SYNC_O | Fitowa | 1 | bugun jini na daidaita aiki a tsaye |
| R_O | Fitowa | LAMBAR PIXELS ✕ Zurfin Launi | Decoded "R" data |
| G_O | Fitowa | LAMBAR PIXELS ✕ Zurfin Launi | Decoded "G" data |
| B_O | Fitowa | LAMBAR PIXELS ✕ Zurfin Launi | Decoded "B" data |
| SDA_O | Fitowa | 1 | I2C serial data fitarwa na DDC |
| HPD_O | Fitowa | 1 | Hot fulogi gano siginar fitarwa |
| ACR_CTS_O | Fitowa | 20 | Lokacin Sake Zagayowar Agogo Audioamp daraja |
| ACR_N_O | Fitowa | 20 | Ƙimar Sake Haɓaka Sauti (N) siga |
| ACR_VALID_O | Fitowa | 1 | Sake Haɓaka Agogon Sauti mai inganci |
| AUDIO_SAMPLE_CH1_O | Fitowa | 24 | Channel 1 audio sampda data |
| AUDIO_SAMPLE_CH2_O | Fitowa | 24 | Channel 2 audio sampda data |
| AUDIO_SAMPLE_CH3_O | Fitowa | 24 | Channel 3 audio sampda data |
| AUDIO_SAMPLE_CH4_O | Fitowa | 24 | Channel 4 audio sampda data |
| AUDIO_SAMPLE_CH5_O | Fitowa | 24 | Channel 5 audio sampda data |
| AUDIO_SAMPLE_CH6_O | Fitowa | 24 | Channel 6 audio sampda data |
| AUDIO_SAMPLE_CH7_O | Fitowa | 24 | Channel 7 audio sampda data |
| AUDIO_SAMPLE_CH8_O | Fitowa | 24 | Channel 8 audio sampda data |
| HDMI_DVI_MODE_O | Fitowa | 1 | Wadannan su ne hanyoyi guda biyu:
|
Tebur mai zuwa yana bayyana shigarwar da tashoshin fitarwa na HDMI RX IP don Interface Bidiyo na AXI4 Stream.
Table 4-3. Shigar da Mashigai na Fitarwa don AXI4 Stream Interface Video
| Sunan tashar jiragen ruwa | Hanyar | Nisa (Bits) | Bayani |
| TDATA_O | Fitowa | LAMBAR PIXELS ✕ Zurfin Launi ✕ 3 rago | Bayanan bidiyo na fitarwa [R, G, B] |
| TVALID_O | Fitowa | 1 | Fitar bidiyo mai inganci |
| Sunan tashar jiragen ruwa | Hanyar | Nisa (Bits) | Bayani |
| TLAST_O | Fitowa | 1 | Siginar ƙarshen firam ɗin fitarwa |
| TUSER_O | Fitowa | 3 |
|
| TSTRB_O | Fitowa | 3 | Fitar da bayanan bidiyo strobe |
| TKEEP_O | Fitowa | 3 | Fitar da bayanan bidiyo |
Tebur mai zuwa yana bayyana shigarwar da tashoshin fitarwa na HDMI RX IP don AXI4 Stream Audio Interface.
Table 4-4. Shigarwa da Tashoshin fitarwa don AXI4 Stream Audio Interface
| Sunan tashar jiragen ruwa | Hanyar | Nisa (Bits) | Bayani |
| AUDIO_TDATA_O | Fitowa | 24 | Fitar bayanan mai jiwuwa |
| AUDIO_TID_O | Fitowa | 3 | Fitar tashar sauti |
| AUDIO_TVALID_O | Fitowa | 1 | Fitar da siginar sauti mai inganci |
Tebur mai zuwa yana lissafin shigarwar da tashoshin fitarwa na HDMI RX IP don ƙirar ƙasa lokacin da Tsarin Launi shine YUV444.
Table 4-5. Shigarwa da Fitarwa don Interface na Ƙasar
| Sunan tashar jiragen ruwa | Hanyar | Nisa (Bits) | Bayani |
| SAKETA_N_I | Shigarwa | 1 | Siginar sake saitin asynchronous mara ƙarancin aiki |
| LANE3_RX_CLK_I | Shigarwa | 1 | Agogon layi daya don tashar Lane 3 daga XCVR |
| LANE2_RX_CLK_I | Shigarwa | 1 | Agogon layi daya don tashar Lane 2 daga XCVR |
| LANE1_RX_CLK_I | Shigarwa | 1 | Agogon layi daya don tashar Lane 1 daga XCVR |
| EDID_RESET_N_I | Shigarwa | 1 | Siginar sake saitin saitin edita mai ƙarancin aiki |
| LANE3_RX_VALID_I | Shigarwa | 1 | Ingantacciyar sigina daga XCVR don bayanan layi ɗaya na Lane 3 |
| LANE2_RX_VALID_I | Shigarwa | 1 | Ingantacciyar sigina daga XCVR don bayanan layi ɗaya na Lane 2 |
| LANE1_RX_VALID_I | Shigarwa | 1 | Ingantacciyar sigina daga XCVR don bayanan layi ɗaya na Lane 1 |
| DATA_LANE3_I | Shigarwa | YAWAN PIXELS ✕ 10 bits | Da aka karɓa Lane 3 bayanan layi ɗaya daga XCVR |
| DATA_LANE2_I | Shigarwa | YAWAN PIXELS ✕ 10 bits | Da aka karɓa Lane 2 bayanan layi ɗaya daga XCVR |
| DATA_LANE1_I | Shigarwa | YAWAN PIXELS ✕ 10 bits | Da aka karɓa Lane 1 bayanan layi ɗaya daga XCVR |
| SCL_I | Shigarwa | 1 | I2C shigarwar agogon serial don DDC |
| HPD_I | Shigarwa | 1 | Filogi mai zafi gano siginar shigarwa. An haɗa tushen tushe don nutsewar siginar HPD ya kamata ya zama babba. |
| SDA_I | Shigarwa | 1 | I2C shigarwar bayanan serial don DDC |
| EDID_CLK_I | Shigarwa | 1 | Agogon tsarin don module I2C |
| BIT_SLIP_LANE3_O | Fitowa | 1 | Siginar zamewa Bit zuwa Lane 3 na transceiver |
| BIT_SLIP_LANE2_O | Fitowa | 1 | Siginar zamewa Bit zuwa Lane 2 na transceiver |
| BIT_SLIP_LANE1_O | Fitowa | 1 | Siginar zamewa Bit zuwa Lane 1 na transceiver |
| VIDEO_DATA_VALID_O | Fitowa | 1 | Bayanan bidiyo ingantacce fitarwa |
| AUDIO_DATA_VALID_O | Fitowa | 1 | Bayanan odiyo ingantaccen fitarwa |
| H_SYNC_O | Fitowa | 1 | A tsaye bugun bugun jini |
| V_SYNC_O | Fitowa | 1 | bugun jini na daidaita aiki a tsaye |
| Sunan tashar jiragen ruwa | Hanyar | Nisa (Bits) | Bayani |
| Y_O | Fitowa | LAMBAR PIXELS ✕ Zurfin Launi | Ƙaddamar da bayanan "Y". |
| Cb_O | Fitowa | LAMBAR PIXELS ✕ Zurfin Launi | Decoded "Cb" data |
| Cr_O | Fitowa | LAMBAR PIXELS ✕ Zurfin Launi | Decoded "Cr" data |
| SDA_O | Fitowa | 1 | I2C serial data fitarwa na DDC |
| HPD_O | Fitowa | 1 | Hot fulogi gano siginar fitarwa |
| ACR_CTS_O | Fitowa | 20 | Agogon Audio Lokacin Zagayowar Farkoamp daraja |
| ACR_N_O | Fitowa | 20 | Ƙimar Sake Haɓaka Sauti (N) siga |
| ACR_VALID_O | Fitowa | 1 | Sake Haɓaka Agogon Sauti mai inganci |
| AUDIO_SAMPLE_CH1_O | Fitowa | 24 | Channel 1 audio sampda data |
| AUDIO_SAMPLE_CH2_O | Fitowa | 24 | Channel 2 audio sampda data |
| AUDIO_SAMPLE_CH3_O | Fitowa | 24 | Channel 3 audio sampda data |
| AUDIO_SAMPLE_CH4_O | Fitowa | 24 | Channel 4 audio sampda data |
| AUDIO_SAMPLE_CH5_O | Fitowa | 24 | Channel 5 audio sampda data |
| AUDIO_SAMPLE_CH6_O | Fitowa | 24 | Channel 6 audio sampda data |
| AUDIO_SAMPLE_CH7_O | Fitowa | 24 | Channel 7 audio sampda data |
| AUDIO_SAMPLE_CH8_O | Fitowa | 24 | Channel 8 audio sampda data |
Tebur mai zuwa yana lissafin shigarwar da tashoshin fitarwa na HDMI RX IP don ƙirar ƙasa lokacin da Tsarin Launi shine YUV422.
Table 4-6. Shigarwa da Fitarwa don Interface na Ƙasar
| Sunan tashar jiragen ruwa | Hanyar | Nisa (Bits) | Bayani |
| SAKETA_N_I | Shigarwa | 1 | Siginar sake saitin asynchronous mara ƙarancin aiki |
| LANE3_RX_CLK_I | Shigarwa | 1 | Agogon layi daya don tashar Lane 3 daga XCVR |
| LANE2_RX_CLK_I | Shigarwa | 1 | Agogon layi daya don tashar Lane 2 daga XCVR |
| LANE1_RX_CLK_I | Shigarwa | 1 | Agogon layi daya don tashar Lane 1 daga XCVR |
| EDID_RESET_N_I | Shigarwa | 1 | Siginar sake saitin saitin edita mai ƙarancin aiki |
| LANE3_RX_VALID_I | Shigarwa | 1 | Ingantacciyar sigina daga XCVR don bayanan layi ɗaya na Lane 3 |
| LANE2_RX_VALID_I | Shigarwa | 1 | Ingantacciyar sigina daga XCVR don bayanan layi ɗaya na Lane 2 |
| LANE1_RX_VALID_I | Shigarwa | 1 | Ingantacciyar sigina daga XCVR don bayanan layi ɗaya na Lane 1 |
| DATA_LANE3_I | Shigarwa | YAWAN PIXELS ✕ 10 bits | Da aka karɓa Lane 3 bayanan layi ɗaya daga XCVR |
| DATA_LANE2_I | Shigarwa | YAWAN PIXELS ✕ 10 bits | Da aka karɓa Lane 2 bayanan layi ɗaya daga XCVR |
| DATA_LANE1_I | Shigarwa | YAWAN PIXELS ✕ 10 bits | Da aka karɓa Lane 1 bayanan layi ɗaya daga XCVR |
| SCL_I | Shigarwa | 1 | I2C shigarwar agogon serial don DDC |
| HPD_I | Shigarwa | 1 | Filogi mai zafi gano siginar shigarwa. An haɗa tushen tushe don nutsewar siginar HPD ya kamata ya zama babba. |
| SDA_I | Shigarwa | 1 | I2C shigarwar bayanan serial don DDC |
| EDID_CLK_I | Shigarwa | 1 | Agogon tsarin don module I2C |
| BIT_SLIP_LANE3_O | Fitowa | 1 | Siginar zamewa Bit zuwa Lane 3 na transceiver |
| BIT_SLIP_LANE2_O | Fitowa | 1 | Siginar zamewa Bit zuwa Lane 2 na transceiver |
| BIT_SLIP_LANE1_O | Fitowa | 1 | Siginar zamewa Bit zuwa Lane 1 na transceiver |
| VIDEO_DATA_VALID_O | Fitowa | 1 | Bayanan bidiyo ingantacce fitarwa |
| Sunan tashar jiragen ruwa | Hanyar | Nisa (Bits) | Bayani |
| AUDIO_DATA_VALID_O | Fitowa | 1 | Bayanan odiyo ingantaccen fitarwa |
| H_SYNC_O | Fitowa | 1 | A tsaye bugun bugun jini |
| V_SYNC_O | Fitowa | 1 | bugun jini na daidaita aiki a tsaye |
| Y_O | Fitowa | LAMBAR PIXELS ✕ Zurfin Launi | Ƙaddamar da bayanan "Y". |
| C_O | Fitowa | LAMBAR PIXELS ✕ Zurfin Launi | Decoded "C" data |
| SDA_O | Fitowa | 1 | I2C serial data fitarwa na DDC |
| HPD_O | Fitowa | 1 | Hot fulogi gano siginar fitarwa |
| ACR_CTS_O | Fitowa | 20 | Agogon Audio Lokacin Zagayowar Farkoamp daraja |
| ACR_N_O | Fitowa | 20 | Ƙimar Sake Haɓaka Sauti (N) siga |
| ACR_VALID_O | Fitowa | 1 | Sake Haɓaka Agogon Sauti mai inganci |
| AUDIO_SAMPLE_CH1_O | Fitowa | 24 | Channel 1 audio sampda data |
| AUDIO_SAMPLE_CH2_O | Fitowa | 24 | Channel 2 audio sampda data |
| AUDIO_SAMPLE_CH3_O | Fitowa | 24 | Channel 3 audio sampda data |
| AUDIO_SAMPLE_CH4_O | Fitowa | 24 | Channel 4 audio sampda data |
| AUDIO_SAMPLE_CH5_O | Fitowa | 24 | Channel 5 audio sampda data |
| AUDIO_SAMPLE_CH6_O | Fitowa | 24 | Channel 6 audio sampda data |
| AUDIO_SAMPLE_CH7_O | Fitowa | 24 | Channel 7 audio sampda data |
| AUDIO_SAMPLE_CH8_O | Fitowa | 24 | Channel 8 audio sampda data |
Tebur mai zuwa yana lissafin shigarwa da tashoshin fitarwa na HDMI RX IP don keɓancewar ƙasa lokacin da aka kunna SCRAMBLER.
Table 4-7. Shigarwa da Fitarwa don Interface na Ƙasar
| Sunan tashar jiragen ruwa | Hanyar | Nisa (Bits) | Bayani |
| SAKETA_N_I | Shigarwa | 1 | Siginar sake saitin asynchronous mara ƙarancin aiki |
| R_RX_CLK_I | Shigarwa | 1 | Agogon layi daya don tashar "R" daga XCVR |
| G_RX_CLK_I | Shigarwa | 1 | Agogon layi daya don tashar "G" daga XCVR |
| B_RX_CLK_I | Shigarwa | 1 | Agogon layi daya don tashar "B" daga XCVR |
| EDID_RESET_N_I | Shigarwa | 1 | Siginar sake saitin saitin edita mai ƙarancin aiki |
| HDMI_CABLE_CLK_I | Shigarwa | 1 | Cable Agogo daga tushen HDMI |
| R_RX_VALID_I | Shigarwa | 1 | Ingantacciyar sigina daga XCVR don bayanan tashar “R” daidai gwargwado |
| G_RX_VALID_I | Shigarwa | 1 | Ingantacciyar sigina daga XCVR don bayanan tashar “G” daidai gwargwado |
| B_RX_VALID_I | Shigarwa | 1 | Ingantacciyar sigina daga XCVR don bayanan tashar “B” daidai gwargwado |
| DATA_R_I | Shigarwa | YAWAN PIXELS ✕ 10 bits | An karɓi bayanan tashar "R" daidaitattun bayanai daga XCVR |
| DATA_G_I | Shigarwa | YAWAN PIXELS ✕ 10 bits | An karɓi bayanan tashar "G" daidaitattun bayanai daga XCVR |
| DATA_B_I | Shigarwa | YAWAN PIXELS ✕ 10 bits | An karɓi bayanan tashar "B" daidaitattun bayanai daga XCVR |
| SCL_I | Shigarwa | 1 | I2C shigarwar agogon serial don DDC |
| HPD_I | Shigarwa | 1 | Filogi mai zafi gano siginar shigarwa. An haɗa tushen zuwa nutsewa, kuma siginar HPD ya kamata ya zama babba. |
| SDA_I | Shigarwa | 1 | I2C shigarwar bayanan serial don DDC |
| EDID_CLK_I | Shigarwa | 1 | Agogon tsarin don module I2C |
| BIT_SLIP_R_O | Fitowa | 1 | Siginar zamewa Bit zuwa tashar "R" na transceiver |
| BIT_SLIP_G_O | Fitowa | 1 | Siginar zamewa Bit zuwa tashar "G" na transceiver |
| Sunan tashar jiragen ruwa | Hanyar | Nisa (Bits) | Bayani |
| BIT_SLIP_B_O | Fitowa | 1 | Siginar zamewa Bit zuwa tashar "B" na transceiver |
| VIDEO_DATA_VALID_O | Fitowa | 1 | Bayanan bidiyo ingantacce fitarwa |
| AUDIO_DATA_VALID_O | Fitowa 1 | 1 | Bayanan odiyo ingantaccen fitarwa |
| H_SYNC_O | Fitowa | 1 | A tsaye bugun bugun jini |
| V_SYNC_O | Fitowa | 1 | bugun jini na daidaita aiki a tsaye |
| DATA_ RATE_O | Fitowa | 16 | Farashin data Rx. Waɗannan su ne ƙimar ƙimar bayanai:
|
| R_O | Fitowa | LAMBAR PIXELS ✕ Zurfin Launi | Decoded "R" data |
| G_O | Fitowa | LAMBAR PIXELS ✕ Zurfin Launi | Decoded "G" data |
| B_O | Fitowa | LAMBAR PIXELS ✕ Zurfin Launi | Decoded "B" data |
| SDA_O | Fitowa | 1 | I2C serial data fitarwa na DDC |
| HPD_O | Fitowa | 1 | Hot fulogi gano siginar fitarwa |
| ACR_CTS_O | Fitowa | 20 | Agogon Audio Lokacin Zagayowar Farkoamp daraja |
| ACR_N_O | Fitowa | 20 | Ƙimar Sake Haɓaka Sauti (N) siga |
| ACR_VALID_O | Fitowa | 1 | Sake Haɓaka Agogon Sauti mai inganci |
| AUDIO_SAMPLE_CH1_O | Fitowa | 24 | Channel 1 audio sampda data |
| AUDIO_SAMPLE_CH2_O | Fitowa | 24 | Channel 2 audio sampda data |
| AUDIO_SAMPLE_CH3_O | Fitowa | 24 | Channel 3 audio sampda data |
| AUDIO_SAMPLE_CH4_O | Fitowa | 24 | Channel 4 audio sampda data |
| AUDIO_SAMPLE_CH5_O | Fitowa | 24 | Channel 5 audio sampda data |
| AUDIO_SAMPLE_CH6_O | Fitowa | 24 | Channel 6 audio sampda data |
| AUDIO_SAMPLE_CH7_O | Fitowa | 24 | Channel 7 audio sampda data |
| AUDIO_SAMPLE_CH8_O | Fitowa | 24 | Channel 8 audio sampda data |
Testbench Simulation (Tambaya Tambaya)
Ana ba da Testbench don duba ayyukan HDMI RX core. Testbench yana aiki ne kawai a cikin Interface na asali lokacin da adadin pixels ya zama ɗaya.
Don kwaikwayi ainihin abin da ke amfani da testbench, yi matakai masu zuwa:
- A cikin Tagar Tsarin Zane, faɗaɗa Ƙirƙiri Zane.
- Danna-dama Ƙirƙiri SmartDesign Testbench, sannan danna Run, kamar yadda aka nuna a cikin adadi mai zuwa.
Hoto na 5-1. Ƙirƙirar SmartDesign Testbench
- Shigar da suna don SmartDesign testbench, sa'an nan kuma danna Ok.
Hoto na 5-2. Sunan SmartDesign Testbench
SmartDesign testbench an ƙirƙira, kuma zane ya bayyana a hannun dama na Fane Flow Design. - Kewaya zuwa Libro® SoC Catalog, zaɓi View > Windows > IP Catalog, sa'an nan kuma fadada Magani-Video. Danna HDMI RX IP sau biyu (v5.4.0) sannan danna Ok.
- Zaɓi duk tashoshin jiragen ruwa, danna-dama kuma zaɓi Ƙara zuwa Babban Matsayi.
- A kan mashaya kayan aikin SmartDesign, danna Ƙirƙirar Bangaren.
- A shafin Stimulus Hierarchy, danna-dama HDMI_RX_TB bench test file, sannan danna Simulate Pre-Synth Design> Buɗe Interactively.
Kayan aikin ModelSim® yana buɗewa tare da bench, kamar yadda aka nuna a cikin adadi mai zuwa.
Hoto na 5-3. ModelSim Tool tare da HDMI RX Testbench File
Muhimmi: If an katse simulation saboda iyakar lokacin gudu da aka ƙayyade a cikin DO file, yi amfani da run-duk umarnin don kammala simulation.
Lasisi (Tambaya Tambaya)
Ana samar da HDMI RX IP tare da zaɓuɓɓukan lasisi guda biyu masu zuwa:
- Rufaffen: An ba da cikakken rufaffiyar lambar RTL don ainihin. Ana samun kyauta tare da kowane lasisin Libero, yana ba da damar ci gaba da kasancewa tare da SmartDesign. Kuna iya yin Simulation, Synthesis, Layout, da tsara silikon FPGA ta amfani da ɗakin ƙirar Libero.
- RTL: Cikakken lambar tushen RTL an kulle lasisi, wanda ke buƙatar siya daban.
Sakamakon kwaikwayo (Tambaya Tambaya)
Zane mai zuwa na lokaci don HDMI RX IP yana nuna bayanan bidiyo da lokutan bayanan sarrafawa.
Hoto na 6-1. Bayanan Bidiyo
Zane mai zuwa yana nuna abubuwan hsync da vsync don madaidaicin bayanan sarrafawa.
Hoto na 6-2. Daidaita Daidaitawa da Siginonin Daidaitawa a tsaye
Zane mai zuwa yana nuna ɓangaren EDID.
Hoto na 6-3. Siginan EDID
Amfani da Albarkatu (Tambaya Tambaya)
Ana aiwatar da HDMI RX IP a cikin PolarFire® FPGA (MPF300T - Kunshin 1FCG1152I). Tebur mai zuwa yana lissafin albarkatun da aka yi amfani da su lokacin da Yawan Pixels = 1 pixels.
Table 7-1. Amfani da Albarkatu don Yanayin Pixel 1
| Tsarin launi | Zurfin Launi | SCRAMBLER | Fabric 4LUT | Farashin DFF | Farashin 4LUT | Farashin DFF | uSRAM (64×12) | LSRAM (20k) |
| RGB | 8 | A kashe | 987 | 1867 | 360 | 360 | 0 | 10 |
| 10 | A kashe | 1585 | 1325 | 456 | 456 | 11 | 9 | |
| 12 | A kashe | 1544 | 1323 | 456 | 456 | 11 | 9 | |
| 16 | A kashe | 1599 | 1331 | 492 | 492 | 14 | 9 | |
| YCbCr422 | 8 | A kashe | 1136 | 758 | 360 | 360 | 3 | 9 |
| YCbCr444 | 8 | A kashe | 1105 | 782 | 360 | 360 | 3 | 9 |
| 10 | A kashe | 1574 | 1321 | 456 | 456 | 11 | 9 | |
| 12 | A kashe | 1517 | 1319 | 456 | 456 | 11 | 9 | |
| 16 | A kashe | 1585 | 1327 | 492 | 492 | 14 | 9 |
Tebur mai zuwa yana lissafin albarkatun da aka yi amfani da su lokacin da Yawan Pixels = 4 pixels.
Table 7-2. Amfani da Albarkatu don Yanayin Pixel 4
| Tsarin launi | Zurfin Launi | SCRAMBLER | Fabric 4LUT | Farashin DFF | Farashin 4LUT | Farashin DFF | uSRAM (64×12) | LSRAM (20k) |
| RGB | 8 | A kashe | 1559 | 1631 | 1080 | 1080 | 9 | 27 |
| 12 | A kashe | 1975 | 2191 | 1344 | 1344 | 31 | 27 | |
| 16 | A kashe | 1880 | 2462 | 1428 | 1428 | 38 | 27 | |
| RGB | 10 | Kunna | 4231 | 3306 | 1008 | 1008 | 3 | 27 |
| 12 | Kunna | 4253 | 3302 | 1008 | 1008 | 3 | 27 | |
| 16 | Kunna | 3764 | 3374 | 1416 | 1416 | 37 | 27 | |
| YCbCr422 | 8 | A kashe | 1485 | 1433 | 912 | 912 | 7 | 23 |
| YCbCr444 | 8 | A kashe | 1513 | 1694 | 1080 | 1080 | 9 | 27 |
| 12 | A kashe | 2001 | 2099 | 1344 | 1344 | 31 | 27 | |
| 16 | A kashe | 1988 | 2555 | 1437 | 1437 | 38 | 27 |
Tebur mai zuwa yana lissafin albarkatun da aka yi amfani da su lokacin da aka kunna Adadin Pixels = 4 pixel da SCRAMBLER.
Table 7-3. An Kunna Amfani da Albarkatu don Yanayin Pixel 4 da SCRAMBLER
| Tsarin launi | Zurfin Launi | SCRAMBLER | Fabric 4LUT | Farashin DFF | Farashin 4LUT | Farashin DFF | uSRAM (64×12) | LSRAM (20k) |
| RGB | 8 | Kunna | 5029 | 5243 | 1126 | 1126 | 9 | 28 |
| YCbCr422 | 8 | Kunna | 4566 | 3625 | 1128 | 1128 | 13 | 27 |
| YCbCr444 | 8 | Kunna | 4762 | 3844 | 1176 | 1176 | 17 | 27 |
Haɗin Tsari (Tambaya Tambaya)
Wannan sashe yana nuna yadda ake haɗa IP cikin ƙirar Libero.
Tebur mai zuwa yana lissafin jeri na PF XCVR, PF TX PLL da PF CCC da ake buƙata don ƙuduri daban-daban da faɗin bit.
Table 8-1. PF XCVR, PF TX PLL da PF CCC Configuration
| Ƙaddamarwa | Nisa Bit | PF XCVR Kanfigareshan | CDR REF CLOCK PADS | PF CCC Kanfigareshan | |||
| Rahoton da aka ƙayyade na RX | RX CDR Ref Mitar Agogo | Nisa Fabric RX PCS | Mitar shigarwa | Yawan fitarwa | |||
| 1 PXL (1080p60) | 8 | 1485 | 148.5 | 10 | AE27, AE28 | NA | NA |
| 1 PXL (1080p30) | 10 | 1485 | 148.5 | 10 | AE27, AE28 | 92.5 | 74 |
| 12 | 1485 | 148.5 | 10 | AE27, AE28 | 74.25 | 111.375 | |
| 16 | 1485 | 148.5 | 10 | AE27, AE28 | 74.25 | 148.5 | |
| 4 PXL (1080p60) | 8 | 1485 | 148.5 | 40 | AE27, AE28 | NA | NA |
| 12 | 1485 | 148.5 | 40 | AE27, AE28 | 55.725 | 37.15 | |
| 16 | 1485 | 148.5 | 40 | AE27, AE28 | 74.25 | 37.125 | |
| 4 PXL (4kp30) | 8 | 1485 | 148.5 | 40 | AE27, AE28 | NA | NA |
| 10 | 3712.5 | 148.5 | 40 | AE29, AE30 | 92.81 | 74.248 | |
| 12 | 4455 | 148.5 | 40 | AE29, AE30 | 111.375 | 74.25 | |
| 16 | 5940 | 148.5 | 40 | AE29, AE30 | 148.5 | 74.25 | |
| 4 PXL (4Kp60) | 8 | 5940 | 148.5 | 40 | AE29, AE30 | NA | NA |
HDMI RX Sampda Design 1: Lokacin da aka saita a Zurfin Launi = 8-bit da Adadin Pixels = Yanayin pixel 1, ana nuna su a cikin adadi mai zuwa.
Hoto na 8-1. HDMI RX Sampda Design 1
Don misaliample, a cikin saitunan 8-bit, abubuwan da ke biyowa sune ɓangaren ƙira:
- PF_XCVR_ERM (PF_XCVR_ERM_C0_0) an saita don TX da RX cikakken yanayin duplex. Adadin bayanan RX na 1485 Mbps a cikin yanayin PMA, tare da saita faɗin bayanan azaman 10 bit don yanayin 1 PXL da agogon tunani 148.5 MHz CDR. Adadin bayanan TX na 1485 Mbps a cikin yanayin PMA, tare da faɗin bayanan da aka saita azaman 10 bit tare da ƙimar rabon agogo 4.
- LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK da LANE3_CDR_REF_CLK ana fitar dasu daga PF_XCVR_REF_CLK tare da AE27, AE28 Pad fil.
- EDID CLK_I fil yakamata a tura shi da agogon 150 MHz tare da CCC.
- R_RX_CLK_I, G_RX_CLK_I da B_RX_CLK_I LANE3_TX_CLK_R, LANE2_TX_CLK_R da LANE1_TX_CLK_R ne ke jagorantar su.
- R_RX_VALID_I, G_RX_VALID_I da B_RX_VALID_I LANE3_RX_VAL, LANE2_RX_VAL da LANE1_RX_VAL, bi da bi.
- DATA_R_I, DATA_G_I da DATA_B_I LANE3_RX_DATA, LANE2_RX_DATA da LANE1_RX_DATA ne ke tafiyar da su.
HDMI RX Sampda Design 2: Lokacin da aka saita a Zurfin Launi = 8-bit da Adadin Pixels = Yanayin pixel 4, ana nuna su a cikin adadi mai zuwa.
Hoto na 8-2. HDMI RX Sampda Design 2
Don misaliample, a cikin saitunan 8-bit, abubuwan da ke biyowa sune ɓangaren ƙira:
- PF_XCVR_ERM (PF_XCVR_ERM_C0_0) an saita don TX da RX cikakken yanayin duplex. Adadin bayanan RX na 1485 Mbps a cikin yanayin PMA, tare da saita faɗin bayanan azaman 40 bit don yanayin 4 PXL da agogon tunani 148.5 MHz CDR. Adadin bayanan TX na 1485 Mbps a cikin yanayin PMA, tare da faɗin bayanan da aka saita azaman 40 bit tare da ƙimar rabon agogo 4.
- LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK da LANE3_CDR_REF_CLK ana fitar dasu daga PF_XCVR_REF_CLK tare da AE27, AE28 Pad fil.
- EDID CLK_I fil yakamata a tura shi da agogon 150 MHz tare da CCC.
- R_RX_CLK_I, G_RX_CLK_I da B_RX_CLK_I LANE3_TX_CLK_R, LANE2_TX_CLK_R da LANE1_TX_CLK_R ne ke jagorantar su.
- R_RX_VALID_I, G_RX_VALID_I da B_RX_VALID_I LANE3_RX_VAL, LANE2_RX_VAL da LANE1_RX_VAL, bi da bi.
- DATA_R_I, DATA_G_I da DATA_B_I LANE3_RX_DATA, LANE2_RX_DATA da LANE1_RX_DATA ne ke tafiyar da su.
HDMI RX Sampda Design 3: Lokacin da aka saita a Zurfin Launi = 8-bit da Adadin Pixels = Yanayin pixel 4 da SCRAMBLER = An kunna, ana nunawa a cikin adadi mai zuwa.
Hoto na 8-3. HDMI RX Sampda Design 3
Don misaliample, a cikin saitunan 8-bit, abubuwan da ke biyowa sune ɓangaren ƙira:
- PF_XCVR_ERM (PF_XCVR_ERM_C0_0) an tsara shi don yanayin TX da RX masu zaman kansu. Adadin bayanan RX na 5940 Mbps a cikin yanayin PMA, tare da saita faɗin bayanan azaman 40 bit don yanayin 4 PXL da agogon tunani na 148.5 MHz CDR. Adadin bayanan TX na 5940 Mbps a cikin yanayin PMA, tare da faɗin bayanan da aka saita azaman 40 bit tare da ma'aunin rarraba agogo 4.
- LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK da LANE3_CDR_REF_CLK ana fitar dasu daga PF_XCVR_REF_CLK tare da AF29, AF30 Pad fil.
- EDID CLK_I fil ya kamata ya tuƙi tare da agogon 150 MHz tare da CCC.
- R_RX_CLK_I, G_RX_CLK_I da B_RX_CLK_I LANE3_TX_CLK_R, LANE2_TX_CLK_R da LANE1_TX_CLK_R ne ke jagorantar su.
- R_RX_VALID_I, G_RX_VALID_I da B_RX_VALID_I LANE3_RX_VAL, LANE2_RX_VAL da LANE1_RX_VAL, bi da bi.
- DATA_R_I, DATA_G_I da DATA_B_I LANE3_RX_DATA, LANE2_RX_DATA da LANE1_RX_DATA ne ke tafiyar da su.
HDMI RX Sampda Design 4: Lokacin da aka saita a Zurfin Launi = 12-bit da Adadin Pixels = Yanayin pixel 4 da SCRAMBLER = An kunna, ana nunawa a cikin adadi mai zuwa.
Hoto na 8-4. HDMI RX Sampda Design 4
Don misaliample, a cikin saitunan 12-bit, abubuwan da ke biyowa sune ɓangaren ƙira:
- PF_XCVR_ERM (PF_XCVR_ERM_C0_0) an saita shi don yanayin RX Kawai. Adadin bayanan RX na 4455 Mbps a cikin yanayin PMA, tare da saita faɗin bayanan azaman 40 bit don yanayin 4 PXL da agogon tunani na 148.5 MHz CDR.
- LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK da LANE3_CDR_REF_CLK ana fitar dasu daga PF_XCVR_REF_CLK tare da AF29, AF30 Pad fil.
- EDID CLK_I fil ya kamata ya tuƙi tare da agogon 150 MHz tare da CCC.
- R_RX_CLK_I, G_RX_CLK_I da B_RX_CLK_I LANE3_TX_CLK_R, LANE2_TX_CLK_R da LANE1_TX_CLK_R ne ke jagorantar su.
- R_RX_VALID_I, G_RX_VALID_I da B_RX_VALID_I LANE3_RX_VAL, LANE2_RX_VAL da LANE1_RX_VAL, bi da bi.
- DATA_R_I, DATA_G_I da DATA_B_I LANE3_RX_DATA, LANE2_RX_DATA da LANE1_RX_DATA ne ke tafiyar da su.
- Tsarin PF_CCC_C0 yana samar da agogo mai suna OUT0_FABCLK_0 tare da mitar 74.25 MHz, wanda aka samo daga agogon shigarwa na 111.375 MHz, wanda LANE1_RX_CLK_R ke tafiyar da shi.
HDMI RX Sampda Design 5: Lokacin da aka saita a Zurfin Launi = 8-bit, Adadin Pixels = Yanayin pixel 4 da SCRAMBLER = An kunna shi a cikin adadi mai zuwa. Wannan ƙirar ƙira ce mai ƙarfi na bayanai tare da DRI.
Hoto na 8-5. HDMI RX Sampda Design 5
Don misaliample, a cikin saitunan 8-bit, abubuwan da ke biyowa sune ɓangaren ƙira:
- An saita PF_XCVR_ERM (PF_XCVR_ERM_C0_0) don yanayin RX Kawai tare da kunna fasalin sake daidaitawa. Adadin bayanan RX na 5940 Mbps a cikin yanayin PMA, tare da saita faɗin bayanan azaman 40 bit don yanayin 4 PXL da agogon tunani na 148.5 MHz CDR.
- LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK da LANE3_CDR_REF_CLK ana fitar dasu daga PF_XCVR_REF_CLK tare da AF29, AF30 Pad fil.
- EDID CLK_I fil ya kamata ya tuƙi tare da agogon 150 MHz tare da CCC.
- R_RX_CLK_I, G_RX_CLK_I da B_RX_CLK_I LANE3_TX_CLK_R, LANE2_TX_CLK_R da LANE1_TX_CLK_R ne ke jagorantar su.
- R_RX_VALID_I, G_RX_VALID_I da B_RX_VALID_I LANE3_RX_VAL, LANE2_RX_VAL da LANE1_RX_VAL, bi da bi.
- DATA_R_I, DATA_G_I da DATA_B_I LANE3_RX_DATA, LANE2_RX_DATA da LANE1_RX_DATA ne ke tafiyar da su.
Tarihin Bita (Tambaya Tambaya)
Tarihin bita ya bayyana canje-canjen da aka aiwatar a cikin takaddar. Canje-canjen an jera su ta bita, farawa da mafi kyawun ɗaba'ar.
Table 9-1. Tarihin Bita
| Bita | Kwanan wata | Bayani |
| D | 02/2025 | Mai zuwa shine jerin canje-canjen da aka yi a cikin bita C na daftarin aiki:
|
| C | 02/2023 | Mai zuwa shine jerin canje-canjen da aka yi a cikin bita C na daftarin aiki:
|
| B | 09/2022 | Mai zuwa shine jerin canje-canjen da aka yi a cikin bita na B na takaddar:
|
| A | 04/2022 | Mai zuwa shine jerin canje-canje a cikin bita A na daftarin aiki:
|
| 2.0 | — | Mai zuwa shine taƙaitaccen canje-canjen da aka yi a cikin wannan bita.
|
| 1.0 | 08/2021 | Bita na farko. |
Tallafin FPGA Microchip
Ƙungiyar samfuran Microchip FPGA tana goyan bayan samfuran ta tare da sabis na tallafi daban-daban, gami da Sabis na Abokin Ciniki, Cibiyar Tallafin Fasaha ta Abokin Ciniki, a website, da ofisoshin tallace-tallace na duniya. Ana ba abokan ciniki shawarar ziyartar albarkatun kan layi na Microchip kafin tuntuɓar tallafi saboda da yuwuwar an riga an amsa tambayoyinsu. Tuntuɓi Cibiyar Tallafawa Fasaha ta hanyar websaiti a www.microchip.com/support. Ambaci lambar Sashe na Na'urar FPGA, zaɓi nau'in shari'ar da ta dace, da ƙaddamar da ƙira files yayin ƙirƙirar shari'ar tallafin fasaha. Tuntuɓi Sabis na Abokin Ciniki don tallafin samfur mara fasaha, kamar farashin samfur, haɓaka samfur, sabunta bayanai, matsayin tsari, da izini.
- Daga Arewacin Amirka, kira 800.262.1060
- Daga sauran duniya, kira 650.318.4460
- Fax, daga ko'ina cikin duniya, 650.318.8044
Bayanin Microchip
Alamomin kasuwanci
Sunan “Microchip” da tambarin, tambarin “M”, da sauran sunaye, tambura, da alamu suna rajista da alamun kasuwanci marasa rijista na Microchip Technology Incorporated ko alaƙa da/ko rassanta a Amurka da/ko wasu ƙasashe (“Microchip). Alamar kasuwanci")). Ana iya samun bayanai game da Alamar kasuwanci ta Microchip a https://www.microchip.com/en-us/about/legal-information/microchip-trademarks.
ISBN: 979-8-3371-0744-8
Sanarwa na Shari'a
Ana iya amfani da wannan ɗaba'ar da bayanin nan tare da samfuran Microchip kawai, gami da ƙira, gwadawa, da haɗa samfuran Microchip tare da aikace-aikacenku. Amfani da wannan bayanin ta kowace hanya ya saba wa waɗannan sharuɗɗan. Bayani game da aikace-aikacen na'ura an bayar da shi ne kawai don jin daɗin ku kuma ana iya maye gurbinsu da sabuntawa. Alhakin ku ne don tabbatar da cewa aikace-aikacenku ya dace da ƙayyadaddun bayananku. Tuntuɓi ofishin tallace-tallace na Microchip na gida don ƙarin tallafi ko, sami ƙarin tallafi a www.microchip.com/en-us/support/design-help/client-support-services.
WANNAN BAYANI AN BAYAR DA MICROCHIP "KAMAR YADDA". MICROCHIP BA YA YI WAKILI KO GARANTIN KOWANE IRIN BAYANI KO BAYANI, RUBUTU KO BAKI, DOKA KO SAURAN BA, GAME DA BAYANIN GAME DA BAYANI AMMA BAI IYA IYAKA GA WANI GARGADI BA, DA KYAUTATA DON MUSAMMAN MANUFAR, KO GARANTIN DA KE DANGANTA DA SHARADINSA, INGANCI, KO AIKINSA.
BABU WANI FARKO MICROCHIP BA ZAI IYA HANNU GA DUK WATA BAYANI NA MUSAMMAN, HUKUNCI, MASU FARU, KO SAKAMAKON RASHI, LALATA, KUDI, KO KUDI NA KOWANE IRIN ABINDA YA DANGANE BAYANI KO SAMUN HANYAR AMFANINSA, ANA SHAWARAR DA YIWU KO LALACEWAR DA AKE SANYA. ZUWA CIKAKKIYAR DOKA, JAMA'AR DOKAR MICROCHIP A KAN DUK DA'AWA A KOWANE HANYA DAKE DANGANTA BAYANI KO AMFANINSA BA ZAI WUCE YAWAN KUDADE BA, IDAN WATA, CEWA KA BIYA GASKIYA GA GADON.
Amfani da na'urorin Microchip a cikin tallafin rayuwa da/ko aikace-aikacen aminci gabaɗaya yana cikin haɗarin mai siye, kuma mai siye ya yarda ya kare, ramuwa da riƙe Microchip mara lahani daga kowane lalacewa, iƙirari, dacewa, ko kashe kuɗi sakamakon irin wannan amfani. Ba a isar da lasisi, a fakaice ko akasin haka, ƙarƙashin kowane haƙƙin mallaka na Microchip sai dai in an faɗi haka.
Siffar Kariyar Lambar Na'urorin Microchip
Kula da cikakkun bayanai masu zuwa na fasalin kariyar lambar akan samfuran Microchip:
- Samfuran Microchip sun haɗu da ƙayyadaddun bayanai da ke ƙunshe a cikin takamaiman takaddar bayanan Microchip ɗin su.
- Microchip ya yi imanin cewa dangin samfuran sa suna da tsaro lokacin da aka yi amfani da su ta hanyar da aka yi niyya, cikin ƙayyadaddun aiki, da kuma ƙarƙashin yanayi na yau da kullun.
- Ƙimar Microchip kuma tana kare haƙƙin mallaka na fasaha da ƙarfi. Ƙoƙarin keta fasalin kariyar lambar samfuran Microchip an haramta shi sosai kuma yana iya keta Dokar Haƙƙin mallaka ta Millennium Digital.
- Babu Microchip ko duk wani masana'anta na semiconductor ba zai iya tabbatar da amincin lambar sa ba. Kariyar lambar ba yana nufin muna ba da garantin cewa samfurin “ba zai karye ba”. Kariyar lambar tana ci gaba da haɓakawa. Microchip ya himmatu don ci gaba da haɓaka fasalin kariyar lambar samfuranmu.
© 2025 Microchip Technology Inc. da rassansa
FAQ
- Tambaya: Ta yaya zan sabunta HDMI RX IP core?
A: Ana iya sabunta tushen IP ta hanyar software na Libero SoC ko kuma zazzage shi da hannu daga kasida. Da zarar an shigar da shi a cikin software na Libero SoC IP Catalog, ana iya daidaita shi, ƙirƙira, da kuma sanya shi cikin SmartDesign don haɗawa cikin aikin.
Takardu / Albarkatu
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