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MICROCHIP PolarFire FPGA High Definition Multimedia Interface HDMI nnata

MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-nnata- Ngwaahịa-Oyiyi

Okwu mmalite (Jụọ ajụjụ)
Ihe nnabata IP nke Microchip's High-Definition Multimedia Interface (HDMI) na-akwado data vidiyo na nnabata data ngwugwu ọdịyo akọwara na nkọwa ọkọlọtọ HDMI. HDMI RX IP bụ kpọmkwem maka PolarFire® FPGA na PolarFire System on Chip (SoC) FPGA ngwaọrụ na-akwado HDMI 2.0 maka mkpebi ruo 1920 × 1080 na 60 Hz na otu pixel mode na ruo 3840 × 2160 na 60 Hz na anọ pixel mode. RX IP na-akwado Hot Plug Detect (HPD) maka nlekota ike ma ọ bụ gbanyụọ ma wepụ ma ọ bụ nkwụnye ihe omume iji gosi nkwurịta okwu n'etiti isi iyi HDMI na HDMI sink.

Isi iyi HDMI na-eji ọwa Data Ngosipụta (DDC) gụọ data njirimara Extended Display (EDID) iji chọpụta nhazi na/ma ọ bụ ike nke Sink. HDMI RX IP nwere EDID emebere ya, nke isi iyi HDMI nwere ike ịgụ site na ọwa I2C ọkọlọtọ. A na-eji PolarFire FPGA na PolarFire SoC FPGA transceivers ngwaọrụ yana RX IP iji mebie data serial n'ime data 10-bit. A na-ekwe ka ọwa data dị na HDMI nwee nnukwu skew n'etiti ha. HDMI RX IP na-ewepụ skew n'etiti ọwa data site na iji First-In First-Out (FIFO). IP a na-atụgharị data Transition Minimized Differential Signaling (TMDS) enwetara site na isi iyi HDMI site na transceiver n'ime data pixel 24-bit RGB, data ọdịyo 24-bit na akara njikwa. A na-eji akara akara njikwa ọkọlọtọ anọ akọwapụtara na protocol HDMI iji kwado data ahụ n'oge nrụpụta.

Nchịkọta

Tebụlụ na-esonụ na-enye nchịkọta nke àgwà HDMI RX IP.

Tebụl 1. HDMI RX IP Njirimara

Ụdị isi Ntuziaka onye ọrụ a na-akwado HDMI RX IP v5.4.
Ezinụlọ Ngwaọrụ akwadoro
  • PolarFire® SoC
  • PolarFire
Ngwa Ngwa akwadoro Chọrọ mwepụta Libero® SoC v12.0 ma ọ bụ emechaa.
Ihe ntanetị akwadoro Interface nke HDMI RX IP kwadoro bụ:
  • AXI4-Stream: Isi a na-akwado AXI4-Stream na ọdụ ụgbọ mmiri mmepụta. Mgbe ahaziri ya na ọnọdụ a, IP na-ewepụta akara ngosi mkpesa ọkọlọtọ AXI4 Stream.
  • Nwa amaala: Mgbe ahaziri ya na ọnọdụ a, IP na-ewepụta akara ngosi vidiyo na ọdịyo obodo.
Inye ikike Enyere HDMI RX IP na nhọrọ ikike abụọ ndị a:
  • Ezoro ezo: Enyere koodu RTL ezoro ezo zuru oke maka isi. Ọ dị maka n'efu site na iji ikike ọ bụla nke Libero, na-eme ka isi nweta ya na SmartDesign ozugbo. Ị nwere ike ịme Simulation, Synthesis, Layout na hazie silicon FPGA site na iji ụlọ ọrụ Libero.
  • RTL: Koodu isi mmalite RTL zuru ezu ka akpọchiri ikike, nke kwesịrị ịzụrụ iche.

Atụmatụ

HDMI RX IP nwere atụmatụ ndị a:

  • Dakọtara maka HDMI 2.0
  • Na-akwado 8, 10, 12 na 16 Bits Omimi Agba
  • Na-akwado Ụdị agba dị ka RGB, YUV 4: 2: 2 na YUV 4: 4: 4
  • Na-akwado otu pikselụ ma ọ bụ anọ kwa ntinye elekere
  • Na-akwado mkpebi ruo 1920 ✕ 1080 na 60 Hz na otu Pixel mode yana ruo 3840✕ 2160 na 60 Hz na ọnọdụ Pixel anọ.
  • Na-achọpụta ihe nkwụnye ọkụ
  • Na-akwado atụmatụ ngbanwe - TMDS
  • Na-akwado ntinye DVI
  • Na-akwado ọwa data ngosi (DDC) yana ọwa data ngosi emelitere (E-DDC)
  • Na-akwado Native na AXI4 Stream Video Interface maka ịnyefe data vidiyo
  • Na-akwado Native na AXI4 Stream Audio Interface maka nnyefe data ọdịyo

Atụmatụ anaghị akwado

Ndị a bụ njirimara HDMI RX IP anaghị akwado:

  • 4: 2: 0 ụdị agba anaghị akwado.
  • Akwa Dynamic Range (HDR) na nchekwa ọdịnaya dijitalụ dị elu (HDCP) adịghị akwado.
  • A naghị akwado ọnụego ume ọhụrụ agbanwe agbanwe (VRR) na Ụdị nkwụsịtụ obere akpaaka (ALLM).
  • A naghị akwado usoro oge kwụ ọtọ nke anọ na-ekewaghị na ọnọdụ Pixel anọ.

Ntuziaka nwụnye
A ga-etinyerịrị isi IP na katalọgụ IP nke ngwanrọ Libero® SoC na-akpaghị aka site na ọrụ mmelite IP Catalog dị na ngwanrọ Libero SoC, ma ọ bụ jiri aka budata ya na katalọgụ. Ozugbo etinyere isi IP na Libero SoC software IP katalọgụ, a na-ahazi ya, mepụta ya na ozugbo n'ime Smart Design maka itinye na ọrụ Libero.

Ngwaọrụ Isi mmalite nwalere (Jụọ ajụjụ)

Tebụl na-esonụ na-edepụta ngwaọrụ isi mmalite anwalela.

Isiokwu 1-1. Ngwaọrụ Isi mmalite nwalere

Ngwaọrụ Ụdị Pixel A nwalere mkpebi Omimi Agba (Bit) Ụdị agba Audio
quantumdata™ M41h HDMI Analyzer 1 720P 30 FPS, 720P 60 FPS na 1080P 60 FPS 8 RGB, YUV444 na YUV422 Ee
1080P 30 FPS 8, 10, 12 na 16
4 720P 30 FPS, 1080P 30 FPS na 4K 60 FPS 8
1080P 60 FPS 8, 12 na 16
4K 30 FPS 8, 10, 12 na 16
Lenovo™ 20U1A007IG 1 1080P 60 FPS 8 RGB Ee
4 1080P 60 FPS na 4K 30 FPS
Dell Latitude 3420 1 1080P 60 FPS 8 RGB Ee
4 4K 30 FPS na 4K 60 FPS
Astro VA-1844A HDMI® nwale 1 720P 30 FPS, 720P 60 FPS na 1080P 60 FPS 8 RGB, YUV444 na YUV422 Ee
1080P 30 FPS 8, 10, 12 na 16
4 720P 30 FPS, 1080P 30 FPS na 4K 30 FPS 8
1080P 30 FPS 8, 12 na 16
NVIDIA® Jetson AGX Orin 32GB H01 Kit 1 1080P 30 FPS 8 RGB Mba
4 4K 60 FPS

HDMI RX IP nhazi (Jụọ ajụjụ)

Akụkụ a na-enye ihe nfeview nke HDMI RX IP Configurator interface na akụkụ ya. HDMI RX IP Configurator na-enye interface eserese iji guzobe isi HDMI RX. Onye nhazi a na-enye onye ọrụ ohere ịhọrọ paramita dị ka Ọnụ ọgụgụ nke Pixels, Ọnụọgụ nke ọwa ọdịyo, Interface Video, Audio Interface, SCRAMBLER, Depth Agba, Ụdị agba, Testbench na License. Ihe nrụnye nhazi na-agụnye menu ndọpụta na nhọrọ iji hazie ntọala. A kọwara nhazi igodo ndị ahụ na Tebụl 4-1. Ọnụ ọgụgụ na-esonụ na-enye nkọwa zuru ezu view nke HDMI RX IP Configurator interface.

Ọgụgụ 2-1. HDMI RX IP nhazi

MICROCHIP-PolarFire-FPGA-Nkọwa dị elu-Multimedia-Interface-HDMI- Nnata- (1)

Ọhụụ ahụ tinyekwara bọtịnụ OK na Kagbuo iji kwado ma ọ bụ tụfuo nhazi ahụ.

Mmejuputa ngwaike (Jụọ ajụjụ)

Ọnụọgụ ndị a na-akọwa HDMI RX IP interface nwere transceiver (XCVR).

Ọgụgụ 3-1. Ihe osise HDMI RX Block

MICROCHIP-PolarFire-FPGA-Nkọwa dị elu-Multimedia-Interface-HDMI- Nnata- (2)

Ọgụgụ 3-2. Eserese ngọngọ zuru ezu nke nnata

MICROCHIP-PolarFire-FPGA-Nkọwa dị elu-Multimedia-Interface-HDMI- Nnata- (3)

HDMI RX nwere s atọtages:

  • Usoro aligner na-ahazi data agbakwunyere n'ihe gbasara akara akara akara site na iji transceiver bit slip.
  • Ihe ngbanwe TMDS na-atụgharị data 10-bit etinyere ka ọ bụrụ data pikselụ vidiyo 8-bit, data ngwugwu ọdịyo 4-bit na akara njikwa 2-bit.
  • Ndị FIFO na-ewepụ skew n'etiti elekere R, G na B ụzọ.

Nhazi usoro (Jụọ ajụjụ)
Data myirịta 10-bit sitere na XCVR anaghị adabara mgbe niile n'ihe gbasara oke mkpụrụokwu TMDS. Ọ dị mkpa ka gbanwetụrụ data ndị ahụ n'otu n'otu wee kwekọọ iji dekọọ data ahụ. Nhazi nke usoro na-ahazi data ndakọrịta na-abata na oke okwu site na iji njirimara bit-slip dị na XCVR. XCVR na Per-Monitor DPI Awareness (PMA) mode na-enye ohere njiri mwepu, ebe ọ na-edozi nhazi nke okwu 10-bit deserialized site na 1-bit. Oge ọ bụla, mgbe emezigharịrị okwu 10-bit site na 1 bit slip ọnọdụ, a na-atụnyere ya na nke ọ bụla n'ime akara akara anọ nke usoro HDMI iji kpọchie ọnọdụ ahụ n'oge oge njikwa. Okwu 10-bit ka ahaziri nke ọma wee were ya na ọ dabara maka s na-esotetages. Ọwa agba ọ bụla nwere nhazi usoro nke ya, ihe nrụzi TMDS na-amalite ngbanwe naanị mgbe akpọchiri usoro niile iji dozie oke okwu.

TMDS Decoder (Jụọ ajụjụ)
Ihe ngbanwe nke TMDS na-akọwapụta 10-bit deserialized site na transceiver n'ime data pixel 8-bit n'oge vidiyo. A na-emepụta HSYNC, VSYNC na PACKET HEADER n'oge njikwa site na data ọwa blue 10-bit. A na-edobe data ngwungwu ọdịyo na ọwa R na G nke ọ bụla nwere bit anọ. Ihe ngbanwe TMDS nke ọwa ọ bụla na-arụ ọrụ na elekere nke ya. N'ihi ya, ọ nwere ike inwe ụfọdụ skew n'etiti ọwa.

Ọwa ka ọwa De-Skew (Jụọ ajụjụ)
A na-eji ezi uche de-skew dabere na FIFO iji wepụ skew n'etiti ọwa. Ọwa ọ bụla na-enweta mgbama ziri ezi site na nkeji nhazi oge iji gosi ma ọ bụrụ na data 10-bit na-abata sitere na nhazi usoro dị irè. Ọ bụrụ na ọwa niile dị irè (enwetala nhazi oge), FIFO modul na-amalite ịnyefe data site na modul FIFO site na iji akara na-agụ ma dee na-enyere aka (na-aga n'ihu na-ede ma na-agụpụta). Mgbe achọpụtara akara njikwa na nke ọ bụla n'ime ihe FIFO, a na-akwụsịtụ ịgbasa agụpụta, a na-emepụta akara ngosi achọpụtara iji gosi mbata nke otu akara na iyi vidiyo. Usoro agụpụta na-amaliteghachi naanị mgbe akara a rutere na ọwa atọ ahụ. N'ihi ya, a na-ewepụ skew dị mkpa. FIFO nke elekere abụọ na-emekọrịta iyi data atọ niile na elekere igwe anụnụ anụnụ iji wepụ skew dị mkpa. Ọnụ ọgụgụ na-esonụ na-akọwa ọwa ka ọwa de-skew Usoro.

Ọgụgụ 3-3. Ọwa ka ọwa De-Skew

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DDC (Jụọ ajụjụ)
DDC bụ ọwa nkwukọrịta dabere na nkọwa ụgbọ ala I2C. Isi mmalite na-eji iwu I2C gụọ ozi sitere na E-EDID sink nwere adreesị ohu. HDMI RX IP na-eji EDID buru ụzọ kọwapụta yana ọtụtụ mkpebi na-akwado mkpebi ruo 1920 ✕ 1080 na 60 Hz na otu Pixel mode yana ruo 3840✕ 2160 na 60 Hz na ọnọdụ Pixel anọ.
EDID na-anọchi anya aha ngosi dị ka ihe ngosi Microchip HDMI.

Ihe ngosi HDMI RX na akara ngosi (Jụọ ajụjụ)

Akụkụ a na-atụle paramita dị na HDMI RX GUI configurator na akara I/O.

Nhazi nhazi (Jụọ ajụjụ)
Tebụlụ na-esonụ na-edepụta usoro nhazi na HDMI RX IP.

Isiokwu 4-1. Nhazi nhazi

Aha oke Nkọwa
Ụdị agba Na-akọwa oghere agba. Na-akwado usoro agba ndị a:
  • RGB
  • YCbCr422
  • YCbCr444
Omimi agba Na-akọwapụta ọnụọgụ nke ibe n'ibe kwa mpaghara agba. Na-akwado 8, 10, 12 na 16 bit kwa akụrụngwa.
Ọnụ ọgụgụ pikselụ Na-egosi ọnụọgụ pikselụ kwa ntinye elekere:
  • Pixel kwa elekere = 1
  • Pixel kwa elekere = 4
SCRAMBLER Nkwado maka mkpebi 4K na okpokolo agba 60 kwa nkeji:
  • Mgbe 1, agbanyere nkwado Scrambler
  • Mgbe 0, nkwado Scrambler nwere nkwarụ
Ọnụọgụ ọwa ọdịyo Na-akwado ọnụọgụ ọwa ọdịyo:
  • 2 ọwa ọdịyo
  • 8 ọwa ọdịyo
Ntinye Video iyi nke ala na AXI
Interface ọdịyo iyi nke ala na AXI
Nwale oche Na-enye ohere nhọrọ nke gburugburu bench ule. Na-akwado nhọrọ bench ule ndị a:
  • Onye ọrụ
  • Ọ dịghị
Ikikere Na-akọwapụta ụdị akwụkwọ ikike. Na-enye nhọrọ ikike abụọ ndị a:
  • RTL
  • ezoro ezo

Ọdụ ụgbọ mmiri (Jụọ ajụjụ)
Tebụlụ na-esote depụtara ọdụ ụgbọ mmiri ntinye na mmepụta nke HDMI RX IP maka interface ala ala mgbe Ụdị agba bụ RGB.

Isiokwu 4-2. Ntinye na ntinye maka interface obodo

Aha mgbaàmà Ntuziaka Obosara (Bits) Nkọwa
RESET_N_I Ntinye 1 Mgbama nrụpụta asynchronous dị ala na-arụ ọrụ
R_RX_CLK_I Ntinye 1 Okirikiri elekere maka ọwa “R” sitere na XCVR
G_RX_CLK_I Ntinye 1 Okirikiri elekere maka ọwa “G” sitere na XCVR
B_RX_CLK_I Ntinye 1 Okirikiri elekere maka ọwa “B” sitere na XCVR
EDID_RESET_N_I Ntinye 1 Mgbama nrụpụta nrụgharị asynchronous dị ala na-arụ ọrụ
R_RX_VALID_I Ntinye 1 Mgbama ziri ezi sitere na XCVR maka data myirịta ọwa "R".
G_RX_VALID_I Ntinye 1 Mgbama ziri ezi sitere na XCVR maka data myirịta ọwa "G".
B_RX_VALID_I Ntinye 1 Mgbama ziri ezi sitere na XCVR maka data myirịta ọwa "B".
Aha mgbaàmà Ntuziaka Obosara (Bits) Nkọwa
DATA_R_I Ntinye Ọnụọgụ PIXELS ✕ 10bit Anatara data ọwa “R” na XCVR
DATA_G_I Ntinye Ọnụọgụ PIXELS ✕ 10bit Anatara data ọwa “G” n'otu n'otu sitere na XCVR
DATA_B_I Ntinye Ọnụọgụ PIXELS ✕ 10bit Anatara data ọwa "B" data n'otu n'otu site na XCVR
SCL_I Ntinye 1 Ntinye elekere I2C maka DDC
HPD_I Ntinye 1 Nkwụnye ọkụ chọpụta mgbama ntinye. Ejikọrọ isi iyi na mgbama HPD sink kwesịrị ịdị elu.
SDA_I Ntinye 1 Ntinye data serial I2C maka DDC
EDID_CLK_I Ntinye 1 Elekere sistemụ maka modul I2C
BIT_SLIP_R_O Mpụta 1 Mgbama ntanye Bit na ọwa “R” nke transceiver
BIT_SLIP_G_O Mpụta 1 Mgbama ntanye Bit gaa na ọwa “G” nke transceiver
BIT_SLIP_B_O Mpụta 1 Mgbama ntanye Bit na ọwa “B” nke transceiver
VIDIO_DATA_VALID_O Mpụta 1 Ntinye data vidiyo dabara adaba
AUDIO_DATA_VALID_O Mpụta 1 Data ọdịyo dị irè mmepụta
H_SYNC_O Mpụta 1 Ọkụ mmekọrịta kwụ ọtọ
V_SYNC_O Mpụta 1 Ụda mmekọrịta kwụ ọtọ na-arụ ọrụ
R_O Mpụta Ọnụọgụ PIXELS ✕ Omimi agba Decoded "R" data
G_O Mpụta Ọnụọgụ PIXELS ✕ Omimi agba Decoded "G" data
B_O Mpụta Ọnụọgụ PIXELS ✕ Omimi agba Decoded "B" data
SDA_O Mpụta 1 Mmepụta data serial I2C maka DDC
HPD_O Mpụta 1 Nkwụnye ọkụ chọpụta mgbama mmepụta
ACR_CTS_O Mpụta 20 Oge mmụgharị elekere ọdịyoamp uru
ACR_N_O Mpụta 20 Oke elekere mmụgharị ọdịyo (N).
ACR_VALID_O Mpụta 1 Mgbama nrụgharị elekere ọdịyo dabara adaba
AUDIO_SAMPLE_CH1_O Mpụta 24 Ọwa 1 audio sampna data
AUDIO_SAMPLE_CH2_O Mpụta 24 Ọwa 2 audio sampna data
AUDIO_SAMPLE_CH3_O Mpụta 24 Ọwa 3 audio sampna data
AUDIO_SAMPLE_CH4_O Mpụta 24 Ọwa 4 audio sampna data
AUDIO_SAMPLE_CH5_O Mpụta 24 Ọwa 5 audio sampna data
AUDIO_SAMPLE_CH6_O Mpụta 24 Ọwa 6 audio sampna data
AUDIO_SAMPLE_CH7_O Mpụta 24 Ọwa 7 audio sampna data
AUDIO_SAMPLE_CH8_O Mpụta 24 Ọwa 8 audio sampna data
HDMI_DVI_MODE_O Mpụta 1 Ndị a bụ usoro abụọ a:
  • 1: HDMI mode
  • 0: ụdị DVI

Tebụlụ na-esonụ na-akọwa ntinye na ọdụ ụgbọ mmiri mmepụta nke HDMI RX IP maka AXI4 Stream Video Interface.
Isiokwu 4-3. Ọdụ ụgbọ mmiri ntinye na ntinye maka AXI4 Stream Video Interface

Aha Port Ntuziaka Obosara (Bits) Nkọwa
TDATA_O Mpụta Ọnụọgụ PIXELS ✕ Omimi Agba ✕ 3 bit Ihe ngosi vidiyo [R, G, B]
TVALID_O Mpụta 1 Vidiyo mpụta ziri ezi
Aha Port Ntuziaka Obosara (Bits) Nkọwa
TLAST_O Mpụta 1 Mgbama njedebe etiti mmepụta
TUSER_O Mpụta 3
  • bit 0 = VSYNC
  • bit 1 = Hsync
  •  nkeji 2 = 0
  • nkeji 3 = 0
TSTRB_O Mpụta 3 Mpụta vidiyo data strobe
TKEEP_O Mpụta 3 Debe data vidiyo mmepụta

Tebụlụ na-esonụ na-akọwa ntinye na ọdụ ụgbọ mmiri nke HDMI RX IP maka AXI4 Stream Audio Interface.

Isiokwu 4-4. Ọdụ ụgbọ mmiri ntinye na ntinye maka AXI4 Stream Audio Interface

Aha Port Ntuziaka Obosara (Bits) Nkọwa
AUDIO_TDATA_O Mpụta 24 Wepụta data ọdịyo
AUDIO_TID_O Mpụta 3 Ọwa ọdịyo pụta
AUDIO_TVALID_O Mpụta 1 Mgbama ọdịyo dabara adaba

Tebụlụ na-esote depụtara ọdụ ụgbọ mmiri ntinye na mmepụta nke HDMI RX IP maka interface obodo mgbe Ụdị agba bụ YUV444.

Isiokwu 4-5. Ntinye na ntinye maka interface obodo

Aha Port Ntuziaka Obosara (Bits) Nkọwa
RESET_N_I Ntinye 1 Mgbama nrụpụta asynchronous dị ala na-arụ ọrụ
LANE3_RX_CLK_I Ntinye 1 Okirikiri elekere maka ọwa Lane 3 sitere na XCVR
LANE2_RX_CLK_I Ntinye 1 Okirikiri elekere maka ọwa Lane 2 sitere na XCVR
LANE1_RX_CLK_I Ntinye 1 Okirikiri elekere maka ọwa Lane 1 sitere na XCVR
EDID_RESET_N_I Ntinye 1 Mgbama nrụpụta nrụgharị asynchronous dị ala na-arụ ọrụ
LANE3_RX_VALID_I Ntinye 1 Mgbama ziri ezi sitere na XCVR maka data yiri Lane 3
LANE2_RX_VALID_I Ntinye 1 Mgbama ziri ezi sitere na XCVR maka data yiri Lane 2
LANE1_RX_VALID_I Ntinye 1 Mgbama ziri ezi sitere na XCVR maka data yiri Lane 1
DATA_LANE3_I Ntinye Ọnụọgụ PIXELS ✕ 10bit Enwetara data myirịta Lane 3 site na XCVR
DATA_LANE2_I Ntinye Ọnụọgụ PIXELS ✕ 10bit Enwetara data myirịta Lane 2 site na XCVR
DATA_LANE1_I Ntinye Ọnụọgụ PIXELS ✕ 10bit Enwetara data myirịta Lane 1 site na XCVR
SCL_I Ntinye 1 Ntinye elekere I2C maka DDC
HPD_I Ntinye 1 Nkwụnye ọkụ chọpụta mgbama ntinye. Ejikọrọ isi iyi na mgbama HPD sink kwesịrị ịdị elu.
SDA_I Ntinye 1 Ntinye data serial I2C maka DDC
EDID_CLK_I Ntinye 1 Elekere sistemụ maka modul I2C
BIT_SLIP_LANE3_O Mpụta 1 Mgbama ntanye Bit na Lane 3 nke transceiver
BIT_SLIP_LANE2_O Mpụta 1 Mgbama ntanye Bit na Lane 2 nke transceiver
BIT_SLIP_LANE1_O Mpụta 1 Mgbama ntanye Bit na Lane 1 nke transceiver
VIDIO_DATA_VALID_O Mpụta 1 Ntinye data vidiyo dabara adaba
AUDIO_DATA_VALID_O Mpụta 1 Data ọdịyo dị irè mmepụta
H_SYNC_O Mpụta 1 Ọkụ mmekọrịta kwụ ọtọ
V_SYNC_O Mpụta 1 Ụda mmekọrịta kwụ ọtọ na-arụ ọrụ
Aha Port Ntuziaka Obosara (Bits) Nkọwa
Y_O Mpụta Ọnụọgụ PIXELS ✕ Omimi agba Decoded "Y" data
Cb_O Mpụta Ọnụọgụ PIXELS ✕ Omimi agba Decoded "Cb" data
Cr_O Mpụta Ọnụọgụ PIXELS ✕ Omimi agba Decoded "Cr" data
SDA_O Mpụta 1 Mmepụta data serial I2C maka DDC
HPD_O Mpụta 1 Nkwụnye ọkụ chọpụta mgbama mmepụta
ACR_CTS_O Mpụta 20 Oge mmụgharị elekere ọdịyoamp uru
ACR_N_O Mpụta 20 Oke elekere mmụgharị ọdịyo (N).
ACR_VALID_O Mpụta 1 Mgbama nrụgharị elekere ọdịyo dabara adaba
AUDIO_SAMPLE_CH1_O Mpụta 24 Ọwa 1 audio sampna data
AUDIO_SAMPLE_CH2_O Mpụta 24 Ọwa 2 audio sampna data
AUDIO_SAMPLE_CH3_O Mpụta 24 Ọwa 3 audio sampna data
AUDIO_SAMPLE_CH4_O Mpụta 24 Ọwa 4 audio sampna data
AUDIO_SAMPLE_CH5_O Mpụta 24 Ọwa 5 audio sampna data
AUDIO_SAMPLE_CH6_O Mpụta 24 Ọwa 6 audio sampna data
AUDIO_SAMPLE_CH7_O Mpụta 24 Ọwa 7 audio sampna data
AUDIO_SAMPLE_CH8_O Mpụta 24 Ọwa 8 audio sampna data

Tebụlụ na-esote depụtara ọdụ ụgbọ mmiri ntinye na mmepụta nke HDMI RX IP maka interface obodo mgbe Ụdị agba bụ YUV422.

Isiokwu 4-6. Ntinye na ntinye maka interface obodo

Aha Port Ntuziaka Obosara (Bits) Nkọwa
RESET_N_I Ntinye 1 Mgbama nrụpụta asynchronous dị ala na-arụ ọrụ
LANE3_RX_CLK_I Ntinye 1 Okirikiri elekere maka ọwa Lane 3 sitere na XCVR
LANE2_RX_CLK_I Ntinye 1 Okirikiri elekere maka ọwa Lane 2 sitere na XCVR
LANE1_RX_CLK_I Ntinye 1 Okirikiri elekere maka ọwa Lane 1 sitere na XCVR
EDID_RESET_N_I Ntinye 1 Mgbama nrụpụta nrụgharị asynchronous dị ala na-arụ ọrụ
LANE3_RX_VALID_I Ntinye 1 Mgbama ziri ezi sitere na XCVR maka data yiri Lane 3
LANE2_RX_VALID_I Ntinye 1 Mgbama ziri ezi sitere na XCVR maka data yiri Lane 2
LANE1_RX_VALID_I Ntinye 1 Mgbama ziri ezi sitere na XCVR maka data yiri Lane 1
DATA_LANE3_I Ntinye Ọnụọgụ PIXELS ✕ 10bit Enwetara data myirịta Lane 3 site na XCVR
DATA_LANE2_I Ntinye Ọnụọgụ PIXELS ✕ 10bit Enwetara data myirịta Lane 2 site na XCVR
DATA_LANE1_I Ntinye Ọnụọgụ PIXELS ✕ 10bit Enwetara data myirịta Lane 1 site na XCVR
SCL_I Ntinye 1 Ntinye elekere I2C maka DDC
HPD_I Ntinye 1 Nkwụnye ọkụ chọpụta mgbama ntinye. Ejikọrọ isi iyi na mgbama HPD sink kwesịrị ịdị elu.
SDA_I Ntinye 1 Ntinye data serial I2C maka DDC
EDID_CLK_I Ntinye 1 Elekere sistemụ maka modul I2C
BIT_SLIP_LANE3_O Mpụta 1 Mgbama ntanye Bit na Lane 3 nke transceiver
BIT_SLIP_LANE2_O Mpụta 1 Mgbama ntanye Bit na Lane 2 nke transceiver
BIT_SLIP_LANE1_O Mpụta 1 Mgbama ntanye Bit na Lane 1 nke transceiver
VIDIO_DATA_VALID_O Mpụta 1 Ntinye data vidiyo dabara adaba
Aha Port Ntuziaka Obosara (Bits) Nkọwa
AUDIO_DATA_VALID_O Mpụta 1 Data ọdịyo dị irè mmepụta
H_SYNC_O Mpụta 1 Ọkụ mmekọrịta kwụ ọtọ
V_SYNC_O Mpụta 1 Ụda mmekọrịta kwụ ọtọ na-arụ ọrụ
Y_O Mpụta Ọnụọgụ PIXELS ✕ Omimi agba Decoded "Y" data
C_O Mpụta Ọnụọgụ PIXELS ✕ Omimi agba Decoded "C" data
SDA_O Mpụta 1 Mmepụta data serial I2C maka DDC
HPD_O Mpụta 1 Nkwụnye ọkụ chọpụta mgbama mmepụta
ACR_CTS_O Mpụta 20 Oge mmụgharị elekere ọdịyoamp uru
ACR_N_O Mpụta 20 Oke elekere mmụgharị ọdịyo (N).
ACR_VALID_O Mpụta 1 Mgbama nrụgharị elekere ọdịyo dabara adaba
AUDIO_SAMPLE_CH1_O Mpụta 24 Ọwa 1 audio sampna data
AUDIO_SAMPLE_CH2_O Mpụta 24 Ọwa 2 audio sampna data
AUDIO_SAMPLE_CH3_O Mpụta 24 Ọwa 3 audio sampna data
AUDIO_SAMPLE_CH4_O Mpụta 24 Ọwa 4 audio sampna data
AUDIO_SAMPLE_CH5_O Mpụta 24 Ọwa 5 audio sampna data
AUDIO_SAMPLE_CH6_O Mpụta 24 Ọwa 6 audio sampna data
AUDIO_SAMPLE_CH7_O Mpụta 24 Ọwa 7 audio sampna data
AUDIO_SAMPLE_CH8_O Mpụta 24 Ọwa 8 audio sampna data

Tebụlụ na-esonụ depụtara ntinye na ọdụ ụgbọ mmiri mmepụta nke HDMI RX IP maka interface ala ala mgbe SCRAMBLER kwadoro.

Isiokwu 4-7. Ntinye na ntinye maka interface obodo

Aha Port Ntuziaka Obosara (Bits) Nkọwa
RESET_N_I Ntinye 1 Mgbama nrụpụta asynchronous dị ala na-arụ ọrụ
R_RX_CLK_I Ntinye 1 Okirikiri elekere maka ọwa “R” sitere na XCVR
G_RX_CLK_I Ntinye 1 Okirikiri elekere maka ọwa “G” sitere na XCVR
B_RX_CLK_I Ntinye 1 Okirikiri elekere maka ọwa “B” sitere na XCVR
EDID_RESET_N_I Ntinye 1 Mgbama nrụpụta nrụgharị asynchronous dị ala na-arụ ọrụ
HDMI_CABLE_CLK_I Ntinye 1 Elekere USB sitere na isi iyi HDMI
R_RX_VALID_I Ntinye 1 Mgbama ziri ezi sitere na XCVR maka data myirịta ọwa "R".
G_RX_VALID_I Ntinye 1 Mgbama ziri ezi sitere na XCVR maka data myirịta ọwa "G".
B_RX_VALID_I Ntinye 1 Mgbama ziri ezi sitere na XCVR maka data myirịta ọwa "B".
DATA_R_I Ntinye Ọnụọgụ PIXELS ✕ 10bit Anatara data ọwa “R” na XCVR
DATA_G_I Ntinye Ọnụọgụ PIXELS ✕ 10bit Anatara data ọwa “G” n'otu n'otu sitere na XCVR
DATA_B_I Ntinye Ọnụọgụ PIXELS ✕ 10bit Anatara data ọwa "B" data n'otu n'otu site na XCVR
SCL_I Ntinye 1 Ntinye elekere I2C maka DDC
HPD_I Ntinye 1 Nkwụnye ọkụ chọpụta mgbama ntinye. Ejikọtara isi iyi na sink, na mgbaàmà HPD kwesịrị ịdị elu.
SDA_I Ntinye 1 Ntinye data serial I2C maka DDC
EDID_CLK_I Ntinye 1 Elekere sistemụ maka modul I2C
BIT_SLIP_R_O Mpụta 1 Mgbama ntanye Bit na ọwa “R” nke transceiver
BIT_SLIP_G_O Mpụta 1 Mgbama ntanye Bit gaa na ọwa “G” nke transceiver
Aha Port Ntuziaka Obosara (Bits) Nkọwa
BIT_SLIP_B_O Mpụta 1 Mgbama ntanye Bit na ọwa “B” nke transceiver
VIDIO_DATA_VALID_O Mpụta 1 Ntinye data vidiyo dabara adaba
AUDIO_DATA_VALID_O Mmeputa1 1 Data ọdịyo dị irè mmepụta
H_SYNC_O Mpụta 1 Ọkụ mmekọrịta kwụ ọtọ
V_SYNC_O Mpụta 1 Ụda mmekọrịta kwụ ọtọ na-arụ ọrụ
DATA_ RATE_O Mpụta 16 Ọnụego data Rx. Ndị a bụ ụkpụrụ ọnụego data:
  • x1734 = 5940Mbps
  • x0B9A = 2960Mbps
  •  x05CD = 1485 Mbps
  • x2E6 = 742.5Mbps
R_O Mpụta Ọnụọgụ PIXELS ✕ Omimi agba Decoded "R" data
G_O Mpụta Ọnụọgụ PIXELS ✕ Omimi agba Decoded "G" data
B_O Mpụta Ọnụọgụ PIXELS ✕ Omimi agba Decoded "B" data
SDA_O Mpụta 1 Mmepụta data serial I2C maka DDC
HPD_O Mpụta 1 Nkwụnye ọkụ chọpụta mgbama mmepụta
ACR_CTS_O Mpụta 20 Oge mmụgharị elekere ọdịyoamp uru
ACR_N_O Mpụta 20 Oke elekere mmụgharị ọdịyo (N).
ACR_VALID_O Mpụta 1 Mgbama nrụgharị elekere ọdịyo dabara adaba
AUDIO_SAMPLE_CH1_O Mpụta 24 Ọwa 1 audio sampna data
AUDIO_SAMPLE_CH2_O Mpụta 24 Ọwa 2 audio sampna data
AUDIO_SAMPLE_CH3_O Mpụta 24 Ọwa 3 audio sampna data
AUDIO_SAMPLE_CH4_O Mpụta 24 Ọwa 4 audio sampna data
AUDIO_SAMPLE_CH5_O Mpụta 24 Ọwa 5 audio sampna data
AUDIO_SAMPLE_CH6_O Mpụta 24 Ọwa 6 audio sampna data
AUDIO_SAMPLE_CH7_O Mpụta 24 Ọwa 7 audio sampna data
AUDIO_SAMPLE_CH8_O Mpụta 24 Ọwa 8 audio sampna data

Testbench Simulation (Jụọ ajụjụ)

A na-enye Testbench iji lelee ọrụ HDMI RX isi. Testbench na-arụ ọrụ naanị na interface obodo mgbe ọnụọgụ pikselụ bụ otu.

Iji testbench mee ihe isi ihe, mee usoro ndị a:

  1. Na windo Flow imewe, gbasaa Mepụta Design.
  2. Pịa aka nri Mepụta SmartDesign Testbench, wee pịa Run, dị ka egosiri na foto a.
    Ọgụgụ 5-1. Ịmepụta SmartDesign TestbenchMICROCHIP-PolarFire-FPGA-Nkọwa dị elu-Multimedia-Interface-HDMI- Nnata- (5)
  3. Tinye aha maka SmartDesign testbench, wee pịa OK.
    Ọgụgụ 5-2. Ịkpọ SmartDesign TestbenchMICROCHIP-PolarFire-FPGA-Nkọwa dị elu-Multimedia-Interface-HDMI- Nnata- (6)Emepụtara SmartDesign testbench, na kwaaji pụtara n'aka nri nke pane Flow Design.
  4. Gaa na katalọgụ Libero® SoC, họrọ View > Windows > Katalọgụ IP, wee gbasaa Ngwọta-Video. Pịa HDMI RX IP ugboro abụọ (v5.4.0) wee pịa OK.
  5. Họrọ ọdụ ụgbọ mmiri niile, pịa aka nri wee họrọ Kwalite n'ọkwa kacha.
  6. Na SmartDesign ngwá ọrụ mmanya, pịa n'ịwa akụrụngwa.
  7. Na taabụ Stimulus Hierarchy, pịa aka nri HDMI_RX_TB testbench file, wee pịa Simulate Pre-Synth Design> Mepee mmekọrịta.

Ngwá ọrụ ModelSim® na-eji testbench na-emepe, dịka egosiri na foto a.

Ọgụgụ 5-3. Ngwá ọrụ ModelSim nwere HDMI RX Testbench File

MICROCHIP-PolarFire-FPGA-Nkọwa dị elu-Multimedia-Interface-HDMI- Nnata- (7)

Ihe dị mkpa: If a kwụsịrị ịme anwansị ahụ n'ihi oke oge ịgba ọsọ akọwapụtara na DO file, jiri ọsọ-niile iwu imezu simulation.

Ikikere (Jụọ ajụjụ)

Enyere HDMI RX IP na nhọrọ ikike abụọ ndị a:

  • Ezoro ezo: Enyere koodu RTL ezoro ezo zuru oke maka isi. Ọ dị maka n'efu site na iji ikike ọ bụla nke Libero, na-eme ka isi nweta ya na SmartDesign ozugbo. Ị nwere ike ịme Simulation, Synthesis, Layout, na hazie silicon FPGA site na iji ụlọ ọrụ Libero.
  • RTL: Koodu isi mmalite RTL zuru ezu ka akpọchiri ikike, nke kwesịrị ịzụrụ iche.

Nsonaazụ ịme anwansị (Jụọ ajụjụ)

Eserese oge na-esote maka HDMI RX IP na-egosi data vidiyo na oge data njikwa.

Ọgụgụ 6-1. Data vidiyo

MICROCHIP-PolarFire-FPGA-Nkọwa dị elu-Multimedia-Interface-HDMI- Nnata- (8)

Eserese na-esonụ na-egosi mpụta hsync na vsync maka ntinye data njikwa kwekọrọ.

Ọgụgụ 6-2. Mmekọrịta kwụ ọtọ na akara ngosi mmekọrịta kwụ ọtọ

MICROCHIP-PolarFire-FPGA-Nkọwa dị elu-Multimedia-Interface-HDMI- Nnata- (9)

Eserese na-esonụ na-egosi akụkụ EDID.

Ọgụgụ 6-3. Akara ngosi EDID

MICROCHIP-PolarFire-FPGA-Nkọwa dị elu-Multimedia-Interface-HDMI- Nnata- (10)

Iji akụrụngwa (Jụọ ajụjụ)

A na-emejuputa HDMI RX IP na PolarFire® FPGA (ngwugwu MPF300T - 1FCG1152I). Tebụlụ na-esonụ na-edepụta akụrụngwa ejiri mee ihe mgbe Ọnụ ọgụgụ nke pikselụ = 1 pikselụ.

Isiokwu 7-1. Iji akụrụngwa maka 1 Pixel Mode

Ụdị agba Omimi agba SCRAMBLER Akpụkpọ anụ 4LUT Akpụkpọ anụ DFF Interface 4LUT Ọnụ ụzọ DFF USRAM (64×12) LSRAM (20k)
RGB 8 Gbanyụọ 987 1867 360 360 0 10
10 Gbanyụọ 1585 1325 456 456 11 9
12 Gbanyụọ 1544 1323 456 456 11 9
16 Gbanyụọ 1599 1331 492 492 14 9
YCbCr422 8 Gbanyụọ 1136 758 360 360 3 9
YCbCr444 8 Gbanyụọ 1105 782 360 360 3 9
10 Gbanyụọ 1574 1321 456 456 11 9
12 Gbanyụọ 1517 1319 456 456 11 9
16 Gbanyụọ 1585 1327 492 492 14 9

Tebụlụ na-esonụ na-edepụta akụrụngwa ejiri mee ihe mgbe Ọnụ ọgụgụ nke pikselụ = 4 pikselụ.

Isiokwu 7-2. Iji akụrụngwa maka 4 Pixel Mode

Ụdị agba Omimi agba SCRAMBLER Akpụkpọ anụ 4LUT Akpụkpọ anụ DFF Interface 4LUT Ọnụ ụzọ DFF USRAM (64×12) LSRAM (20k)
RGB 8 Gbanyụọ 1559 1631 1080 1080 9 27
12 Gbanyụọ 1975 2191 1344 1344 31 27
16 Gbanyụọ 1880 2462 1428 1428 38 27
RGB 10 Kwado 4231 3306 1008 1008 3 27
12 Kwado 4253 3302 1008 1008 3 27
16 Kwado 3764 3374 1416 1416 37 27
YCbCr422 8 Gbanyụọ 1485 1433 912 912 7 23
YCbCr444 8 Gbanyụọ 1513 1694 1080 1080 9 27
12 Gbanyụọ 2001 2099 1344 1344 31 27
16 Gbanyụọ 1988 2555 1437 1437 38 27

Tebụlụ na-esote depụtara akụrụngwa eji arụ ọrụ mgbe ọnụọgụ pixels = 4 pikselụ na SCRAMBLER agbanyere.

Isiokwu 7-3. Agbanyere akụrụngwa maka ọnọdụ Pixel 4 yana SCRAMBLER

Ụdị agba Omimi agba SCRAMBLER Akpụkpọ anụ 4LUT Akpụkpọ anụ DFF Interface 4LUT Ọnụ ụzọ DFF USRAM (64×12) LSRAM (20k)
RGB 8 Kwado 5029 5243 1126 1126 9 28
YCbCr422 8 Kwado 4566 3625 1128 1128 13 27
YCbCr444 8 Kwado 4762 3844 1176 1176 17 27

Ngwakọta sistemu (Jụọ ajụjụ)

Akụkụ a na-egosi otu esi ejikọta IP n'ime imewe Libero.
Tebụlụ na-esote depụtara nhazi nke PF XCVR, PF TX PLL na PF CCC chọrọ maka mkpebi dị iche iche na obosara bit.

Isiokwu 8-1. PF XCVR, PF TX PLL na PF CCC Nhazi

Mkpebi Obosara Bit Nhazi PF XCVR Mpempe akwụkwọ elekere CDR REF Nhazi PF CCC
Ọnụego data RX Ugboro elekere RX CDR Obosara ákwà PCS RX Ugboro ntinye Ugboro mmepụta
1 PXL (1080p60) 8 1485 148.5 10 AE27, AE28 NA NA
1 PXL (1080p30) 10 1485 148.5 10 AE27, AE28 92.5 74
12 1485 148.5 10 AE27, AE28 74.25 111.375
16 1485 148.5 10 AE27, AE28 74.25 148.5
4 PXL (1080p60) 8 1485 148.5 40 AE27, AE28 NA NA
12 1485 148.5 40 AE27, AE28 55.725 37.15
16 1485 148.5 40 AE27, AE28 74.25 37.125
4 PXL (4kp30) 8 1485 148.5 40 AE27, AE28 NA NA
10 3712.5 148.5 40 AE29, AE30 92.81 74.248
12 4455 148.5 40 AE29, AE30 111.375 74.25
16 5940 148.5 40 AE29, AE30 148.5 74.25
4 PXL (4Kp60) 8 5940 148.5 40 AE29, AE30 NA NA

HDMI RX Sample Design 1: Mgbe ahazi ya na Omimi Agba = 8-bit na Ọnụ ọgụgụ nke Pixels = 1 Pixel mode, egosiri na foto a.

Ọgụgụ 8-1. HDMI RX Sample Design 1

MICROCHIP-PolarFire-FPGA-Nkọwa dị elu-Multimedia-Interface-HDMI- Nnata- (11)

Maka example, na nhazi 8-bit, ihe ndị a bụ akụkụ nke imewe:

  • PF_XCVR_ERM (PF_XCVR_ERM_C0_0) ka ahaziri maka ọnọdụ TX na RX zuru oke. Ọnụego data RX nke 1485 Mbps na ọnọdụ PMA, yana obosara data ahaziri dị ka 10 bit maka ọnọdụ 1 PXL yana elekere ntụaka 148.5 MHz CDR. Ọnụego data TX nke 1485 Mbps na ọnọdụ PMA, yana obosara data ahaziri dị ka 10 bit nwere ihe nkewa elekere 4.
  • LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK na LANE3_CDR_REF_CLK na-achụpụ ya na PF_XCVR_REF_CLK na AE27, AE28 Pad pin.
  • Ekwesịrị iji CCC jiri elekere 150 MHz were EDID CLK_I pin.
  • R_RX_CLK_I, G_RX_CLK_I na B_RX_CLK_I bụ LANE3_TX_CLK_R, LANE2_TX_CLK_R na LANE1_TX_CLK_R, n'otu n'otu.
  • R_RX_VALID_I, G_RX_VALID_I na B_RX_VALID_I bụ LANE3_RX_VAL, LANE2_RX_VAL na LANE1_RX_VAL, n'otu n'otu.
  • DATA_R_I, DATA_G_I na DATA_B_I bụ LANE3_RX_DATA, LANE2_RX_DATA na LANE1_RX_DATA, n'otu n'otu.

HDMI RX Sample Design 2: Mgbe ahazi ya na Omimi Agba = 8-bit na Ọnụ ọgụgụ nke Pixels = 4 Pixel mode, egosiri na foto a.

Ọgụgụ 8-2. HDMI RX Sample Design 2

MICROCHIP-PolarFire-FPGA-Nkọwa dị elu-Multimedia-Interface-HDMI- Nnata- (12)

Maka example, na nhazi 8-bit, ihe ndị a bụ akụkụ nke imewe:

  • PF_XCVR_ERM (PF_XCVR_ERM_C0_0) ka ahaziri maka ọnọdụ TX na RX zuru oke. Ọnụego data RX nke 1485 Mbps na ọnọdụ PMA, yana obosara data ahaziri dị ka 40 bit maka ọnọdụ 4 PXL yana elekere ntụaka 148.5 MHz CDR. Ọnụego data TX nke 1485 Mbps na ọnọdụ PMA, yana obosara data ahaziri dị ka 40 bit nwere ihe nkewa elekere 4.
  • LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK na LANE3_CDR_REF_CLK na-achụpụ ya na PF_XCVR_REF_CLK na AE27, AE28 Pad pin.
  • Ekwesịrị iji CCC jiri elekere 150 MHz were EDID CLK_I pin.
  • R_RX_CLK_I, G_RX_CLK_I na B_RX_CLK_I bụ LANE3_TX_CLK_R, LANE2_TX_CLK_R na LANE1_TX_CLK_R, n'otu n'otu.
  • R_RX_VALID_I, G_RX_VALID_I na B_RX_VALID_I bụ LANE3_RX_VAL, LANE2_RX_VAL na LANE1_RX_VAL, n'otu n'otu.
  • DATA_R_I, DATA_G_I na DATA_B_I bụ LANE3_RX_DATA, LANE2_RX_DATA na LANE1_RX_DATA, n'otu n'otu.

HDMI RX Sample Design 3: Mgbe ahazi ya na Omimi Agba = 8-bit na Ọnụ ọgụgụ nke Pixels = 4 Pixel mode na SCRAMBLER = Kwanyere, egosiri na foto a.

Ọgụgụ 8-3. HDMI RX Sample Design 3

MICROCHIP-PolarFire-FPGA-Nkọwa dị elu-Multimedia-Interface-HDMI- Nnata- (13)

Maka example, na nhazi 8-bit, ihe ndị a bụ akụkụ nke imewe:

  • PF_XCVR_ERM (PF_XCVR_ERM_C0_0) ka ahaziri maka ọnọdụ TX na RX nọọrọ onwe ya. Ọnụego data RX nke 5940 Mbps na ọnọdụ PMA, yana obosara data ahaziri dị ka 40 bit maka ọnọdụ 4 PXL yana elekere ntụaka 148.5 MHz CDR. Ọnụego data TX nke 5940 Mbps na ọnọdụ PMA, yana obosara data ahaziri dị ka 40 bit nwere ihe nkewa elekere 4.
  • LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK na LANE3_CDR_REF_CLK na-achụpụ site na PF_XCVR_REF_CLK na AF29, AF30 Pad pin.
  • EDID CLK_I pin kwesịrị iji elekere 150 MHz jiri CCC kwọọ.
  • R_RX_CLK_I, G_RX_CLK_I na B_RX_CLK_I bụ LANE3_TX_CLK_R, LANE2_TX_CLK_R na LANE1_TX_CLK_R, n'otu n'otu.
  • R_RX_VALID_I, G_RX_VALID_I na B_RX_VALID_I bụ LANE3_RX_VAL, LANE2_RX_VAL na LANE1_RX_VAL, n'otu n'otu.
  • DATA_R_I, DATA_G_I na DATA_B_I bụ LANE3_RX_DATA, LANE2_RX_DATA na LANE1_RX_DATA, n'otu n'otu.

HDMI RX Sample Design 4: Mgbe ahazi ya na Omimi Agba = 12-bit na Ọnụ ọgụgụ nke Pixels = 4 Pixel mode na SCRAMBLER = Kwanyere, egosiri na foto a.

Ọgụgụ 8-4. HDMI RX Sample Design 4

MICROCHIP-PolarFire-FPGA-Nkọwa dị elu-Multimedia-Interface-HDMI- Nnata- (14)

Maka example, na nhazi 12-bit, ihe ndị a bụ akụkụ nke imewe:

  • PF_XCVR_ERM (PF_XCVR_ERM_C0_0) ka ahaziri maka naanị ụdị RX. Ọnụego data RX nke 4455 Mbps na ọnọdụ PMA, yana obosara data ahaziri dị ka 40 bit maka ọnọdụ 4 PXL yana elekere ntụaka 148.5 MHz CDR.
  • LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK na LANE3_CDR_REF_CLK na-achụpụ site na PF_XCVR_REF_CLK na AF29, AF30 Pad pin.
  • EDID CLK_I pin kwesịrị iji elekere 150 MHz jiri CCC kwọọ.
  • R_RX_CLK_I, G_RX_CLK_I na B_RX_CLK_I bụ LANE3_TX_CLK_R, LANE2_TX_CLK_R na LANE1_TX_CLK_R, n'otu n'otu.
  • R_RX_VALID_I, G_RX_VALID_I na B_RX_VALID_I bụ LANE3_RX_VAL, LANE2_RX_VAL na LANE1_RX_VAL, n'otu n'otu.
  • DATA_R_I, DATA_G_I na DATA_B_I bụ LANE3_RX_DATA, LANE2_RX_DATA na LANE1_RX_DATA, n'otu n'otu.
  • Modul PF_CCC_C0 na-ewepụta elekere aha ya bụ OUT0_FABCLK_0 nwere ugboro nke 74.25 MHz, ewepụtara na elekere ntinye nke 111.375 MHz, nke LANE1_RX_CLK_R na-ebugharị.

HDMI RX Sample Design 5: Mgbe a na-ahazi ya na Omimi Agba = 8-bit, Ọnụ ọgụgụ nke Pixels = 4 Pixel mode na SCRAMBLER = Agbanyere na-egosi na foto a. Nhazi a bụ ọnụọgụ data siri ike na DRI.

Ọgụgụ 8-5. HDMI RX Sample Design 5

MICROCHIP-PolarFire-FPGA-Nkọwa dị elu-Multimedia-Interface-HDMI- Nnata- (15)

Maka example, na nhazi 8-bit, ihe ndị a bụ akụkụ nke imewe:

  • PF_XCVR_ERM (PF_XCVR_ERM_C0_0) ka ahaziri maka ọnọdụ RX naanị yana interface nhazigharị ike nwere ike. Ọnụego data RX nke 5940 Mbps na ọnọdụ PMA, yana obosara data ahaziri dị ka 40 bit maka ọnọdụ 4 PXL yana elekere ntụaka 148.5 MHz CDR.
  • LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK na LANE3_CDR_REF_CLK na-achụpụ site na PF_XCVR_REF_CLK na AF29, AF30 Pad pin.
  • EDID CLK_I pin kwesịrị iji elekere 150 MHz jiri CCC kwọọ.
  • R_RX_CLK_I, G_RX_CLK_I na B_RX_CLK_I bụ LANE3_TX_CLK_R, LANE2_TX_CLK_R na LANE1_TX_CLK_R, n'otu n'otu.
  • R_RX_VALID_I, G_RX_VALID_I na B_RX_VALID_I bụ LANE3_RX_VAL, LANE2_RX_VAL na LANE1_RX_VAL, n'otu n'otu.
  • DATA_R_I, DATA_G_I na DATA_B_I bụ LANE3_RX_DATA, LANE2_RX_DATA na LANE1_RX_DATA, n'otu n'otu.

Akụkọ ngbanwe (Jụọ ajụjụ)

Akụkọ ngbanwe ahụ na-akọwa mgbanwe ndị etinyere na akwụkwọ ahụ. Edepụtara mgbanwe ndị a site na ntughari, malite na mbipụta kachasị ugbu a.

Isiokwu 9-1. Akụkọ ngbanwe

Ndozigharị Ụbọchị Nkọwa
D 02/2025 Nke a bụ ndepụta mgbanwe emere na ntughari C nke akwụkwọ ahụ:
  • Emelitere ụdị HDMI RX IP ka ọ bụrụ 5.4.
  • Mmelite emelitere site na njirimara yana atụmatụ anaghị akwado ya.
  • Akụkụ Ngwaọrụ Isi mmalite agbakwunyere.
  • Ọgụgụ 3-1 emelitere na eserese 3-3 na ngalaba Mmejuputa ngwaike.
  • Ngalaba Nhazi agbakwunyere.
  • Isiokwu emelitere 4-2, Tebụl 4-4, Tebụl 4-5, Tebụl 4-6 na Tebụl 4-7 na ngalaba ọdụ ụgbọ mmiri.
  • Ọgụgụ 5-2 emelitere na ngalaba Simulation Testbench.
  • Tebụl 7-1 emelitere na Tebụl 7-2 agbakwunyere Tebụl 7-3 na ngalaba iji akụrụngwa.
  • Ọgụgụ 8-1 emelitere, eserese 8-2, eserese 8-3 na eserese 8-4 na ngalaba njikọta Sistemu.
  • Ọnụego data siri ike agbakwunyere ya na imewe DRI example na System Integration ngalaba.
C 02/2023 Nke a bụ ndepụta mgbanwe emere na ntughari C nke akwụkwọ ahụ:
  • Emelitere ụdị HDMI RX IP ka ọ bụrụ 5.2
  • Emelitere mkpebi akwadoro na ọnọdụ pikselụ anọ n'ime akwụkwọ ahụ dum
  • Ọgụgụ 2-1 emelitere
B 09/2022 Nke a bụ ndepụta mgbanwe emere na ngbanwe B ​​nke akwụkwọ ahụ:
  • Emelitere akwụkwọ maka v5.1
  • Tebụl emelitere 4-2 na tebụl 4-3
A 04/2022 Nke a bụ ndepụta mgbanwe na ntughari A nke akwụkwọ ahụ:
  • Ebugara akwụkwọ a na ndebiri Microchip
  • Emelitere nọmba akwụkwọ ahụ ka ọ bụrụ DS50003298A site na 50200863
  • Akụkụ emelitere TMDS Decoder
  • Tebụl emelitere Tebụl 4-2 na Tebụl 4-3
  •  Ihe osise 5-3 emelitere, eserese 6-1, eserese 6-2
2.0 Ihe na-esonụ bụ nchịkọta mgbanwe ndị emere na nlegharị anya a.
  • Tebụl agbakwunyere 4-3
  • Tebụl ojiji akụrụngwa emelitere
1.0 08/2021 Ndozigharị izizi.

Nkwado FPGA Microchip
Otu ngwaahịa Microchip FPGA na-eji ọrụ nkwado dị iche iche kwado ngwaahịa ya, gụnyere Ọrụ Ndị Ahịa, Ụlọ Ọrụ Nkwado nka na ụzụ Ndị Ahịa, a websaịtị, na ụlọ ahịa ahịa zuru ụwa ọnụ. A na-atụ aro ka ndị ahịa gaa na akụrụngwa Microchip n'ịntanetị tupu ha akpọtụrụ nkwado n'ihi na o yikarịrị ka azaghachila ajụjụ ha. Kpọtụrụ Ụlọ Ọrụ Nkwado nka na ụzụ site na websaịtị na www.microchip.com/support. Kwuo nọmba akụkụ ngwaọrụ FPGA, họrọ udi ikpe dabara adaba, wee bulite imewe files mgbe ị na-ekepụta ikpe nkwado teknụzụ. Kpọtụrụ ọrụ ndị ahịa maka nkwado ngwaahịa na-abụghị teknụzụ, dị ka ọnụ ahịa ngwaahịa, nkwalite ngwaahịa, mmelite ozi, ọkwa ịtụ na ikike.

  • Site na North America, kpọọ 800.262.1060
  • Site na ụwa ndị ọzọ, kpọọ 650.318.4460
  • Fax, si n'ebe ọ bụla n'ụwa, 650.318.8044

Ozi Microchip

Akara ụghalaahia
Aha na akara “Microchip”, akara “M”, na aha ndị ọzọ, akara ngosi, na ụdị bụ aha ụghalaahịa edenyere n'akwụkwọ ikikere nke Microchip Technology Incorporated ma ọ bụ ndị mmekọ na/ma ọ bụ ndị enyemaka na United States na/ma ọ bụ obodo ndị ọzọ (“Microchip). Akara ụghalaahịa”). Enwere ike ịhụ ozi gbasara ụghalaahịa Microchip na https://www.microchip.com/en-us/about/legal-information/microchip-trademarks.

ISBN: 979-8-3371-0744-8

Akwụkwọ Ozi Iwu
Enwere ike iji akwụkwọ a na ozi dị n'ime ya naanị site na ngwaahịa Microchip, gụnyere iji chepụta, nwalee ma jikọta ngwaahịa Microchip na ngwa gị. Iji ozi a n'ụzọ ọ bụla ọzọ mebiri usoro ndị a. A na-enye ozi gbasara ngwa ngwaọrụ naanị maka ịdị mma gị yana mmelite nwere ike dochie ya. Ọ bụ ọrụ gị ịhụ na ngwa gị dabara na nkọwapụta gị. Kpọtụrụ ụlọ ọrụ ịre ahịa Microchip mpaghara gị maka nkwado ọzọ ma ọ bụ nweta nkwado ọzọ na www.microchip.com/en-us/support/design-help/client-support-services.

Ozi a bụ MICROCHIP “DỊ KA Ọ BỤ”. MICROCHIP emeghị nnochite anya ma ọ bụ akwụkwọ ikike n'ụdị ọ bụla ma ekwupụta ma ọ bụ kwupụta ya, edere ma ọ bụ n'ọnụ, usoro iwu ma ọ bụ ọzọ, metụtara ozi ahụ gụnyere mana ọnweghị oke n'iwu ọ bụla na-akwadoghị, iwu na-akwadoghị. NA ahụ dị mma maka ebumnuche pụrụ iche, ma ọ bụ akwụkwọ ikike metụtara ọnọdụ ya, ogo ya, ma ọ bụ arụmọrụ ya.
Ọ BỤGHỊ ỌMỤNỤ Ọ BỤGHỊ MICROCHIP GA-AKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỌ Ọ BỤLA OZI Ọ BỤ Ọ BỤ Ọ BỤLA. AKWỤKWỌ NDỊ NDỊ DỊ MMADỤ N'ỤRỤ IKE MA Ọ BỤ NDỊ MMADỤ AHỤ. Ruo n'ụzọ zuru ezu iwu kwadoro, MICROCHIP'S TOTAL IBLIability na ebubo niile n'ụzọ ọ bụla metụtara ozi ahụ ma ọ bụ ojiji ya agaghị agafe ego nke ụgwọ, ma ọ bụrụ na ọ bụla, na ị kwụrụ ozugbo na-agwa ya.
Iji ngwaọrụ Microchip na nkwado ndụ yana/ma ọ bụ ngwa nchekwa bụ kpamkpam n'ihe ize ndụ nke onye zụrụ ya, onye na-azụ ya kwenyere ịgbachitere, kwụọ ụgwọ ma jide Microchip na-adịghị emerụ ahụ site na mmebi ọ bụla, nkwuputa, uwe, ma ọ bụ mmefu sitere na ụdị ojiji ahụ. Ọnweghị ikike ebugara, n'ezoghị ọnụ ma ọ bụ n'ụzọ ọzọ, n'okpuru ikike ikike ọgụgụ isi Microchip ọ gwụla ma ekwuputaghị ya.

Njirimara Nchekwa Koodu Ngwaọrụ Microchip

Rịba ama nkọwa ndị a nke njirimara nchedo koodu na ngwaahịa Microchip:

  • Ngwaahịa Microchip na-ezute nkọwapụta dị na mpempe data Microchip ha.
  • Microchip kwenyere na ezinaụlọ nke ngwaahịa ya nwere nchekwa mgbe ejiri ya n'ụzọ achọrọ, n'ime nkọwapụta ọrụ yana n'okpuru ọnọdụ nkịtị.
  • Ụkpụrụ Microchip na-eji ike na-echebe ikike ikike ọgụgụ isi ya. Mgbalị imebi njirimara nchedo koodu nke ngwaahịa Microchip bụ nke amachibidoro nke ọma ma nwee ike imebi iwu nwebiisinka nke Millennium Digital.
  • Ma Microchip ma ọ bụ ndị nrụpụta semiconductor ọ bụla enweghị ike ikwe nkwa nchekwa nke koodu ya. Nchedo koodu apụtaghị na anyị na-ekwe nkwa na ngwaahịa a "enweghị ike imebi". Nchekwa koodu na-agbanwe mgbe niile. Microchip agba mbọ na-aga n'ihu na-emeziwanye njirimara nchedo koodu nke ngwaahịa anyị.

© 2025 Microchip Technology Inc. na ndị enyemaka ya

FAQ

  • Ajụjụ: Kedu ka m ga-esi melite HDMI RX IP core?
    A: Enwere ike imelite isi IP site na ngwanrọ Libero SoC ma ọ bụ jiri aka budata ya na katalọgụ. Ozugbo etinyere na sọftụwia Libero SoC IP katalọgụ, enwere ike ịhazi ya, mepụta ya na ozugbo n'ime SmartDesign maka itinye n'ọrụ a.

Akwụkwọ / akụrụngwa

MICROCHIP PolarFire FPGA High Definition Multimedia Interface HDMI nnata [pdf] Ntuziaka onye ọrụ
PolarFire FPGA, PolarFire FPGA High Definition Multimedia Interface HDMI Nnata, Elu Definition Multimedia Interface HDMI Nnata, Multimedia Interface HDMI Nnata, Interface HDMI Nnata, HDMI Nnata.

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