MICROCHIP PolarFire FPGA High Definition Multimedia Interface HDMI Receiver

Chiyambi (Funsani Funso)
Microchip's High-Definition Multimedia Interface (HDMI) wolandila IP amathandizira data yamavidiyo ndi kulandila kwapaketi yapaketi yolongosoledwa mu HDMI standard specification. HDMI RX IP idapangidwira makamaka PolarFire® FPGA ndi PolarFire System on Chip (SoC) FPGA zida zothandizira HDMI 2.0 pazosankha mpaka 1920 × 1080 pa 60 Hz mumayendedwe a pixel imodzi mpaka 3840 × 2160 pa 60 Hz mumayendedwe anayi a pixel. RX IP imathandizira Hot Plug Detect (HPD) powunikira kapena kuzimitsa ndi kutulutsa kapena plug zochitika kuti ziwonetse kulumikizana pakati pa gwero la HDMI ndi sinki ya HDMI.

Gwero la HDMI limagwiritsa ntchito njira ya Display Data (DDC) kuti iwerenge za Sink Extended Display Identification Data (EDID) kuti mudziwe masinthidwe ndi/kapena kuthekera kwa Sink. HDMI RX IP ili ndi EDID yokonzedweratu, yomwe gwero la HDMI limatha kuwerenga kudzera mu njira yokhazikika ya I2C. PolarFire FPGA ndi PolarFire SoC FPGA ma transceivers a chipangizo amagwiritsidwa ntchito limodzi ndi RX IP kuti awononge deta ya serial kukhala 10-bit data. Njira zama data mu HDMI zimaloledwa kukhala ndi skew yayikulu pakati pawo. HDMI RX IP imachotsa skew pakati pa ma data pogwiritsa ntchito First-In First-Out (FIFOs). IP iyi imasintha data ya Transition Minimized Differential Signaling (TMDS) yolandilidwa kuchokera ku HDMI gwero kudzera pa transceiver kupita ku data ya pixel ya 24-bit RGB, data ya 24-bit audio ndi zizindikiro zowongolera. Zizindikiro zinayi zowongolera zomwe zafotokozedwa mu protocol ya HDMI zimagwiritsidwa ntchito kugwirizanitsa deta panthawi ya deerialization.

Chidule

Gome lotsatirali limapereka chidule cha mawonekedwe a HDMI RX IP.

Table 1. HDMI RX IP Makhalidwe

Core Version	Bukuli limathandizira HDMI RX IP v5.4.
Mabanja a Chipangizo Chothandizira	PolarFire® SoC PolarFire
Kuyenda kwa Chida Chothandizira	Imafunika Libero® SoC v12.0 kapena kutulutsidwa pambuyo pake.
Ma Interface Othandizira	Mawonekedwe othandizidwa ndi HDMI RX IP ndi awa: AXI4-Stream: Chigawo ichi chimathandizira AXI4-Stream kumadoko otuluka. Ikakhazikitsidwa motere, IP imatulutsa zizindikiro zodandaula za AXI4 Stream. Wachibadwidwe: Mukakonzedwa motere, IP imatulutsa mavidiyo ndi ma audio.
Kupereka chilolezo	HDMI RX IP imaperekedwa ndi njira ziwiri zotsatirazi: Zosungidwa: Nambala yathunthu ya RTL yosungidwa imaperekedwa pachimake. Imapezeka kwaulere ndi layisensi iliyonse ya Libero, zomwe zimapangitsa kuti mazikowo akhazikitsidwe ndi SmartDesign. Mutha kupanga Mafanizidwe, Kaphatikizidwe, Kapangidwe ndikukonzekera silicon ya FPGA pogwiritsa ntchito Libero design suite. RTL: Khodi yathunthu ya RTL ndi laisensi yotsekedwa, yomwe imayenera kugulidwa padera.

Mawonekedwe

HDMI RX IP ili ndi izi:

• Yogwirizana ndi HDMI 2.0
• Imathandiza 8, 10, 12 ndi 16 Bits Kuzama kwa Mtundu
• Imathandizira Mitundu Yamitundu ngati RGB, YUV 4:2:2 ndi YUV 4:4:4
• Imathandizira Pixels Imodzi kapena Inayi Pakulowetsa kwa Clock
• Imathandizira Resolutions mpaka 1920 ✕ 1080 pa 60 Hz mu One Pixel mode mpaka 3840 ✕ 2160 pa 60 Hz mu Four Pixel mode.
• Imazindikira Hot-plug
• Imathandizira Decoding Scheme - TMDS
• Imathandizira Kuyika kwa DVI
• Imathandizira Display Data Channel (DDC) ndi Njira Yowonjezera Yowonetsera Data (E-DDC)
• Imathandizira Native ndi AXI4 Stream Video Interface ya Video Data Transfer
• Imathandizira Native ndi AXI4 Stream Audio Interface ya Audio Data Transfer

Zosathandiza

Zotsatirazi ndi zosagwirizana ndi HDMI RX IP:

• 4: 2: 0 mtundu mtundu sichimathandizidwa.
• High Dynamic Range (HDR) ndi High-bandwidth Digital Content Protection (HDCP) sizimathandizidwa.
• Variable Refresh Rate (VRR) ndi Auto Low Latency Mode (ALLM) sizothandiza.
• Magawo a Horizontal Timing omwe sagawika ndi anayi mumayendedwe a Four Pixel sagwiritsidwa ntchito.

Malangizo oyika
IP core iyenera kukhazikitsidwa ku IP Catalogue ya pulogalamu ya Libero® SoC yokha kudzera mu pulogalamu ya IP Catalog mu pulogalamu ya Libero SoC, kapena imatsitsidwa pamanja pamndandanda. IP core ikayikidwa mu Libero SoC pulogalamu ya IP Catalog, imakonzedwa, kupangidwa ndikukhazikitsidwa mkati mwa Smart Design kuti iphatikizidwe mu projekiti ya Libero.

Zida Zoyeserera (Funsani Funso)

Pansipa pali mndandanda wa zida zoyesedwa.

Gulu 1-1. Zida Zoyesedwa

Zipangizo	Mtundu wa Pixel	Zosankha Zayesedwa	Kuzama kwa Mtundu (Pang'ono)	Mtundu wamtundu	Zomvera
quantumdata™ M41h HDMI Analyzer	1	720P 30 FPS, 720P 60 FPS ndi 1080P 60 FPS	8	RGB, YUV444 ndi YUV422	Inde
		1080P 30 FPS	8, 10, 12 ndi 16
	4	720P 30 FPS, 1080P 30 FPS ndi 4K 60 FPS	8
		1080P 60 FPS	8, 12 ndi 16
		4K 30 FPS	8, 10, 12 ndi 16
Lenovo™ 20U1A007IG	1	1080P 60 FPS	8	RGB	Inde
	4	1080P 60 FPS ndi 4K 30 FPS
Dell Latitude 3420	1	1080P 60 FPS	8	RGB	Inde
	4	4K 30 FPS ndi 4K 60 FPS
Astro VA-1844A HDMI® Tester	1	720P 30 FPS, 720P 60 FPS ndi 1080P 60 FPS	8	RGB, YUV444 ndi YUV422	Inde
		1080P 30 FPS	8, 10, 12 ndi 16
	4	720P 30 FPS, 1080P 30 FPS ndi 4K 30 FPS	8
		1080P 30 FPS	8, 12 ndi 16
NVIDIA® Jetson AGX Orin 32GB H01 Kit	1	1080P 30 FPS	8	RGB	Ayi
	4	4K 60 FPS

Kukonzekera kwa HDMI RX IP (Funsani Funso)

Chigawo ichi chimapereka chowonjezeraview ya HDMI RX IP Configurator mawonekedwe ndi zigawo zake. HDMI RX IP Configurator imapereka mawonekedwe owonetsera kuti akhazikitse pakati pa HDMI RX. Zosinthazi zimalola wogwiritsa ntchito kusankha magawo monga Nambala ya Pixels, Chiwerengero cha mayendedwe omvera, Chiyankhulo cha Kanema, Chiyankhulo cha Audio, SCRAMBLER, Kuzama kwa Mtundu, Mtundu wa Mtundu, Testbench ndi License. Mawonekedwe a Configurator ali ndi mindandanda yotsitsa ndi zosankha kuti musinthe makonda. Zosintha zazikulu zikufotokozedwa mu Table 4-1. Chithunzi chotsatirachi chikupereka mwatsatanetsatane view ya HDMI RX IP Configurator mawonekedwe.

Chithunzi 2-1. HDMI RX IP Configurator

Mawonekedwewa amaphatikizanso mabatani a OK ndi Cancel kuti atsimikizire kapena kutaya masinthidwe.

Kukhazikitsa kwa Hardware (Funsani Funso)

Ziwerengero zotsatirazi zikufotokoza mawonekedwe a HDMI RX IP okhala ndi transceiver (XCVR).

Chithunzi 3-1. Chithunzi cha HDMI RX Block

Chithunzi 3-2. Chithunzi cha Block Detailed Receiver

HDMI RX ili ndi s atatutages:

• Gawo lolinganiza limagwirizanitsa deta yofananira pokhudzana ndi malire a zizindikiro pogwiritsa ntchito transceiver bit slip.
• Decoder ya TMDS imasintha data yosungidwa ya 10-bit kukhala data ya pixel yamavidiyo 8-bit, data ya paketi ya 4-bit ndi ma siginecha a 2-bit.
• Ma FIFO amachotsa skew pakati pa mawotchi a R, G ndi B.

Phase Aligner (Funsani Funso)
Deta yofananira ya 10-bit yochokera ku XCVR sinthawi zonse imayenderana ndi malire a mawu a TMDS. Deta yofananira iyenera kusinthidwa pang'ono ndikuyanjanitsidwa kuti izindikire deta. Phase aligner imagwirizanitsa zomwe zikubwera zofanana ndi malire a mawu pogwiritsa ntchito mawonekedwe otsetsereka mu XCVR. XCVR mu mawonekedwe a Per-Monitor DPI Awareness (PMA) imalola mawonekedwe otsetsereka pang'ono, pomwe amasinthira kutengera kwa mawu a 10-bit deserialized ndi 1-bit. Nthawi iliyonse, mutatha kusintha mawu a 10-bit ndi malo otsetsereka a 1, amafanizidwa ndi chimodzi mwa zizindikiro zinayi zolamulira za HDMI protocol kuti atseke malo panthawi yolamulira. Mawu a 10-bit amayanjanitsidwa bwino ndipo amaonedwa kuti ndi ovomerezeka kwa s lotsatiratages. Njira iliyonse yamtundu imakhala ndi gawo lake, decoder ya TMDS imayamba kumasulira kokha pamene ma aligners onse atsekedwa kuti akonze malire a mawu.

TMDS Decoder (Funso Funso)
TMDS decoder decode 10-bit deserialized from transceiver kupita ku data ya 8-bit pixel panthawi ya kanema. HSYNC, VSYNC ndi PACKET HEADER amapangidwa panthawi yolamulira kuchokera pa data ya 10-bit blue channel. Deta ya paketi yomvera imayikidwa pa tchanelo cha R ndi G chilichonse ndi ma bits anayi. TMDS decoder ya tchanelo chilichonse imagwira ntchito pa wotchi yake. Chifukwa chake, imatha kukhala ndi mkangano wina pakati pa mayendedwe.

Channel to Channel De-Skew (Funsani Funso)
FIFO yochokera ku de-skew logic imagwiritsidwa ntchito kuchotsa skew pakati pa mayendedwe. Njira iliyonse imalandira chizindikiro chovomerezeka kuchokera kumagulu ogwirizanitsa magawo kuti asonyeze ngati deta yomwe ikubwera ya 10-bit kuchokera ku gawo ili ndi yovomerezeka. Ngati ma tchanelo onse ali ovomerezeka (akwaniritsa kukhazikitsidwa kwa gawo), gawo la FIFO limayamba kutumiza deta kudzera mumodule ya FIFO pogwiritsa ntchito kuwerenga ndi kulemba kumathandizira ma siginecha (kulemba mosalekeza ndikuwerenga). Chizindikiro chowongolera chikazindikirika muzotulutsa zilizonse za FIFO, kutulutsa kowerengera kumayimitsidwa, ndipo chizindikiro chodziwika chimapangidwa kuti chiwonetse kubwera kwa chikhomo china mumtsinje wa kanema. Kuwerenga kowerengera kumayambiranso pokhapokha cholemberachi chafika pamakanema onse atatu. Chifukwa chake, skew yoyenera imachotsedwa. Ma FIFO a mawotchi apawiri amagwirizanitsa mitsinje yonse itatu ya data ku wotchi ya buluu kuti achotse skew yoyenera. Chithunzi chotsatirachi chikufotokoza njira yosinthira njira ya de-skew.

Chithunzi 3-3. Channel kupita ku Channel De-Skew

DDC (Ask a Question)
DDC ndi njira yolumikizirana yotengera ma I2C mabasi. Gwero limagwiritsa ntchito malamulo a I2C kuti muwerenge zambiri kuchokera ku E-EDID ya sink yokhala ndi adilesi ya kapolo. HDMI RX IP imagwiritsa ntchito EDID yodziwikiratu yokhala ndi malingaliro angapo imathandizira malingaliro mpaka 1920 ✕ 1080 pa 60 Hz mu One Pixel mode mpaka 3840 ✕ 2160 pa 60 Hz mu Four Pixel mode.
EDID imayimira dzina lowonetsera ngati chiwonetsero cha Microchip HDMI.

HDMI RX Parameters ndi Interface Signals (Funsani Funso)

Gawoli likukambirana za magawo mu HDMI RX GUI configurator ndi zizindikiro za I / O.

Zosintha Zosintha (Funsani Funso)
Gome lotsatirali likulemba magawo osinthika mu HDMI RX IP.

Gulu 4-1. Zosintha Zosintha

Dzina la Parameter	Kufotokozera
Mtundu wamtundu	Imatanthauzira malo amtundu. Imathandizira mitundu iyi: RGB YCbCr422 YCbCr444
Kuzama Kwamitundu	Imatchula kuchuluka kwa ma bits pamtundu uliwonse. Imathandizira 8, 10, 12 ndi 16 bits pagawo lililonse.
Nambala ya Mapikiselo	Ikuwonetsa kuchuluka kwa ma pixel pa wotchi iliyonse: Pixel pa wotchi = 1 Pixel pa wotchi = 4
SCRAMBLER	Kuthandizira kusamvana kwa 4K pamafelemu 60 pamphindikati: Pamene 1, thandizo la Scrambler limayatsidwa Pamene 0, thandizo la Scrambler limayimitsidwa
Chiwerengero cha makanema omvera	Imathandizira kuchuluka kwa makanema amawu: 2 njira zomvera 8 njira zomvera
Kanema Wamakanema	Native ndi AXI mtsinje
Audio Interface	Native ndi AXI mtsinje
Benchi yoyesera	Amalola kusankha malo oyesera. Imathandizira zosankha zotsatirazi za benchi: Wogwiritsa Palibe
Chilolezo	Imatchula mtundu wa chilolezo. Amapereka njira ziwiri zalayisensi zotsatirazi: Mtengo RTL Zosungidwa

Madoko (Funsani Funso)
Gome lotsatirali limatchula madoko olowera ndi otuluka a HDMI RX IP ya mawonekedwe a Native pomwe Mtundu wa Mtundu uli RGB.

Gulu 4-2. Zolowetsa ndi Zotulutsa za Native Interface

Dzina la Signal	Mayendedwe	M'lifupi (Bits)	Kufotokozera
RESET_N_I	Zolowetsa	1	Chizindikiro chokhazikika chokhazikika chokhazikika
R_RX_CLK_I	Zolowetsa	1	Wotchi yofananira ya njira ya "R" kuchokera ku XCVR
G_RX_CLK_I	Zolowetsa	1	Wotchi yofananira ya tchanelo cha "G" kuchokera ku XCVR
B_RX_CLK_I	Zolowetsa	1	Wotchi yofananira ya tchanelo cha "B" kuchokera ku XCVR
EDID_RESET_N_I	Zolowetsa	1	Chizindikiro chokhazikika cha asynchronous edid chokhazikika
R_RX_VALID_I	Zolowetsa	1	Chizindikiro chovomerezeka kuchokera ku XCVR cha data yofananira ya "R".
G_RX_VALID_I	Zolowetsa	1	Chizindikiro chovomerezeka kuchokera ku XCVR cha data yofananira ya "G".
B_RX_VALID_I	Zolowetsa	1	Chizindikiro chovomerezeka chochokera ku XCVR cha data yofanana ndi tchanelo "B".

Dzina la Signal	Mayendedwe	M'lifupi (Bits)	Kufotokozera
DATA_R_I	Zolowetsa	NUMBER OF PIXELS ✕ 10 bits	Adalandira "R" data yofananira kuchokera ku XCVR
DATA_G_I	Zolowetsa	NUMBER OF PIXELS ✕ 10 bits	Adalandira "G" data yofananira kuchokera ku XCVR
DATA_B_I	Zolowetsa	NUMBER OF PIXELS ✕ 10 bits	Adalandira "B" data yofananira kuchokera ku XCVR
SCL_I	Zolowetsa	1	Kuyika kwa wotchi ya I2C ya DDC
HPD_I	Zolowetsa	1	Pulagi yotentha imazindikira chizindikiro cholowera. Gwero lolumikizidwa ndi sink ya HPD yakuya iyenera kukhala yayikulu.
SDA_ine	Zolowetsa	1	I2C serial data input ya DDC
EDID_CLK_I	Zolowetsa	1	Wotchi yadongosolo ya module ya I2C
BIT_SLIP_R_O	Zotulutsa	1	Chizindikiro chotsetsereka pang'ono kupita ku njira ya "R" ya transceiver
BIT_SLIP_G_O	Zotulutsa	1	Chizindikiro chozembera pang'ono kupita ku njira ya "G" ya transceiver
BIT_SLIP_B_O	Zotulutsa	1	Chizindikiro chozembera pang'ono kupita ku njira ya "B" ya transceiver
VIDEO_DATA_VALID_O	Zotulutsa	1	Kanema deta zomveka linanena bungwe
AUDIO_DATA_VALID_O	Zotulutsa	1	Zomvera zomveka zotuluka
H_SYNC_O	Zotulutsa	1	Chopingasa kulunzanitsa kugunda
V_SYNC_O	Zotulutsa	1	Kuthamanga koyima koyima kokhazikika
R_O	Zotulutsa	NUMBER OF PIXELS ✕ Kuzama kwa mitundu	Decode "R" data
G_O	Zotulutsa	NUMBER OF PIXELS ✕ Kuzama kwa mitundu	Decode "G" data
B_O	Zotulutsa	NUMBER OF PIXELS ✕ Kuzama kwa mitundu	Decode "B" data
SDA_O	Zotulutsa	1	I2C serial data output ya DDC
HPD_O	Zotulutsa	1	Hot pulagi kuzindikira linanena bungwe chizindikiro
ACR_CTS_O	Zotulutsa	20	Audio Clock Regeneration Cycle Timestamp mtengo
ACR_N_O	Zotulutsa	20	Mtengo Wosinthanso Wotchi Yomvera (N).
ACR_VALID_O	Zotulutsa	1	Audio Clock Regeneration chizindikiro chovomerezeka
AUDIO_SAMPLE_CH1_O	Zotulutsa	24	Channel 1 zomveraample data
AUDIO_SAMPLE_CH2_O	Zotulutsa	24	Channel 2 zomveraample data
AUDIO_SAMPLE_CH3_O	Zotulutsa	24	Channel 3 zomveraample data
AUDIO_SAMPLE_CH4_O	Zotulutsa	24	Channel 4 zomveraample data
AUDIO_SAMPLE_CH5_O	Zotulutsa	24	Channel 5 zomveraample data
AUDIO_SAMPLE_CH6_O	Zotulutsa	24	Channel 6 zomveraample data
AUDIO_SAMPLE_CH7_O	Zotulutsa	24	Channel 7 zomveraample data
AUDIO_SAMPLE_CH8_O	Zotulutsa	24	Channel 8 zomveraample data
HDMI_DVI_MODE_O	Zotulutsa	1	Zotsatirazi ndi njira ziwiri: 1: HDMI mode 0: DVI mode

Gome lotsatirali likufotokoza zolowetsa ndi zotuluka za HDMI RX IP ya AXI4 Stream Video Interface.
Gulu 4-3. Zolowetsa ndi Zotulutsa za AXI4 Stream Video Interface

Dzina la Port	Mayendedwe	M'lifupi (Bits)	Kufotokozera
TDATA_O	Zotulutsa	NUMBER OF PIXELS ✕ Kuzama kwa Mtundu ✕ 3 bits	Kanema wotulutsa [R, G, B]
TVALID_O	Zotulutsa	1	Kanema wotuluka ndi wovomerezeka

Dzina la Port	Mayendedwe	M'lifupi (Bits)	Kufotokozera
TLAST_O	Zotulutsa	1	Chizindikiro chakumapeto kwa chimango chotuluka
TUSER_O	Zotulutsa	3	pang'ono 0 = VSYNC pang'ono 1 = Hsync  gawo 2 = 0 gawo 3 = 0
TSTRB_O	Zotulutsa	3	Linanena bungwe kanema deta strobe
TKEEP_O	Zotulutsa	3	Linanena bungwe kanema deta kusunga

Gome lotsatirali likufotokoza zolowetsa ndi zotuluka za HDMI RX IP ya AXI4 Stream Audio Interface.

Gulu 4-4. Zolowetsa ndi Zotulutsa za AXI4 Stream Audio Interface

Dzina la Port	Mayendedwe	M'lifupi (Bits)	Kufotokozera
AUDIO_TDATA_O	Zotulutsa	24	Linanena bungwe zomvetsera
AUDIO_TID_O	Zotulutsa	3	Kutulutsa mawu
AUDIO_TVALID_O	Zotulutsa	1	Kutulutsa mawu siginecha yovomerezeka

Gome lotsatirali limatchula zolowetsa ndi zotuluka za HDMI RX IP ya mawonekedwe a Native pamene Mtundu wa Format ndi YUV444.

Gulu 4-5. Zolowetsa ndi Zotulutsa za Native Interface

Dzina la Port	Mayendedwe	M'lifupi (Bits)	Kufotokozera
RESET_N_I	Zolowetsa	1	Chizindikiro chokhazikika chokhazikika chokhazikika
LANE3_RX_CLK_I	Zolowetsa	1	Wotchi yofananira panjira ya Lane 3 kuchokera ku XCVR
LANE2_RX_CLK_I	Zolowetsa	1	Wotchi yofananira panjira ya Lane 2 kuchokera ku XCVR
LANE1_RX_CLK_I	Zolowetsa	1	Wotchi yofananira panjira ya Lane 1 kuchokera ku XCVR
EDID_RESET_N_I	Zolowetsa	1	Chizindikiro chokhazikika cha asynchronous edid chokhazikika
LANE3_RX_VALID_I	Zolowetsa	1	Chizindikiro chovomerezeka kuchokera ku XCVR pa data yofanana ya Lane 3
LANE2_RX_VALID_I	Zolowetsa	1	Chizindikiro chovomerezeka kuchokera ku XCVR pa data yofanana ya Lane 2
LANE1_RX_VALID_I	Zolowetsa	1	Chizindikiro chovomerezeka kuchokera ku XCVR pa data yofanana ya Lane 1
DATA_LANE3_I	Zolowetsa	NUMBER OF PIXELS ✕ 10 bits	Adalandira data yofananira ya Lane 3 kuchokera ku XCVR
DATA_LANE2_I	Zolowetsa	NUMBER OF PIXELS ✕ 10 bits	Adalandira data yofananira ya Lane 2 kuchokera ku XCVR
DATA_LANE1_I	Zolowetsa	NUMBER OF PIXELS ✕ 10 bits	Adalandira data yofananira ya Lane 1 kuchokera ku XCVR
SCL_I	Zolowetsa	1	Kuyika kwa wotchi ya I2C ya DDC
HPD_I	Zolowetsa	1	Pulagi yotentha imazindikira chizindikiro cholowera. Gwero lolumikizidwa ndi sink ya HPD yakuya iyenera kukhala yayikulu.
SDA_ine	Zolowetsa	1	I2C serial data input ya DDC
EDID_CLK_I	Zolowetsa	1	Wotchi yadongosolo ya module ya I2C
BIT_SLIP_LANE3_O	Zotulutsa	1	Chizindikiro cha Bit Slip kupita ku Lane 3 ya transceiver
BIT_SLIP_LANE2_O	Zotulutsa	1	Chizindikiro cha Bit Slip kupita ku Lane 2 ya transceiver
BIT_SLIP_LANE1_O	Zotulutsa	1	Chizindikiro cha Bit Slip kupita ku Lane 1 ya transceiver
VIDEO_DATA_VALID_O	Zotulutsa	1	Kanema deta zomveka linanena bungwe
AUDIO_DATA_VALID_O	Zotulutsa	1	Zomvera zomveka zotuluka
H_SYNC_O	Zotulutsa	1	Chopingasa kulunzanitsa kugunda
V_SYNC_O	Zotulutsa	1	Kuthamanga koyima koyima kokhazikika

Dzina la Port	Mayendedwe	M'lifupi (Bits)	Kufotokozera
Y_O	Zotulutsa	NUMBER OF PIXELS ✕ Kuzama kwa mitundu	Decode "Y" data
Cb_O	Zotulutsa	NUMBER OF PIXELS ✕ Kuzama kwa mitundu	Decoded "Cb" data
Cr_O	Zotulutsa	NUMBER OF PIXELS ✕ Kuzama kwa mitundu	Decoded "Cr" data
SDA_O	Zotulutsa	1	I2C serial data output ya DDC
HPD_O	Zotulutsa	1	Hot pulagi kuzindikira linanena bungwe chizindikiro
ACR_CTS_O	Zotulutsa	20	Nthawi ya Audio Clock Regeneration Cycleamp mtengo
ACR_N_O	Zotulutsa	20	Mtengo Wosinthanso Wotchi Yomvera (N).
ACR_VALID_O	Zotulutsa	1	Audio Clock Regeneration chizindikiro chovomerezeka
AUDIO_SAMPLE_CH1_O	Zotulutsa	24	Channel 1 zomveraample data
AUDIO_SAMPLE_CH2_O	Zotulutsa	24	Channel 2 zomveraample data
AUDIO_SAMPLE_CH3_O	Zotulutsa	24	Channel 3 zomveraample data
AUDIO_SAMPLE_CH4_O	Zotulutsa	24	Channel 4 zomveraample data
AUDIO_SAMPLE_CH5_O	Zotulutsa	24	Channel 5 zomveraample data
AUDIO_SAMPLE_CH6_O	Zotulutsa	24	Channel 6 zomveraample data
AUDIO_SAMPLE_CH7_O	Zotulutsa	24	Channel 7 zomveraample data
AUDIO_SAMPLE_CH8_O	Zotulutsa	24	Channel 8 zomveraample data

Gome lotsatirali limatchula zolowetsa ndi zotuluka za HDMI RX IP ya mawonekedwe a Native pamene Mtundu wa Format ndi YUV422.

Gulu 4-6. Zolowetsa ndi Zotulutsa za Native Interface

Dzina la Port	Mayendedwe	M'lifupi (Bits)	Kufotokozera
RESET_N_I	Zolowetsa	1	Chizindikiro chokhazikika chokhazikika chokhazikika
LANE3_RX_CLK_I	Zolowetsa	1	Wotchi yofananira panjira ya Lane 3 kuchokera ku XCVR
LANE2_RX_CLK_I	Zolowetsa	1	Wotchi yofananira panjira ya Lane 2 kuchokera ku XCVR
LANE1_RX_CLK_I	Zolowetsa	1	Wotchi yofananira panjira ya Lane 1 kuchokera ku XCVR
EDID_RESET_N_I	Zolowetsa	1	Chizindikiro chokhazikika cha asynchronous edid chokhazikika
LANE3_RX_VALID_I	Zolowetsa	1	Chizindikiro chovomerezeka kuchokera ku XCVR pa data yofanana ya Lane 3
LANE2_RX_VALID_I	Zolowetsa	1	Chizindikiro chovomerezeka kuchokera ku XCVR pa data yofanana ya Lane 2
LANE1_RX_VALID_I	Zolowetsa	1	Chizindikiro chovomerezeka kuchokera ku XCVR pa data yofanana ya Lane 1
DATA_LANE3_I	Zolowetsa	NUMBER OF PIXELS ✕ 10 bits	Adalandira data yofananira ya Lane 3 kuchokera ku XCVR
DATA_LANE2_I	Zolowetsa	NUMBER OF PIXELS ✕ 10 bits	Adalandira data yofananira ya Lane 2 kuchokera ku XCVR
DATA_LANE1_I	Zolowetsa	NUMBER OF PIXELS ✕ 10 bits	Adalandira data yofananira ya Lane 1 kuchokera ku XCVR
SCL_I	Zolowetsa	1	Kuyika kwa wotchi ya I2C ya DDC
HPD_I	Zolowetsa	1	Pulagi yotentha imazindikira chizindikiro cholowera. Gwero lolumikizidwa ndi sink ya HPD yakuya iyenera kukhala yayikulu.
SDA_ine	Zolowetsa	1	I2C serial data input ya DDC
EDID_CLK_I	Zolowetsa	1	Wotchi yadongosolo ya module ya I2C
BIT_SLIP_LANE3_O	Zotulutsa	1	Chizindikiro cha Bit Slip kupita ku Lane 3 ya transceiver
BIT_SLIP_LANE2_O	Zotulutsa	1	Chizindikiro cha Bit Slip kupita ku Lane 2 ya transceiver
BIT_SLIP_LANE1_O	Zotulutsa	1	Chizindikiro cha Bit Slip kupita ku Lane 1 ya transceiver
VIDEO_DATA_VALID_O	Zotulutsa	1	Kanema deta zomveka linanena bungwe

Dzina la Port	Mayendedwe	M'lifupi (Bits)	Kufotokozera
AUDIO_DATA_VALID_O	Zotulutsa	1	Zomvera zomveka zotuluka
H_SYNC_O	Zotulutsa	1	Chopingasa kulunzanitsa kugunda
V_SYNC_O	Zotulutsa	1	Kuthamanga koyima koyima kokhazikika
Y_O	Zotulutsa	NUMBER OF PIXELS ✕ Kuzama kwa mitundu	Decode "Y" data
C_O	Zotulutsa	NUMBER OF PIXELS ✕ Kuzama kwa mitundu	Decode "C" data
SDA_O	Zotulutsa	1	I2C serial data output ya DDC
HPD_O	Zotulutsa	1	Hot pulagi kuzindikira linanena bungwe chizindikiro
ACR_CTS_O	Zotulutsa	20	Nthawi ya Audio Clock Regeneration Cycleamp mtengo
ACR_N_O	Zotulutsa	20	Mtengo Wosinthanso Wotchi Yomvera (N).
ACR_VALID_O	Zotulutsa	1	Audio Clock Regeneration chizindikiro chovomerezeka
AUDIO_SAMPLE_CH1_O	Zotulutsa	24	Channel 1 zomveraample data
AUDIO_SAMPLE_CH2_O	Zotulutsa	24	Channel 2 zomveraample data
AUDIO_SAMPLE_CH3_O	Zotulutsa	24	Channel 3 zomveraample data
AUDIO_SAMPLE_CH4_O	Zotulutsa	24	Channel 4 zomveraample data
AUDIO_SAMPLE_CH5_O	Zotulutsa	24	Channel 5 zomveraample data
AUDIO_SAMPLE_CH6_O	Zotulutsa	24	Channel 6 zomveraample data
AUDIO_SAMPLE_CH7_O	Zotulutsa	24	Channel 7 zomveraample data
AUDIO_SAMPLE_CH8_O	Zotulutsa	24	Channel 8 zomveraample data

Gome lotsatirali likulemba madoko olowera ndi otuluka a HDMI RX IP ya mawonekedwe a Native pomwe SCRABLER Yayatsidwa.

Gulu 4-7. Zolowetsa ndi Zotulutsa za Native Interface

Dzina la Port	Mayendedwe	M'lifupi (Bits)	Kufotokozera
RESET_N_I	Zolowetsa	1	Chizindikiro chokhazikika chokhazikika chokhazikika
R_RX_CLK_I	Zolowetsa	1	Wotchi yofananira ya njira ya "R" kuchokera ku XCVR
G_RX_CLK_I	Zolowetsa	1	Wotchi yofananira ya tchanelo cha "G" kuchokera ku XCVR
B_RX_CLK_I	Zolowetsa	1	Wotchi yofananira ya tchanelo cha "B" kuchokera ku XCVR
EDID_RESET_N_I	Zolowetsa	1	Chizindikiro chokhazikika cha asynchronous edid chokhazikika
HDMI_CABLE_CLK_I	Zolowetsa	1	Wotchi ya chingwe kuchokera ku gwero la HDMI
R_RX_VALID_I	Zolowetsa	1	Chizindikiro chovomerezeka kuchokera ku XCVR cha data yofananira ya "R".
G_RX_VALID_I	Zolowetsa	1	Chizindikiro chovomerezeka kuchokera ku XCVR cha data yofananira ya "G".
B_RX_VALID_I	Zolowetsa	1	Chizindikiro chovomerezeka chochokera ku XCVR cha data yofanana ndi tchanelo "B".
DATA_R_I	Zolowetsa	NUMBER OF PIXELS ✕ 10 bits	Adalandira "R" data yofananira kuchokera ku XCVR
DATA_G_I	Zolowetsa	NUMBER OF PIXELS ✕ 10 bits	Adalandira "G" data yofananira kuchokera ku XCVR
DATA_B_I	Zolowetsa	NUMBER OF PIXELS ✕ 10 bits	Adalandira "B" data yofananira kuchokera ku XCVR
SCL_I	Zolowetsa	1	Kuyika kwa wotchi ya I2C ya DDC
HPD_I	Zolowetsa	1	Pulagi yotentha imazindikira chizindikiro cholowera. Gwero limalumikizidwa ndi kuzama, ndipo chizindikiro cha HPD chiyenera kukhala chokwera.
SDA_ine	Zolowetsa	1	I2C serial data input ya DDC
EDID_CLK_I	Zolowetsa	1	Wotchi yadongosolo ya module ya I2C
BIT_SLIP_R_O	Zotulutsa	1	Chizindikiro chotsetsereka pang'ono kupita ku njira ya "R" ya transceiver
BIT_SLIP_G_O	Zotulutsa	1	Chizindikiro chozembera pang'ono kupita ku njira ya "G" ya transceiver

Dzina la Port	Mayendedwe	M'lifupi (Bits)	Kufotokozera
BIT_SLIP_B_O	Zotulutsa	1	Chizindikiro chozembera pang'ono kupita ku njira ya "B" ya transceiver
VIDEO_DATA_VALID_O	Zotulutsa	1	Kanema deta zomveka linanena bungwe
AUDIO_DATA_VALID_O	Zotulutsa1	1	Zomvera zomveka zotuluka
H_SYNC_O	Zotulutsa	1	Chopingasa kulunzanitsa kugunda
V_SYNC_O	Zotulutsa	1	Kuthamanga koyima koyima kokhazikika
DATA_ RATE_O	Zotulutsa	16	Mtengo wa Rx. Zotsatirazi ndi milingo ya data: x1734 = 5940 Mbps x0B9A = 2960 Mbps  x05CD = 1485 Mbps x2E6 = 742.5 Mbps
R_O	Zotulutsa	NUMBER OF PIXELS ✕ Kuzama kwa mitundu	Decode "R" data
G_O	Zotulutsa	NUMBER OF PIXELS ✕ Kuzama kwa mitundu	Decode "G" data
B_O	Zotulutsa	NUMBER OF PIXELS ✕ Kuzama kwa mitundu	Decode "B" data
SDA_O	Zotulutsa	1	I2C serial data output ya DDC
HPD_O	Zotulutsa	1	Hot pulagi kuzindikira linanena bungwe chizindikiro
ACR_CTS_O	Zotulutsa	20	Nthawi ya Audio Clock Regeneration Cycleamp mtengo
ACR_N_O	Zotulutsa	20	Mtengo Wosinthanso Wotchi Yomvera (N).
ACR_VALID_O	Zotulutsa	1	Audio Clock Regeneration chizindikiro chovomerezeka
AUDIO_SAMPLE_CH1_O	Zotulutsa	24	Channel 1 zomveraample data
AUDIO_SAMPLE_CH2_O	Zotulutsa	24	Channel 2 zomveraample data
AUDIO_SAMPLE_CH3_O	Zotulutsa	24	Channel 3 zomveraample data
AUDIO_SAMPLE_CH4_O	Zotulutsa	24	Channel 4 zomveraample data
AUDIO_SAMPLE_CH5_O	Zotulutsa	24	Channel 5 zomveraample data
AUDIO_SAMPLE_CH6_O	Zotulutsa	24	Channel 6 zomveraample data
AUDIO_SAMPLE_CH7_O	Zotulutsa	24	Channel 7 zomveraample data
AUDIO_SAMPLE_CH8_O	Zotulutsa	24	Channel 8 zomveraample data

Kuyerekeza kwa Testbench (Funsani Funso)

Testbench imaperekedwa kuti iwonetse magwiridwe antchito a HDMI RX pachimake. Testbench imagwira ntchito mu Native Interface pomwe chiwerengero cha pixel chili chimodzi.

Kuti muyesere pachimake pogwiritsa ntchito testbench, chitani izi:

1. Muwindo la Design Flow, onjezerani Pangani Design.
2. Dinani kumanja Pangani SmartDesign Testbench, ndiyeno dinani Thamangani, monga momwe chithunzichi chikusonyezera.
   Chithunzi 5-1. Kupanga SmartDesign Testbench
3. Lowetsani dzina la SmartDesign testbench, kenako dinani Chabwino.
   Chithunzi 5-2. Kutchula SmartDesign TestbenchSmartDesign testbench idapangidwa, ndipo chinsalu chikuwoneka kumanja kwa gawo la Design Flow.
4. Pitani ku Libero® SoC Catalog, sankhani View > Mawindo > IP Catalog, ndiyeno kuwonjezera Solutions-Video. Dinani kawiri HDMI RX IP (v5.4.0) ndiyeno dinani Chabwino.
5. Sankhani madoko onse, dinani kumanja ndikusankha Kwezani Kumtunda Wapamwamba.
6. Pazida za SmartDesign, dinani Pangani Chigawo.
7. Pa tabu ya Stimulus Hierarchy, dinani kumanja HDMI_RX_TB testbench file, ndiyeno dinani Sanzirani Pre-Synth Design > Open Interactively.

Chida cha ModelSim® chimatsegula ndi testbench, monga momwe tawonetsera pa chithunzi chotsatira.

Chithunzi 5-3. Chida cha ModelSim chokhala ndi HDMI RX Testbench File

Chofunika: If kuyerekezera kumasokonekera chifukwa cha nthawi yothamanga yomwe yafotokozedwa mu DO file, gwiritsani ntchito run -all command kuti mumalize kuyerekezera.

License (Funso Funso)

HDMI RX IP imaperekedwa ndi njira ziwiri zotsatirazi:

• Zosungidwa: Nambala yathunthu ya RTL yosungidwa imaperekedwa pachimake. Imapezeka kwaulere ndi layisensi iliyonse ya Libero, zomwe zimapangitsa kuti mazikowo akhazikitsidwe ndi SmartDesign. Mutha kupanga Simulation, Synthesis, Layout, ndikukonzekera silicon ya FPGA pogwiritsa ntchito Libero design suite.
• RTL: Khodi yathunthu ya RTL ndi laisensi yotsekedwa, yomwe imayenera kugulidwa padera.

Zotsatira Zoyeserera (Funsani Funso)

Chithunzi chotsatira cha nthawi ya HDMI RX IP chikuwonetsa deta yamavidiyo ndikuwongolera nthawi ya data.

Chithunzi 6-1. Data Data

Chithunzi chotsatira chikuwonetsa zotuluka za hsync ndi vsync pazolowera zowongolera zomwe zikugwirizana.

Chithunzi 6-2. Kulunzanitsa kwa Horizontal ndi Zizindikiro Zolumikizira Zoyimirira

Chithunzi chotsatira chikuwonetsa gawo la EDID.

Chithunzi 6-3. Zizindikiro za EDID

Kugwiritsa Ntchito Zida (Funso Funso)

HDMI RX IP ikugwiritsidwa ntchito mu PolarFire® FPGA (MPF300T - 1FCG1152I Package). Gome lotsatirali likutchula zinthu zomwe zimagwiritsidwa ntchito pamene Number of Pixels = 1 pixel.

Gulu 7-1. Kugwiritsa Ntchito Zothandizira pa 1 Pixel Mode

Mtundu wamtundu	Kuzama Kwamitundu	SCRAMBLER	Nsalu 4LUT	Nsalu DFF	Chithunzi cha 4LUT	Chiyankhulo cha DFF	SRAM (64×12)	LSRAM (20k)
RGB	8	Letsani	987	1867	360	360	0	10
	10	Letsani	1585	1325	456	456	11	9
	12	Letsani	1544	1323	456	456	11	9
	16	Letsani	1599	1331	492	492	14	9
YCbCr422	8	Letsani	1136	758	360	360	3	9
YCbCr444	8	Letsani	1105	782	360	360	3	9
	10	Letsani	1574	1321	456	456	11	9
	12	Letsani	1517	1319	456	456	11	9
	16	Letsani	1585	1327	492	492	14	9

Gome lotsatirali likutchula zinthu zomwe zimagwiritsidwa ntchito pamene Number of Pixels = 4 pixel.

Gulu 7-2. Kugwiritsa Ntchito Zothandizira pa 4 Pixel Mode

Mtundu wamtundu	Kuzama Kwamitundu	SCRAMBLER	Nsalu 4LUT	Nsalu DFF	Chithunzi cha 4LUT	Chiyankhulo cha DFF	SRAM (64×12)	LSRAM (20k)
RGB	8	Letsani	1559	1631	1080	1080	9	27
	12	Letsani	1975	2191	1344	1344	31	27
	16	Letsani	1880	2462	1428	1428	38	27
RGB	10	Yambitsani	4231	3306	1008	1008	3	27
	12	Yambitsani	4253	3302	1008	1008	3	27
	16	Yambitsani	3764	3374	1416	1416	37	27
YCbCr422	8	Letsani	1485	1433	912	912	7	23
YCbCr444	8	Letsani	1513	1694	1080	1080	9	27
	12	Letsani	2001	2099	1344	1344	31	27
	16	Letsani	1988	2555	1437	1437	38	27

Gome lotsatirali likutchula zinthu zomwe zimagwiritsidwa ntchito Nambala ya Pixels = 4 pixel ndi SCRAMBLER yayatsidwa.

Gulu 7-3. Kugwiritsa Ntchito Zothandizira pa 4 Pixel Mode ndi SCRAMBLER Yayatsidwa

Mtundu wamtundu	Kuzama Kwamitundu	SCRAMBLER	Nsalu 4LUT	Nsalu DFF	Chithunzi cha 4LUT	Chiyankhulo cha DFF	SRAM (64×12)	LSRAM (20k)
RGB	8	Yambitsani	5029	5243	1126	1126	9	28
YCbCr422	8	Yambitsani	4566	3625	1128	1128	13	27
YCbCr444	8	Yambitsani	4762	3844	1176	1176	17	27

Kuphatikiza System (Funsani Funso)

Gawoli likuwonetsa momwe mungaphatikizire IP mu kapangidwe ka Libero.
Gome lotsatirali likuwonetsa masanjidwe a PF XCVR, PF TX PLL ndi PF CCC yofunikira pamalingaliro osiyanasiyana ndi m'lifupi mwake.

Gulu 8-1. PF XCVR, PF TX PLL ndi PF CCC Configurations

Kusamvana	Bit Width	Kusintha kwa PF XCVR			CDR REF CLOCK PADS	Kusintha kwa PF CCC
		Mtengo wa RX	RX CDR Ref Clock Clock Frequency	RX PCS Fabric Width		Kulowetsa pafupipafupi	Zotulutsa pafupipafupi
1 PXL (1080p60)	8	1485	148.5	10	AE27, AE28	NA	NA
1 PXL (1080p30)	10	1485	148.5	10	AE27, AE28	92.5	74
	12	1485	148.5	10	AE27, AE28	74.25	111.375
	16	1485	148.5	10	AE27, AE28	74.25	148.5
4 PXL (1080p60)	8	1485	148.5	40	AE27, AE28	NA	NA
	12	1485	148.5	40	AE27, AE28	55.725	37.15
	16	1485	148.5	40	AE27, AE28	74.25	37.125
4 PXL (4kp30)	8	1485	148.5	40	AE27, AE28	NA	NA
	10	3712.5	148.5	40	AE29, AE30	92.81	74.248
	12	4455	148.5	40	AE29, AE30	111.375	74.25
	16	5940	148.5	40	AE29, AE30	148.5	74.25
4 PXL (4Kp60)	8	5940	148.5	40	AE29, AE30	NA	NA

HDMI RX Sampndi Design 1: Mukakonzedwa mu Colour Depth = 8-bit ndi Number of Pixels = 1 Pixel mode, ikuwonetsedwa pachithunzi chotsatira.

Chithunzi 8-1. HDMI RX Sampndi Design 1

Za example, mu 8-bit kasinthidwe, zigawo zotsatirazi ndi gawo la mapangidwe:

• PF_XCVR_ERM (PF_XCVR_ERM_C0_0) idasinthidwa kuti ikhale TX ndi RX full duplex mode. RX data mlingo wa 1485 Mbps mu PMA mode, ndi m'lifupi deta kusinthidwa kukhala 10 bit kwa 1 PXL mode ndi 148.5 MHz CDR wotchi. TX mlingo wa data wa 1485 Mbps mu PMA mode, ndi m'lifupi mwake deta kusinthidwa kukhala 10 bit ndi wotchi division factor 4.
• LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK ndi LANE3_CDR_REF_CLK amayendetsedwa kuchokera ku PF_XCVR_REF_CLK ndi AE27, AE28 Pad pin.
• Pini ya EDID CLK_I iyenera kuyendetsedwa ndi wotchi ya 150 MHz yokhala ndi CCC.
• R_RX_CLK_I, G_RX_CLK_I ndi B_RX_CLK_I imayendetsedwa ndi LANE3_TX_CLK_R, LANE2_TX_CLK_R ndi LANE1_TX_CLK_R, motsatana.
• R_RX_VALID_I, G_RX_VALID_I ndi B_RX_VALID_I amayendetsedwa ndi LANE3_RX_VAL, LANE2_RX_VAL ndi LANE1_RX_VAL, motsatana.
• DATA_R_I, DATA_G_I ndi DATA_B_I amayendetsedwa ndi LANE3_RX_DATA, LANE2_RX_DATA ndi LANE1_RX_DATA, motsatana.

HDMI RX Sampndi Design 2: Mukakonzedwa mu Colour Depth = 8-bit ndi Number of Pixels = 4 Pixel mode, ikuwonetsedwa pachithunzi chotsatira.

Chithunzi 8-2. HDMI RX Sampndi Design 2

Za example, mu 8-bit kasinthidwe, zigawo zotsatirazi ndi gawo la mapangidwe:

• PF_XCVR_ERM (PF_XCVR_ERM_C0_0) idasinthidwa kuti ikhale TX ndi RX full duplex mode. RX data mlingo wa 1485 Mbps mu PMA mode, ndi m'lifupi deta kusinthidwa kukhala 40 bit kwa 4 PXL mode ndi 148.5 MHz CDR wotchi. TX mlingo wa data wa 1485 Mbps mu PMA mode, ndi m'lifupi mwake deta kusinthidwa kukhala 40 bit ndi wotchi division factor 4.
• LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK ndi LANE3_CDR_REF_CLK amayendetsedwa kuchokera ku PF_XCVR_REF_CLK ndi AE27, AE28 Pad pin.
• Pini ya EDID CLK_I iyenera kuyendetsedwa ndi wotchi ya 150 MHz yokhala ndi CCC.
• R_RX_CLK_I, G_RX_CLK_I ndi B_RX_CLK_I imayendetsedwa ndi LANE3_TX_CLK_R, LANE2_TX_CLK_R ndi LANE1_TX_CLK_R, motsatana.
• R_RX_VALID_I, G_RX_VALID_I ndi B_RX_VALID_I amayendetsedwa ndi LANE3_RX_VAL, LANE2_RX_VAL ndi LANE1_RX_VAL, motsatana.
• DATA_R_I, DATA_G_I ndi DATA_B_I amayendetsedwa ndi LANE3_RX_DATA, LANE2_RX_DATA ndi LANE1_RX_DATA, motsatana.

HDMI RX Sampndi Design 3: Mukakonzedwa mu Kuzama kwa Mtundu = 8-bit ndi Number of Pixels = 4 Pixel mode ndi SCRAMBLER = Yothandizira, ikuwonetsedwa mu chithunzi chotsatira.

Chithunzi 8-3. HDMI RX Sampndi Design 3

Za example, mu 8-bit kasinthidwe, zigawo zotsatirazi ndi gawo la mapangidwe:

• PF_XCVR_ERM (PF_XCVR_ERM_C0_0) idasinthidwa kukhala TX ndi RX Independent mode. RX data rate ya 5940 Mbps mu PMA mode, ndi m'lifupi mwake data kusinthidwa kukhala 40 bit for 4 PXL mode ndi 148.5 MHz CDR reference clock. Chiwerengero cha data cha TX cha 5940 Mbps mu PMA mode, ndi makulidwe a data omwe amasinthidwa kukhala 40 bit ndi mawotchi division factor 4.
• LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK ndi LANE3_CDR_REF_CLK amayendetsedwa kuchokera ku PF_XCVR_REF_CLK ndi AF29, AF30 mapini a Pad.
• Pini ya EDID CLK_I iyenera kuyendetsa ndi wotchi ya 150 MHz ndi CCC.
• R_RX_CLK_I, G_RX_CLK_I ndi B_RX_CLK_I imayendetsedwa ndi LANE3_TX_CLK_R, LANE2_TX_CLK_R ndi LANE1_TX_CLK_R, motsatana.
• R_RX_VALID_I, G_RX_VALID_I ndi B_RX_VALID_I amayendetsedwa ndi LANE3_RX_VAL, LANE2_RX_VAL ndi LANE1_RX_VAL, motsatana.
• DATA_R_I, DATA_G_I ndi DATA_B_I amayendetsedwa ndi LANE3_RX_DATA, LANE2_RX_DATA ndi LANE1_RX_DATA, motsatana.

HDMI RX Sampndi Design 4: Mukakonzedwa mu Kuzama kwa Mtundu = 12-bit ndi Number of Pixels = 4 Pixel mode ndi SCRAMBLER = Yothandizira, ikuwonetsedwa mu chithunzi chotsatira.

Chithunzi 8-4. HDMI RX Sampndi Design 4

Za example, mu 12-bit kasinthidwe, zigawo zotsatirazi ndi gawo la mapangidwe:

• PF_XCVR_ERM (PF_XCVR_ERM_C0_0) idasinthidwa kukhala RX Only mode. RX data rate ya 4455 Mbps mu PMA mode, ndi m'lifupi mwake data kusinthidwa kukhala 40 bit for 4 PXL mode ndi 148.5 MHz CDR reference clock.
• LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK ndi LANE3_CDR_REF_CLK amayendetsedwa kuchokera ku PF_XCVR_REF_CLK ndi AF29, AF30 mapini a Pad.
• Pini ya EDID CLK_I iyenera kuyendetsa ndi wotchi ya 150 MHz ndi CCC.
• R_RX_CLK_I, G_RX_CLK_I ndi B_RX_CLK_I imayendetsedwa ndi LANE3_TX_CLK_R, LANE2_TX_CLK_R ndi LANE1_TX_CLK_R, motsatana.
• R_RX_VALID_I, G_RX_VALID_I ndi B_RX_VALID_I amayendetsedwa ndi LANE3_RX_VAL, LANE2_RX_VAL ndi LANE1_RX_VAL, motsatana.
• DATA_R_I, DATA_G_I ndi DATA_B_I amayendetsedwa ndi LANE3_RX_DATA, LANE2_RX_DATA ndi LANE1_RX_DATA, motsatana.
• PF_CCC_C0 module imapanga wotchi yotchedwa OUT0_FABCLK_0 yokhala ndi ma frequency a 74.25 MHz, yochokera ku wotchi yolowera ya 111.375 MHz, yomwe imayendetsedwa ndi LANE1_RX_CLK_R.

HDMI RX Sampndi Design 5: Mukakonzedwa mu Kuzama kwa Mtundu = 8-bit, Number of Pixels = 4 Pixel mode ndi SCRAMBLER = Yothandizira ikuwonetsedwa mu chithunzi chotsatira. Mapangidwe awa ndi osinthika ma data ndi DRI.

Chithunzi 8-5. HDMI RX Sampndi Design 5

Za example, mu 8-bit kasinthidwe, zigawo zotsatirazi ndi gawo la mapangidwe:

• PF_XCVR_ERM (PF_XCVR_ERM_C0_0) idasinthidwa kukhala RX Only yokhala ndi mawonekedwe osinthika osinthika. RX data rate ya 5940 Mbps mu PMA mode, ndi m'lifupi mwake data kusinthidwa kukhala 40 bit for 4 PXL mode ndi 148.5 MHz CDR reference clock.
• LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK ndi LANE3_CDR_REF_CLK amayendetsedwa kuchokera ku PF_XCVR_REF_CLK ndi AF29, AF30 mapini a Pad.
• Pini ya EDID CLK_I iyenera kuyendetsa ndi wotchi ya 150 MHz ndi CCC.
• R_RX_CLK_I, G_RX_CLK_I ndi B_RX_CLK_I imayendetsedwa ndi LANE3_TX_CLK_R, LANE2_TX_CLK_R ndi LANE1_TX_CLK_R, motsatana.
• R_RX_VALID_I, G_RX_VALID_I ndi B_RX_VALID_I amayendetsedwa ndi LANE3_RX_VAL, LANE2_RX_VAL ndi LANE1_RX_VAL, motsatana.
• DATA_R_I, DATA_G_I ndi DATA_B_I amayendetsedwa ndi LANE3_RX_DATA, LANE2_RX_DATA ndi LANE1_RX_DATA, motsatana.

Mbiri Yakanikanso (Funsani Funso)

Mbiri yokonzanso ikufotokoza zosintha zomwe zidakhazikitsidwa muzolemba. Zosinthazo zandandalikidwa ndi kubwereza, kuyambira ndi zofalitsa zamakono.

Gulu 9-1. Mbiri Yobwereza

Kubwereza	Tsiku	Kufotokozera
D	02/2025	Zotsatirazi ndi mndandanda wa zosintha zomwe zasinthidwa mu chikalata C: Adasintha mtundu wa HDMI RX IP kukhala 5.4. Mawu Oyamba Osinthidwa okhala ndi mawonekedwe komanso zosagwirizana. Gawo la Zida Zoyesedwa Zoyesedwa. Kusinthidwa Chithunzi 3-1 ndi Chithunzi 3-3 mu gawo la Hardware Implementation. Gawo lowonjezera la Configuration Parameters. Zasinthidwa Table 4-2, Table 4-4, Table 4-5, Table 4-6 and Table 4-7 in the Ports section. Kusinthidwa Chithunzi 5-2 mu gawo la Testbench Simulation. Kusinthidwa Table 7-1 ndi Table 7-2 anawonjezera Table 7-3 mu Resource Utilization gawo. Chithunzi Chosinthidwa 8-1, Chithunzi 8-2, Chithunzi 8-3 ndi Chithunzi 8-4 mu gawo la System Integration. Adawonjezera kuchuluka kwa data ndi DRI design example mu System Integration gawo.
C	02/2023	Zotsatirazi ndi mndandanda wa zosintha zomwe zasinthidwa mu chikalata C: Adasintha mtundu wa HDMI RX IP kukhala 5.2 Kusinthidwa kusamvana kothandizira mumayendedwe a pixel anayi muzolemba zonse Chithunzi Chosinthidwa 2-1
B	09/2022	Zotsatirazi ndi mndandanda wa zosintha zomwe zasinthidwa mu B wa chikalatacho: Kusintha chikalata cha v5.1 Zasinthidwa Table 4-2 ndi Table 4-3
A	04/2022	Zotsatirazi ndi mndandanda wa zosintha pakukonzanso A kwa chikalatacho: Chikalatacho chinasamutsidwa kupita ku template ya Microchip Nambala ya chikalatacho idasinthidwa kukhala DS50003298A kuchokera ku 50200863 Gawo losinthidwa la TMDS Decoder Matebulo osinthidwa Table 4-2 ndi Table 4-3  Chithunzi Chosinthidwa 5-3, Chithunzi 6-1, Chithunzi 6-2
2.0	—	M'munsimu ndi chidule cha zosintha zomwe zasinthidwa. Zowonjezera Gulu 4-3 Matebulo Ogwiritsidwa Ntchito Osinthidwa
1.0	08/2021	Kubwereza Koyamba.

Thandizo la Microchip FPGA
Gulu lazinthu za Microchip FPGA limathandizira zogulitsa zake ndi ntchito zosiyanasiyana zothandizira, kuphatikiza Makasitomala, Customer Technical Support Center, a webmalo, ndi maofesi ogulitsa padziko lonse lapansi. Makasitomala akulangizidwa kuti aziyendera zapaintaneti za Microchip asanakumane ndi chithandizo chifukwa ndizotheka kuti mafunso awo ayankhidwa kale. Lumikizanani ndi Technical Support Center kudzera pa website pa www.microchip.com/support. Tchulani nambala ya Gawo la Chipangizo cha FPGA, sankhani gulu loyenera, ndikuyika mapangidwe files popanga chithandizo chaukadaulo. Lumikizanani ndi Makasitomala kuti muthandizidwe ndi zinthu zomwe si zaukadaulo, monga mitengo yazinthu, kukweza kwazinthu, zambiri zosintha, mawonekedwe oyitanitsa, ndi chilolezo.

• Kuchokera ku North America, imbani 800.262.1060
• Kuchokera kudziko lonse lapansi, imbani 650.318.4460
• Fax, kuchokera kulikonse padziko lapansi, 650.318.8044

Zambiri za Microchip

Zizindikiro
Dzina ndi logo ya “Microchip”, logo ya “M”, ndi mayina ena, ma logo, ndi mitundu ndi zizindikilo zolembetsedwa ndi zosalembetsedwa za Microchip Technology Incorporated kapena mabungwe ake ndi/kapena mabungwe aku United States ndi/kapena mayiko ena (“Microchip Zizindikiro "). Zambiri zokhuza Zizindikiro za Microchip zitha kupezeka pa https://www.microchip.com/en-us/about/legal-information/microchip-trademarks.

ISBN: 979-8-3371-0744-8

Chidziwitso chazamalamulo
Bukuli ndi zambiri zomwe zili pano zitha kugwiritsidwa ntchito ndi zinthu za Microchip zokha, kuphatikiza kupanga, kuyesa, ndi kuphatikiza zinthu za Microchip ndi pulogalamu yanu. Kugwiritsa ntchito chidziwitsochi mwanjira ina iliyonse kumaphwanya mawuwa. Zambiri zokhudzana ndi kugwiritsa ntchito zida zimaperekedwa kuti zitheke ndipo zitha kulowedwa m'malo ndi zosintha. Ndi udindo wanu kuwonetsetsa kuti pulogalamu yanu ikugwirizana ndi zomwe mukufuna. Lumikizanani ndi ofesi yogulitsa za Microchip kwanuko kuti muthandizidwe zina kapena, pezani thandizo lina pa www.microchip.com/en-us/support/design-help/client-support-services.

ZIMENEZI AMAPEREKA NDI MICROCHIP "MONGA ILI". MICROCHIP SIIPEREKERA ZINTHU KAPENA ZIZINDIKIRO ZA MTIMA ULIWONSE KAYA KUTANTHAUZIRA KAPENA KUTANTHAWIRIKA, KULEMBEDWA KAPENA MWAMWAMBA, MALAMULO KAPENA ZINTHU ZINA, ZOKHUDZANA NDI CHIZINDIKIRO KUPHATIKIZAPO KOMA ZOSAKHALA PA CHENJEZO KILICHONSE, KUTENGA ZIPANGIZO, KUTENGA CHIZINDIKIRO, KUCHITIKA, NTCHITO, NTCHITO. PA CHOLINGA ENA, KAPENA ZINTHU ZOKHUDZA ZOKHUDZANA NDI MKHALIDWE WAKE, UKHALIDWE, KAPENA NTCHITO YAKE.
PAMENE MICROCHIP IDZAKHALA NDI NTCHITO PA CHIZINDIKIRO CHILICHONSE, CHAPADERA, CHILANGO, ZOCHITIKA, KAPENA ZOTSATIRA ZOTSATIRA, KUonongeka, mtengo, KAPENA NTCHITO ZONSE ZOMWE ZILI ZOKHUDZA CHIdziwitso KAPENA NTCHITO YAKE, KOMA CHIFUKWA CHIFUKWA CHOCHITIKA, ZOCHITIKA KAPENA ZOWONONGWA NDI ZOONERA. KUBWERA KWABWINO KWAMBIRI ZOLOLEZEDWA NDI MALAMULO, NDONDOMEKO YONSE YA MICROCHIP PA ZINSINSI ZONSE MU NJIRA ILIYONSE YOKHUDZANA NDI CHIdziwitso KAPENA KUKGWIRITSA NTCHITO CHOSAPYOTSA KUCHULUKA KWA ZOLIMBIKITSA, NGATI KULIPO, ZIMENE MULIPITSA CHIFUKWA CHIFUKWA CHIFUKWA CHIYANI.
Kugwiritsa ntchito zipangizo za Microchip pa chithandizo cha moyo ndi / kapena ntchito za chitetezo ndizoopsa kwa wogula, ndipo wogula akuvomera kuteteza, kubwezera ndi kusunga Microchip yopanda vuto lililonse ku zowonongeka, zodandaula, masuti, kapena ndalama zomwe zimachokera ku ntchito yotere. Palibe zilolezo zomwe zimaperekedwa, mobisa kapena mwanjira ina, pansi pa ufulu wazinthu zaukadaulo za Microchip pokhapokha zitanenedwa.

Chitetezo cha Microchip Devices Code

Zindikirani tsatanetsatane wotsatira wa chitetezo cha code pazinthu za Microchip:

• Zogulitsa za Microchip zimakwaniritsa zomwe zili mu Microchip Data Sheet yawo.
• Microchip imakhulupirira kuti katundu wake ndi wotetezeka akagwiritsidwa ntchito m'njira yomwe akufuna, malinga ndi momwe amagwirira ntchito, komanso m'mikhalidwe yabwinobwino.
• Ma Microchip amawakonda ndikuteteza mwamphamvu ufulu wake wazinthu zamaluntha. Kuyesa kuphwanya malamulo otetezedwa ndi zinthu za Microchip ndizoletsedwa ndipo zitha kuphwanya Digital Millennium Copyright Act.
• Ngakhale Microchip kapena wopanga semiconductor wina aliyense sangatsimikizire chitetezo cha code yake. Kutetezedwa kwa ma code sikutanthauza kuti tikutsimikizira kuti chinthucho ndi "chosasweka". Chitetezo cha code chikusintha nthawi zonse. Microchip yadzipereka mosalekeza kuwongolera mawonekedwe achitetezo azinthu zathu.

© 2025 Microchip Technology Inc. ndi mabungwe ake

FAQ

• Q: Kodi ine kusintha HDMI RX IP pachimake?
  A: IP core imatha kusinthidwa kudzera pa pulogalamu ya Libero SoC kapena kutsitsidwa pamanja kuchokera pamndandanda. Ikayikidwa mu Libero SoC pulogalamu ya IP Catalog, imatha kukonzedwa, kupangidwa, ndikukhazikitsidwa mkati mwa SmartDesign kuti iphatikizidwe mu polojekitiyi.

Zolemba / Zothandizira

MICROCHIP PolarFire FPGA High Definition Multimedia Interface HDMI Receiver [pdf] Buku Logwiritsa Ntchito PolarFire FPGA, PolarFire FPGA High Definition Multimedia Interface HDMI Receiver, High Definition Multimedia Interface HDMI Receiver, Multimedia Interface HDMI Receiver, Interface HDMI Receiver, HDMI Receiver.

Maumboni

• Buku Logwiritsa Ntchito