MICROCHIP PolarFire FPGA High Definition Multimedia Interface HDMI Receiver

Folasaga (Fai se Fesili)
O le Microchip's High-Definition Multimedia Interface (HDMI) receiver IP e lagolagoina faʻamatalaga vitio ma le mauaina o faʻamatalaga pusa leo o loʻo faʻamatalaina i le HDMI tulaga faʻapitoa. HDMI RX IP ua mamanuina faapitoa mo PolarFire® FPGA ma PolarFire System i Chip (SoC) FPGA masini e lagolagoina le HDMI 2.0 mo iugafono e oo atu i le 1920 × 1080 i le 60 Hz i le tasi pixel mode ma luga atu i le 3840 × 2160 i le 60 Hz i le fa pixel mode. E lagolagoina e le RX IP le Hot Plug Detect (HPD) mo le mata'ituina o le mana i luga pe tape ma se'i pe fa'apipi'i mea e tutupu e fa'ailoa ai feso'ota'iga i le va o le puna HDMI ma le fa'amau HDMI.

E fa'aoga e le fa'apogai HDMI le alaleo Fa'aaliga Fa'amatalaga (DDC) e faitau ai Fa'amatalaga Fa'ailoa Fa'amatalaga Fa'alautele a le pusa (EDID) e iloa ai le fa'atulagaina ma/po'o le gafatia o le Sink. O le HDMI RX IP o loʻo faʻapipiʻiina EDID, lea e mafai e se puna HDMI ona faitau i se ala masani I2C. PolarFire FPGA ma PolarFire SoC FPGA masini transceivers o loʻo faʻaogaina faʻatasi ma RX IP e faʻaumatia faʻamaumauga faʻasologa i 10-bit data. O faʻamatalaga faʻamatalaga ile HDMI e faʻatagaina e iai se vaʻaiga tele i le va o latou. O le HDMI RX IP e aveese le skew i totonu o faʻamatalaga faʻaoga e faʻaaoga ai le First-In First-Out (FIFOs). O lenei IP e faʻaliliuina le Transition Minimized Differential Signaling (TMDS) faʻamatalaga na maua mai le HDMI puna e ala i le transceiver i le 24-bit RGB pixel data, 24-bit leo faʻalogo ma faʻailoga faʻatonutonu. O fa'ailoga fa'atonu e fa o lo'o fa'amaoti mai i le HDMI protocol e fa'aogaina e fa'afetaui ai fa'amaumauga i le taimi o le deserialization.

Aotelega

O le laulau o lo'o i lalo o lo'o tu'uina atu ai se aotelega o uiga HDMI RX IP.

Laulau 1. HDMI RX IP Uiga

Autu Version	O lenei taiala fa'aoga e lagolagoina le HDMI RX IP v5.4.
Aiga Meafaigaluega Lagolago	PolarFire® SoC PolarAfi
Lagolago Meafaigaluega tafe	Manaomia Libero® SoC v12.0 po'o fa'asalalauga mulimuli ane.
Fa'afeso'ota'i Lagolago	Interfaces e lagolagoina e le HDMI RX IP o: AXI4-Stream: O lenei autu e lagolagoina le AXI4-Stream i ports gaosiga. A fa'atulagaina i lenei faiga, o le IP e fa'aalia AXI4 Stream fa'ailoga fa'aseā masani. Native: A fa'atulagaina i lenei faiga, e fa'aalia e le IP fa'ailoga vitiō ma fa'alogo.
Laisene	HDMI RX IP o loʻo tuʻuina atu i ai avanoa laisene e lua: Fa'ailoga: O lo'o tu'uina atu le fa'ailoga fa'ailoga RTL atoa mo le autu. E avanoa mo le leai o se totogi ma soʻo se laisene Libero, e mafai ai ona faʻapipiʻi le autu ma SmartDesign. E mafai ona e faia le Simulation, Synthesis, Layout ma polokalame le FPGA silicon e faʻaaoga ai le Libero design suite. RTL: O le RTL source code atoa o lo'o loka laisene, lea e mana'omia ona fa'atau eseese.

Vaega

HDMI RX IP o loʻo i ai uiga nei:

• E fetaui mo HDMI 2.0
• Lagolago 8, 10, 12 ma le 16 Bits Color Depth
• Lagolagoina Fa'ailoga Lanu pei ole RGB, YUV 4:2:2 ma le YUV 4:4:4
• Lagolago tasi pe Fa Pixels i le Uati Ulufale
• Lagolagoina Iugafono e oo atu i le 1920 ✕ 1080 i le 60 Hz i le One Pixel mode ma luga ole 3840 ✕ 2160 i le 60 Hz i le Fa Pixel mode.
• Su'eina Hot-Plug
• Lagolagoina Decoding Scheme - TMDS
• Lagolago DVI Input
• Lagolagoina Fa'aaliga Fa'amatalaga Fa'amatalaga (DDC) ma Fa'aleleia Fa'amatalaga Fa'amatalaga Fa'amatalaga (E-DDC)
• Lagolagoina Native ma le AXI4 Stream Video Interface mo le Faʻaliliuina o Faʻamatalaga Vitio
• Lagolagoina Native ma le AXI4 Stream Audio Interface mo le Faaliliuina o Faʻamatalaga Faʻalogo

Vaega le lagolagoina

O lo'o mulimuli mai vaega le lagolagoina o HDMI RX IP:

• 4:2:0 lanu lanu e le lagolagoina.
• E le lagolagoina le High Dynamic Range (HDR) ma le High-bandwidth Digital Content Protection (HDCP).
• Ole Fua Fa'afou Fesuia'i (VRR) ma le Auto Low Latency Mode (ALLM) e le lagolagoina.
• Fa'asagaga Taimi Fa'asaga'i e le mafai ona vaevae i le fa i le Fa Pixel mode e le lagolagoina.

Fa'atonuga fa'apipi'i
O le IP autu e tatau ona faʻapipiʻi i le IP Catalog of Libero® SoC software e otometi lava e ala i le IP Catalog update function i le Libero SoC software, pe sii mai ma le lima mai le lisi. O le taimi lava e faʻapipiʻi ai le IP core i le Libero SoC software IP Catalog, e faʻapipiʻiina, faʻatupuina ma faʻapipiʻiina i totonu o le Smart Design mo le faʻaofiina i totonu o le poloketi Libero.

Masini Punavai Fa'ata'ita'i (Fa'ai se Fesili)

O le laulau o lo'o i lalo o lo'o lisiina ai masini puna'oa fa'ata'ita'i.

Laulau 1-1. Masini Punavai Fa'ata'ita'i

Meafaigaluega	Faiga Piki	Fa'ai'uga ua Tofotofoina	Lanu loloto (Bit)	Faiga Lanu	Leo
quantumdata™ M41h HDMI Iloiloga	1	720P 30 FPS, 720P 60 FPS ma 1080P 60 FPS	8	RGB, YUV444 ma le YUV422	Ioe
		1080P 30 FPS	8, 10, 12 ma le 16
	4	720P 30 FPS, 1080P 30 FPS ma le 4K 60 FPS	8
		1080P 60 FPS	8, 12 ma le 16
		4K 30 FPS	8, 10, 12 ma le 16
Lenovo™ 20U1A007IG	1	1080P 60 FPS	8	RGB	Ioe
	4	1080P 60 FPS ma le 4K 30 FPS
Dell Latitude 3420	1	1080P 60 FPS	8	RGB	Ioe
	4	4K 30 FPS ma le 4K 60 FPS
Astro VA-1844A HDMI® Su'ega	1	720P 30 FPS, 720P 60 FPS ma 1080P 60 FPS	8	RGB, YUV444 ma le YUV422	Ioe
		1080P 30 FPS	8, 10, 12 ma le 16
	4	720P 30 FPS, 1080P 30 FPS ma le 4K 30 FPS	8
		1080P 30 FPS	8, 12 ma le 16
NVIDIA® Jetson AGX Orin 32GB H01 Kit	1	1080P 30 FPS	8	RGB	Leai
	4	4K 60 FPS

HDMI RX IP Configuration (Fai se Fesili)

O lenei vaega o loʻo tuʻuina atu se faʻaopoopogaview o le HDMI RX IP Configurator interface ma ona vaega. O le HDMI RX IP Configurator e tuʻuina atu se faʻataʻitaʻiga faʻataʻitaʻiga e faʻapipiʻi ai le HDMI RX autu. O lenei configurator e mafai ai e le tagata faʻaoga ona filifili faʻamaufaʻailoga e pei ole Numera o Pixels, Numera o ala leo, Vitio Interface, Audio Interface, SCRAMBLER, Lanu loloto, Faʻailoga lanu, Testbench ma Laisene. O le Configurator interface e aofia ai menus dropdown ma filifiliga e faʻavasega ai faʻatulagaga. O fa'atonuga autu o lo'o fa'amatalaina ile Laulau 4-1. O le ata o loʻo i lalo o loʻo tuʻuina mai ai se auiliiliga view ole fa'aoga HDMI RX IP Configurator.

Ata 2-1. HDMI RX IP Configurator

O lo'o iai fo'i fa'amau fa'amau e fa'amautu pe lafoa'i fa'atonuga i le fa'aoga.

Fa'atinoga o Meafaigaluega (Fai se Fesili)

O fa'atusa nei o lo'o fa'amatalaina ai le feso'ota'iga HDMI RX IP ma le transceiver (XCVR).

Ata 3-1. HDMI RX poloka ata

Ata 3-2. Receiver Detailed Block Diagram

HDMI RX e aofia ai le tolu stage:

• O le fa'asologa o vaega e fa'aogaina fa'amaumauga tutusa e fa'atatau i le fa'atonutonuina o tua'oi fa'ailoga e fa'aaoga ai le fa'ase'e fa'ase'e.
• O le TMDS decoder fa'aliliuina le 10-bit fa'amatalaga fa'ailoga i le 8-bit video pixel data, 4-bit leo fa'amaumauga ma fa'ailoga fa'atonu 2-bit.
• E aveese e le FIFO le skew i le va o uati o laina R, G ma B.

Fa'asa'o Fa'asaga (Fai se Fesili)
Ole 10-bit parallel data mai le XCVR e le'o fa'aogaina i taimi uma e fa'atatau i le TMDS fa'ailoga o le upu tuaoi. O fa'amaumauga tutusa e mana'omia ona fai sina siisii ​​ma fa'aoga tutusa ina ia mafai ona fa'avasega fa'amaumauga. Fa'atonu vaega e fa'aogaina ai fa'amatalaga tutusa o lo'o o'o mai i tua'oi o upu e fa'aaoga ai le vaega fa'ase'e i le XCVR. O le XCVR i le Per-Monitor DPI Awareness (PMA) mode e mafai ai ona faʻaogaina le ata-slip, lea e fetuunai ai le faʻaogaina o le 10-bit deserialized upu i le 1-bit. O taimi taʻitasi, pe a uma ona fetuunai le 10-bit upu i le 1 bit slip position, e faʻatusatusa i soʻo se tasi o faʻailoga faʻatonutonu o le HDMI protocol e loka ai le tulaga i le taimi o le pulea. O le upu 10-bit ua fa'aoga sa'o ma manatu e aoga mo le isi stages. O laina lanu ta'itasi e iai lana fa'aoga vaega, o le TMDS decoder e amata fa'avasega pe a loka uma vaega fa'aoga e fa'asa'o ai le upu tuaoi.

TMDS Decoder (Fai se Fesili)
TMDS decoder decodes le 10-bit deserialized mai le transceiver i 8-bit pixel data i le taimi o vitio. HSYNC, VSYNC ma PACKET HEADER o loʻo faʻatupuina i le taimi o le pulega mai le 10-bit blue channel data. O fa'amaumauga o pusa leo o lo'o fa'aliliu i luga o le R ma le G ala ta'itasi ma fa'ailoga e fa. O le TMDS decoder o auala ta'itasi o lo'o galue i lana lava uati. O le mea lea, e mafai ona i ai se faʻailoga patino i le va o auala.

Auala i le Alavai De-Skew (Fai se Fesili)
O le FIFO e fa'avae le fa'aogaina o le fa'aogaina o lo'o fa'aaogaina e aveese ai le skew i le va o alalaupapa. E maua e alalaupapa ta'itasi se fa'ailo aoga mai vaega fa'aoga vaega e ta'u mai ai pe fa'amaonia le 10-bit fa'amatalaga o lo'o sau mai le fa'asologa o vaega. Afai e aoga uma auala (ua ausia le fa'aogaina o vaega), o le FIFO module e amata ona pasi fa'amaumauga i le FIFO module e fa'aaoga ai le faitau ma le tusitusi e mafai ai (fa'aauau le tusitusi i totonu ma faitau i fafo). A iloa se fa'ailoga fa'atonutonu i so'o se fa'atinoga a le FIFO, e fa'agata le fa'asalalau faitau, ma fa'atupuina se fa'ailoga fa'ailoga e fa'ailoa ai le taunu'u mai o se fa'ailoga fa'apitoa i le ata vitio. Fa'atoa toe fa'aauau le fa'asologa o le faitau pe a o'o mai le fa'ailoga i ala uma e tolu. O se taunuuga, ua aveese le skew talafeagai. O le FIFO lua-uati e fa'amaopoopo fa'amaumauga uma e tolu i le uati o le ala lanumoana e aveese ai le skew talafeagai. O le ata o lo'o i lalo o lo'o fa'amatalaina ai le auala e fa'alava ai le fa'a'ese'ese.

Ata 3-3. Auala i le Alavai De-Skew

DDC (Fai se Fesili)
O le DDC o se fesoʻotaʻiga fesoʻotaʻiga e faʻavae i luga ole faʻamatalaga I2C pasi. O lo'o fa'aogaina e le fa'apogai tulafono a le I2C e faitau fa'amatalaga mai le E-EDID o se pusa ma se tuatusi pologa. O le HDMI RX IP o lo'o fa'aogaina le EDID ma le tele o iugafono e lagolagoina ai iugafono e o'o atu i le 1920 ✕ 1080 i le 60 Hz i le One Pixel mode ma o'o atu i le 3840 ✕ 2160 i le 60 Hz i le Fa Pixel mode.
O le EDID o loʻo faʻatusalia le igoa faʻaaliga o le Microchip HDMI faʻaaliga.

HDMI RX Parameters ma Fa'ailoga Fa'afeso'ota'i (Fa'ai se Fesili)

O lenei vaega o loʻo talanoaina ai faʻamaufaʻailoga i le HDMI RX GUI configurator ma faʻailoga I/O.

Fa'atonuga (Fa'ai se Fesili)
O le laulau o loʻo i lalo o loʻo lisiina ai faʻamaufaʻailoga i le HDMI RX IP.

Laulau 4-1. Fa'atutuga Parata

Igoa Parameter	Fa'amatalaga
Fa'ailoga lanu	Fa'amatala le avanoa lanu. Lagolagoina fa'asologa lanu nei: RGB YCbCr422 YCbCr444
Lanu loloto	Fa'ailoa mai le aofa'i o pa'u ile vaega lanu. Lagolago 8, 10, 12 ma 16 bits i vaega.
Numera o Pixel	Fa'ailoa le aofa'i o pika ile fa'aulu ile uati: Pixel ile uati = 1 Pixel ile uati = 4
TAGATA FA'AVAE	Lagolago mo le 4K iugafono ile 60 fa'avaa ile sekone: A 1, ua mafai le lagolago Scrambler A 0, ua le atoatoa le lagolago a Scrambler
Numera o alaleo leo	Lagolago numera o alaleo leo: 2 alaleo leo 8 alaleo leo
Ata Vitio i luga	Native ma AXI stream
Fa'alogo leo	Native ma AXI stream
nofoa su'ega	Fa'ataga le filifiliga o se siosiomaga nofoa su'ega. Lagolagoina o filifiliga nofoa su'ega nei: Tagata fa'aoga Leai
Laisene	Fa'ailoa mai le ituaiga laisene. Tuuina atu avanoa laisene e lua: RTL Fa'ailoga

Taulaga (Fai se Fesili)
O le laulau o lo'o i lalo o lo'o lisiina ai ports o lo'o tu'uina atu ma fa'aulufaleina o le HDMI RX IP mo le atina'e fa'ale-aganu'u pe a o le Fa'ailoga Lanu o le RGB.

Laulau 4-2. Ulufale ma Galuega Fa'atino mo Fa'amatalaga Fa'a-Native

Igoa Faailoga	Fa'atonuga	Lautele (Piti)	Fa'amatalaga
RESET_N_I	Ulufale	1	Fa'ailoga toe setiina asynchronous-maualalo
R_RX_CLK_I	Ulufale	1	Uati tutusa mo le ala "R" mai le XCVR
G_RX_CLK_I	Ulufale	1	Uati tutusa mo le ala "G" mai le XCVR
B_RX_CLK_I	Ulufale	1	Uati tutusa mo le ala "B" mai le XCVR
EDID_RESET_N_I	Ulufale	1	Fa'ailoga toe setiina edid e fa'agaioi-maualalo asynchronous
R_RX_VALID_I	Ulufale	1	Fa'ailoga aoga mai le XCVR mo fa'amatalaga tutusa o le ala "R".
G_RX_VALID_I	Ulufale	1	Fa'ailoga aoga mai le XCVR mo fa'amatalaga tutusa o le ala "G".
B_RX_VALID_I	Ulufale	1	Fa'ailoga aoga mai le XCVR mo fa'amatalaga tutusa o le ala "B".

Igoa Faailoga	Fa'atonuga	Lautele (Piti)	Fa'amatalaga
DATA_R_I	Ulufale	Numera O PIXELS ✕ 10 bits	Maua "R" alalaupapa tala tutusa mai XCVR
DATA_G_I	Ulufale	Numera O PIXELS ✕ 10 bits	Maua "G" alalaupapa tala tutusa mai XCVR
DATA_B_I	Ulufale	Numera O PIXELS ✕ 10 bits	Maua "B" alalaupapa tala tutusa mai XCVR
SCL_I	Ulufale	1	I2C fa'aoga uati fa'asologa mo DDC
HPD_I	Ulufale	1	Poloka vevela e iloa ai fa'ailo fa'aoga. O lo'o feso'ota'i le puna ile goto ole HPD faailoilo e tatau ona maualuga.
SDA_I	Ulufale	1	I2C fa'amaumauga fa'amaumauga mo DDC
EDID_CLK_I	Ulufale	1	Uati faiga mo I2C module
BIT_SLIP_R_O	Tuuina atu	1	Fa'ailoga fa'ase'e i le ala "R" ole transceiver
BIT_SLIP_G_O	Tuuina atu	1	Fa'ailoga fa'ase'e i le ala "G" ole transceiver
BIT_SLIP_B_O	Tuuina atu	1	Fa'ailoga fa'ase'e i le ala "B" ole transceiver
VIDEO_DATA_VALID_O	Tuuina atu	1	Fa'amatalaga vitiō fa'atino aoga
AUDIO_DATA_VALID_O	Tuuina atu	1	Fa'amatalaga fa'alogo fa'atino fa'amaonia
H_SYNC_O	Tuuina atu	1	Fa'asa'o fa'asaga i pulupulu
V_SYNC_O	Tuuina atu	1	Malosiaga tu'usa'o fa'agaoioi pusi
R_O	Tuuina atu	Numera O PIXELS ✕ Lanu loloto bits	Fa'ailoga "R" fa'amaumauga
G_O	Tuuina atu	Numera O PIXELS ✕ Lanu loloto bits	Fa'aliliuina fa'amaumauga "G".
B_O	Tuuina atu	Numera O PIXELS ✕ Lanu loloto bits	Fa'aliliuina fa'amaumauga "B".
SDA_O	Tuuina atu	1	I2C fa'amaumauga fa'asologa fa'asologa mo DDC
HPD_O	Tuuina atu	1	Poloka vevela e iloa ai fa'ailo fa'aulufale
ACR_CTS_O	Tuuina atu	20	Taimi ole Taimi ole Fa'afouga ole Uati Fa'alogoamp taua
ACR_N_O	Tuuina atu	20	Fa'ata'otoga o le Fa'afouina o le Uati Fa'alogo (N).
ACR_VALID_O	Tuuina atu	1	Fa'ailoilo Fa'afouga Fa'afouina Uati leo
AUDIO_SAMPLE_CH1_O	Tuuina atu	24	Ala 1 leo sample faʻamatalaga
AUDIO_SAMPLE_CH2_O	Tuuina atu	24	Ala 2 leo sample faʻamatalaga
AUDIO_SAMPLE_CH3_O	Tuuina atu	24	Ala 3 leo sample faʻamatalaga
AUDIO_SAMPLE_CH4_O	Tuuina atu	24	Ala 4 leo sample faʻamatalaga
AUDIO_SAMPLE_CH5_O	Tuuina atu	24	Ala 5 leo sample faʻamatalaga
AUDIO_SAMPLE_CH6_O	Tuuina atu	24	Ala 6 leo sample faʻamatalaga
AUDIO_SAMPLE_CH7_O	Tuuina atu	24	Ala 7 leo sample faʻamatalaga
AUDIO_SAMPLE_CH8_O	Tuuina atu	24	Ala 8 leo sample faʻamatalaga
HDMI_DVI_MODE_O	Tuuina atu	1	O auala nei e lua: 1: auala HDMI 0: Faiga DVI

O le laulau o lo'o i lalo o lo'o fa'amatalaina ai le fa'aogaina ma le fa'aogaina o ports o HDMI RX IP mo le AXI4 Stream Video Interface.
Laulau 4-3. Taulaga Fa'aulu ma Fa'aulufale mo le AXI4 Stream Video Interface

Igoa o le Taulaga	Fa'atonuga	Lautele (Piti)	Fa'amatalaga
TDATA_O	Tuuina atu	Numera o PIXELS ✕ Lanu loloto ✕ 3 bits	Tuuina atu fa'amatalaga vitio [R, G, B]
TVALID_O	Tuuina atu	1	Vitio fa'aalia e aoga

Igoa o le Taulaga	Fa'atonuga	Lautele (Piti)	Fa'amatalaga
TLAST_O	Tuuina atu	1	Fa'ailoga pito fa'ai'uga fa'avaa
TUSER_O	Tuuina atu	3	bit 0 = VSYNC bit 1 = Hsync  laititi 2 = 0 laititi 3 = 0
TSTRB_O	Tuuina atu	3	Fa'asolo fa'amatalaga fa'amatalaga vitio
TKEEP_O	Tuuina atu	3	Fa'amauina fa'amaumauga vitio

O le laulau o loʻo i lalo o loʻo faʻamatalaina ai le faʻaogaina ma le gaosiga o ports o HDMI RX IP mo le AXI4 Stream Audio Interface.

Laulau 4-4. Taulaga Fa'aulu ma Fa'aulufale mo le AXI4 Stream Audio Interface

Igoa o le Taulaga	Fa'atonuga	Lautele (Piti)	Fa'amatalaga
AUDIO_TDATA_O	Tuuina atu	24	Fa'amatalaga fa'alogo
AUDIO_TID_O	Tuuina atu	3	Alaleo fa'alogo
AUDIO_TVALID_O	Tuuina atu	1	Fa'ailo aoga leo

O le laulau o lo'o i lalo o lo'o lisiina ai ports o lo'o tu'uina atu ma fa'aulufaleina o le HDMI RX IP mo le fa'aoga Fa'a-Native pe a o le Fa'ailoga Lanu o le YUV444.

Laulau 4-5. Ulufale ma Galuega Fa'atino mo Fa'amatalaga Fa'a-Native

Igoa o le Taulaga	Fa'atonuga	Lautele (Piti)	Fa'amatalaga
RESET_N_I	Ulufale	1	Fa'ailoga toe setiina asynchronous-maualalo
LANE3_RX_CLK_I	Ulufale	1	Uati tutusa mo Lane 3 alalaupapa mai XCVR
LANE2_RX_CLK_I	Ulufale	1	Uati tutusa mo Lane 2 alalaupapa mai XCVR
LANE1_RX_CLK_I	Ulufale	1	Uati tutusa mo Lane 1 alalaupapa mai XCVR
EDID_RESET_N_I	Ulufale	1	Fa'ailoga toe setiina edid e fa'agaioi-maualalo asynchronous
LANE3_RX_VALID_I	Ulufale	1	Fa'ailoga aoga mai le XCVR mo fa'amaumauga tutusa o Lane 3
LANE2_RX_VALID_I	Ulufale	1	Fa'ailoga aoga mai le XCVR mo fa'amaumauga tutusa o Lane 2
LANE1_RX_VALID_I	Ulufale	1	Fa'ailoga aoga mai le XCVR mo fa'amaumauga tutusa o Lane 1
DATA_LANE3_I	Ulufale	Numera O PIXELS ✕ 10 bits	Maua Lane 3 faʻamatalaga tutusa mai XCVR
DATA_LANE2_I	Ulufale	Numera O PIXELS ✕ 10 bits	Maua Lane 2 faʻamatalaga tutusa mai XCVR
DATA_LANE1_I	Ulufale	Numera O PIXELS ✕ 10 bits	Maua Lane 1 faʻamatalaga tutusa mai XCVR
SCL_I	Ulufale	1	I2C fa'aoga uati fa'asologa mo DDC
HPD_I	Ulufale	1	Poloka vevela e iloa ai fa'ailo fa'aoga. O lo'o feso'ota'i le puna ile goto ole HPD faailoilo e tatau ona maualuga.
SDA_I	Ulufale	1	I2C fa'amaumauga fa'amaumauga mo DDC
EDID_CLK_I	Ulufale	1	Uati faiga mo I2C module
BIT_SLIP_LANE3_O	Tuuina atu	1	Fa'ailoga fa'ase'e i le Lane 3 o le transceiver
BIT_SLIP_LANE2_O	Tuuina atu	1	Fa'ailoga fa'ase'e i le Lane 2 o le transceiver
BIT_SLIP_LANE1_O	Tuuina atu	1	Fa'ailoga fa'ase'e i le Lane 1 o le transceiver
VIDEO_DATA_VALID_O	Tuuina atu	1	Fa'amatalaga vitiō fa'atino aoga
AUDIO_DATA_VALID_O	Tuuina atu	1	Fa'amatalaga fa'alogo fa'atino fa'amaonia
H_SYNC_O	Tuuina atu	1	Fa'asa'o fa'asaga i pulupulu
V_SYNC_O	Tuuina atu	1	Malosiaga tu'usa'o fa'agaoioi pusi

Igoa o le Taulaga	Fa'atonuga	Lautele (Piti)	Fa'amatalaga
Y_O	Tuuina atu	Numera O PIXELS ✕ Lanu loloto bits	Su'e fa'amatalaga "Y".
Cb_O	Tuuina atu	Numera O PIXELS ✕ Lanu loloto bits	Fa'aliliuina fa'amaumauga "Cb".
Cr_O	Tuuina atu	Numera O PIXELS ✕ Lanu loloto bits	Fa'aliliuina fa'amaumauga "Cr".
SDA_O	Tuuina atu	1	I2C fa'amaumauga fa'asologa fa'asologa mo DDC
HPD_O	Tuuina atu	1	Poloka vevela e iloa ai fa'ailo fa'aulufale
ACR_CTS_O	Tuuina atu	20	Taimi Fa'afouga Fa'afouina Uati leoamp taua
ACR_N_O	Tuuina atu	20	Fa'ata'otoga o le Fa'afouina o le Uati Fa'alogo (N).
ACR_VALID_O	Tuuina atu	1	Fa'ailoilo Fa'afouga Fa'afouina Uati leo
AUDIO_SAMPLE_CH1_O	Tuuina atu	24	Ala 1 leo sample faʻamatalaga
AUDIO_SAMPLE_CH2_O	Tuuina atu	24	Ala 2 leo sample faʻamatalaga
AUDIO_SAMPLE_CH3_O	Tuuina atu	24	Ala 3 leo sample faʻamatalaga
AUDIO_SAMPLE_CH4_O	Tuuina atu	24	Ala 4 leo sample faʻamatalaga
AUDIO_SAMPLE_CH5_O	Tuuina atu	24	Ala 5 leo sample faʻamatalaga
AUDIO_SAMPLE_CH6_O	Tuuina atu	24	Ala 6 leo sample faʻamatalaga
AUDIO_SAMPLE_CH7_O	Tuuina atu	24	Ala 7 leo sample faʻamatalaga
AUDIO_SAMPLE_CH8_O	Tuuina atu	24	Ala 8 leo sample faʻamatalaga

O le laulau o lo'o i lalo o lo'o lisiina ai ports o lo'o tu'uina atu ma fa'aulufaleina o le HDMI RX IP mo le fa'aoga Fa'a-Native pe a o le Fa'ailoga Lanu o le YUV422.

Laulau 4-6. Ulufale ma Galuega Fa'atino mo Fa'amatalaga Fa'a-Native

Igoa o le Taulaga	Fa'atonuga	Lautele (Piti)	Fa'amatalaga
RESET_N_I	Ulufale	1	Fa'ailoga toe setiina asynchronous-maualalo
LANE3_RX_CLK_I	Ulufale	1	Uati tutusa mo Lane 3 alalaupapa mai XCVR
LANE2_RX_CLK_I	Ulufale	1	Uati tutusa mo Lane 2 alalaupapa mai XCVR
LANE1_RX_CLK_I	Ulufale	1	Uati tutusa mo Lane 1 alalaupapa mai XCVR
EDID_RESET_N_I	Ulufale	1	Fa'ailoga toe setiina edid e fa'agaioi-maualalo asynchronous
LANE3_RX_VALID_I	Ulufale	1	Fa'ailoga aoga mai le XCVR mo fa'amaumauga tutusa o Lane 3
LANE2_RX_VALID_I	Ulufale	1	Fa'ailoga aoga mai le XCVR mo fa'amaumauga tutusa o Lane 2
LANE1_RX_VALID_I	Ulufale	1	Fa'ailoga aoga mai le XCVR mo fa'amaumauga tutusa o Lane 1
DATA_LANE3_I	Ulufale	Numera O PIXELS ✕ 10 bits	Maua Lane 3 faʻamatalaga tutusa mai XCVR
DATA_LANE2_I	Ulufale	Numera O PIXELS ✕ 10 bits	Maua Lane 2 faʻamatalaga tutusa mai XCVR
DATA_LANE1_I	Ulufale	Numera O PIXELS ✕ 10 bits	Maua Lane 1 faʻamatalaga tutusa mai XCVR
SCL_I	Ulufale	1	I2C fa'aoga uati fa'asologa mo DDC
HPD_I	Ulufale	1	Poloka vevela e iloa ai fa'ailo fa'aoga. O lo'o feso'ota'i le puna ile goto ole HPD faailoilo e tatau ona maualuga.
SDA_I	Ulufale	1	I2C fa'amaumauga fa'amaumauga mo DDC
EDID_CLK_I	Ulufale	1	Uati faiga mo I2C module
BIT_SLIP_LANE3_O	Tuuina atu	1	Fa'ailoga fa'ase'e i le Lane 3 o le transceiver
BIT_SLIP_LANE2_O	Tuuina atu	1	Fa'ailoga fa'ase'e i le Lane 2 o le transceiver
BIT_SLIP_LANE1_O	Tuuina atu	1	Fa'ailoga fa'ase'e i le Lane 1 o le transceiver
VIDEO_DATA_VALID_O	Tuuina atu	1	Fa'amatalaga vitiō fa'atino aoga

Igoa o le Taulaga	Fa'atonuga	Lautele (Piti)	Fa'amatalaga
AUDIO_DATA_VALID_O	Tuuina atu	1	Fa'amatalaga fa'alogo fa'atino fa'amaonia
H_SYNC_O	Tuuina atu	1	Fa'asa'o fa'asaga i pulupulu
V_SYNC_O	Tuuina atu	1	Malosiaga tu'usa'o fa'agaoioi pusi
Y_O	Tuuina atu	Numera O PIXELS ✕ Lanu loloto bits	Su'e fa'amatalaga "Y".
C_O	Tuuina atu	Numera O PIXELS ✕ Lanu loloto bits	Fa'ailoga "C" fa'amaumauga
SDA_O	Tuuina atu	1	I2C fa'amaumauga fa'asologa fa'asologa mo DDC
HPD_O	Tuuina atu	1	Poloka vevela e iloa ai fa'ailo fa'aulufale
ACR_CTS_O	Tuuina atu	20	Taimi Fa'afouga Fa'afouina Uati leoamp taua
ACR_N_O	Tuuina atu	20	Fa'ata'otoga o le Fa'afouina o le Uati Fa'alogo (N).
ACR_VALID_O	Tuuina atu	1	Fa'ailoilo Fa'afouga Fa'afouina Uati leo
AUDIO_SAMPLE_CH1_O	Tuuina atu	24	Ala 1 leo sample faʻamatalaga
AUDIO_SAMPLE_CH2_O	Tuuina atu	24	Ala 2 leo sample faʻamatalaga
AUDIO_SAMPLE_CH3_O	Tuuina atu	24	Ala 3 leo sample faʻamatalaga
AUDIO_SAMPLE_CH4_O	Tuuina atu	24	Ala 4 leo sample faʻamatalaga
AUDIO_SAMPLE_CH5_O	Tuuina atu	24	Ala 5 leo sample faʻamatalaga
AUDIO_SAMPLE_CH6_O	Tuuina atu	24	Ala 6 leo sample faʻamatalaga
AUDIO_SAMPLE_CH7_O	Tuuina atu	24	Ala 7 leo sample faʻamatalaga
AUDIO_SAMPLE_CH8_O	Tuuina atu	24	Ala 8 leo sample faʻamatalaga

O le laulau o lo'o i lalo o lo'o lisi ai ports o lo'o tu'uina atu ma fa'aulufaleina o le HDMI RX IP mo le fa'aoga fa'alenatura pe a fa'agaoioi le SCRAMBLER.

Laulau 4-7. Ulufale ma Galuega Fa'atino mo Fa'amatalaga Fa'a-Native

Igoa o le Taulaga	Fa'atonuga	Lautele (Piti)	Fa'amatalaga
RESET_N_I	Ulufale	1	Fa'ailoga toe setiina asynchronous-maualalo
R_RX_CLK_I	Ulufale	1	Uati tutusa mo le ala "R" mai le XCVR
G_RX_CLK_I	Ulufale	1	Uati tutusa mo le ala "G" mai le XCVR
B_RX_CLK_I	Ulufale	1	Uati tutusa mo le ala "B" mai le XCVR
EDID_RESET_N_I	Ulufale	1	Fa'ailoga toe setiina edid e fa'agaioi-maualalo asynchronous
HDMI_CABLE_CLK_I	Ulufale	1	Uati uaea mai le puna HDMI
R_RX_VALID_I	Ulufale	1	Fa'ailoga aoga mai le XCVR mo fa'amatalaga tutusa o le ala "R".
G_RX_VALID_I	Ulufale	1	Fa'ailoga aoga mai le XCVR mo fa'amatalaga tutusa o le ala "G".
B_RX_VALID_I	Ulufale	1	Fa'ailoga aoga mai le XCVR mo fa'amatalaga tutusa o le ala "B".
DATA_R_I	Ulufale	Numera O PIXELS ✕ 10 bits	Maua "R" alalaupapa tala tutusa mai XCVR
DATA_G_I	Ulufale	Numera O PIXELS ✕ 10 bits	Maua "G" alalaupapa tala tutusa mai XCVR
DATA_B_I	Ulufale	Numera O PIXELS ✕ 10 bits	Maua "B" alalaupapa tala tutusa mai XCVR
SCL_I	Ulufale	1	I2C fa'aoga uati fa'asologa mo DDC
HPD_I	Ulufale	1	Poloka vevela e iloa ai fa'ailo fa'aoga. O le puna e fesoʻotaʻi i le pusa, ma e tatau ona maualuga le faailo o le HPD.
SDA_I	Ulufale	1	I2C fa'amaumauga fa'amaumauga mo DDC
EDID_CLK_I	Ulufale	1	Uati faiga mo I2C module
BIT_SLIP_R_O	Tuuina atu	1	Fa'ailoga fa'ase'e i le ala "R" ole transceiver
BIT_SLIP_G_O	Tuuina atu	1	Fa'ailoga fa'ase'e i le ala "G" ole transceiver

Igoa o le Taulaga	Fa'atonuga	Lautele (Piti)	Fa'amatalaga
BIT_SLIP_B_O	Tuuina atu	1	Fa'ailoga fa'ase'e i le ala "B" ole transceiver
VIDEO_DATA_VALID_O	Tuuina atu	1	Fa'amatalaga vitiō fa'atino aoga
AUDIO_DATA_VALID_O	Galuega 1	1	Fa'amatalaga fa'alogo fa'atino fa'amaonia
H_SYNC_O	Tuuina atu	1	Fa'asa'o fa'asaga i pulupulu
V_SYNC_O	Tuuina atu	1	Malosiaga tu'usa'o fa'agaoioi pusi
FAAMATALAGA_ RATE_O	Tuuina atu	16	Rx fa'amaumauga fua. O lo'o taua i lalo le tau o fa'amaumauga: x1734 = 5940 Mbps x0B9A = 2960 Mbps  x05CD = 1485 Mbps x2E6 = 742.5 Mbps
R_O	Tuuina atu	Numera O PIXELS ✕ Lanu loloto bits	Fa'ailoga "R" fa'amaumauga
G_O	Tuuina atu	Numera O PIXELS ✕ Lanu loloto bits	Fa'aliliuina fa'amaumauga "G".
B_O	Tuuina atu	Numera O PIXELS ✕ Lanu loloto bits	Fa'aliliuina fa'amaumauga "B".
SDA_O	Tuuina atu	1	I2C fa'amaumauga fa'asologa fa'asologa mo DDC
HPD_O	Tuuina atu	1	Poloka vevela e iloa ai fa'ailo fa'aulufale
ACR_CTS_O	Tuuina atu	20	Taimi Fa'afouga Fa'afouina Uati leoamp taua
ACR_N_O	Tuuina atu	20	Fa'ata'otoga o le Fa'afouina o le Uati Fa'alogo (N).
ACR_VALID_O	Tuuina atu	1	Fa'ailoilo Fa'afouga Fa'afouina Uati leo
AUDIO_SAMPLE_CH1_O	Tuuina atu	24	Ala 1 leo sample faʻamatalaga
AUDIO_SAMPLE_CH2_O	Tuuina atu	24	Ala 2 leo sample faʻamatalaga
AUDIO_SAMPLE_CH3_O	Tuuina atu	24	Ala 3 leo sample faʻamatalaga
AUDIO_SAMPLE_CH4_O	Tuuina atu	24	Ala 4 leo sample faʻamatalaga
AUDIO_SAMPLE_CH5_O	Tuuina atu	24	Ala 5 leo sample faʻamatalaga
AUDIO_SAMPLE_CH6_O	Tuuina atu	24	Ala 6 leo sample faʻamatalaga
AUDIO_SAMPLE_CH7_O	Tuuina atu	24	Ala 7 leo sample faʻamatalaga
AUDIO_SAMPLE_CH8_O	Tuuina atu	24	Ala 8 leo sample faʻamatalaga

Testbench Simulation (Fai se Fesili)

Ua tuʻuina atu le Testbench e siaki ai le faʻatinoga o le HDMI RX autu. E na'o le Native Interface e galue le Testbench pe a tasi le numera o pika.

Ina ia faʻataʻitaʻiina le autu e faʻaaoga ai le testbench, fai laasaga nei:

1. I le fa'amalama o le Fuafuaga Fa'asolo, fa'alautele le Fausia Fa'ailoga.
2. Kiliki-matau Fausia SmartDesign Testbench, ona kiliki lea o le Run, e pei ona faʻaalia i le ata o loʻo i lalo.
   Ata 5-1. Fausia SmartDesign Testbench
3. Ulufale se igoa mo le SmartDesign testbench, ona kiliki lea OK.
   Ata 5-2. Fa'aigoa SmartDesign TestbenchSmartDesign testbench ua faia, ma o se tapoleni e aliali i le itu taumatau o le Design Flow pane.
4. Su'e ile Libero® SoC Catalog, filifili View > Pupuni > IP Catalog, ona fa'alautele lea o Fofo-Vitio. Kiliki faalua HDMI RX IP (v5.4.0) ona kiliki lea o le OK.
5. Filifili uma ports, kiliki-matau ma filifili Promote to Top Level.
6. I luga o le SmartDesign toolbar, kiliki Fausia Vaega.
7. I luga ole Stimulus Hierarchy tab, kiliki-matau HDMI_RX_TB testbench file, ona kiliki lea Simulate Pre-Synth Design > Open Interactively.

O le ModelSim® meafaigaluega e tatala i le suʻega suʻega, e pei ona faʻaalia i le ata o loʻo i lalo.

Ata 5-3. ModelSim Tool ma HDMI RX Testbench File

Taua: If ua fa'alavelaveina le fa'ata'ita'iga ona o le fa'atapula'aina o le taimi fa'amaoti i le DO file, faʻaaoga le taʻavale -all command e faʻamaeʻa ai le faʻataʻitaʻiga.

Laisene (Fai se Fesili)

HDMI RX IP o loʻo tuʻuina atu i ai avanoa laisene e lua:

• Fa'ailoga: O lo'o tu'uina atu le fa'ailoga fa'ailoga RTL atoa mo le autu. E avanoa mo le leai o se totogi ma soʻo se laisene Libero, e mafai ai ona faʻapipiʻi le autu ma SmartDesign. E mafai ona e faia le Simulation, Synthesis, Layout, ma polokalame le FPGA silicon e faʻaaoga ai le Libero design suite.
• RTL: O le RTL source code atoa o lo'o loka laisene, lea e mana'omia ona fa'atau eseese.

I'uga Fa'ata'ita'iga (Fai se Fesili)

O le ata o loʻo mulimuli mai mo le HDMI RX IP o loʻo faʻaalia ai faʻamatalaga vitio ma faʻatonu taimi faʻamaumauga.

Ata 6-1. Fa'amatalaga Vitio

O le ata o loʻo i lalo o loʻo faʻaalia ai galuega a le hsync ma le vsync mo faʻamaumauga o faʻamaumauga tutusa.

Ata 6-2. Fa'ailoga Fa'asa'o Fa'asaga'i ma Fa'ailoga Fa'asa'o

O le ata o loʻo i lalo o loʻo faʻaalia ai le vaega EDID.

Ata 6-3. Faailoga EDID

Fa'aaogāina o Punaoa (Fai se Fesili)

HDMI RX IP o loʻo faʻatinoina i le PolarFire® FPGA (MPF300T - 1FCG1152I Package). Ole siata o lo'o i lalo o lo'o lisiina ai punaoa na fa'aaogaina pe a Numera o Pixels = 1 pika.

Laulau 7-1. Fa'aogaina o Punaoa mo le 1 Pixel Mode

Fa'ailoga lanu	Lanu loloto	TAGATA FA'AVAE	Ie 4LUT	Ie DFF	Fa'aoga 4LUT	Fa'aoga DFF	uSRAM (64×12)	LSRAM (20k)
RGB	8	Fa'agata	987	1867	360	360	0	10
	10	Fa'agata	1585	1325	456	456	11	9
	12	Fa'agata	1544	1323	456	456	11	9
	16	Fa'agata	1599	1331	492	492	14	9
YCbCr422	8	Fa'agata	1136	758	360	360	3	9
YCbCr444	8	Fa'agata	1105	782	360	360	3	9
	10	Fa'agata	1574	1321	456	456	11	9
	12	Fa'agata	1517	1319	456	456	11	9
	16	Fa'agata	1585	1327	492	492	14	9

Ole siata o lo'o i lalo o lo'o lisiina ai punaoa na fa'aaogaina pe a Numera o Pixels = 4 pika.

Laulau 7-2. Fa'aogaina o Punaoa mo le 4 Pixel Mode

Fa'ailoga lanu	Lanu loloto	TAGATA FA'AVAE	Ie 4LUT	Ie DFF	Fa'aoga 4LUT	Fa'aoga DFF	uSRAM (64×12)	LSRAM (20k)
RGB	8	Fa'agata	1559	1631	1080	1080	9	27
	12	Fa'agata	1975	2191	1344	1344	31	27
	16	Fa'agata	1880	2462	1428	1428	38	27
RGB	10	Fa'amalo	4231	3306	1008	1008	3	27
	12	Fa'amalo	4253	3302	1008	1008	3	27
	16	Fa'amalo	3764	3374	1416	1416	37	27
YCbCr422	8	Fa'agata	1485	1433	912	912	7	23
YCbCr444	8	Fa'agata	1513	1694	1080	1080	9	27
	12	Fa'agata	2001	2099	1344	1344	31	27
	16	Fa'agata	1988	2555	1437	1437	38	27

Ole laulau o lo'o i lalo o lo'o lisiina ai punaoa e fa'aogaina pe a fa'aogaina Numera o Pika = 4 pika ma SCRAMBLER.

Laulau 7-3. Fa'aaogaina Punaoa mo le 4 Pixel Mode ma le SCRAMBLER ua fa'aagaoioia

Fa'ailoga lanu	Lanu loloto	TAGATA FA'AVAE	Ie 4LUT	Ie DFF	Fa'aoga 4LUT	Fa'aoga DFF	uSRAM (64×12)	LSRAM (20k)
RGB	8	Fa'amalo	5029	5243	1126	1126	9	28
YCbCr422	8	Fa'amalo	4566	3625	1128	1128	13	27
YCbCr444	8	Fa'amalo	4762	3844	1176	1176	17	27

System Integration (Fai se Fesili)

O lenei vaega o loʻo faʻaalia ai le faʻaogaina o le IP ile mamanu Libero.
O le laulau o loʻo i lalo o loʻo lisiina ai faʻatonuga o le PF XCVR, PF TX PLL ma le PF CCC e manaʻomia mo faʻaiuga eseese ma lautele lautele.

Laulau 8-1. PF XCVR, PF TX PLL ma PF CCC Configurations

I'ugafono	Bit Lautele	PF XCVR Fa'atonuga			CDR REF CLOCK PADS	PF CCC Configuration
		RX Fa'amatalaga Fa'amatalaga	RX CDR Ref Uati Fa'atele	RX PCS Lautele Ie		Fa'auiga Fa'atele	Fa'auiga Fa'alava
1 PXL (1080p60)	8	1485	148.5	10	AE27, AE28	NA	NA
1 PXL (1080p30)	10	1485	148.5	10	AE27, AE28	92.5	74
	12	1485	148.5	10	AE27, AE28	74.25	111.375
	16	1485	148.5	10	AE27, AE28	74.25	148.5
4 PXL (1080p60)	8	1485	148.5	40	AE27, AE28	NA	NA
	12	1485	148.5	40	AE27, AE28	55.725	37.15
	16	1485	148.5	40	AE27, AE28	74.25	37.125
4 PXL (4kp30)	8	1485	148.5	40	AE27, AE28	NA	NA
	10	3712.5	148.5	40	AE29, AE30	92.81	74.248
	12	4455	148.5	40	AE29, AE30	111.375	74.25
	16	5940	148.5	40	AE29, AE30	148.5	74.25
4 PXL (4Kp60)	8	5940	148.5	40	AE29, AE30	NA	NA

HDMI RX Sample Fuafuaga 1: A faʻapipiʻi i le Laʻau Laʻau = 8-bit ma Numera o Pixels = 1 Pixel mode, o loʻo faʻaalia i le ata o loʻo i lalo.

Ata 8-1. HDMI RX Sample Design 1

Mo example, i 8-bit configurations, o vaega nei o le vaega o le mamanu:

• PF_XCVR_ERM (PF_XCVR_ERM_C0_0) ua configured mo TX ma RX faiga duplex atoa. RX faʻamaumauga o le 1485 Mbps i le PMA mode, faʻatasi ai ma le lautele o faʻamatalaga faʻatulagaina e pei o le 10 bit mo le 1 PXL mode ma le 148.5 MHz CDR faʻamatalaga uati. TX faʻamaumauga o le 1485 Mbps i le PMA mode, faʻatasi ai ma le lautele o faʻamatalaga ua faʻatulagaina e pei o le 10 bit ma le vaega vaevaega o le uati 4.
• LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK ma LANE3_CDR_REF_CLK e tuli mai le PF_XCVR_REF_CLK ma AE27, AE28 Pad pine.
• EDID CLK_I pine e tatau ona ave ile 150 MHz uati ile CCC.
• R_RX_CLK_I, G_RX_CLK_I ma B_RX_CLK_I o lo'o fa'atautaia e LANE3_TX_CLK_R, LANE2_TX_CLK_R ma LANE1_TX_CLK_R.
• R_RX_VALID_I, G_RX_VALID_I ma B_RX_VALID_I o lo'o tulia e LANE3_RX_VAL, LANE2_RX_VAL ma LANE1_RX_VAL.
• DATA_R_I, DATA_G_I ma DATA_B_I o lo'o fa'auluina e LANE3_RX_DATA, LANE2_RX_DATA ma LANE1_RX_DATA.

HDMI RX Sample Fuafuaga 2: A faʻapipiʻi i le Laʻau Laʻau = 8-bit ma Numera o Pixels = 4 Pixel mode, o loʻo faʻaalia i le ata o loʻo i lalo.

Ata 8-2. HDMI RX Sample Design 2

Mo example, i 8-bit configurations, o vaega nei o le vaega o le mamanu:

• PF_XCVR_ERM (PF_XCVR_ERM_C0_0) ua configured mo TX ma RX faiga duplex atoa. RX faʻamaumauga o le 1485 Mbps i le PMA mode, faʻatasi ai ma le lautele o faʻamatalaga faʻatulagaina e pei o le 40 bit mo le 4 PXL mode ma le 148.5 MHz CDR faʻamatalaga uati. TX faʻamaumauga o le 1485 Mbps i le PMA mode, faʻatasi ai ma le lautele o faʻamatalaga ua faʻatulagaina e pei o le 40 bit ma le vaega vaevaega o le uati 4.
• LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK ma LANE3_CDR_REF_CLK e tuli mai le PF_XCVR_REF_CLK ma AE27, AE28 Pad pine.
• EDID CLK_I pine e tatau ona ave ile 150 MHz uati ile CCC.
• R_RX_CLK_I, G_RX_CLK_I ma B_RX_CLK_I o lo'o fa'atautaia e LANE3_TX_CLK_R, LANE2_TX_CLK_R ma LANE1_TX_CLK_R.
• R_RX_VALID_I, G_RX_VALID_I ma B_RX_VALID_I o lo'o tulia e LANE3_RX_VAL, LANE2_RX_VAL ma LANE1_RX_VAL.
• DATA_R_I, DATA_G_I ma DATA_B_I o lo'o fa'auluina e LANE3_RX_DATA, LANE2_RX_DATA ma LANE1_RX_DATA.

HDMI RX Sample Fuafuaga 3: Pe a faʻapipiʻiina i le Laelea o le Lanu = 8-bit ma Numera o Pixels = 4 Pixel mode ma SCRAMBLER = Enabled, o loʻo faʻaalia i le ata o loʻo i lalo.

Ata 8-3. HDMI RX Sample Design 3

Mo example, i 8-bit configurations, o vaega nei o le vaega o le mamanu:

• PF_XCVR_ERM (PF_XCVR_ERM_C0_0) ua configured mo TX ma RX tulaga Tutoatasi. RX faʻamaumauga o le 5940 Mbps i le PMA mode, faʻatasi ai ma le lautele o faʻamatalaga faʻatulagaina e pei o le 40 bit mo le 4 PXL mode ma le 148.5 MHz CDR faʻamatalaga uati. TX faʻamaumauga o le 5940 Mbps i le PMA mode, faʻatasi ai ma le lautele o faʻamatalaga faʻatulagaina e pei o le 40 bit ma le vaega vaevaega o le uati 4.
• LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK ma LANE3_CDR_REF_CLK e tuli mai le PF_XCVR_REF_CLK ma AF29, AF30 Pad pine.
• EDID CLK_I pine e tatau ona ave i le 150 MHz uati ma CCC.
• R_RX_CLK_I, G_RX_CLK_I ma B_RX_CLK_I o lo'o fa'atautaia e LANE3_TX_CLK_R, LANE2_TX_CLK_R ma LANE1_TX_CLK_R.
• R_RX_VALID_I, G_RX_VALID_I ma B_RX_VALID_I o lo'o tulia e LANE3_RX_VAL, LANE2_RX_VAL ma LANE1_RX_VAL.
• DATA_R_I, DATA_G_I ma DATA_B_I o lo'o fa'auluina e LANE3_RX_DATA, LANE2_RX_DATA ma LANE1_RX_DATA.

HDMI RX Sample Fuafuaga 4: Pe a faʻapipiʻiina i le Laelea o le Lanu = 12-bit ma Numera o Pixels = 4 Pixel mode ma SCRAMBLER = Enabled, o loʻo faʻaalia i le ata o loʻo i lalo.

Ata 8-4. HDMI RX Sample Design 4

Mo example, i 12-bit configurations, o vaega nei o le vaega o le mamanu:

• PF_XCVR_ERM (PF_XCVR_ERM_C0_0) ua configured mo RX Na'o le faiga. RX faʻamaumauga o le 4455 Mbps i le PMA mode, faʻatasi ai ma le lautele o faʻamatalaga faʻatulagaina e pei o le 40 bit mo le 4 PXL mode ma le 148.5 MHz CDR faʻamatalaga uati.
• LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK ma LANE3_CDR_REF_CLK e tuli mai le PF_XCVR_REF_CLK ma AF29, AF30 Pad pine.
• EDID CLK_I pine e tatau ona ave i le 150 MHz uati ma CCC.
• R_RX_CLK_I, G_RX_CLK_I ma B_RX_CLK_I o lo'o fa'atautaia e LANE3_TX_CLK_R, LANE2_TX_CLK_R ma LANE1_TX_CLK_R.
• R_RX_VALID_I, G_RX_VALID_I ma B_RX_VALID_I o lo'o tulia e LANE3_RX_VAL, LANE2_RX_VAL ma LANE1_RX_VAL.
• DATA_R_I, DATA_G_I ma DATA_B_I o lo'o fa'auluina e LANE3_RX_DATA, LANE2_RX_DATA ma LANE1_RX_DATA.
• O le PF_CCC_C0 module e gaosia ai se uati e igoa OUT0_FABCLK_0 fa'atasi ai ma le tele o le 74.25 MHz, e maua mai i le uati fa'aoga o le 111.375 MHz, lea e fa'aulu e LANE1_RX_CLK_R.

HDMI RX Sample Fuafuaga 5: Pe a faʻapipiʻiina i le Laelea o le Lanu = 8-bit, Numera o Pixels = 4 Pixel mode ma SCRAMBLER = Enabled o loʻo faʻaalia i le ata o loʻo i lalo. O lenei mamanu o le fa'asologa o fa'amaumauga fa'atasi ma le DRI.

Ata 8-5. HDMI RX Sample Design 5

Mo example, i 8-bit configurations, o vaega nei o le vaega o le mamanu:

• PF_XCVR_ERM (PF_XCVR_ERM_C0_0) o loʻo faʻatulagaina mo le RX Naʻo le faiga faʻatasi ai ma le faʻaogaina o fesoʻotaʻiga faʻafouina. RX faʻamaumauga o le 5940 Mbps i le PMA mode, faʻatasi ai ma le lautele o faʻamatalaga faʻatulagaina e pei o le 40 bit mo le 4 PXL mode ma le 148.5 MHz CDR faʻamatalaga uati.
• LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK ma LANE3_CDR_REF_CLK e tuli mai le PF_XCVR_REF_CLK ma AF29, AF30 Pad pine.
• EDID CLK_I pine e tatau ona ave i le 150 MHz uati ma CCC.
• R_RX_CLK_I, G_RX_CLK_I ma B_RX_CLK_I o lo'o fa'atautaia e LANE3_TX_CLK_R, LANE2_TX_CLK_R ma LANE1_TX_CLK_R.
• R_RX_VALID_I, G_RX_VALID_I ma B_RX_VALID_I o lo'o tulia e LANE3_RX_VAL, LANE2_RX_VAL ma LANE1_RX_VAL.
• DATA_R_I, DATA_G_I ma DATA_B_I o lo'o fa'auluina e LANE3_RX_DATA, LANE2_RX_DATA ma LANE1_RX_DATA.

Toe Iloilo Tala'aga (Fai se Fesili)

O le tala fa'asolopito o lo'o fa'amatalaina suiga na fa'atinoina i le pepa. O suiga o lo'o lisiina e ala i toe iloiloga, amata i le lomiga aupito lata mai.

Laulau 9-1. Toe Iloilo Tala'aga

Toe Iloiloga	Aso	Fa'amatalaga
D	02/2025	Ole lisi lea o suiga na faia ile toe teuteuga C ole pepa: Faʻafouina le HDMI RX IP version i le 5.4. Fa'afou Fa'atomuaga fa'atasi ai ma foliga ma fa'ailoga e le'i lagolagoina. Fa'aopoopoina le vaega o Meafaitino Fa'ata'ita'i. Fa'afou le Ata 3-1 ma le Ata 3-3 ile vaega ole Fa'atinoga o Meafaigaluega. Fa'aopoopo le vaega o Fa'atonuga. Fa'afou le Laulau 4-2, Laulau 4-4, Laulau 4-5, Laulau 4-6 ma Laulau 4-7 ile vaega o Taulaga. Faʻafouina Ata 5-2 i le vaega Testbench Simulation. Fa'afou le Laulau 7-1 ma le Laulau 7-2 fa'aopoopo le Laulau 7-3 i le vaega o le Fa'aaogāina o Punaoa. Faʻafouina Ata 8-1, Ata 8-2, Ata 8-3 ma le Ata 8-4 i le vaega o le System Integration. Fa'aopoopoina fa'amaumauga fa'amalositino fa'atasi ma le DRI design example i le System Integration vaega.
C	02/2023	Ole lisi lea o suiga na faia ile toe teuteuga C ole pepa: Faʻafouina le HDMI RX IP version i le 5.2 Fa'afou le fa'ai'uga lagolago ile fa pika fa'ata'ita'i ile pepa atoa Fa'afouina Ata 2-1
B	09/2022	Ole lisi lea o suiga na faia ile toe iloiloga B ole pepa: Fa'afou le pepa mo v5.1 Fa'afouina le Laulau 4-2 ma le Laulau 4-3
A	04/2022	Ole lisi lea o suiga ile toe iloiloga A ole pepa: O le pepa na ave i le mamanu Microchip Ole numera ole pepa na fa'afouina ile DS50003298A mai le 50200863 Fa'afou vaega TMDS Decoder Fa'afou laulau 4-2 ma le Laulau 4-3  Fa'afouina Ata 5-3, Ata 6-1, Ata 6-2
2.0	—	O lo'o i lalo le aotelega o suiga na faia i lenei toe iloiloga. Faaopoopo le Laulau 4-3 Fa'afou laulau Fa'aaogāga Punaoa
1.0	08/2021	Toe Iloiloga Muamua.

Microchip FPGA Lagolago
Microchip FPGA products group backs its products with various support services, including Customer Service, Customer Technical Support Center, a webnofoaga, ma ofisa faatau i le lalolagi atoa. E fautuaina tagata fa'atau e asiasi i Microchip i luga ole laiga a'o le'i fa'afeso'ota'i le lagolago ona e foliga mai ua uma ona tali a latou fesili. Fa'afeso'ota'i le Nofoaga Autu Lagolago Fa'apitoa e ala ile webnofoaga i www.microchip.com/support. Ta'u le numera o le Vaega o Meafaigaluega FPGA, filifili le vaega o mataupu talafeagai, ma fa'apipi'i le mamanu files a'o faia se mataupu lagolago fa'apitoa. Fa'afeso'ota'i Auaunaga Fa'atau mo le lagolago o oloa e le fa'apitoa, e pei o le tau o oloa, fa'aleleia o oloa, fa'afouga fa'amatalaga, tulaga oka, ma le fa'atagaina.

• Mai Amerika i Matu, valaau 800.262.1060
• Mai le lalolagi atoa, valaau 650.318.4460
• Fax, mai so'o se mea i le lalolagi, 650.318.8044

Microchip Fa'amatalaga

Fa'ailoga Fa'ailoga
O le igoa "Microchip" ma le logo, le "M" logo, ma isi igoa, logos, ma faʻailoga o loʻo resitalaina ma faʻailoga faʻailoga a le Microchip Technology Incorporated poʻo ana paaga ma / poʻo lala i le Iunaite Setete ma / poʻo isi atunuu ("Microchip Fa'ailoga”). Fa'amatalaga e uiga i Microchip Trademarks e mafai ona maua ile https://www.microchip.com/en-us/about/legal-information/microchip-trademarks.

ISBN: 979-8-3371-0744-8

Faasilasilaga Faaletulafono
O lenei lomiga ma faʻamatalaga o loʻo i totonu e mafai ona faʻaaogaina naʻo oloa Microchip, e aofia ai le mamanu, suʻega, ma tuʻufaʻatasia oloa Microchip ma lau talosaga. O le fa'aogaina o nei fa'amatalaga i so'o se isi lava faiga e solia ai nei aiaiga. O fa'amatalaga e uiga i le fa'aogaina o masini e tu'uina atu mo na'o lou fa'amalieina ma e ono suia i fa'afouga. O lau matafaioi le faʻamautinoa o lau talosaga e fetaui ma au faʻamatalaga. Fa'afeso'ota'i lou ofisa fa'atau Microchip fa'apitonu'u mo se lagolago fa'aopoopo pe, maua se lagolago fa'aopoopo ile www.microchip.com/en-us/support/design-help/client-support-services.

O LENEI FAʻAMATALAGA E TUUINA E MICROCHIP "AS IS". E LEAI FAIA e le MICROCHIP ni sui po'o se fa'amaoniga o so'o se ituaiga pe fa'aalia pe fa'aali, tusia pe tugutu, tulāfono po'o se isi mea, e feso'ota'i ma fa'amatalaga e aofia ai ae le tapula'a i so'o se fa'amaoniaga fa'amaonia, fa'amaonia, ma le fa'amaoniaina. FAAMOEMOEGA, POO WARRANTY E FAI I ONA TULAGA, TULAGA, POO LE FAIGALUEGA.
E LEAI SE MEA E TATAU AI MICROCHIP MO SO'O SE FA'AMATALAGA, FA'AMATALAGA, FA'ASA'OGA, FA'AMATALAGA, PO'O LE FA'A'ALI'AGA MA'U'U, FA'AFIA, TAU, PO'O LE TU'U'UINA O SO'O SE I'UGA SO'O SE FA'AIGA I LE FA'AMATALAGA POO LONA FA'A'OGA, PE'O LE MEA NA FA'AUPUNA'I, E tusa lava pe fa'aletonu. FA'ATONU POO LE FA'AFIA E FA'AVAEINA. I LE AGATOGA FA'AALIGA E LE TULAFONO, O LE UMA AOFA'IGA A MICROCHIP I TOTOGI UMA I SO'O SE AUALA E FA'AIGA I LE FA'AMATALAGA POO LONA FA'A'OGA E LE'A LOLOA I LE TOTOGI O TOTOGI, AFAI E IAI, NA E TOTOGI SA'O I LE MICROCHIP MO LE FA'AMATALAGA.
O le fa'aogaina o masini Microchip i le tausiga o le ola ma/po'o le saogalemu o lo'o i le tulaga lamatia o le tagata fa'atau, ma e malie le tagata fa'atau e puipuia, fa'aleaga ma taofia Microchip le afaina mai so'o se mea leaga, tagi, suti, po'o tupe alu e mafua mai i lea fa'aoga. E leai ni laisene e tu'uina atu, fa'aalia po'o se isi mea, i lalo o so'o se Microchip aia tatau tau le atamai se'i vagana ua ta'ua.

Fa'ailoga Puipuiga o Fa'ailoga Fa'atonu a Microchip

Manatua faʻamatalaga o loʻo i lalo o le faʻaogaina o le puipuiga o tulafono i luga o oloa Microchip:

• O oloa Microchip e fetaui ma faʻamatalaga o loʻo i totonu o la latou Pepa Faʻamatalaga Microchip.
• E talitonu Microchip o lona aiga o oloa e saogalemu pe a faʻaaogaina i le auala faʻamoemoeina, i totonu o faʻamatalaga faʻaogaina, ma i lalo o tulaga masani.
• Microchip fa'atauaina ma puipuia fa'amalosi ana aia tatau tau meatotino. O taumafaiga e soli le tulafono o le puipuiga o oloa Microchip e matua fa'asaina ma e ono solia ai le Digital Millennium Copyright Act.
• E le mafai e le Microchip poʻo se isi mea gaosi semiconductor ona faʻamaonia le saogalemu o lana tulafono. O le puipuiga o tulafono laiti e le o lona uiga tatou te faʻamautinoa o le oloa e "le mafai ona motusia". O le puipuiga o tulafono laiti o lo'o fa'asolosolo pea. Microchip ua tuuto atu i le faʻaauauina pea o le faʻaleleia atili o uiga puipuia o tulafono a tatou oloa.

© 2025 Microchip Technology Inc. ma ona lala

FAQ

• Q: E fa'afefea ona ou fa'afouina le HDMI RX IP core?
  A: O le IP autu e mafai ona faʻafouina e ala i le Libero SoC software poʻo le sii mai ma le lima mai le lisi. A maeʻa ona faʻapipiʻi i le Libero SoC software IP Catalog, e mafai ona faʻapipiʻiina, gaosia, ma faʻapipiʻi i totonu o SmartDesign mo le faʻaofiina i totonu o le poloketi.

Pepa / Punaoa

MICROCHIP PolarFire FPGA High Definition Multimedia Interface HDMI Receiver [pdf] Taiala mo Tagata Fa'aoga PolarFire FPGA, PolarFire FPGA High Definition Multimedia Interface HDMI Receiver, High Definition Multimedia Interface HDMI Receiver, Multimedia Interface HDMI Receiver, Interface HDMI Receiver, HDMI Receiver

Fa'asinomaga

• Tusi Taiala