Cov ntsiab lus zais
1 MICROCHIP PolarFire FPGA Siab txhais Multimedia Interface HDMI Receiver
2 Cov ntsiab lus
3 Nta
4 Tested Source Devices (Nug ib lo lus nug)
5 HDMI RX IP Configuration (Nug ib lo lus nug)
6 Hardware Implementation (Nug ib lo lus nug)
7 HDMI RX Parameters thiab Interface Signals (Nug ib lo lus nug)
8 Testbench Simulation (Nug ib lo lus nug)
9 Simulation Results (Nug ib lo lus nug)
10 Kev siv peev txheej (nug ib lo lus nug)
11 System Integration (Nug ib lo lus nug)
12 Revision History (Nug ib lo lus nug)
13 Cov ntaub ntawv Microchip
14 FAQ
15 Cov ntaub ntawv / Cov ntaub ntawv
15.1 Cov ntaub ntawv
16 Related Posts

MICROCHIP-LOGO

MICROCHIP PolarFire FPGA Siab txhais Multimedia Interface HDMI Receiver

MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- PRODUCT-IMAGE

Introduction (Nug ib lo lus nug)
Microchip's High-Definition Multimedia Interface (HDMI) receiver IP txhawb nqa cov ntaub ntawv video thiab audio packet cov ntaub ntawv txais tau piav qhia hauv HDMI tus qauv specification. HDMI RX IP yog tsim tshwj xeeb rau PolarFire® FPGA thiab PolarFire System ntawm Chip (SoC) FPGA li txhawb HDMI 2.0 rau kev daws teeb meem txog 1920 × 1080 ntawm 60 Hz hauv ib pixel hom thiab mus txog 3840 × 2160 ntawm 60 Hz hauv plaub pixel hom. RX IP txhawb nqa Kub Plug Detect (HPD) rau kev saib xyuas lub zog ntawm lossis tawm thiab tshem tawm lossis ntsaws cov xwm txheej los qhia kev sib txuas lus ntawm HDMI qhov chaw thiab HDMI dab dej.

Lub HDMI qhov chaw siv Display Data channel (DDC) los nyeem lub dab dej Extended Display Identification Data (EDID) kom pom lub dab dej qhov teeb tsa thiab / lossis muaj peev xwm. Lub HDMI RX IP muaj pre-programmed EDID, uas ib tug HDMI qhov chaw yuav nyeem tau los ntawm tus qauv I2C channel. PolarFire FPGA thiab PolarFire SoC FPGA ntaus ntawv transceivers yog siv nrog rau RX IP los deserialize cov ntaub ntawv serial rau hauv 10-ntsis cov ntaub ntawv. Cov ntaub ntawv raws hauv HDMI tau tso cai kom muaj qhov sib txawv ntawm lawv. Lub HDMI RX IP tshem tawm cov skew ntawm cov ntaub ntawv raws siv First-In First-Out (FIFOs). Qhov IP no hloov pauv cov ntaub ntawv hloov pauv Minimized Differential Signaling (TMDS) cov ntaub ntawv tau txais los ntawm HDMI qhov chaw los ntawm transceiver rau 24-ntsis RGB pixel cov ntaub ntawv, 24-ntsis suab ntaub ntawv thiab tswj cov teeb liab. Plaub tus qauv tswj tokens teev nyob rau hauv HDMI raws tu qauv yog siv rau theem dlhos cov ntaub ntawv thaum deserialization.

Cov ntsiab lus

Cov lus hauv qab no muab cov ntsiab lus ntawm HDMI RX IP yam ntxwv.

Table 1. HDMI RX IP yam ntxwv

Core Version Cov neeg siv phau ntawv qhia no txhawb HDMI RX IP v5.4.
Txhawb Cov Tsev Neeg
  • PolarFire® SoC
  • PolarFire
Txhawb Tool Flow Yuav tsum tau Libero® SoC v12.0 lossis tom qab tso tawm.
Txhawb Interfaces Interfaces txhawb los ntawm HDMI RX IP yog:
  • AXI4-Stream: Cov tub ntxhais no txhawb nqa AXI4-kwj mus rau qhov chaw tso zis. Thaum teeb tsa hauv hom no, IP outputs AXI4 Stream tus qauv kev tsis txaus siab teeb liab.
  • Haiv neeg: Thaum teeb tsa hauv hom no, IP outputs haiv neeg yees duab thiab suab teeb liab.
Daim ntawv tso cai HDMI RX IP yog muab nrog ob daim ntawv tso cai hauv qab no:
  • Encrypted: Ua kom tiav encrypted RTL code yog muab rau cov tub ntxhais. Nws muaj pub dawb nrog ib qho ntawm Libero daim ntawv tso cai, ua kom cov tub ntxhais ua kom nrawm nrog SmartDesign. Koj tuaj yeem ua Simulation, Synthesis, Layout thiab program FPGA silicon siv Libero tsim suite.
  • RTL: Ua tiav RTL qhov chaws yog daim ntawv tso cai kaw, uas yuav tsum tau yuav nyias.

Nta

HDMI RX IP muaj cov yam ntxwv hauv qab no:

  • Tau tshaj rau HDMI 2.0
  • Txhawb 8, 10, 12 thiab 16 Bits Xim Qhov tob
  • Txhawb xim hom xws li RGB, YUV 4: 2: 2 thiab YUV 4: 4: 4
  • Txhawb Ib lossis Plaub Pixels Ib Lub Clock Input
  • Txhawb kev daws teeb meem txog 1920 ✕ 1080 ntawm 60 Hz hauv Ib Pixel hom thiab mus txog 3840 ✕ 2160 ntawm 60 Hz hauv plaub Pixel hom.
  • Pom Kub-Plug
  • Txhawb Kev Txiav Txim Siab - TMDS
  • Txhawb DVI Input
  • Txhawb Display Data Channel (DDC) thiab Enhanced Display Data Channel (E-DDC)
  • Txhawb haiv neeg thiab AXI4 Stream Video Interface rau Video Data Transfer
  • Txhawb haiv neeg thiab AXI4 Kwj Suab Interface rau Suab Cov Ntaub Ntawv Hloov

Unsupported Features

Hauv qab no yog cov yam ntxwv tsis txhawb nqa ntawm HDMI RX IP:

  • 4: 2: 0 xim hom tsis txaus siab.
  • High Dynamic Range (HDR) thiab High-bandwidth Digital Content Protection (HDCP) tsis txaus siab.
  • Tsis muaj qhov hloov pauv hloov tshiab (VRR) thiab Tsis Siv Neeg Tsis Siv Neeg Latency Mode (ALLM) tsis txaus siab.
  • Kab rov tav Sijhawm tsis tau uas tsis tau faib los ntawm plaub hauv plaub Pixel hom tsis txaus siab.

Cov lus qhia installation
Cov tub ntxhais IP yuav tsum tau nruab rau IP Catalog ntawm Libero® SoC software tau txais los ntawm IP Catalog hloov tshiab muaj nuj nqi hauv Libero SoC software, lossis nws yog manually rub tawm los ntawm phau ntawv teev npe. Thaum tus tub ntxhais IP raug teeb tsa hauv Libero SoC software IP Catalog, nws tau teeb tsa, tsim thiab ua tiav hauv Smart Design rau kev suav nrog hauv Libero project.

Tested Source Devices (Nug ib lo lus nug)

Cov lus hauv qab no teev cov khoom siv kuaj sim.

Table 1-1. Tested Sources Devices

Cov khoom siv Pixel Hom Kev daws teeb meem kuaj Xim qhov tob (ntsis) Xim hom Suab
quantumdata™ M41h HDMI Analyzer 1 720P 30 FPS, 720P 60 FPS thiab 1080P 60 FPS 8 RGB, YUV 444, YUV 422 Yog lawm
1080P 30 FPS 8, 10, 12 thiab 16
4 720P 30 FPS, 1080P 30 FPS thiab 4K 60 FPS 8
1080P 60 FPS 8, 12 thiab 16
4K 30 FPS 8, 10, 12 thiab 16
Lenovo™ 20U1A007IG 1 1080P 60 FPS 8 RGB Yog lawm
4 1080P 60 FPS thiab 4K 30 FPS
Dell Latitude 3420 1 1080P 60 FPS 8 RGB Yog lawm
4 4K 30 FPS thiab 4K 60 FPS
Astro VA-1844A HDMI® Tester 1 720P 30 FPS, 720P 60 FPS thiab 1080P 60 FPS 8 RGB, YUV 444, YUV 422 Yog lawm
1080P 30 FPS 8, 10, 12 thiab 16
4 720P 30 FPS, 1080P 30 FPS thiab 4K 30 FPS 8
1080P 30 FPS 8, 12 thiab 16
NVIDIA® Jetson AGX Orin 32GB H01 Kit 1 1080P 30 FPS 8 RGB Tsis muaj
4 4K 60 FPS

HDMI RX IP Configuration (Nug ib lo lus nug)

Ntu no muab ib qho ntxivview ntawm HDMI RX IP Configurator interface thiab nws cov khoom. Lub HDMI RX IP Configurator muab lub graphical interface los teeb tsa HDMI RX core. Qhov kev teeb tsa no tso cai rau tus neeg siv xaiv qhov tsis xws li Number of Pixels, Number of audio channels, Video Interface, Audio Interface, SCRAMBLER, Color Depth, Color Format, Testbench thiab License. Configurator interface suav nrog dropdown menus thiab cov kev xaiv los kho qhov chaw. Cov kev teeb tsa tseem ceeb tau piav qhia hauv Table 4-1. Daim duab hauv qab no muab cov ncauj lus kom ntxaws view ntawm HDMI RX IP Configurator interface.

Daim duab 2-1. HDMI RX IP Configurator

MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (1)

Lub interface kuj suav nrog OK thiab Ncua tseg cov nyees khawm kom paub meej lossis pov tseg cov kev teeb tsa.

Hardware Implementation (Nug ib lo lus nug)

Cov duab hauv qab no piav qhia txog HDMI RX IP interface nrog transceiver (XCVR).

Daim duab 3-1. HDMI RX Block Diagram

MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (2)

Daim duab 3-2. Tus neeg txais kev nthuav dav Block Diagram

MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (3)

HDMI RX muaj peb stages:

  • The theem aligner aligns cov ntaub ntawv thaum uas tig mus nrog kev hwm rau tswj token ciam teb siv transceiver ntsis plam.
  • TMDS decoder hloov cov ntaub ntawv 10-ntsis encoded rau hauv 8-ntsis video pixel cov ntaub ntawv, 4-ntsis audio pob ntawv cov ntaub ntawv thiab 2-ntsis tswj cov cim.
  • Lub FIFOs tshem tawm cov skew ntawm lub moos ntawm R, G thiab B kab.

Phase Aligner (Nug ib lo lus nug)
10-ntsis parallel cov ntaub ntawv los ntawm XCVR tsis yog ib txwm ua raws li kev hwm rau TMDS encoded lo lus ciam teb. Cov ntaub ntawv sib luag yuav tsum tau hloov me ntsis thiab ua kom zoo nyob rau hauv thiaj li yuav txiav txim siab cov ntaub ntawv. Phase aligner aligns cov ntaub ntawv nkag mus rau qhov sib npaug rau lo lus ciam teb siv qhov me ntsis-slip feature hauv XCVR. XCVR nyob rau hauv Per-Monitor DPI Awareness (PMA) hom tso cai me ntsis-slip feature, qhov uas nws kho qhov kev sib raug zoo ntawm 10-ntsis deserialized lo lus los ntawm 1-ntsis. Txhua zaus, tom qab kho 10-ntsis lo lus los ntawm 1 me ntsis plam txoj hauj lwm, nws yog muab piv nrog ib qho ntawm plaub tswj tokens ntawm HDMI raws tu qauv kom xauv txoj hauj lwm thaum lub sij hawm tswj. Lo lus 10-ntsis yog ua kom raug thiab suav tias siv tau rau s tom ntejtages. Txhua qhov xim channel muaj nws tus kheej theem aligner, TMDS decoder pib txiav txim siab tsuas yog thaum tag nrho cov theem aligners raug kaw los kho cov lus ciam teb.

TMDS Decoder (Nug ib lo lus nug)
TMDS decoder decodes 10-ntsis deserialized los ntawm transceiver rau 8-ntsis pixel cov ntaub ntawv thaum lub sij hawm yees duab. HSYNC, VSYNC thiab PACKET HEADER yog tsim los ntawm lub sijhawm tswj hwm los ntawm 10-ntsis xiav channel cov ntaub ntawv. Cov ntaub ntawv audio pob ntawv tau txiav txim siab rau R thiab G channel txhua qhov muaj plaub ntu. TMDS decoder ntawm txhua channel ua haujlwm ntawm nws tus kheej lub moos. Li no, nws tuaj yeem muaj qee qhov sib txawv ntawm cov channel.

Channel rau Channel De-Skew (Nug ib lo lus nug)
FIFO raws li de-skew logic yog siv los tshem tawm cov skew ntawm cov channel. Txhua lub channel tau txais cov teeb liab siv tau los ntawm cov theem sib dhos kom qhia tau tias cov ntaub ntawv 10-ntsis tuaj los ntawm theem aligner siv tau. Yog tias txhua txoj kev siv tau (tau ua tiav theem kev sib raug zoo), FIFO module pib dhau cov ntaub ntawv los ntawm FIFO module siv nyeem thiab sau cov cim qhia (nruam sau ntawv hauv thiab nyeem tawm). Thaum lub token tswj tau pom nyob rau hauv ib qho ntawm FIFO outputs, qhov kev nyeem tawm khiav yog raug tshem tawm, thiab ib tug marker pom lub teeb liab yog generated los qhia txog lub sij hawm tuaj txog ntawm ib tug marker nyob rau hauv cov kwj video. Qhov kev nyeem tawm ntws rov pib tsuas yog thaum tus cim no tau tuaj txog ntawm tag nrho peb cov channel. Yog li ntawd, qhov cuam tshuam skew raug tshem tawm. Lub moos ob lub FIFOs synchronize tag nrho peb cov ntaub ntawv ntws mus rau lub moos xiav channel kom tshem tawm qhov cuam tshuam. Daim duab hauv qab no piav qhia txog cov channel rau channel de-skew txheej txheem.

Daim duab 3-3. Channel De-Skew

MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (4)

DDC (Nug ib lo lus nug)
DDC yog ib qho kev sib txuas lus raws li I2C tsheb npav specification. Lub hauv paus siv I2C cov lus txib los nyeem cov ntaub ntawv los ntawm lub dab dej E-EDID nrog tus qhev chaw nyob. Lub HDMI RX IP siv EDID ua ntej nrog ntau qhov kev daws teeb meem txhawb kev daws teeb meem txog 1920 ✕ 1080 ntawm 60 Hz hauv Ib Pixel hom thiab mus txog 3840 ✕ 2160 ntawm 60 Hz hauv Plaub Pixel hom.
Lub EDID sawv cev rau lub npe zaub ua Microchip HDMI zaub.

HDMI RX Parameters thiab Interface Signals (Nug ib lo lus nug)

Tshooj lus no tham txog qhov tsis muaj nyob hauv HDMI RX GUI configurator thiab I/O cov cim.

Configuration Parameters (Nug ib lo lus nug)
Cov lus hauv qab no teev cov kev teeb tsa tsis raug hauv HDMI RX IP.

Table 4-1. Configuration Parameters

Lub npe Parameter Kev piav qhia
Xim hom Txhais qhov chaw xim. Txhawb cov hom xim hauv qab no:
  • RGB
  • YCbCr422
  • YCbCr444
Xim Qhov tob Qhia tus naj npawb ntawm cov khoom ib xim. Txhawb 8, 10, 12 thiab 16 khoom ib feem.
Tus lej Pixels Qhia tus naj npawb ntawm pixels ib lub moos input:
  • Pixel ib moos = 1
  • Pixel ib moos = 4
SCRAMBLER Kev them nyiaj yug rau 4K daws teeb meem ntawm 60 ntas ib ob:
  • Thaum 1, kev txhawb nqa Scrambler tau qhib
  • Thaum 0, kev txhawb nqa Scrambler yog neeg xiam
Tus naj npawb ntawm cov channels Txhawb tus naj npawb ntawm cov channels:
  • 2 audio channels
  • 8 audio channels
Txuas Siv Video Native thiab AXI ntws
Suab Interface Native thiab AXI ntws
Test lub rooj zaum Tso cai rau kev xaiv ntawm ib puag ncig lub rooj zaum. Txhawb nqa cov kev xaiv xeem hauv qab no:
  • Cov neeg siv
  • Tsis muaj
Daim ntawv tso cai Qhia txog hom ntawv tso cai. Muab ob daim ntawv tso cai hauv qab no:
  • RTL
  • Encrypted

Ports (Nug ib lo lus nug)
Cov lus hauv qab no teev cov tswv yim thiab cov chaw nres nkoj ntawm HDMI RX IP rau Native interface thaum Xim Hom yog RGB.

Table 4-2. Input thiab Output rau Native Interface

Lub Npe Lub Npe Kev taw qhia Dav (ntsis) Kev piav qhia
RESET_N_I Tswv yim 1 Active-low asynchronous pib dua teeb liab
R_RX_CLK_I Tswv yim 1 Parallel moos rau "R" channel los ntawm XCVR
G_RX_CLK_I Tswv yim 1 Parallel moos rau "G" channel los ntawm XCVR
B_RX_CLK_I Tswv yim 1 Parallel moos rau "B" channel los ntawm XCVR
EDID_RESET_N_I Tswv yim 1 Active-low asynchronous edid pib dua teeb liab
R_RX_VALID_I Tswv yim 1 Cov teeb liab siv tau los ntawm XCVR rau "R" channel cov ntaub ntawv sib luag
G_RX_VALID_I Tswv yim 1 Cov teeb liab siv tau los ntawm XCVR rau "G" channel cov ntaub ntawv sib luag
B_RX_VALID_I Tswv yim 1 Cov teeb liab siv tau los ntawm XCVR rau "B" channel cov ntaub ntawv sib luag
Lub Npe Lub Npe Kev taw qhia Dav (ntsis) Kev piav qhia
DATA_R_I Tswv yim NUMBER OF PIXELS ✕ 10 me ntsis Tau txais "R" channel parallel cov ntaub ntawv los ntawm XCVR
DATA_G_I Tswv yim NUMBER OF PIXELS ✕ 10 me ntsis Tau txais "G" channel parallel cov ntaub ntawv los ntawm XCVR
DATA_B_I Tswv yim NUMBER OF PIXELS ✕ 10 me ntsis Tau txais "B" channel parallel cov ntaub ntawv los ntawm XCVR
SCL_I Tswv yim 1 I2C serial moos input rau DDC
HPD_I Tswv yim 1 Kub plug ntes input teeb liab. Qhov chaw txuas nrog lub dab dej HPD teeb liab yuav tsum siab.
SDA_I Tswv yim 1 Kev lees paub rau lub dav hlau I2C-DDC data
EDID_CLK_I Tswv yim 1 System moos rau I2C module
BIT_SLIP_R_O Tso zis 1 Lub teeb liab me ntsis rau "R" channel ntawm transceiver
BIT_SLIP_G_O Tso zis 1 Lub teeb liab me ntsis rau "G" channel ntawm transceiver
BIT_SLIP_B_O Tso zis 1 Lub teeb liab me ntsis rau "B" channel ntawm transceiver
VIDEO_DATA_VALID_O Tso zis 1 Cov ntaub ntawv yees duab siv tau
AUDIO_DATA_VALID_O Tso zis 1 Cov ntaub ntawv audio siv tau
H_SYNC_O Tso zis 1 Kab rov tav sync mem tes
V_SYNC_O Tso zis 1 Active ntsug sync mem tes
R_O Tso zis NUMBER OF PIXELS ✕ Xim Qhov tob Decoded "R" cov ntaub ntawv
G_O Tso zis NUMBER OF PIXELS ✕ Xim Qhov tob Decoded "G" cov ntaub ntawv
B_O Tso zis NUMBER OF PIXELS ✕ Xim Qhov tob Decoded "B" cov ntaub ntawv
SDA_O Tso zis 1 I2C cov ntaub ntawv tso tawm rau DDC
HPD_O Tso zis 1 Kub plug ntes tso zis teeb liab
ACR_CTS_O Tso zis 20 Lub Sijhawm Clock Regeneration Cycle Timestamp tus nqi
ACR_N_O Tso zis 20 Suab moos Regeneration tus nqi (N) parameter
ACR_VALID_O Tso zis 1 Suab moos Regeneration siv tau teeb liab
AUDIO_SAMPLE_CH1_O Tso zis 24 Channel 1 audio sample data
AUDIO_SAMPLE_CH2_O Tso zis 24 Channel 2 audio sample data
AUDIO_SAMPLE_CH3_O Tso zis 24 Channel 3 audio sample data
AUDIO_SAMPLE_CH4_O Tso zis 24 Channel 4 audio sample data
AUDIO_SAMPLE_CH5_O Tso zis 24 Channel 5 audio sample data
AUDIO_SAMPLE_CH6_O Tso zis 24 Channel 6 audio sample data
AUDIO_SAMPLE_CH7_O Tso zis 24 Channel 7 audio sample data
AUDIO_SAMPLE_CH8_O Tso zis 24 Channel 8 audio sample data
HDMI_DVI_MODE_O Tso zis 1 Cov hauv qab no yog ob hom:
  • 1: HDMI hom
  • 0: DVI hom

Cov lus hauv qab no piav qhia txog cov tswv yim thiab cov chaw nres nkoj ntawm HDMI RX IP rau AXI4 Stream Video Interface.
Table 4-3. Cov tswv yim thiab tso zis ports rau AXI4 Kwj Video Interface

Chaw nres nkoj npe Kev taw qhia Dav (ntsis) Kev piav qhia
TSI_O Tso zis NUMBER OF PIXELS ✕ Xim Qhov tob ✕ 3 khoom Tso zis video ntaub ntawv [R, G, B]
TVALID_O Tso zis 1 Tso zis video siv tau
Chaw nres nkoj npe Kev taw qhia Dav (ntsis) Kev piav qhia
TLAST_O Tso zis 1 Output ncej kawg teeb liab
TUSER_O Tso zis 3
  • bit 0 = VSYNC
  • bit 1 = Hsync
  •  ib 2 = 0
  • ib 3 = 0
TSTRB_O Tso zis 3 Tso zis video ntaub ntawv strobe
TKEEP_O Tso zis 3 Tso zis video ntaub ntawv khaws cia

Cov lus hauv qab no piav qhia txog cov tswv yim thiab cov chaw nres nkoj ntawm HDMI RX IP rau AXI4 Stream Audio Interface.

Table 4-4. Tawm tswv yim thiab tso zis Ports rau AXI4 Kwj Suab Interface

Chaw nres nkoj npe Kev taw qhia Dav (ntsis) Kev piav qhia
AUDIO_TDATA_O Tso zis 24 Tso cov ntaub ntawv audio
AUDIO_TID_O Tso zis 3 Tawm suab channel
AUDIO_TVALID_O Tso zis 1 Tawm suab siv tau teeb liab

Cov lus hauv qab no teev cov tswv yim thiab cov chaw nres nkoj ntawm HDMI RX IP rau Native interface thaum Xim Hom yog YUV444.

Table 4-5. Input thiab Output rau Native Interface

Chaw nres nkoj npe Kev taw qhia Dav (ntsis) Kev piav qhia
RESET_N_I Tswv yim 1 Active-low asynchronous pib dua teeb liab
LANE3_RX_CLK_I Tswv yim 1 Parallel moos rau Kab 3 channel los ntawm XCVR
LANE2_RX_CLK_I Tswv yim 1 Parallel moos rau Kab 2 channel los ntawm XCVR
LANE1_RX_CLK_I Tswv yim 1 Parallel moos rau Kab 1 channel los ntawm XCVR
EDID_RESET_N_I Tswv yim 1 Active-low asynchronous edid pib dua teeb liab
LANE3_RX_VALID_I Tswv yim 1 Cov teeb liab siv tau los ntawm XCVR rau Kab 3 cov ntaub ntawv sib luag
LANE2_RX_VALID_I Tswv yim 1 Cov teeb liab siv tau los ntawm XCVR rau Kab 2 cov ntaub ntawv sib luag
LANE1_RX_VALID_I Tswv yim 1 Cov teeb liab siv tau los ntawm XCVR rau Kab 1 cov ntaub ntawv sib luag
DATA_LANE3_I Tswv yim NUMBER OF PIXELS ✕ 10 me ntsis Tau txais Lane 3 parallel data los ntawm XCVR
DATA_LANE2_I Tswv yim NUMBER OF PIXELS ✕ 10 me ntsis Tau txais Lane 2 parallel data los ntawm XCVR
DATA_LANE1_I Tswv yim NUMBER OF PIXELS ✕ 10 me ntsis Tau txais Lane 1 parallel data los ntawm XCVR
SCL_I Tswv yim 1 I2C serial moos input rau DDC
HPD_I Tswv yim 1 Kub plug ntes input teeb liab. Qhov chaw txuas nrog lub dab dej HPD teeb liab yuav tsum siab.
SDA_I Tswv yim 1 Kev lees paub rau lub dav hlau I2C-DDC data
EDID_CLK_I Tswv yim 1 System moos rau I2C module
BIT_SLIP_LANE3_O Tso zis 1 Lub teeb liab me ntsis rau kab 3 ntawm transceiver
BIT_SLIP_LANE2_O Tso zis 1 Lub teeb liab me ntsis rau kab 2 ntawm transceiver
BIT_SLIP_LANE1_O Tso zis 1 Lub teeb liab me ntsis rau kab 1 ntawm transceiver
VIDEO_DATA_VALID_O Tso zis 1 Cov ntaub ntawv yees duab siv tau
AUDIO_DATA_VALID_O Tso zis 1 Cov ntaub ntawv audio siv tau
H_SYNC_O Tso zis 1 Kab rov tav sync mem tes
V_SYNC_O Tso zis 1 Active ntsug sync mem tes
Chaw nres nkoj npe Kev taw qhia Dav (ntsis) Kev piav qhia
Y_O Tso zis NUMBER OF PIXELS ✕ Xim Qhov tob Decoded "Y" cov ntaub ntawv
Cb_O Tso zis NUMBER OF PIXELS ✕ Xim Qhov tob Decoded "Cb" cov ntaub ntawv
Cr_O Tso zis NUMBER OF PIXELS ✕ Xim Qhov tob Decoded "Cr" cov ntaub ntawv
SDA_O Tso zis 1 I2C cov ntaub ntawv tso tawm rau DDC
HPD_O Tso zis 1 Kub plug ntes tso zis teeb liab
ACR_CTS_O Tso zis 20 Lub Sijhawm Clock Regeneration Cycle timestamp tus nqi
ACR_N_O Tso zis 20 Suab moos Regeneration tus nqi (N) parameter
ACR_VALID_O Tso zis 1 Suab moos Regeneration siv tau teeb liab
AUDIO_SAMPLE_CH1_O Tso zis 24 Channel 1 audio sample data
AUDIO_SAMPLE_CH2_O Tso zis 24 Channel 2 audio sample data
AUDIO_SAMPLE_CH3_O Tso zis 24 Channel 3 audio sample data
AUDIO_SAMPLE_CH4_O Tso zis 24 Channel 4 audio sample data
AUDIO_SAMPLE_CH5_O Tso zis 24 Channel 5 audio sample data
AUDIO_SAMPLE_CH6_O Tso zis 24 Channel 6 audio sample data
AUDIO_SAMPLE_CH7_O Tso zis 24 Channel 7 audio sample data
AUDIO_SAMPLE_CH8_O Tso zis 24 Channel 8 audio sample data

Cov lus hauv qab no teev cov tswv yim thiab cov chaw nres nkoj ntawm HDMI RX IP rau Native interface thaum Xim Hom yog YUV422.

Table 4-6. Input thiab Output rau Native Interface

Chaw nres nkoj npe Kev taw qhia Dav (ntsis) Kev piav qhia
RESET_N_I Tswv yim 1 Active-low asynchronous pib dua teeb liab
LANE3_RX_CLK_I Tswv yim 1 Parallel moos rau Kab 3 channel los ntawm XCVR
LANE2_RX_CLK_I Tswv yim 1 Parallel moos rau Kab 2 channel los ntawm XCVR
LANE1_RX_CLK_I Tswv yim 1 Parallel moos rau Kab 1 channel los ntawm XCVR
EDID_RESET_N_I Tswv yim 1 Active-low asynchronous edid pib dua teeb liab
LANE3_RX_VALID_I Tswv yim 1 Cov teeb liab siv tau los ntawm XCVR rau Kab 3 cov ntaub ntawv sib luag
LANE2_RX_VALID_I Tswv yim 1 Cov teeb liab siv tau los ntawm XCVR rau Kab 2 cov ntaub ntawv sib luag
LANE1_RX_VALID_I Tswv yim 1 Cov teeb liab siv tau los ntawm XCVR rau Kab 1 cov ntaub ntawv sib luag
DATA_LANE3_I Tswv yim NUMBER OF PIXELS ✕ 10 me ntsis Tau txais Lane 3 parallel data los ntawm XCVR
DATA_LANE2_I Tswv yim NUMBER OF PIXELS ✕ 10 me ntsis Tau txais Lane 2 parallel data los ntawm XCVR
DATA_LANE1_I Tswv yim NUMBER OF PIXELS ✕ 10 me ntsis Tau txais Lane 1 parallel data los ntawm XCVR
SCL_I Tswv yim 1 I2C serial moos input rau DDC
HPD_I Tswv yim 1 Kub plug ntes input teeb liab. Qhov chaw txuas nrog lub dab dej HPD teeb liab yuav tsum siab.
SDA_I Tswv yim 1 Kev lees paub rau lub dav hlau I2C-DDC data
EDID_CLK_I Tswv yim 1 System moos rau I2C module
BIT_SLIP_LANE3_O Tso zis 1 Lub teeb liab me ntsis rau kab 3 ntawm transceiver
BIT_SLIP_LANE2_O Tso zis 1 Lub teeb liab me ntsis rau kab 2 ntawm transceiver
BIT_SLIP_LANE1_O Tso zis 1 Lub teeb liab me ntsis rau kab 1 ntawm transceiver
VIDEO_DATA_VALID_O Tso zis 1 Cov ntaub ntawv yees duab siv tau
Chaw nres nkoj npe Kev taw qhia Dav (ntsis) Kev piav qhia
AUDIO_DATA_VALID_O Tso zis 1 Cov ntaub ntawv audio siv tau
H_SYNC_O Tso zis 1 Kab rov tav sync mem tes
V_SYNC_O Tso zis 1 Active ntsug sync mem tes
Y_O Tso zis NUMBER OF PIXELS ✕ Xim Qhov tob Decoded "Y" cov ntaub ntawv
C_O Tso zis NUMBER OF PIXELS ✕ Xim Qhov tob Decoded "C" cov ntaub ntawv
SDA_O Tso zis 1 I2C cov ntaub ntawv tso tawm rau DDC
HPD_O Tso zis 1 Kub plug ntes tso zis teeb liab
ACR_CTS_O Tso zis 20 Lub Sijhawm Clock Regeneration Cycle timestamp tus nqi
ACR_N_O Tso zis 20 Suab moos Regeneration tus nqi (N) parameter
ACR_VALID_O Tso zis 1 Suab moos Regeneration siv tau teeb liab
AUDIO_SAMPLE_CH1_O Tso zis 24 Channel 1 audio sample data
AUDIO_SAMPLE_CH2_O Tso zis 24 Channel 2 audio sample data
AUDIO_SAMPLE_CH3_O Tso zis 24 Channel 3 audio sample data
AUDIO_SAMPLE_CH4_O Tso zis 24 Channel 4 audio sample data
AUDIO_SAMPLE_CH5_O Tso zis 24 Channel 5 audio sample data
AUDIO_SAMPLE_CH6_O Tso zis 24 Channel 6 audio sample data
AUDIO_SAMPLE_CH7_O Tso zis 24 Channel 7 audio sample data
AUDIO_SAMPLE_CH8_O Tso zis 24 Channel 8 audio sample data

Cov lus hauv qab no teev cov tswv yim thiab cov chaw nres nkoj ntawm HDMI RX IP rau Native interface thaum SCRAMBLER Enabled.

Table 4-7. Input thiab Output rau Native Interface

Chaw nres nkoj npe Kev taw qhia Dav (ntsis) Kev piav qhia
RESET_N_I Tswv yim 1 Active-low asynchronous pib dua teeb liab
R_RX_CLK_I Tswv yim 1 Parallel moos rau "R" channel los ntawm XCVR
G_RX_CLK_I Tswv yim 1 Parallel moos rau "G" channel los ntawm XCVR
B_RX_CLK_I Tswv yim 1 Parallel moos rau "B" channel los ntawm XCVR
EDID_RESET_N_I Tswv yim 1 Active-low asynchronous edid pib dua teeb liab
HDMI_CABLE_CLK_I Tswv yim 1 Cable moos los ntawm HDMI qhov chaw
R_RX_VALID_I Tswv yim 1 Cov teeb liab siv tau los ntawm XCVR rau "R" channel cov ntaub ntawv sib luag
G_RX_VALID_I Tswv yim 1 Cov teeb liab siv tau los ntawm XCVR rau "G" channel cov ntaub ntawv sib luag
B_RX_VALID_I Tswv yim 1 Cov teeb liab siv tau los ntawm XCVR rau "B" channel cov ntaub ntawv sib luag
DATA_R_I Tswv yim NUMBER OF PIXELS ✕ 10 me ntsis Tau txais "R" channel parallel cov ntaub ntawv los ntawm XCVR
DATA_G_I Tswv yim NUMBER OF PIXELS ✕ 10 me ntsis Tau txais "G" channel parallel cov ntaub ntawv los ntawm XCVR
DATA_B_I Tswv yim NUMBER OF PIXELS ✕ 10 me ntsis Tau txais "B" channel parallel cov ntaub ntawv los ntawm XCVR
SCL_I Tswv yim 1 I2C serial moos input rau DDC
HPD_I Tswv yim 1 Kub plug ntes input teeb liab. Lub hauv paus yog txuas nrog lub dab dej, thiab HPD teeb liab yuav tsum siab.
SDA_I Tswv yim 1 Kev lees paub rau lub dav hlau I2C-DDC data
EDID_CLK_I Tswv yim 1 System moos rau I2C module
BIT_SLIP_R_O Tso zis 1 Lub teeb liab me ntsis rau "R" channel ntawm transceiver
BIT_SLIP_G_O Tso zis 1 Lub teeb liab me ntsis rau "G" channel ntawm transceiver
Chaw nres nkoj npe Kev taw qhia Dav (ntsis) Kev piav qhia
BIT_SLIP_B_O Tso zis 1 Lub teeb liab me ntsis rau "B" channel ntawm transceiver
VIDEO_DATA_VALID_O Tso zis 1 Cov ntaub ntawv yees duab siv tau
AUDIO_DATA_VALID_O Cov zis 1 1 Cov ntaub ntawv audio siv tau
H_SYNC_O Tso zis 1 Kab rov tav sync mem tes
V_SYNC_O Tso zis 1 Active ntsug sync mem tes
DATA_RATE_O Tso zis 16 Rx data tus nqi. Cov hauv qab no yog cov ntaub ntawv tus nqi ntsuas:
  • x1734 = 5940 Mbps
  • x0B9A = 2960 Mbps
  •  x05CD = 1485 Mbps
  • x2E6 = 742.5 Mbps
R_O Tso zis NUMBER OF PIXELS ✕ Xim Qhov tob Decoded "R" cov ntaub ntawv
G_O Tso zis NUMBER OF PIXELS ✕ Xim Qhov tob Decoded "G" cov ntaub ntawv
B_O Tso zis NUMBER OF PIXELS ✕ Xim Qhov tob Decoded "B" cov ntaub ntawv
SDA_O Tso zis 1 I2C cov ntaub ntawv tso tawm rau DDC
HPD_O Tso zis 1 Kub plug ntes tso zis teeb liab
ACR_CTS_O Tso zis 20 Lub Sijhawm Clock Regeneration Cycle timestamp tus nqi
ACR_N_O Tso zis 20 Suab moos Regeneration tus nqi (N) parameter
ACR_VALID_O Tso zis 1 Suab moos Regeneration siv tau teeb liab
AUDIO_SAMPLE_CH1_O Tso zis 24 Channel 1 audio sample data
AUDIO_SAMPLE_CH2_O Tso zis 24 Channel 2 audio sample data
AUDIO_SAMPLE_CH3_O Tso zis 24 Channel 3 audio sample data
AUDIO_SAMPLE_CH4_O Tso zis 24 Channel 4 audio sample data
AUDIO_SAMPLE_CH5_O Tso zis 24 Channel 5 audio sample data
AUDIO_SAMPLE_CH6_O Tso zis 24 Channel 6 audio sample data
AUDIO_SAMPLE_CH7_O Tso zis 24 Channel 7 audio sample data
AUDIO_SAMPLE_CH8_O Tso zis 24 Channel 8 audio sample data

Testbench Simulation (Nug ib lo lus nug)

Testbench yog muab los xyuas qhov ua haujlwm ntawm HDMI RX core. Testbench ua haujlwm tsuas yog hauv Native Interface thaum tus naj npawb ntawm pixels yog ib qho.

Txhawm rau simulate cov tub ntxhais siv lub testbench, ua cov kauj ruam hauv qab no:

  1. Nyob rau hauv lub qhov rais tsim Flow, nthuav Tsim Tsim.
  2. Txoj cai-nias Tsim SmartDesign Testbench, thiab tom qab ntawd nyem Khiav, raws li pom hauv daim duab hauv qab no.
    Daim duab 5-1. Tsim SmartDesign TestbenchMICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (5)
  3. Sau lub npe rau SmartDesign testbench, thiab tom qab ntawd nyem OK.
    Daim duab 5-2. Sau npe SmartDesign TestbenchMICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (6)SmartDesign testbench yog tsim, thiab ib lub canvas tshwm rau sab xis ntawm Design Flow pane.
  4. Mus rau Libero® SoC Catalog, xaiv View > Windows > IP Catalog, thiab tom qab ntawd nthuav cov Solutions-Video. Ob-nias HDMI RX IP (v5.4.0) thiab tom qab ntawd nyem OK.
  5. Xaiv tag nrho cov chaw nres nkoj, right-click thiab xaiv Txhawb nqa mus rau qib siab.
  6. Ntawm SmartDesign tool bar, nyem Tsim Cov Khoom Siv.
  7. Ntawm Stimulus Hierarchy tab, right-click HDMI_RX_TB testbench file, thiab tom qab ntawd nyem Simulate Pre-Synth Tsim> Qhib Kev Sib Tham.

Cov cuab yeej ModelSim® qhib nrog lub testbench, raws li qhia hauv daim duab hauv qab no.

Daim duab 5-3. ModelSim Tool nrog HDMI RX Testbench File

MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (7)

Qhov tseem ceeb: If qhov kev simulation raug cuam tshuam vim lub sijhawm ua haujlwm tau teev tseg hauv DO file, siv lub run -all hais kom ua kom tiav qhov simulation.

Daim ntawv tso cai (Nug ib lo lus nug)

HDMI RX IP yog muab nrog ob daim ntawv tso cai hauv qab no:

  • Encrypted: Ua kom tiav encrypted RTL code yog muab rau cov tub ntxhais. Nws muaj pub dawb nrog ib qho ntawm Libero daim ntawv tso cai, ua kom cov tub ntxhais ua kom nrawm nrog SmartDesign. Koj tuaj yeem ua Simulation, Synthesis, Layout, thiab program FPGA silicon siv Libero tsim suite.
  • RTL: Ua tiav RTL qhov chaws yog daim ntawv tso cai kaw, uas yuav tsum tau yuav nyias.

Simulation Results (Nug ib lo lus nug)

Daim duab lub sijhawm nram qab no rau HDMI RX IP qhia cov ntaub ntawv video thiab tswj cov ntaub ntawv lub sijhawm.

Daim duab 6-1. Cov ntaub ntawv yees duab

MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (8)

Cov duab hauv qab no qhia tau hais tias hsync thiab vsync outputs rau kev tswj cov ntaub ntawv nkag.

Daim duab 6-2. Kab rov tav Sync thiab ntsug Sync teeb liab

MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (9)

Daim duab hauv qab no qhia txog EDID ib feem.

Daim duab 6-3. EDID Signals

MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (10)

Kev siv peev txheej (nug ib lo lus nug)

HDMI RX IP yog siv rau hauv PolarFire® FPGA (MPF300T - 1FCG1152I Pob). Cov lus hauv qab no teev cov peev txheej siv thaum Number of Pixels = 1 pixel.

Table 7-1. Kev siv peev txheej rau 1 Pixel Hom

Xim hom Xim Qhov tob SCRAMBLER Fabric 4 LUT Fabric DFF Interface 4 LUT Interface DFF URAM (64 × 12) LSRAM (20k)
RGB 8 Disable 987 1867 360 360 0 10
10 Disable 1585 1325 456 456 11 9
12 Disable 1544 1323 456 456 11 9
16 Disable 1599 1331 492 492 14 9
YCbCr422 8 Disable 1136 758 360 360 3 9
YCbCr444 8 Disable 1105 782 360 360 3 9
10 Disable 1574 1321 456 456 11 9
12 Disable 1517 1319 456 456 11 9
16 Disable 1585 1327 492 492 14 9

Cov lus hauv qab no teev cov peev txheej siv thaum Number of Pixels = 4 pixel.

Table 7-2. Kev siv peev txheej rau 4 Pixel Hom

Xim hom Xim Qhov tob SCRAMBLER Fabric 4 LUT Fabric DFF Interface 4 LUT Interface DFF URAM (64 × 12) LSRAM (20k)
RGB 8 Disable 1559 1631 1080 1080 9 27
12 Disable 1975 2191 1344 1344 31 27
16 Disable 1880 2462 1428 1428 38 27
RGB 10 Pab 4231 3306 1008 1008 3 27
12 Pab 4253 3302 1008 1008 3 27
16 Pab 3764 3374 1416 1416 37 27
YCbCr422 8 Disable 1485 1433 912 912 7 23
YCbCr444 8 Disable 1513 1694 1080 1080 9 27
12 Disable 2001 2099 1344 1344 31 27
16 Disable 1988 2555 1437 1437 38 27

Cov lus hauv qab no teev cov peev txheej tau siv thaum Number of Pixels = 4 pixel thiab SCRAMBLER tau qhib.

Table 7-3. Kev siv peev txheej rau 4 Pixel Hom thiab SCRAMBLER tau qhib

Xim hom Xim Qhov tob SCRAMBLER Fabric 4 LUT Fabric DFF Interface 4 LUT Interface DFF URAM (64 × 12) LSRAM (20k)
RGB 8 Pab 5029 5243 1126 1126 9 28
YCbCr422 8 Pab 4566 3625 1128 1128 13 27
YCbCr444 8 Pab 4762 3844 1176 1176 17 27

System Integration (Nug ib lo lus nug)

Tshooj lus no qhia yuav ua li cas koom ua ke IP rau hauv Libero tsim.
Cov lus hauv qab no teev cov kev teeb tsa ntawm PF XCVR, PF TX PLL thiab PF CCC xav tau rau cov kev daws teeb meem sib txawv thiab qhov dav me ntsis.

Table 8-1. PF XCVR, PF TX PLL and PF CCC Configurations

Kev daws teeb meem Qhov dav me ntsis PF XCVR Configuration CDR REF CLOCK PADS PF CCC Configuration
RX Cov ntaub ntawv tus nqi RX CDR Ref Clock Frequency RX PCS Fabric Dav Input zaus Tso zis zaus
1 PXL (1080p60) 8 1485 148.5 10 AW 27, AE 28 NA NA
1 PXL (1080p30) 10 1485 148.5 10 AW 27, AE 28 92.5 74
12 1485 148.5 10 AW 27, AE 28 74.25 111.375
16 1485 148.5 10 AW 27, AE 28 74.25 148.5
4 PXL (1080p60) 8 1485 148.5 40 AW 27, AE 28 NA NA
12 1485 148.5 40 AW 27, AE 28 55.725 37.15
16 1485 148.5 40 AW 27, AE 28 74.25 37.125
4 PXL (4kp30) 8 1485 148.5 40 AW 27, AE 28 NA NA
10 3712.5 148.5 40 AW 29, AE 30 92.81 74.248
12 4455 148.5 40 AW 29, AE 30 111.375 74.25
16 5940 148.5 40 AW 29, AE 30 148.5 74.25
4 PXL (4Kp60) 8 5940 148.5 40 AW 29, AE 30 NA NA

HDMI RX Sampli Design 1: Thaum teeb tsa hauv Xim Qhov tob = 8-ntsis thiab Tus lej ntawm Pixels = 1 Pixel hom, yog qhia hauv daim duab hauv qab no.

Daim duab 8-1. HDMI RX Sample Design 1

MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (11)

Rau example, nyob rau hauv 8-ntsis configurations, cov nram qab no Cheebtsam yog ib feem ntawm tus tsim:

  • PF_XCVR_ERM (PF_XCVR_ERM_C0_0) yog configured rau TX thiab RX puv duplex hom. RX cov ntaub ntawv tus nqi ntawm 1485 Mbps hauv PMA hom, nrog cov ntaub ntawv dav teeb tsa raws li 10 ntsis rau 1 PXL hom thiab 148.5 MHz CDR siv moos. TX cov ntaub ntawv tus nqi ntawm 1485 Mbps nyob rau hauv PMA hom, nrog rau cov ntaub ntawv dav configured li 10 ntsis nrog moos division factor 4.
  • LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK thiab LANE3_CDR_REF_CLK yog tsav los ntawm PF_XCVR_REF_CLK nrog AE27, AE28 Pad pins.
  • EDID CLK_I tus pin yuav tsum tau tsav nrog 150 MHz moos nrog CCC.
  • R_RX_CLK_I, G_RX_CLK_I thiab B_RX_CLK_I yog tsav los ntawm LANE3_TX_CLK_R, LANE2_TX_CLK_R thiab LANE1_TX_CLK_R, feem.
  • R_RX_VALID_I, G_RX_VALID_I thiab B_RX_VALID_I yog tsav los ntawm LANE3_RX_VAL, LANE2_RX_VAL thiab LANE1_RX_VAL, feem.
  • DATA_R_I, DATA_G_I thiab DATA_B_I yog tsav los ntawm LANE3_RX_DATA, LANE2_RX_DATA thiab LANE1_RX_DATA, feem.

HDMI RX Sampli Design 2: Thaum teeb tsa hauv Xim Qhov tob = 8-ntsis thiab Tus lej ntawm Pixels = 4 Pixel hom, yog qhia hauv daim duab hauv qab no.

Daim duab 8-2. HDMI RX Sample Design 2

MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (12)

Rau example, nyob rau hauv 8-ntsis configurations, cov nram qab no Cheebtsam yog ib feem ntawm tus tsim:

  • PF_XCVR_ERM (PF_XCVR_ERM_C0_0) yog configured rau TX thiab RX puv duplex hom. RX cov ntaub ntawv tus nqi ntawm 1485 Mbps hauv PMA hom, nrog cov ntaub ntawv dav teeb tsa raws li 40 ntsis rau 4 PXL hom thiab 148.5 MHz CDR siv moos. TX cov ntaub ntawv tus nqi ntawm 1485 Mbps nyob rau hauv PMA hom, nrog rau cov ntaub ntawv dav configured li 40 ntsis nrog moos division factor 4.
  • LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK thiab LANE3_CDR_REF_CLK yog tsav los ntawm PF_XCVR_REF_CLK nrog AE27, AE28 Pad pins.
  • EDID CLK_I tus pin yuav tsum tau tsav nrog 150 MHz moos nrog CCC.
  • R_RX_CLK_I, G_RX_CLK_I thiab B_RX_CLK_I yog tsav los ntawm LANE3_TX_CLK_R, LANE2_TX_CLK_R thiab LANE1_TX_CLK_R, feem.
  • R_RX_VALID_I, G_RX_VALID_I thiab B_RX_VALID_I yog tsav los ntawm LANE3_RX_VAL, LANE2_RX_VAL thiab LANE1_RX_VAL, feem.
  • DATA_R_I, DATA_G_I thiab DATA_B_I yog tsav los ntawm LANE3_RX_DATA, LANE2_RX_DATA thiab LANE1_RX_DATA, feem.

HDMI RX Sampli Design 3: Thaum teeb tsa hauv Xim Qhov tob = 8-ntsis thiab Tus lej ntawm Pixels = 4 Pixel hom thiab SCRAMBLER = Enabled, yog qhia hauv daim duab hauv qab no.

Daim duab 8-3. HDMI RX Sample Design 3

MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (13)

Rau example, nyob rau hauv 8-ntsis configurations, cov nram qab no Cheebtsam yog ib feem ntawm tus tsim:

  • PF_XCVR_ERM (PF_XCVR_ERM_C0_0) yog configured rau TX thiab RX Independent hom. RX cov ntaub ntawv tus nqi ntawm 5940 Mbps nyob rau hauv PMA hom, nrog rau cov ntaub ntawv dav configured li 40 ntsis rau 4 PXL hom thiab 148.5 MHz CDR siv moos. TX cov ntaub ntawv tus nqi ntawm 5940 Mbps nyob rau hauv PMA hom, nrog rau cov ntaub ntawv dav configured li 40 ntsis nrog moos division factor 4.
  • LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK thiab LANE3_CDR_REF_CLK yog tsav los ntawm PF_XCVR_REF_CLK nrog AF29, AF30 Pad pins.
  • EDID CLK_I tus pin yuav tsum tsav nrog 150 MHz moos nrog CCC.
  • R_RX_CLK_I, G_RX_CLK_I thiab B_RX_CLK_I yog tsav los ntawm LANE3_TX_CLK_R, LANE2_TX_CLK_R thiab LANE1_TX_CLK_R, feem.
  • R_RX_VALID_I, G_RX_VALID_I thiab B_RX_VALID_I yog tsav los ntawm LANE3_RX_VAL, LANE2_RX_VAL thiab LANE1_RX_VAL, feem.
  • DATA_R_I, DATA_G_I thiab DATA_B_I yog tsav los ntawm LANE3_RX_DATA, LANE2_RX_DATA thiab LANE1_RX_DATA, feem.

HDMI RX Sampli Design 4: Thaum teeb tsa hauv Xim Qhov tob = 12-ntsis thiab Tus lej ntawm Pixels = 4 Pixel hom thiab SCRAMBLER = Enabled, yog qhia hauv daim duab hauv qab no.

Daim duab 8-4. HDMI RX Sample Design 4

MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (14)

Rau example, nyob rau hauv 12-ntsis configurations, cov nram qab no Cheebtsam yog ib feem ntawm tus tsim:

  • PF_XCVR_ERM (PF_XCVR_ERM_C0_0) yog configured rau RX nkaus xwb hom. RX cov ntaub ntawv tus nqi ntawm 4455 Mbps nyob rau hauv PMA hom, nrog rau cov ntaub ntawv dav configured li 40 ntsis rau 4 PXL hom thiab 148.5 MHz CDR siv moos.
  • LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK thiab LANE3_CDR_REF_CLK yog tsav los ntawm PF_XCVR_REF_CLK nrog AF29, AF30 Pad pins.
  • EDID CLK_I tus pin yuav tsum tsav nrog 150 MHz moos nrog CCC.
  • R_RX_CLK_I, G_RX_CLK_I thiab B_RX_CLK_I yog tsav los ntawm LANE3_TX_CLK_R, LANE2_TX_CLK_R thiab LANE1_TX_CLK_R, feem.
  • R_RX_VALID_I, G_RX_VALID_I thiab B_RX_VALID_I yog tsav los ntawm LANE3_RX_VAL, LANE2_RX_VAL thiab LANE1_RX_VAL, feem.
  • DATA_R_I, DATA_G_I thiab DATA_B_I yog tsav los ntawm LANE3_RX_DATA, LANE2_RX_DATA thiab LANE1_RX_DATA, feem.
  • Lub PF_CCC_C0 module tsim lub moos hu ua OUT0_FABCLK_0 nrog zaus ntawm 74.25 MHz, muab los ntawm lub moos input ntawm 111.375 MHz, uas yog tsav los ntawm LANE1_RX_CLK_R.

HDMI RX Sampli Design 5: Thaum teeb tsa hauv Xim Qhov tob = 8-ntsis, Tus lej ntawm Pixels = 4 Pixel hom thiab SCRAMBLER = Enabled yog qhia hauv daim duab hauv qab no. Cov qauv no yog dynamic cov ntaub ntawv tus nqi nrog DRI.

Daim duab 8-5. HDMI RX Sample Design 5

MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (15)

Rau example, nyob rau hauv 8-ntsis configurations, cov nram qab no Cheebtsam yog ib feem ntawm tus tsim:

  • PF_XCVR_ERM (PF_XCVR_ERM_C0_0) yog configured rau RX nkaus xwb hom nrog enabled dynamic reconfiguration interface. RX cov ntaub ntawv tus nqi ntawm 5940 Mbps nyob rau hauv PMA hom, nrog rau cov ntaub ntawv dav configured li 40 ntsis rau 4 PXL hom thiab 148.5 MHz CDR siv moos.
  • LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK thiab LANE3_CDR_REF_CLK yog tsav los ntawm PF_XCVR_REF_CLK nrog AF29, AF30 Pad pins.
  • EDID CLK_I tus pin yuav tsum tsav nrog 150 MHz moos nrog CCC.
  • R_RX_CLK_I, G_RX_CLK_I thiab B_RX_CLK_I yog tsav los ntawm LANE3_TX_CLK_R, LANE2_TX_CLK_R thiab LANE1_TX_CLK_R, feem.
  • R_RX_VALID_I, G_RX_VALID_I thiab B_RX_VALID_I yog tsav los ntawm LANE3_RX_VAL, LANE2_RX_VAL thiab LANE1_RX_VAL, feem.
  • DATA_R_I, DATA_G_I thiab DATA_B_I yog tsav los ntawm LANE3_RX_DATA, LANE2_RX_DATA thiab LANE1_RX_DATA, feem.

Revision History (Nug ib lo lus nug)

Cov ntaub ntawv kho dua tshiab piav qhia txog cov kev hloov pauv uas tau ua hauv daim ntawv. Cov kev hloov pauv tau teev tseg los ntawm kev kho dua tshiab, pib nrog kev tshaj tawm tam sim no.

Table 9-1. Kev kho keeb kwm

Kev kho dua Hnub tim Kev piav qhia
D 02/2025 Cov hauv qab no yog cov npe ntawm cov kev hloov pauv tau hloov kho C ntawm cov ntaub ntawv:
  • Hloov kho HDMI RX IP version rau 5.4.
  • Hloov Kho Kev Taw Qhia nrog cov yam ntxwv thiab cov yam ntxwv tsis txhawb nqa.
  • Added Tested Source Devices section.
  • Hloov kho daim duab 3-1 thiab daim duab 3-3 nyob rau hauv tshooj Hardware Implementation.
  • Ntxiv Configuration Parameters seem.
  • Hloov tshiab Table 4-2, Table 4-4, Table 4-5, Table 4-6 thiab Table 4-7 nyob rau hauv lub ports section.
  • Hloov kho Daim duab 5-2 hauv seem Testbench Simulation.
  • Hloov kho Table 7-1 thiab Table 7-2 ntxiv Table 7-3 nyob rau hauv seem Kev Siv Khoom Siv.
  • Hloov kho daim duab 8-1, Daim duab 8-2, Daim duab 8-3 thiab daim duab 8-4 nyob rau hauv seem System Integration.
  • Ntxiv dynamic cov ntaub ntawv tus nqi nrog DRI tsim exampnyob rau hauv qhov System Integrationn ntu.
C 02/2023 Cov hauv qab no yog cov npe ntawm cov kev hloov pauv tau hloov kho C ntawm cov ntaub ntawv:
  • Hloov kho HDMI RX IP version rau 5.2
  • Hloov kho qhov kev daws teeb meem txhawb nqa hauv plaub pixel hom thoob plaws hauv daim ntawv
  • Hloov kho daim duab 2-1
B 09/2022 Cov hauv qab no yog cov npe ntawm cov kev hloov pauv hloov kho B ntawm cov ntaub ntawv:
  • Hloov kho cov ntaub ntawv rau v5.1
  • Hloov tshiab Table 4-2 thiab Table 4-3
A 04/2022 Cov hauv qab no yog cov npe ntawm cov kev hloov pauv hloov kho A ntawm cov ntaub ntawv:
  • Cov ntaub ntawv tau tsiv mus rau Microchip template
  • Cov ntaub ntawv xov tooj tau hloov kho rau DS50003298A los ntawm 50200863
  • Hloov kho ntu TMDS Decoder
  • Hloov tshiab Table 4-2 thiab Table 4-3
  •  Hloov kho Daim duab 5-3, Daim duab 6-1, Daim duab 6-2
2.0 — Cov hauv qab no yog cov ntsiab lus ntawm cov kev hloov pauv hauv qhov kev hloov kho no.
  • Ntxiv Table 4-3
  • Hloov tshiab cov ntaub ntawv siv cov ntaub ntawv
1.0 08/2021 Kev kho tshiab.

Microchip FPGA Kev them nyiaj yug
Microchip FPGA cov khoom lag luam pab pawg txhawb nqa nws cov khoom nrog ntau yam kev pabcuam, suav nrog Kev Pabcuam Cov Neeg Siv Khoom, Lub Chaw Pabcuam Cov Neeg Siv Khoom, a website, thiab chaw muag khoom thoob ntiaj teb. Cov neeg siv khoom tau hais kom mus ntsib Microchip online cov peev txheej ua ntej hu rau kev txhawb nqa vim nws muaj feem ntau tias lawv cov lus nug tau teb lawm. Hu rau Technical Support Center los ntawm website ntawm www.microchip.com/support. Hais txog FPGA Ntaus Tus lej, xaiv cov ntaub ntawv tsim nyog, thiab xa cov qauv tsim files thaum tsim rooj plaub kev txhawb nqa. Hu rau Lub Chaw Pabcuam Cov Neeg Siv Khoom rau kev txhawb nqa cov khoom lag luam uas tsis yog khoom siv, xws li cov nqi khoom, kev hloov khoom dua tshiab, cov ntaub ntawv hloov tshiab, kev txiav txim raws li txoj cai, thiab kev tso cai.

  • Los ntawm North America, hu rau 800.262.1060
  • Los ntawm lwm lub ntiaj teb, hu rau 650.318.4460
  • Fax, los ntawm txhua qhov chaw hauv ntiaj teb, 650.318.8044

Cov ntaub ntawv Microchip

Cov cim lag luam
Lub npe "Microchip" thiab lub logo, "M" logo, thiab lwm lub npe, lub logo, thiab cov npe tau sau npe thiab tsis tau sau npe ua lag luam ntawm Microchip Technology Incorporated lossis nws cov koom tes thiab / lossis cov koom tes hauv Tebchaws Meskas thiab / lossis lwm lub tebchaws ("Microchip Cov cim lag luam”). Cov ntaub ntawv hais txog Microchip Trademarks tuaj yeem nrhiav tau ntawm https://www.microchip.com/en-us/about/legal-information/microchip-trademarks.

ISBN: 979-8-3371-0744-8

Daim Ntawv Ceeb Toom
Cov ntawv tshaj tawm no thiab cov ntaub ntawv ntawm no tsuas yog siv nrog cov khoom siv Microchip, suav nrog rau kev tsim, sim, thiab sib xyaw cov khoom siv Microchip nrog koj daim ntawv thov. Kev siv cov ntaub ntawv no ua txhaum txoj cai no. Cov ntaub ntawv hais txog cov ntawv thov ntaus ntawv tsuas yog muab rau koj yooj yim thiab tuaj yeem hloov pauv los ntawm kev hloov tshiab. Nws yog koj lub luag haujlwm los xyuas kom meej tias koj daim ntawv thov ua tau raws li koj cov lus qhia tshwj xeeb. Hu rau koj lub chaw muag khoom Microchip hauv zos rau kev txhawb nqa ntxiv lossis, tau txais kev txhawb nqa ntxiv ntawm www.microchip.com/en-us/support/design-help/client-support-services.

Cov ntaub ntawv no yog muab los ntawm microchip "raws li yog". MICROCHIP tsis muaj kev sawv cev lossis kev lav phib xaub ntawm txhua yam txawm hais tias nthuav tawm lossis txhais, sau lossis hais lus, kev cai lij choj lossis lwm yam, cuam tshuam rau cov ntaub ntawv suav nrog tab sis tsis txwv rau WARNING TSIS TXAUS SIAB, Kev muag khoom, thiab kev nyab xeeb rau lub hom phiaj tshwj xeeb, lossis kev lav phib xaub cuam tshuam txog nws qhov xwm txheej, zoo, lossis kev ua tau zoo.
TSIS MUAJ IB TUG MICROCHIP yuav raug lav rau txhua qhov kev cuam tshuam, tshwj xeeb, raug nplua, xwm txheej, lossis cuam tshuam rau kev poob, kev puas tsuaj, nqi, lossis kev siv nyiaj ntawm txhua yam kev cuam tshuam rau kev hloov pauv, lossis kev siv nyiaj txiag, MICROCHIP tau qhia txog qhov ua tau lossis qhov kev puas tsuaj yog FORESEEABLE. YUAV TSUM TAU TXAIS NTAWM LEEJ TWG, MICROCHIP TAG NRHO LUB SIJ HAWM NTAWM TXOJ CAI NTAWM TXOJ HAUJ LWM HAUV QHOV CHAW UA HAUJ LWM HAUJ LWM HAUJ LWM HAUJ LWM los yog nws siv yuav tsis pub tshaj tus nqi ntawm cov nqi, yog tias muaj, yog tias koj tau txais cov nyiaj tau los Xov xwm.
Kev siv cov khoom siv Microchip hauv kev txhawb nqa lub neej thiab / lossis daim ntawv thov kev nyab xeeb yog tag nrho ntawm tus neeg yuav khoom qhov kev pheej hmoo, thiab tus neeg yuav khoom pom zoo tiv thaiv, them nyiaj thiab tuav Microchip tsis raug mob los ntawm ib qho thiab tag nrho cov kev puas tsuaj, kev thov, foob, lossis cov nuj nqis uas tshwm sim los ntawm kev siv. Tsis muaj ntawv tso cai raug xa tawm, tsis hais los yog lwm yam, raws li cov cai ntawm Microchip cov cuab yeej cuab tam tshwj tsis yog hais tias lwm yam.

Microchip Devices Code Protection Feature

Nco ntsoov cov ntsiab lus hauv qab no ntawm cov cai tiv thaiv ntawm cov khoom siv Microchip:

  • Cov khoom siv microchip ua tau raws li cov lus qhia tshwj xeeb uas muaj nyob rau hauv lawv cov ntaub ntawv Microchip tshwj xeeb.
  • Microchip ntseeg hais tias nws tsev neeg ntawm cov khoom muaj kev ruaj ntseg thaum siv raws li lub hom phiaj, nyob rau hauv kev khiav hauj lwm specifications, thiab nyob rau hauv ib txwm tej yam kev mob.
  • Microchip muaj nuj nqis thiab tiv thaiv nws txoj cai kev txawj ntse. Kev sim ua txhaum cai tiv thaiv cov yam ntxwv ntawm Microchip cov khoom raug txwv nruj heev thiab tej zaum yuav ua txhaum txoj cai Digital Millennium Copyright Act.
  • Tsis yog Microchip lossis lwm lub chaw tsim khoom semiconductor tuaj yeem lav qhov kev ruaj ntseg ntawm nws cov cai. Kev tiv thaiv Code tsis txhais hais tias peb tau lees tias cov khoom yog "tsis tawg". Kev tiv thaiv code yog hloov zuj zus mus tas li. Microchip tau cog lus tias yuav txhim kho cov cai tiv thaiv cov yam ntxwv ntawm peb cov khoom tsis tu ncua.

© 2025 Microchip Technology Inc. thiab nws cov koom haum

FAQ

  • Q: Kuv yuav hloov kho HDMI RX IP core li cas?
    A: Cov tub ntxhais IP tuaj yeem hloov kho los ntawm Libero SoC software lossis rub tawm los ntawm phau ntawv teev npe. Ib zaug ntsia hauv Libero SoC software IP Catalog, nws tuaj yeem teeb tsa, tsim tawm, thiab ua kom sai sai hauv SmartDesign rau kev suav nrog hauv qhov project.

Cov ntaub ntawv / Cov ntaub ntawv

MICROCHIP PolarFire FPGA Siab txhais Multimedia Interface HDMI Receiver [ua pdf] Cov neeg siv phau ntawv qhia
PolarFire FPGA, PolarFire FPGA High Definition Multimedia Interface HDMI Receiver, Siab txhais Multimedia Interface HDMI Receiver, Multimedia Interface HDMI Receiver, Interface HDMI Receiver, HDMI Receiver

Cov ntaub ntawv

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