MICROCHIP PolarFire FPGA High Definition Multimedia Interface HDMI Isamkeli
Intshayelelo (Buza umbuzo)
I-Microchip's High-Definition Multimedia Interface (HDMI) i-IP receiver IP ixhasa idatha yevidiyo kunye nolwamkelo lwedatha yepakethi ye-audio echazwe kwi-HDMI inkcazo esemgangathweni. I-HDMI i-RX IP yenzelwe ngokukodwa i-PolarFire® FPGA kunye ne-PolarFire System kwi-Chip (SoC) izixhobo ze-FPGA ezixhasa i-HDMI 2.0 yezigqibo ukuya kwi-1920 × 1080 kwi-60 Hz kwimodi ye-pixel enye kunye ne-3840 × 2160 kwi-60 Hz kwimodi ye-pixel ezine. I-RX IP ixhasa i-Hot Plug Detect (HPD) yokubeka iliso kumandla okanye ukucima kunye nokukhupha okanye ukuvala iziganeko ukubonisa unxibelelwano phakathi komthombo we-HDMI kunye ne-HDMI isinki.
Umthombo we-HDMI usebenzisa i-Display Data channel (DDC) ukufunda i-Sink's Extended Display Identification Data (EDID) ukufumanisa ukucwangciswa kweSink kunye / okanye amandla. I-HDMI RX IP ine-EDID ecwangcisiweyo ngaphambili, apho umthombo we-HDMI unokufunda nge-channel ye-I2C eqhelekileyo. I-PolarFire FPGA kunye ne-PolarFire SoC FPGA ii-transceivers zesixhobo zisetyenziswa kunye ne-RX IP ukukhupha idatha ye-serial kwidatha ye-10-bit. Iziteshi zedatha kwi-HDMI zivumelekile ukuba zibe ne-skew enkulu phakathi kwazo. I-HDMI RX IP isusa i-skew phakathi kwamajelo edatha usebenzisa i-First-In First-Out (FIFOs). Le IP iguqula idatha yeTransition Minimized Differential Signaling (TMDS) efunyenwe kumthombo we-HDMI nge-transceiver kwidatha ye-pixel ye-24-bit ye-RGB, idatha ye-audio ye-24-bit kunye neempawu zokulawula. Iithokheni ezine zokulawula ezisemgangathweni ezichazwe kwi-HDMI protocol zisetyenziselwa ukulungelelanisa idatha ngexesha le-deserialization.
Isishwankathelo
Uluhlu olulandelayo lunika isishwankathelo seempawu ze-HDMI RX IP.
Itheyibhile 1. HDMI RX IP Iimpawu
| Core Version | Esi sikhokelo somsebenzisi sixhasa i-HDMI RX IP v5.4. |
| Izixhobo ezixhaswayo Iintsapho |
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| UkuHamba kwesixhobo esixhaswayo | Ifuna i-Libero® SoC v12.0 okanye ikhutshwe kamva. |
| Ii-interface ezixhaswayo | Ujongano oluxhaswa yi-HDMI RX IP zezi:
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| Ukukhutshwa kwelayisensi | I-HDMI RX IP ibonelelwe ngezi ndlela zimbini zilandelayo zelayisensi:
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Iimbonakalo
I-HDMI RX IP inezi mpawu zilandelayo:
- Iyahambelana neHDMI 2.0
- Ixhasa i-8, 10, 12 kunye ne-16 Bits Ubunzulu boMbala
- Ixhasa iiFomathi zoMbala njengeRGB, YUV 4:2:2 kunye neYUV 4:4:4
- Ixhasa iPixels enye okanye ezine ngeClock nganye
- Ixhasa iziGqibo ukuya kuthi ga kwi-1920 ✕ 1080 kwi-60 Hz kwimowudi yePixel enye kunye ne-3840 ✕ 2160 kwi-60 Hz kwimodi yePixel eZine.
- Ichonga i-Hot-Plug
- Ixhasa i-Decoding Scheme - TMDS
- Ixhasa Igalelo leDVI
- Ixhasa iSiteshi seDatha sokuBonisa (i-DDC) kunye neSiteshi seDatha esiBonelekileyo (E-DDC)
- Ixhasa iNative kunye ne-AXI4 i-Streaming Interface yeVidiyo yoTshintsho lweDatha yeVidiyo
- Ixhasa iNative kunye ne-AXI4 ye-Streaming Audio Interface yokuTshintshwa kweDatha yomsindo
Iimpawu ezingaxhaswanga
Okulandelayo ziimpawu ezingaxhaswanga zeHDMI RX IP:
- 4:2:0 ifomathi yombala ayixhaswanga.
- Uluhlu oluPhezulu lweDynamic (HDR) kunye ne-High-bandwidth yoKhuseleko lweDijithali yeDijithali (HDCP) ayixhaswanga.
- Inqanaba loHlaziyo oluguquguqukayo (VRR) kunye neMowudi yokuLatezeka okuPhantsi okuzenzekelayo (ALLM) ayixhaswanga.
- Iiparamitha zexesha ezithe tyaba ezingohlulwahlulwa ngesine kwimowudi yePixel ezine azixhaswa.
Imiyalelo yokuFakela
Ingundoqo ye-IP kufuneka ifakwe kwi-IP Catalogue ye-software ye-Libero® SoC ngokuzenzekelayo nge-IP Catalog yokuhlaziya umsebenzi kwi-software ye-Libero SoC, okanye ikhutshwe ngesandla kwikhathalogu. Emva kokuba i-IP core ifakwe kwi-Libero SoC ye-software ye-IP Catalogue, iqwalaselwe, yenziwe kwaye ifakwe ngaphakathi kwe-Smart Design ukuze ifakwe kwiprojekthi ye-Libero.
Izixhobo zoMthombo ovavanyiweyo (Buza umbuzo)
Le theyibhile ilandelayo idwelisa izixhobo zomthombo ovavanyiweyo.
Uluhlu 1-1. Izixhobo zoMthombo ezivavanyiweyo
| Izixhobo | Imowudi yePixel | Izigqibo Zivavanyiwe | Ubunzulu boMbala (Bit) | Imo Yombala | Umsindo |
| quantumdata™ M41h HDMI Uhlalutyi | 1 | 720P 30 FPS, 720P 60 FPS kunye1080P 60 FPS | 8 | I-RGB, i-YUV444 kunye ne-YUV422 | Ewe |
| 1080P 30 FPS | 8, 10, 12 kunye ne-16 | ||||
| 4 | 720P 30 FPS, 1080P 30 FPS kunye ne4K 60 FPS | 8 | |||
| 1080P 60 FPS | 8, 12 kunye ne-16 | ||||
| 4K 30 FPS | 8, 10, 12 kunye ne-16 | ||||
| ILenovo™ 20U1A007IG | 1 | 1080P 60 FPS | 8 | RGB | Ewe |
| 4 | I-1080P 60 FPS kunye ne-4K 30 FPS | ||||
| IDell Latitude 3420 | 1 | 1080P 60 FPS | 8 | RGB | Ewe |
| 4 | I-4K 30 FPS kunye ne-4K 60 FPS | ||||
| I-Astro VA-1844A HDMI® Tester | 1 | 720P 30 FPS, 720P 60 FPS kunye1080P 60 FPS | 8 | I-RGB, i-YUV444 kunye ne-YUV422 | Ewe |
| 1080P 30 FPS | 8, 10, 12 kunye ne-16 | ||||
| 4 | 720P 30 FPS, 1080P 30 FPS kunye ne4K 30 FPS | 8 | |||
| 1080P 30 FPS | 8, 12 kunye ne-16 | ||||
| NVIDIA® Jetson AGX Orin 32GB H01 Kit | 1 | 1080P 30 FPS | 8 | RGB | Hayi |
| 4 | 4K 60 FPS |
Uqwalaselo lwe-HDMI RX IP (Buza umbuzo)
Eli candelo libonelela ngaphezuluview ye-HDMI RX IP Configurator interface kunye nezixhobo zayo. I-HDMI RX IP Configurator ibonelela ngojongano lwegraphical ukuseta undoqo we-HDMI RX. Lo mququzeleli uvumela umsebenzisi ukuba akhethe iiparameters ezifana neNani leePixels, Inani leziteshi zomsindo, i-Video Interface, i-Audio Interface, i-SCRAMBLER, ubunzulu boMbala, iFomati yoMbala, i-Testbench kunye neLayisensi. I-Configurator interface ibandakanya iimenu ezihlayo kunye neenketho zokulungisa useto. Ulungelelwaniso oluphambili luchazwe kwiThebhile 4-1. Lo mfanekiso ulandelayo unika iinkcukacha view ye-HDMI RX IP Configurator interface.
Umfanekiso 2-1. I-HDMI RX IP Configurator
I-interface ikwabandakanya u-Kulungile kunye no-Rhoxisa amaqhosha ukuqinisekisa okanye ukulahla ulungelelwaniso.
Ukuphunyezwa kweHardware (Buza umbuzo)
La manani alandelayo achaza i-HDMI RX IP interface kunye ne-transceiver (XCVR).
Umfanekiso 3-1. I-HDMI RX Block Diagram
Umfanekiso 3-2. Umamkeli ngeNgcaciso yeBlock Diagram
I-HDMI RX iqulathe imizuzwana emithathutages:
- Ulungelelwaniso lwesigaba lulungelelanisa idatha ehambelanayo ngokubhekiselele kwimida yokulawula ithokheni usebenzisa i-transceiver bit slip.
- I-decoder ye-TMDS iguqula idatha ye-10-bit encoded kwidatha ye-pixel yevidiyo ye-8-bit, i-4-bit yedatha yepakethe ye-audio kunye ne-2-bit yokulawula iimpawu.
- I-FIFOs isusa i-skew phakathi kweewotshi ze-R, G kunye ne-B lanes.
Ulungelelwaniso lweSigaba (Buza umbuzo)
Idatha ye-10-bit parallel esuka kwi-XCVR ayisoloko ihambelana ngokubhekiselele kwimida yegama elifakwe kwi-TMDS. Idatha enxuseneyo kufuneka iguqulwe kwaye ilungelelaniswe ukuze ikwazi ukucacisa idatha. Ulungelelwaniso lwesigaba lulungelelanisa idatha ehambelanayo engenayo kwimida yamagama usebenzisa i-bit-slip feature kwi-XCVR. I-XCVR kwi-Per-Monitor DPI Awareness (PMA) imowudi ivumela i-bit-slip feature, apho ilungelelanisa ukulungelelaniswa kwegama le-10-bit deserialized nge-1-bit. Ngexesha ngalinye, emva kokulungelelanisa igama le-10-bit nge-1 bit slip position, lifaniswa nayo nayiphi na enye yeempawu zokulawula ezine ze-HDMI protocol ukuvala isikhundla ngexesha lokulawula. Igama le-10-bit lilungelelaniswe ngokuchanekileyo kwaye lithathwa njengelisebenzayo kwi-s elilandelayotages. Ijelo ngalinye lombala linolungelelaniso lwalo lwesigaba, i-decoder ye-TMDS iqala ukucacisa kuphela xa zonke izilungelelaniso zesigaba zivaliwe ukulungisa imida yegama.
Idikhowuda ye-TMDS (Buza umbuzo)
Idikhowuda ye-TMDS idikhowuda i-10-bit deserialized ukusuka kwi-transceiver ukuya kwidatha ye-pixel ye-8-bit ngexesha levidiyo. I-HSYNC, i-VSYNC kunye ne-PACKET HEADER ziveliswa ngexesha lolawulo ukusuka kwi-data ye-blue channel ye-10-bit. Ipakethe yedatha yeaudiyo inqunyulwa kwitshaneli ye-R kunye ne-G nganye inamasuntswana amane. Idikhowuda ye-TMDS yetshaneli nganye isebenza ngewotshi yayo. Ngenxa yoko, inokuba ne-skew ethile phakathi kwamajelo.
Isitishi ukuya kwiChannel De-Skew (Buza umbuzo)
I-FIFO esekelwe kwi-de-skew logic isetyenziselwa ukususa i-skew phakathi kwamajelo. Ishaneli nganye ifumana isignali esebenzayo kwiiyunithi zokulungelelaniswa kwesigaba ukubonisa ukuba idatha ye-10-bit engenayo evela kukulungelelanisa isigaba iyasebenza. Ukuba onke amajelo asebenzayo (aye azuza ulungelelwaniso lwesigaba), imodyuli yeFIFO iqalisa ukugqithisa idatha ngemodyuli yeFIFO isebenzisa imiqondiso yokufunda nokubhala (ukubhala ngokuqhubekayo nokufunda ngaphandle). Xa ithokheni yokulawula ifunyenwe kuyo nayiphi na imveliso ye-FIFO, ukuhamba kokufunda kuyanqunyanyiswa, kwaye i-marker ifunyenwe isignali iveliswa ukubonisa ukufika kommakishi othile kwividiyo. Ukuqukuqela kokufunda kuqalisa kwakhona kuphela xa esi siphawuli sifikile kuzo zontathu iitshaneli. Ngenxa yoko, i-skew efanelekileyo iyasuswa. Ii-FIFOs zewotshi ezimbini zilungelelanisa yonke imijelo emithathu yedatha kwiwotshi yesitishi esiluhlaza ukususa i-skew efanelekileyo. Lo mzobo ulandelayo uchaza itshaneli yokususa isikhewu.
Umfanekiso 3-3. Umjelo ukuya kwiChannel De-Skew
DDC (Buza umbuzo)
I-DDC lijelo lonxibelelwano elisekelwe kwinkcazo yebhasi ye-I2C. Umthombo usebenzisa imiyalelo ye-I2C ukufunda ulwazi kwi-E-EDID ye-sink kunye nedilesi yekhoboka. I-HDMI RX IP isebenzisa i-EDID echazwe kwangaphambili kunye nesisombululo esininzi sixhasa izigqibo ukuya kuthi ga kwi-1920 ✕ 1080 kwi-60 Hz kwimodi yePixel enye kwaye ukuya kuthi ga kwi-3840 ✕ 2160 kwi-60 Hz kwimodi yePixel eZine.
I-EDID imele igama elibonisiweyo njenge-Microchip HDMI display.
Iiparamitha ze-HDMI zeRX kunye neMiqondiso yoNxibelelwano (Buza umbuzo)
Eli candelo lixoxa ngeeparamitha kwi-HDMI RX GUI configurator kunye neempawu ze-I / O.
Uqwalaselo lweParameters (Buza umbuzo)
Itheyibhile ilandelayo idwelisa iiparamitha zoqwalaselo kwi-HDMI RX IP.
Uluhlu 4-1. Iiparamitha zoqwalaselo
| Igama leParameter | Inkcazo |
| Ubume boMbala | Ichaza indawo yombala. Ixhasa ezi fomati zombala zilandelayo:
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| Ubunzulu boMbala | Ixela inani lamasuntswana ngokwecandelo lombala. Ixhasa i-8, 10, 12 kunye ne-16 bits ngecandelo ngalinye. |
| Inani leePixels | Ibonisa inani leepixels ngokwewotshi nganye:
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| I-SCRAMBLER | Inkxaso yesisombululo se-4K kwiifreyimu ezingama-60 ngomzuzwana:
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| Inani lamajelo omsindo | Ixhasa inani lamajelo omsindo:
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| Ujongano lweVidiyo | Umsinga woMthonyama kunye ne-AXI |
| Ujongano lomsindo | Umsinga woMthonyama kunye ne-AXI |
| Ibhentshi yovavanyo | Ivumela ukhetho lwendawo yebhentshi yovavanyo. Ixhasa olu khetho lwebhentshi lulandelayo:
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| Ilayisensi | Ichaza uhlobo lwelayisensi. Ibonelela ngolu hlobo lulandelayo lwelayisenisi ezimbini:
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Amazibuko (Buza umbuzo)
Le theyibhile ilandelayo idwelisa igalelo kunye nemveliso yamazibuko e-HDMI RX IP yojongano lweNative xa iFomathi yoMbala iyi-RGB.
Uluhlu 4-2. Igalelo kunye nesiphumo soNxibelelwano lweNative
| Igama loMqondiso | Isalathiso | Ububanzi (Amasuntswana) | Inkcazo |
| RESET_N_I | Igalelo | 1 | Isiginali yokuseta ngokutsha esebenzayo-phantsi |
| R_RX_CLK_I | Igalelo | 1 | Iwotshi enxuseneyo yetshaneli "R" evela kwiXCVR |
| G_RX_CLK_I | Igalelo | 1 | Iwotshi enxuseneyo yetshaneli "G" evela kwiXCVR |
| B_RX_CLK_I | Igalelo | 1 | Iwotshi enxuseneyo yetshaneli "B" evela kwiXCVR |
| EDID_RESET_N_I | Igalelo | 1 | Isiginali yokusetha ngokutsha i-asynchronous edid esebenzayo-phantsi |
| R_RX_VALID_I | Igalelo | 1 | Isiginali esebenzayo evela kwi-XCVR yedatha yetshaneli "R" ehambelanayo |
| G_RX_VALID_I | Igalelo | 1 | Isiginali esebenzayo evela kwi-XCVR yedatha yetshaneli “G” ehambelanayo |
| B_RX_VALID_I | Igalelo | 1 | Isiginali esebenzayo evela kwi-XCVR yedatha yetshaneli “B” ehambelanayo |
| Igama loMqondiso | Isalathiso | Ububanzi (Amasuntswana) | Inkcazo |
| DATA_R_I | Igalelo | INANI LEEPILESISI ✕ 10 bits | Kufunyenwe idatha yetshaneli "R" ehambelana neXCVR |
| DATA_G_I | Igalelo | INANI LEEPILESISI ✕ 10 bits | Kufunyenwe idatha yetshaneli "G" ehambelana neXCVR |
| DATA_B_I | Igalelo | INANI LEEPILESISI ✕ 10 bits | Kufunyenwe idatha yetshaneli engu-“B” ehambelana neXCVR |
| SCL_I | Igalelo | 1 | I2C uthotho lwewotshi igalelo kwi DDC |
| HPD_I | Igalelo | 1 | Iplagi eshushu ibona uphawu longeniso. Umthombo uqhagamshelwe kwisiginali ye-HPD yokutshona kufuneka ibe phezulu. |
| SDA_I | Igalelo | 1 | Ukufakwa kwedatha ye-I2C yochungechunge lwe-DDC |
| EDID_CLK_I | Igalelo | 1 | Ikloko yenkqubo yemodyuli ye-I2C |
| BIT_SLIP_R_O | Isiphumo | 1 | Umqondiso wokutyibilika kancinci ukuya kwitshaneli "R" ye-transceiver |
| BIT_SLIP_G_O | Isiphumo | 1 | Umqondiso wokutyibilika kancinci kwitshaneli "G" ye-transceiver |
| BIT_SLIP_B_O | Isiphumo | 1 | Umqondiso wokutyibilika kancinci ukuya kwitshaneli ethi "B" ye-transceiver |
| VIDEO_DATA_VALID_O | Isiphumo | 1 | Idatha yevidiyo isiphumo esisebenzayo |
| AUDIO_DATA_VALID_O | Isiphumo | 1 | Idatha yomsindo isiphumo esisebenzayo |
| H_SYNC_O | Isiphumo | 1 | Ukubetha kwe-sync othe tye |
| V_SYNC_O | Isiphumo | 1 | I-sync esebenzayo nkqo |
| R_O | Isiphumo | INANI LEPIKSISI ✕ Amasuntswana obunzulu boMbala | Decoded "R" data |
| G_O | Isiphumo | INANI LEPIKSISI ✕ Amasuntswana obunzulu boMbala | Idatha ye-"G" echongiweyo |
| B_O | Isiphumo | INANI LEPIKSISI ✕ Amasuntswana obunzulu boMbala | Idatha ethi "B" echongiweyo |
| SDA_O | Isiphumo | 1 | I2C imveliso yothotho lwedatha yeDDC |
| HPD_O | Isiphumo | 1 | Iplagi eshushu ibona uphawu lwemveliso |
| ACR_CTS_O | Isiphumo | 20 | Ikloko yeAudiyo yokuHlaziya uMjikelo weTimestamp ixabiso |
| ACR_N_O | Isiphumo | 20 | Ixabiso leClock yeAudio yoHlaziyo (N) ipharamitha |
| ACR_VALID_O | Isiphumo | 1 | Uhlaziyo lwewotshi yeAudio uphawu olusebenzayo |
| I-AUDIO_SAMPLE_CH1_O | Isiphumo | 24 | Umjelo woku-1 we-audio sample data |
| I-AUDIO_SAMPLE_CH2_O | Isiphumo | 24 | Umjelo woku-2 we-audio sample data |
| I-AUDIO_SAMPLE_CH3_O | Isiphumo | 24 | Umjelo woku-3 we-audio sample data |
| I-AUDIO_SAMPLE_CH4_O | Isiphumo | 24 | Umjelo woku-4 we-audio sample data |
| I-AUDIO_SAMPLE_CH5_O | Isiphumo | 24 | Umjelo woku-5 we-audio sample data |
| I-AUDIO_SAMPLE_CH6_O | Isiphumo | 24 | Umjelo woku-6 we-audio sample data |
| I-AUDIO_SAMPLE_CH7_O | Isiphumo | 24 | Umjelo woku-7 we-audio sample data |
| I-AUDIO_SAMPLE_CH8_O | Isiphumo | 24 | Umjelo woku-8 we-audio sample data |
| HDMI_DVI_MODE_O | Isiphumo | 1 | Ezi ndlela zimbini zilandelayo:
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Itheyibhile ilandelayo ichaza igalelo kunye nemveliso yezibuko ze-HDMI RX IP ye-AXI4 Stream Video Interface.
Itheyibhile 4-3. IiPorts zokuPhuma kunye neZiphumo ze-AXI4 Stream Video Interface
| Igama lePort | Isalathiso | Ububanzi (Amasuntswana) | Inkcazo |
| TDATA_O | Isiphumo | INANI LEPIKseli ✕ Ubunzulu boMbala ✕ amasuntswana ama-3 | Imveliso yedatha yevidiyo [R, G, B] |
| TVALID_O | Isiphumo | 1 | Imveliso yevidiyo iyasebenza |
| Igama lePort | Isalathiso | Ububanzi (Amasuntswana) | Inkcazo |
| TLAST_O | Isiphumo | 1 | Isakhelo sesiphumo sophawu lokuphela |
| TUSER_O | Isiphumo | 3 |
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| TSTRB_O | Isiphumo | 3 | Imveliso yevidiyo strobe data |
| TKEEP_O | Isiphumo | 3 | Gcina idatha yevidiyo |
Itheyibhile ilandelayo ichaza igalelo kunye nemveliso yezibuko ze-HDMI RX IP ye-AXI4 Stream Audio Interface.
Itheyibhile 4-4. IiPorts zeNgeniso kunye neZiphumo ze-AXI4 Stream Audio Interface
| Igama lePort | Isalathiso | Ububanzi (Amasuntswana) | Inkcazo |
| AUDIO_TDATA_O | Isiphumo | 24 | Imveliso yedatha yomsindo |
| AUDIO_TID_O | Isiphumo | 3 | Isitishi somsindo wemveliso |
| AUDIO_TVALID_O | Isiphumo | 1 | Imveliso yomsindo wesignali esebenzayo |
Itheyibhile ilandelayo idwelisa igalelo kunye nemveliso ye-HDMI i-IP ye-IP ye-Native interface xa i-Color Format yi-YUV444.
Uluhlu 4-5. Igalelo kunye nesiphumo soNxibelelwano lweNative
| Igama lePort | Isalathiso | Ububanzi (Amasuntswana) | Inkcazo |
| RESET_N_I | Igalelo | 1 | Isiginali yokuseta ngokutsha esebenzayo-phantsi |
| LANE3_RX_CLK_I | Igalelo | 1 | Iwotshi enxuseneyo yetshaneli yeLane 3 esuka kwiXCVR |
| LANE2_RX_CLK_I | Igalelo | 1 | Iwotshi enxuseneyo yetshaneli yeLane 2 esuka kwiXCVR |
| LANE1_RX_CLK_I | Igalelo | 1 | Iwotshi enxuseneyo yetshaneli yeLane 1 esuka kwiXCVR |
| EDID_RESET_N_I | Igalelo | 1 | Isiginali yokusetha ngokutsha i-asynchronous edid esebenzayo-phantsi |
| LANE3_RX_VALID_I | Igalelo | 1 | Isignali esebenzayo esuka kwi-XCVR ye-Lane 3 data parallel |
| LANE2_RX_VALID_I | Igalelo | 1 | Isignali esebenzayo esuka kwi-XCVR ye-Lane 2 data parallel |
| LANE1_RX_VALID_I | Igalelo | 1 | Isignali esebenzayo esuka kwi-XCVR ye-Lane 1 data parallel |
| DATA_LANE3_I | Igalelo | INANI LEEPILESISI ✕ 10 bits | Kufunyenwe idatha yeLane 3 parallel kwi-XCVR |
| DATA_LANE2_I | Igalelo | INANI LEEPILESISI ✕ 10 bits | Kufunyenwe idatha yeLane 2 parallel kwi-XCVR |
| DATA_LANE1_I | Igalelo | INANI LEEPILESISI ✕ 10 bits | Kufunyenwe idatha yeLane 1 parallel kwi-XCVR |
| SCL_I | Igalelo | 1 | I2C uthotho lwewotshi igalelo kwi DDC |
| HPD_I | Igalelo | 1 | Iplagi eshushu ibona uphawu longeniso. Umthombo uqhagamshelwe kwisiginali ye-HPD yokutshona kufuneka ibe phezulu. |
| SDA_I | Igalelo | 1 | Ukufakwa kwedatha ye-I2C yochungechunge lwe-DDC |
| EDID_CLK_I | Igalelo | 1 | Ikloko yenkqubo yemodyuli ye-I2C |
| BIT_SLIP_LANE3_O | Isiphumo | 1 | Umqondiso wokutyibilika kancinci ukuya kwiNdlela yesi-3 ye-transceiver |
| BIT_SLIP_LANE2_O | Isiphumo | 1 | Umqondiso wokutyibilika kancinci ukuya kwiNdlela yesi-2 ye-transceiver |
| BIT_SLIP_LANE1_O | Isiphumo | 1 | Umqondiso wokutyibilika kancinci ukuya kwiNdlela yesi-1 ye-transceiver |
| VIDEO_DATA_VALID_O | Isiphumo | 1 | Idatha yevidiyo isiphumo esisebenzayo |
| AUDIO_DATA_VALID_O | Isiphumo | 1 | Idatha yomsindo isiphumo esisebenzayo |
| H_SYNC_O | Isiphumo | 1 | Ukubetha kwe-sync othe tye |
| V_SYNC_O | Isiphumo | 1 | I-sync esebenzayo nkqo |
| Igama lePort | Isalathiso | Ububanzi (Amasuntswana) | Inkcazo |
| Y_O | Isiphumo | INANI LEPIKSISI ✕ Amasuntswana obunzulu boMbala | Idatha ye-"Y" ekhethiweyo |
| Cb_O | Isiphumo | INANI LEPIKSISI ✕ Amasuntswana obunzulu boMbala | Decoded "Cb" data |
| Cr_O | Isiphumo | INANI LEPIKSISI ✕ Amasuntswana obunzulu boMbala | I-Decoded "Cr" idatha |
| SDA_O | Isiphumo | 1 | I2C imveliso yothotho lwedatha yeDDC |
| HPD_O | Isiphumo | 1 | Iplagi eshushu ibona uphawu lwemveliso |
| ACR_CTS_O | Isiphumo | 20 | Amaxesha eClock yeAudio yoHlaziyo lweMjikeloamp ixabiso |
| ACR_N_O | Isiphumo | 20 | Ixabiso leClock yeAudio yoHlaziyo (N) ipharamitha |
| ACR_VALID_O | Isiphumo | 1 | Uhlaziyo lwewotshi yeAudio uphawu olusebenzayo |
| I-AUDIO_SAMPLE_CH1_O | Isiphumo | 24 | Umjelo woku-1 we-audio sample data |
| I-AUDIO_SAMPLE_CH2_O | Isiphumo | 24 | Umjelo woku-2 we-audio sample data |
| I-AUDIO_SAMPLE_CH3_O | Isiphumo | 24 | Umjelo woku-3 we-audio sample data |
| I-AUDIO_SAMPLE_CH4_O | Isiphumo | 24 | Umjelo woku-4 we-audio sample data |
| I-AUDIO_SAMPLE_CH5_O | Isiphumo | 24 | Umjelo woku-5 we-audio sample data |
| I-AUDIO_SAMPLE_CH6_O | Isiphumo | 24 | Umjelo woku-6 we-audio sample data |
| I-AUDIO_SAMPLE_CH7_O | Isiphumo | 24 | Umjelo woku-7 we-audio sample data |
| I-AUDIO_SAMPLE_CH8_O | Isiphumo | 24 | Umjelo woku-8 we-audio sample data |
Itheyibhile ilandelayo idwelisa igalelo kunye nemveliso ye-HDMI i-IP ye-IP ye-Native interface xa i-Color Format yi-YUV422.
Uluhlu 4-6. Igalelo kunye nesiphumo soNxibelelwano lweNative
| Igama lePort | Isalathiso | Ububanzi (Amasuntswana) | Inkcazo |
| RESET_N_I | Igalelo | 1 | Isiginali yokuseta ngokutsha esebenzayo-phantsi |
| LANE3_RX_CLK_I | Igalelo | 1 | Iwotshi enxuseneyo yetshaneli yeLane 3 esuka kwiXCVR |
| LANE2_RX_CLK_I | Igalelo | 1 | Iwotshi enxuseneyo yetshaneli yeLane 2 esuka kwiXCVR |
| LANE1_RX_CLK_I | Igalelo | 1 | Iwotshi enxuseneyo yetshaneli yeLane 1 esuka kwiXCVR |
| EDID_RESET_N_I | Igalelo | 1 | Isiginali yokusetha ngokutsha i-asynchronous edid esebenzayo-phantsi |
| LANE3_RX_VALID_I | Igalelo | 1 | Isignali esebenzayo esuka kwi-XCVR ye-Lane 3 data parallel |
| LANE2_RX_VALID_I | Igalelo | 1 | Isignali esebenzayo esuka kwi-XCVR ye-Lane 2 data parallel |
| LANE1_RX_VALID_I | Igalelo | 1 | Isignali esebenzayo esuka kwi-XCVR ye-Lane 1 data parallel |
| DATA_LANE3_I | Igalelo | INANI LEEPILESISI ✕ 10 bits | Kufunyenwe idatha yeLane 3 parallel kwi-XCVR |
| DATA_LANE2_I | Igalelo | INANI LEEPILESISI ✕ 10 bits | Kufunyenwe idatha yeLane 2 parallel kwi-XCVR |
| DATA_LANE1_I | Igalelo | INANI LEEPILESISI ✕ 10 bits | Kufunyenwe idatha yeLane 1 parallel kwi-XCVR |
| SCL_I | Igalelo | 1 | I2C uthotho lwewotshi igalelo kwi DDC |
| HPD_I | Igalelo | 1 | Iplagi eshushu ibona uphawu longeniso. Umthombo uqhagamshelwe kwisiginali ye-HPD yokutshona kufuneka ibe phezulu. |
| SDA_I | Igalelo | 1 | Ukufakwa kwedatha ye-I2C yochungechunge lwe-DDC |
| EDID_CLK_I | Igalelo | 1 | Ikloko yenkqubo yemodyuli ye-I2C |
| BIT_SLIP_LANE3_O | Isiphumo | 1 | Umqondiso wokutyibilika kancinci ukuya kwiNdlela yesi-3 ye-transceiver |
| BIT_SLIP_LANE2_O | Isiphumo | 1 | Umqondiso wokutyibilika kancinci ukuya kwiNdlela yesi-2 ye-transceiver |
| BIT_SLIP_LANE1_O | Isiphumo | 1 | Umqondiso wokutyibilika kancinci ukuya kwiNdlela yesi-1 ye-transceiver |
| VIDEO_DATA_VALID_O | Isiphumo | 1 | Idatha yevidiyo isiphumo esisebenzayo |
| Igama lePort | Isalathiso | Ububanzi (Amasuntswana) | Inkcazo |
| AUDIO_DATA_VALID_O | Isiphumo | 1 | Idatha yomsindo isiphumo esisebenzayo |
| H_SYNC_O | Isiphumo | 1 | Ukubetha kwe-sync othe tye |
| V_SYNC_O | Isiphumo | 1 | I-sync esebenzayo nkqo |
| Y_O | Isiphumo | INANI LEPIKSISI ✕ Amasuntswana obunzulu boMbala | Idatha ye-"Y" ekhethiweyo |
| C_O | Isiphumo | INANI LEPIKSISI ✕ Amasuntswana obunzulu boMbala | I-Decoded "C" idatha |
| SDA_O | Isiphumo | 1 | I2C imveliso yothotho lwedatha yeDDC |
| HPD_O | Isiphumo | 1 | Iplagi eshushu ibona uphawu lwemveliso |
| ACR_CTS_O | Isiphumo | 20 | Amaxesha eClock yeAudio yoHlaziyo lweMjikeloamp ixabiso |
| ACR_N_O | Isiphumo | 20 | Ixabiso leClock yeAudio yoHlaziyo (N) ipharamitha |
| ACR_VALID_O | Isiphumo | 1 | Uhlaziyo lwewotshi yeAudio uphawu olusebenzayo |
| I-AUDIO_SAMPLE_CH1_O | Isiphumo | 24 | Umjelo woku-1 we-audio sample data |
| I-AUDIO_SAMPLE_CH2_O | Isiphumo | 24 | Umjelo woku-2 we-audio sample data |
| I-AUDIO_SAMPLE_CH3_O | Isiphumo | 24 | Umjelo woku-3 we-audio sample data |
| I-AUDIO_SAMPLE_CH4_O | Isiphumo | 24 | Umjelo woku-4 we-audio sample data |
| I-AUDIO_SAMPLE_CH5_O | Isiphumo | 24 | Umjelo woku-5 we-audio sample data |
| I-AUDIO_SAMPLE_CH6_O | Isiphumo | 24 | Umjelo woku-6 we-audio sample data |
| I-AUDIO_SAMPLE_CH7_O | Isiphumo | 24 | Umjelo woku-7 we-audio sample data |
| I-AUDIO_SAMPLE_CH8_O | Isiphumo | 24 | Umjelo woku-8 we-audio sample data |
Le theyibhile ilandelayo idwelisa igalelo kunye nemveliso yamazibuko e-HDMI RX IP yojongano lweNative xa i-SCRAMBLER Ivuliwe.
Uluhlu 4-7. Igalelo kunye nesiphumo soNxibelelwano lweNative
| Igama lePort | Isalathiso | Ububanzi (Amasuntswana) | Inkcazo |
| RESET_N_I | Igalelo | 1 | Isiginali yokuseta ngokutsha esebenzayo-phantsi |
| R_RX_CLK_I | Igalelo | 1 | Iwotshi enxuseneyo yetshaneli "R" evela kwiXCVR |
| G_RX_CLK_I | Igalelo | 1 | Iwotshi enxuseneyo yetshaneli "G" evela kwiXCVR |
| B_RX_CLK_I | Igalelo | 1 | Iwotshi enxuseneyo yetshaneli "B" evela kwiXCVR |
| EDID_RESET_N_I | Igalelo | 1 | Isiginali yokusetha ngokutsha i-asynchronous edid esebenzayo-phantsi |
| HDMI_CABLE_CLK_I | Igalelo | 1 | Iwotshi yekhebhula evela kumthombo we-HDMI |
| R_RX_VALID_I | Igalelo | 1 | Isiginali esebenzayo evela kwi-XCVR yedatha yetshaneli "R" ehambelanayo |
| G_RX_VALID_I | Igalelo | 1 | Isiginali esebenzayo evela kwi-XCVR yedatha yetshaneli “G” ehambelanayo |
| B_RX_VALID_I | Igalelo | 1 | Isiginali esebenzayo evela kwi-XCVR yedatha yetshaneli “B” ehambelanayo |
| DATA_R_I | Igalelo | INANI LEEPILESISI ✕ 10 bits | Kufunyenwe idatha yetshaneli "R" ehambelana neXCVR |
| DATA_G_I | Igalelo | INANI LEEPILESISI ✕ 10 bits | Kufunyenwe idatha yetshaneli "G" ehambelana neXCVR |
| DATA_B_I | Igalelo | INANI LEEPILESISI ✕ 10 bits | Kufunyenwe idatha yetshaneli engu-“B” ehambelana neXCVR |
| SCL_I | Igalelo | 1 | I2C uthotho lwewotshi igalelo kwi DDC |
| HPD_I | Igalelo | 1 | Iplagi eshushu ibona uphawu longeniso. Umthombo uqhagamshelwe kwi-sink, kwaye isibonakaliso se-HPD kufuneka sibe phezulu. |
| SDA_I | Igalelo | 1 | Ukufakwa kwedatha ye-I2C yochungechunge lwe-DDC |
| EDID_CLK_I | Igalelo | 1 | Ikloko yenkqubo yemodyuli ye-I2C |
| BIT_SLIP_R_O | Isiphumo | 1 | Umqondiso wokutyibilika kancinci ukuya kwitshaneli "R" ye-transceiver |
| BIT_SLIP_G_O | Isiphumo | 1 | Umqondiso wokutyibilika kancinci kwitshaneli "G" ye-transceiver |
| Igama lePort | Isalathiso | Ububanzi (Amasuntswana) | Inkcazo |
| BIT_SLIP_B_O | Isiphumo | 1 | Umqondiso wokutyibilika kancinci ukuya kwitshaneli ethi "B" ye-transceiver |
| VIDEO_DATA_VALID_O | Isiphumo | 1 | Idatha yevidiyo isiphumo esisebenzayo |
| AUDIO_DATA_VALID_O | Iziphumo1 | 1 | Idatha yomsindo isiphumo esisebenzayo |
| H_SYNC_O | Isiphumo | 1 | Ukubetha kwe-sync othe tye |
| V_SYNC_O | Isiphumo | 1 | I-sync esebenzayo nkqo |
| DATA_ RATE_O | Isiphumo | 16 | Ireyithi yedatha ye-Rx. Oku kulandelayo ngamaxabiso ereyithi yedatha:
|
| R_O | Isiphumo | INANI LEPIKSISI ✕ Amasuntswana obunzulu boMbala | Decoded "R" data |
| G_O | Isiphumo | INANI LEPIKSISI ✕ Amasuntswana obunzulu boMbala | Idatha ye-"G" echongiweyo |
| B_O | Isiphumo | INANI LEPIKSISI ✕ Amasuntswana obunzulu boMbala | Idatha ethi "B" echongiweyo |
| SDA_O | Isiphumo | 1 | I2C imveliso yothotho lwedatha yeDDC |
| HPD_O | Isiphumo | 1 | Iplagi eshushu ibona uphawu lwemveliso |
| ACR_CTS_O | Isiphumo | 20 | Amaxesha eClock yeAudio yoHlaziyo lweMjikeloamp ixabiso |
| ACR_N_O | Isiphumo | 20 | Ixabiso leClock yeAudio yoHlaziyo (N) ipharamitha |
| ACR_VALID_O | Isiphumo | 1 | Uhlaziyo lwewotshi yeAudio uphawu olusebenzayo |
| I-AUDIO_SAMPLE_CH1_O | Isiphumo | 24 | Umjelo woku-1 we-audio sample data |
| I-AUDIO_SAMPLE_CH2_O | Isiphumo | 24 | Umjelo woku-2 we-audio sample data |
| I-AUDIO_SAMPLE_CH3_O | Isiphumo | 24 | Umjelo woku-3 we-audio sample data |
| I-AUDIO_SAMPLE_CH4_O | Isiphumo | 24 | Umjelo woku-4 we-audio sample data |
| I-AUDIO_SAMPLE_CH5_O | Isiphumo | 24 | Umjelo woku-5 we-audio sample data |
| I-AUDIO_SAMPLE_CH6_O | Isiphumo | 24 | Umjelo woku-6 we-audio sample data |
| I-AUDIO_SAMPLE_CH7_O | Isiphumo | 24 | Umjelo woku-7 we-audio sample data |
| I-AUDIO_SAMPLE_CH8_O | Isiphumo | 24 | Umjelo woku-8 we-audio sample data |
Ukulinganisa kweTestbench (Buza umbuzo)
I-Testbench inikezelwa ukujonga ukusebenza kwe-HDMI RX core. I-Testbench isebenza kuphela kwi-Native Interface xa inani leepixels lilinye.
Ukulinganisa i-core usebenzisa i-testbench, yenza la manyathelo alandelayo:
- Kwifestile yoYilo oluQuquza, yandisa Yenza uYilo.
- Cofa ekunene Yenza i-SmartDesign Testbench, uze ucofe u-Run, njengoko kubonisiwe kulo mfanekiso ulandelayo.
Umzobo 5-1. Ukudala iSmartDesign Testbench
- Faka igama le-SmartDesign testbench, uze ucofe u-Kulungile.
Umfanekiso 5-2. Ukuthiya iSmartDesign Testbench
I-SmartDesign testbench yenziwe, kwaye i-canvas ibonakala ngasekunene kwePhaneli yoYilo lokuQula. - Yiya kwikhathalogu yeLibero® SoC, khetha View > Windows > Ikhathalogu ye-IP, kwaye wandise iziSombululo-Ividiyo. Cofa kabini i-HDMI RX IP (v5.4.0) uze ucofe u-Kulungile.
- Khetha onke amazibuko, cofa ekunene kwaye ukhethe ukunyusela kwiNqanaba eliphezulu.
- Kwibar yesixhobo seSmartDesign, cofa ukuvelisa icandelo.
- Kwi-Stimulus Hierarchy thebhu, cofa ekunene HDMI_RX_TB testbench file, kwaye emva koko ucofe Lingisa i-Pre-Synth Design> Vula ngokuSebenzayo.
Isixhobo se-ModelSim® sivula nge-testbench, njengoko kuboniswe kulo mfanekiso ulandelayo.
Umfanekiso 5-3. Isixhobo seModelSim esine-HDMI RX Testbench File
Kubalulekile: If ukulinganisa kuphazamisekile ngenxa yomda wexesha lokuqhuba elichazwe kwi-DO file, sebenzisa i run -all command ukugqiba ukulinganisa.
Ilayisensi (Buza umbuzo)
I-HDMI RX IP ibonelelwe ngezi ndlela zimbini zilandelayo zelayisensi:
- Uguqulelo Oluntsonkothileyo: Ikhowudi ye-RTL efihliweyo epheleleyo inikezelwe ngondoqo. Ifumaneka simahla ngayo nayiphi na ilayisensi yeLibero, eyenza ukuba undoqo uqiniswe ngeSmartDesign. Unokwenza Ufaniso, uHlangano, uYilo, kunye nenkqubo yesilicon yeFPGA usebenzisa iLibero design suite.
- I-RTL: Gqibezela ikhowudi yomthombo we-RTL ilayisenisi itshixiwe, ekufuneka ithengwe ngokwahlukeneyo.
Iziphumo zokulinganisa (Buza umbuzo)
Idayagram yexesha elilandelayo ye-HDMI RX IP ibonisa idatha yevidiyo kunye namaxesha okulawula idatha.
Umfanekiso 6-1. Idatha yeVidiyo
Lo mzobo ulandelayo ubonisa iziphumo ze-hsync kunye ne-vsync yokufakwa kwedatha yolawulo oluhambelanayo.
Umfanekiso 6-2. Ungqamaniso oluthe tyaba kunye neMiqondiso eNqolileyo yoQhagamshelwano
Lo mzobo ulandelayo ubonisa inxalenye ye-EDID.
Umfanekiso 6-3. Iimpawu zeEDID
Usetyenziso lweziBonelelo (Buza umbuzo)
I-HDMI RX IP iphunyezwe kwi-PolarFire® FPGA (MPF300T - 1FCG1152I Package). Le theyibhile ilandelayo idwelisa izixhobo ezisetyenziswa xa Inani leePixels = 1 pixel.
Uluhlu 7-1. Usetyenziso lweziBonelelo kwiMowudi yePixel eyi-1
| Ubume boMbala | Ubunzulu boMbala | I-SCRAMBLER | Ilaphu 4LUT | Ilaphu DFF | Ujongano 4LUT | Ujongano lweDFF | ISRAM (64×12) | I-LSRAM (20k) |
| RGB | 8 | Khubaza | 987 | 1867 | 360 | 360 | 0 | 10 |
| 10 | Khubaza | 1585 | 1325 | 456 | 456 | 11 | 9 | |
| 12 | Khubaza | 1544 | 1323 | 456 | 456 | 11 | 9 | |
| 16 | Khubaza | 1599 | 1331 | 492 | 492 | 14 | 9 | |
| YCbCr422 | 8 | Khubaza | 1136 | 758 | 360 | 360 | 3 | 9 |
| YCbCr444 | 8 | Khubaza | 1105 | 782 | 360 | 360 | 3 | 9 |
| 10 | Khubaza | 1574 | 1321 | 456 | 456 | 11 | 9 | |
| 12 | Khubaza | 1517 | 1319 | 456 | 456 | 11 | 9 | |
| 16 | Khubaza | 1585 | 1327 | 492 | 492 | 14 | 9 |
Le theyibhile ilandelayo idwelisa izixhobo ezisetyenziswa xa Inani leePixels = 4 pixels.
Uluhlu 7-2. Usetyenziso lweziBonelelo kwiMowudi yePixel eyi-4
| Ubume boMbala | Ubunzulu boMbala | I-SCRAMBLER | Ilaphu 4LUT | Ilaphu DFF | Ujongano 4LUT | Ujongano lweDFF | ISRAM (64×12) | I-LSRAM (20k) |
| RGB | 8 | Khubaza | 1559 | 1631 | 1080 | 1080 | 9 | 27 |
| 12 | Khubaza | 1975 | 2191 | 1344 | 1344 | 31 | 27 | |
| 16 | Khubaza | 1880 | 2462 | 1428 | 1428 | 38 | 27 | |
| RGB | 10 | Vulela | 4231 | 3306 | 1008 | 1008 | 3 | 27 |
| 12 | Vulela | 4253 | 3302 | 1008 | 1008 | 3 | 27 | |
| 16 | Vulela | 3764 | 3374 | 1416 | 1416 | 37 | 27 | |
| YCbCr422 | 8 | Khubaza | 1485 | 1433 | 912 | 912 | 7 | 23 |
| YCbCr444 | 8 | Khubaza | 1513 | 1694 | 1080 | 1080 | 9 | 27 |
| 12 | Khubaza | 2001 | 2099 | 1344 | 1344 | 31 | 27 | |
| 16 | Khubaza | 1988 | 2555 | 1437 | 1437 | 38 | 27 |
Le theyibhile ilandelayo idwelisa izixhobo ezisetyenziswayo xa Inani leePixels = 4 pixel kunye ne-SCRAMBLER yenziwe yasebenza.
Uluhlu 7-3. Ukusetyenziswa koVimba kwiMowudi yePixel ye-4 kunye ne-SCRAMBLER ivuliwe
| Ubume boMbala | Ubunzulu boMbala | I-SCRAMBLER | Ilaphu 4LUT | Ilaphu DFF | Ujongano 4LUT | Ujongano lweDFF | ISRAM (64×12) | I-LSRAM (20k) |
| RGB | 8 | Vulela | 5029 | 5243 | 1126 | 1126 | 9 | 28 |
| YCbCr422 | 8 | Vulela | 4566 | 3625 | 1128 | 1128 | 13 | 27 |
| YCbCr444 | 8 | Vulela | 4762 | 3844 | 1176 | 1176 | 17 | 27 |
Ukudityaniswa kweNkqubo (Buza umbuzo)
Eli candelo libonisa indlela yokudibanisa i-IP kuyilo lweLibero.
Le theyibhile ilandelayo idwelisa ulungelelwaniso lwePF XCVR, PF TX PLL kunye nePF CCC ezifunekayo kwizisombululo ezahlukeneyo kunye nobubanzi bebit.
Itheyibhile 8-1. PF XCVR, PF TX PLL kunye nePF CCC Configurations
| Isigqibo | Ububanzi Bit | PF XCVR uqwalaselo | CDR REF WOSHI PADS | Uqwalaselo lwe-PF CCC | |||
| Ireyithi yedatha ye-RX | RX CDR Ref Clock Frequency | RX PCS Fabric Ububanzi | Ukuphindaphinda kongeniso | Ubuninzi beziphumo | |||
| 1 PXL (1080p60) | 8 | 1485 | 148.5 | 10 | AE27, AE28 | NA | NA |
| 1 PXL (1080p30) | 10 | 1485 | 148.5 | 10 | AE27, AE28 | 92.5 | 74 |
| 12 | 1485 | 148.5 | 10 | AE27, AE28 | 74.25 | 111.375 | |
| 16 | 1485 | 148.5 | 10 | AE27, AE28 | 74.25 | 148.5 | |
| 4 PXL (1080p60) | 8 | 1485 | 148.5 | 40 | AE27, AE28 | NA | NA |
| 12 | 1485 | 148.5 | 40 | AE27, AE28 | 55.725 | 37.15 | |
| 16 | 1485 | 148.5 | 40 | AE27, AE28 | 74.25 | 37.125 | |
| 4 PXL (4kp30) | 8 | 1485 | 148.5 | 40 | AE27, AE28 | NA | NA |
| 10 | 3712.5 | 148.5 | 40 | AE29, AE30 | 92.81 | 74.248 | |
| 12 | 4455 | 148.5 | 40 | AE29, AE30 | 111.375 | 74.25 | |
| 16 | 5940 | 148.5 | 40 | AE29, AE30 | 148.5 | 74.25 | |
| 4 PXL (4Kp60) | 8 | 5940 | 148.5 | 40 | AE29, AE30 | NA | NA |
I-HDMI RX SampkuYilo 1: Xa iqwalaselwe kubunzulu boMbala = 8-bit kunye nenani lePixels = 1 imowudi yePixel, iboniswe kulo mfanekiso ulandelayo.
Umfanekiso 8-1. I-HDMI RX Sample Uyilo 1
UmzekeloampLe, kuqwalaselo lwe-8-bit, la malungu alandelayo ayinxalenye yoyilo:
- PF_XCVR_ERM (PF_XCVR_ERM_C0_0) imiselwe i-TX kunye ne-RX imowudi ephindwe kabini. Ireyithi yedatha ye-RX ye-1485 Mbps kwimo ye-PMA, kunye nobubanzi bedatha obulungiselelwe njenge-bit ye-10 kwimowudi ye-1 ye-PXL kunye ne-148.5 MHz CDR yewotshi yereferensi. Ireyithi yedatha ye-TX ye-1485 Mbps kwimodi ye-PMA, kunye nobubanzi bedatha obulungiselelwe njenge-bit ye-10 kunye ne-clock division factor 4.
- I-LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK kunye ne-LANE3_CDR_REF_CLK ziqhutywa kwi-PF_XCVR_REF_CLK nge-AE27, AE28 yezikhonkwane zePad.
- Iphini ye-EDID CLK_I kufuneka iqhutywe ngewotshi ye-150 MHz nge-CCC.
- R_RX_CLK_I, G_RX_CLK_I kunye ne-B_RX_CLK_I ziqhutywa yi-LANE3_TX_CLK_R, LANE2_TX_CLK_R kunye ne-LANE1_TX_CLK_R, ngokulandelelanayo.
- R_RX_VALID_I, G_RX_VALID_I kunye ne-B_RX_VALID_I ziqhutywa yi-LANE3_RX_VAL, LANE2_RX_VAL kunye ne-LANE1_RX_VAL, ngokulandelelanayo.
- DATA_R_I, DATA_G_I kunye ne-DATA_B_I ziqhutywa yi-LANE3_RX_DATA, LANE2_RX_DATA kunye ne-LANE1_RX_DATA, ngokulandelelanayo.
I-HDMI RX SampkuYilo 2: Xa iqwalaselwe kubunzulu boMbala = 8-bit kunye nenani lePixels = 4 imowudi yePixel, iboniswe kulo mfanekiso ulandelayo.
Umfanekiso 8-2. I-HDMI RX Sample Uyilo 2
UmzekeloampLe, kuqwalaselo lwe-8-bit, la malungu alandelayo ayinxalenye yoyilo:
- PF_XCVR_ERM (PF_XCVR_ERM_C0_0) imiselwe i-TX kunye ne-RX imowudi ephindwe kabini. Ireyithi yedatha ye-RX ye-1485 Mbps kwimo ye-PMA, kunye nobubanzi bedatha obulungiselelwe njenge-bit ye-40 kwimowudi ye-4 ye-PXL kunye ne-148.5 MHz CDR yewotshi yereferensi. Ireyithi yedatha ye-TX ye-1485 Mbps kwimodi ye-PMA, kunye nobubanzi bedatha obulungiselelwe njenge-bit ye-40 kunye ne-clock division factor 4.
- I-LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK kunye ne-LANE3_CDR_REF_CLK ziqhutywa kwi-PF_XCVR_REF_CLK nge-AE27, AE28 yezikhonkwane zePad.
- Iphini ye-EDID CLK_I kufuneka iqhutywe ngewotshi ye-150 MHz nge-CCC.
- R_RX_CLK_I, G_RX_CLK_I kunye ne-B_RX_CLK_I ziqhutywa yi-LANE3_TX_CLK_R, LANE2_TX_CLK_R kunye ne-LANE1_TX_CLK_R, ngokulandelelanayo.
- R_RX_VALID_I, G_RX_VALID_I kunye ne-B_RX_VALID_I ziqhutywa yi-LANE3_RX_VAL, LANE2_RX_VAL kunye ne-LANE1_RX_VAL, ngokulandelelanayo.
- DATA_R_I, DATA_G_I kunye ne-DATA_B_I ziqhutywa yi-LANE3_RX_DATA, LANE2_RX_DATA kunye ne-LANE1_RX_DATA, ngokulandelelanayo.
I-HDMI RX SampkuYilo 3: Xa iqwalaselwe kubunzulu boMbala = 8-bit kunye nenani lePixels = 4 imowudi yePixel kunye ne-SCRAMBLER = Inikwe amandla, iboniswe kulo mfanekiso ulandelayo.
Umfanekiso 8-3. I-HDMI RX Sample Uyilo 3
UmzekeloampLe, kuqwalaselo lwe-8-bit, la malungu alandelayo ayinxalenye yoyilo:
- PF_XCVR_ERM (PF_XCVR_ERM_C0_0) imiselwe i-TX kunye ne-RX imo eZimeleyo. Ireyithi yedatha ye-RX ye-5940 Mbps kwimo ye-PMA, kunye nobubanzi bedatha obulungiselelwe njenge-bit ye-40 ye-4 imo ye-PXL kunye ne-148.5 MHz CDR yewotshi yereferensi. Ireyithi yedatha ye-TX ye-5940 Mbps kwimodi ye-PMA, kunye nobubanzi bedatha obulungiselelwe njenge-40 bit kunye ne-clock division factor 4.
- I-LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK kunye ne-LANE3_CDR_REF_CLK ziqhutywa kwi-PF_XCVR_REF_CLK nge-AF29, AF30 yezikhonkwane zePad.
- EDID CLK_I pin kufuneka iqhube nge 150 MHz iwotshi nge CCC.
- R_RX_CLK_I, G_RX_CLK_I kunye ne-B_RX_CLK_I ziqhutywa yi-LANE3_TX_CLK_R, LANE2_TX_CLK_R kunye ne-LANE1_TX_CLK_R, ngokulandelelanayo.
- R_RX_VALID_I, G_RX_VALID_I kunye ne-B_RX_VALID_I ziqhutywa yi-LANE3_RX_VAL, LANE2_RX_VAL kunye ne-LANE1_RX_VAL, ngokulandelelanayo.
- DATA_R_I, DATA_G_I kunye ne-DATA_B_I ziqhutywa yi-LANE3_RX_DATA, LANE2_RX_DATA kunye ne-LANE1_RX_DATA, ngokulandelelanayo.
I-HDMI RX SampkuYilo 4: Xa iqwalaselwe kubunzulu boMbala = 12-bit kunye nenani lePixels = 4 imowudi yePixel kunye ne-SCRAMBLER = Inikwe amandla, iboniswe kulo mfanekiso ulandelayo.
Umfanekiso 8-4. I-HDMI RX Sample Uyilo 4
UmzekeloampLe, kuqwalaselo lwe-12-bit, la malungu alandelayo ayinxalenye yoyilo:
- PF_XCVR_ERM (PF_XCVR_ERM_C0_0) imiselwe imo ye-RX Kuphela. Ireyithi yedatha ye-RX ye-4455 Mbps kwimo ye-PMA, kunye nobubanzi bedatha obulungiselelwe njenge-bit ye-40 ye-4 imo ye-PXL kunye ne-148.5 MHz CDR yewotshi yereferensi.
- I-LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK kunye ne-LANE3_CDR_REF_CLK ziqhutywa kwi-PF_XCVR_REF_CLK nge-AF29, AF30 yezikhonkwane zePad.
- EDID CLK_I pin kufuneka iqhube nge 150 MHz iwotshi nge CCC.
- R_RX_CLK_I, G_RX_CLK_I kunye ne-B_RX_CLK_I ziqhutywa yi-LANE3_TX_CLK_R, LANE2_TX_CLK_R kunye ne-LANE1_TX_CLK_R, ngokulandelelanayo.
- R_RX_VALID_I, G_RX_VALID_I kunye ne-B_RX_VALID_I ziqhutywa yi-LANE3_RX_VAL, LANE2_RX_VAL kunye ne-LANE1_RX_VAL, ngokulandelelanayo.
- DATA_R_I, DATA_G_I kunye ne-DATA_B_I ziqhutywa yi-LANE3_RX_DATA, LANE2_RX_DATA kunye ne-LANE1_RX_DATA, ngokulandelelanayo.
- Imodyuli ye-PF_CCC_C0 ivelisa iwotshi ebizwa ngokuba yi-OUT0_FABCLK_0 kunye ne-frequency ye-74.25 MHz, ephuma kwi-clock yokufaka ye-111.375 MHz, eqhutywa yi-LANE1_RX_CLK_R.
I-HDMI RX SampkuYilo 5: Xa iqwalaselwe kubunzulu boMbala = 8-bit, Inani leePixels = 4 Imowudi yePixel kunye ne-SCRAMBLER = Inikwe amandla iboniswe kulo mfanekiso ulandelayo. Olu luyilo luyireyithi yedatha eguqukayo kunye ne-DRI.
Umfanekiso 8-5. I-HDMI RX Sample Uyilo 5
UmzekeloampLe, kuqwalaselo lwe-8-bit, la malungu alandelayo ayinxalenye yoyilo:
- PF_XCVR_ERM (PF_XCVR_ERM_C0_0) imiselwe imo ye-RX Kuphela enojongano olusebenzayo lohlengahlengiso. Ireyithi yedatha ye-RX ye-5940 Mbps kwimo ye-PMA, kunye nobubanzi bedatha obulungiselelwe njenge-bit ye-40 ye-4 imo ye-PXL kunye ne-148.5 MHz CDR yewotshi yereferensi.
- I-LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK kunye ne-LANE3_CDR_REF_CLK ziqhutywa kwi-PF_XCVR_REF_CLK nge-AF29, AF30 yezikhonkwane zePad.
- EDID CLK_I pin kufuneka iqhube nge 150 MHz iwotshi nge CCC.
- R_RX_CLK_I, G_RX_CLK_I kunye ne-B_RX_CLK_I ziqhutywa yi-LANE3_TX_CLK_R, LANE2_TX_CLK_R kunye ne-LANE1_TX_CLK_R, ngokulandelelanayo.
- R_RX_VALID_I, G_RX_VALID_I kunye ne-B_RX_VALID_I ziqhutywa yi-LANE3_RX_VAL, LANE2_RX_VAL kunye ne-LANE1_RX_VAL, ngokulandelelanayo.
- DATA_R_I, DATA_G_I kunye ne-DATA_B_I ziqhutywa yi-LANE3_RX_DATA, LANE2_RX_DATA kunye ne-LANE1_RX_DATA, ngokulandelelanayo.
Imbali yoHlaziyo (Buza umbuzo)
Imbali yohlaziyo ichaza utshintsho oluthe lwaphunyezwa kuxwebhu. Ezi nguqulelo zidweliswe ngohlaziyo, kuqalwa kolona papasho lwangoku.
Uluhlu 9-1. Imbali yohlaziyo
| Uhlaziyo | Umhla | Inkcazo |
| D | 02/2025 | Oku kulandelayo luluhlu lweenguqu ezenziwe kuhlaziyo C loxwebhu:
|
| C | 02/2023 | Oku kulandelayo luluhlu lweenguqu ezenziwe kuhlaziyo C loxwebhu:
|
| B | 09/2022 | Oku kulandelayo luluhlu lweenguqu ezenziwe kuhlaziyo B loxwebhu:
|
| A | 04/2022 | Oku kulandelayo luluhlu lweenguqu kuhlaziyo A loxwebhu:
|
| 2.0 | — | Oku kulandelayo sisishwankathelo sotshintsho olwenziwe kolu hlaziyo.
|
| 1.0 | 08/2021 | Uhlaziyo lokuqala. |
Microchip FPGA Inkxaso
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- Ukusuka eMntla Melika, fowunela 800.262.1060
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Iimpawu zokuthengisa
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Isaziso soMthetho
Olu papasho kunye nolwazi olulapha lunokusetyenziswa kuphela ngeemveliso zeMicrochip, kubandakanywa ukuyila, ukuvavanya, kunye nokudibanisa iimveliso zeMicrochip kunye nesicelo sakho. Ukusetyenziswa kolu lwazi ngayo nayiphi na enye indlela kwaphula le migaqo. Ulwazi malunga nosetyenziso lwesixhobo lunikezelwa kuphela ukulungiselela wena kwaye lunokuthi luthathelwe indawo luhlaziyo. Luxanduva lwakho ukuqinisekisa ukuba isicelo sakho siyadibana neenkcukacha zakho. Qhagamshelana neofisi yakho yentengiso yeMicrochip yengingqi ngenkxaso eyongezelelweyo okanye, ufumane inkxaso eyongezelelweyo kwi www.microchip.com/en-us/support/design-help/client-support-services.
OLU LWAZI LUBONWA NGE-MICROCHIP “NJENGOKO ZINJALO”. I-MICROCHIP AYENZA Mmeli OKANYE IZIQINISEKISO ZALO NALUPHI UHLOBO, OKANYE INGCACILEYO OKANYE IYATHENWA, IYABHALWA OKANYE NGOMLOMO, NGOMTHETHO OKANYE NGOLUNYE, ENXULUMENE NOLWAZI KUBANDAKANYA KODWA AYIMDALWA KUSO NAsiphi na ISIQINISEKISO SOKUBANISWA, UKUFANELEKILEYO NGENJONGO ETHILE, OKANYE IZIQINISEKISO EZINXULUMENE NEMEKO, UMGANGATHO, OKANYE UKUSEBENZA KWAYO.
AKUKHO SIGANEKO IYA KUTHWATHWA NALUPHI NA I-MICROCHIP ESIYA KUTHWALA NGALO NALUPHI NA ULWAZI, OLUKHETHEKILEYO, LWESOHLWAYO, NGESIGANEKO, OKANYE OKUPHUMELELE Ilahleko, UMONAKALO, IINDLEKO, OKANYE INKCITHO YALO NOLUPHI NA UHLOBO ELUYANXULUMENE NOLWAZI OKANYE UKUSETYENZISWA KWALO, NANGONA INGCACISO, NANGENZWENI. OKUSEKO OKANYE UMONAKALO UYABONAKALA. NGOKUPHELELEYO UXANDUVA LUVUMELEKILEYO NGOMTHETHO, UXANDUVA LWONKE LE-MICROCHIP KULONKE AMABANGO NGAYO NAYIPHI NA IINDLELA EZINXULUMENE NOLWAZI OKANYE UKUSETYENZISWA KWALO AKUYI KUGQIBELA ISIXA SOMRHUMO, UKUBA NAKHO, OWUHLAWULE NGQO UKUBA ULWAZI LWAZI.
Ukusetyenziswa kwezixhobo zeMicrochip kwinkxaso yobomi kunye / okanye izicelo zokhuseleko ngokupheleleyo kumngcipheko womthengi, kwaye umthengi uyavuma ukukhusela, ukuhlawulela kwaye ubambe iMicrochip engenabungozi kuyo nayiphi na kunye nawo wonke umonakalo, amabango, iisuti, okanye iindleko ezibangelwa kukusetyenziswa okunjalo. Akukho zilayisenisi zigqithiswayo, ngokungafihlisiyo okanye ngenye indlela, phantsi kwawo nawaphi na amalungelo epropathi yemveliso yeMicrochip ngaphandle kokuba kuchazwe ngenye indlela.
Microchip Devices Code Protection Feature
Qaphela ezi nkcukacha zilandelayo zenqaku lokhuseleko lwekhowudi kwiimveliso zeMicrochip:
- Iimveliso zeMicrochip ziyahlangabezana nemigaqo equlethwe kwiMicrochip Data Sheet yazo.
- IMicrochip ikholelwa ukuba usapho lwayo lweemveliso lukhuselekile xa lusetyenziswa ngendlela ecetywayo, ngokwemigaqo yokusebenza, naphantsi kweemeko eziqhelekileyo.
- Ixabiso leMicrochip kwaye likhusela ngokungqongqo amalungelo epropathi enomgangatho ophezulu wokuqonda. Iinzame zokwaphula ikhowudi yokukhusela iimpawu zeemveliso zeMicrochip zithintelwe ngokungqongqo kwaye zinokwaphula umthetho weDigital Millennium Copyright Act.
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FAQ
- Umbuzo: Ndiyihlaziya njani i-HDMI RX IP core?
A: Undoqo we-IP unokuhlaziywa ngesoftware ye-Libero SoC okanye ukhutshelwe ngesandla kwikhathalogu. Nje ukuba ifakwe kwiKhathalogu ye-IP yesoftware ye-Libero SoC, inokulungiswa, yenziwe, kwaye ifakwe ngaphakathi kwi-SmartDesign ukuze ifakwe kwiprojekthi.
Amaxwebhu / Izibonelelo
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