Intel FPGA Programmable Acceleration Card N3000 User Guide
Intshayelelo
Imvelaphi
I-Intel FPGA Programmable Acceleration Card N3000 kwi-virtualized radio access network (vRAN) ifuna inkxaso ye-IEEE1588v2 njengeProtocol yeXesha lePrecision (PTP) iTelecom Slave Clocks (T-TSC) ukucwangcisa imisebenzi yesoftware ngokufanelekileyo. I-Intel Ethernet Controller XL710 kwi-Intel® FPGA PAC N3000 ibonelela ngenkxaso ye-IEEE1588v2. Nangona kunjalo, indlela yedatha yeFPGA yazisa ijitter echaphazela ukusebenza kwePTP. Ukongeza iwashi ecacileyo (T-TC) isekethe yenza ukuba i-Intel FPGA PAC N3000 ibuyekeze i-FPGA yayo yangaphakathi kwaye inciphise iziphumo zejitter, evumela i-T-TSC ukuba iqikelele iXesha leMini le-Grandmaster (ToD) ngokufanelekileyo.
Injongo
Ezi mvavanyo ziqinisekisa ukusetyenziswa kwe-Intel FPGA PAC N3000 njengekhoboka le-IEEE1588v2 kwi-Open Radio Access Network (O-RAN). Olu xwebhu luchaza:
- Ukuseta uvavanyo
- Inkqubo yokuqinisekisa
- Uvavanyo lokusebenza kwendlela yewotshi ecacileyo kwindlela yeFPGA ye-Intel FPGA PAC N3000
- Ukusebenza kwe-PTP ye-Intel FPGA PAC N3000 Ukusebenza kwe-Intel FPGA PAC N3000 exhasa iwotshi ebonakalayo
xa kuthelekiswa ne-Intel FPGA PAC N3000 ngaphandle kwewotshi ebonakalayo kunye nelinye ikhadi le-Ethernet XXV710 phantsi kweemeko ezahlukeneyo zendlela kunye noqwalaselo lwe-PTP.
Iimpawu kunye neMida
Iimpawu kunye nemida yokuqinisekisa ye-Intel FPGA PAC N3000 IEEE1588v2 inkxaso ilandelayo:
- Ukupakishwa kwesoftware esetyenzisiweyo: Iprojekthi yeLinux PTP (PTP4l)
- Ixhasa i-telecom pro ilandelayofiles:
- 1588v2 (ehlala ikho)
- G. 8265.1
- G. 8275.1
- Ixhasa amanyathelo amabini ewotshi yekhoboka le-PTP.
Intel Corporation. Onke Amalungelo Agciniwe. I-Intel, ilogo ye-Intel, kunye nezinye iimpawu ze-Intel ziimpawu zorhwebo ze-Intel Corporation okanye iinkampani eziphantsi kwayo. I-Intel iqinisekisa ukusebenza kweFPGA yayo kunye neemveliso zesemiconductor kwiinkcukacha zangoku ngokuhambelana newaranti esemgangathweni ye-Intel, kodwa inelungelo lokwenza utshintsho kuzo naziphi na iimveliso kunye neenkonzo nangaliphi na ixesha ngaphandle kwesaziso. I-Intel ayithathi xanduva okanye ityala elivela kwisicelo okanye ukusetyenziswa kwalo naluphi na ulwazi, imveliso, okanye inkonzo echazwe apha ngaphandle kokuba kuvunyelwene ngokubhaliweyo yi-Intel. Abathengi be-Intel bayacetyiswa ukuba bafumane inguqulelo yamva nje yeenkcazo zesixhobo ngaphambi kokuba baxhomekeke kulo naluphi na ulwazi olupapashiweyo naphambi kokubeka iiodolo zeemveliso okanye iinkonzo. *Amanye amagama kunye neempawu zingabangwa njengempahla yabanye.
- Ixhasa imowudi yosasazo oluninzi ukuya ekupheleni.
- Ixhasa utshintshiselwano lomyalezo we-PTP ukuya kuthi ga kwi-128 Hz.
- Lo ngumda wesicwangciso sokuqinisekisa kwaye uqeshwe i-Grandmaster. Ulungelelwaniso lwe-PTP olungaphezulu kweepakethe ze-128 ngesekhondi kwimiyalezo ye-PTP lunokwenzeka.
- Ngenxa yokulinganiselwa kweCisco* Nexus* 93180YC-FX iswitshi esetyenziswe kulungiselelo lokuqinisekisa, iziphumo zokusebenza phantsi kweemeko ze-iperf3 zethrafikhi zibhekisa kwireyithi yokutshintshiselana komyalezo we-PTP we-8 Hz.
- Inkxaso ye-encapsulation:
- Ukuthutha ngaphaya kwe-L2 (i-Ethernet ekrwada) kunye ne-L3 (UDP/IPv4/IPv6)
Phawula: Kulo xwebhu, zonke iziphumo zisebenzisa ikhonkco enye ye-25Gbps ye-Ethernet.
- Ukuthutha ngaphaya kwe-L2 (i-Ethernet ekrwada) kunye ne-L3 (UDP/IPv4/IPv6)
Izixhobo kunye neenguqulelo zomqhubi
| Izixhobo | Inguqulelo |
| BIOS | Ibhodi ye-Intel Server S2600WF 00.01.0013 |
| OS | I-CentOS 7.6 |
| I-Kernel | i-kernel-rt-3.10.0-693.2.2.rt56.623.el7.src. |
| IKit yoPhuhliso lwePlanethi yeDatha (DPDK) | 18.08 |
| Intel C Compiler | 19.0.3 |
| Umqhubi we-Intel XL710 (umqhubi we-i40e) | 2.8.432.9.21 |
| PTP4l | 2.0 |
| IxExplorer | 8.51.1800.7 EA-Patch1 |
| lperf3 | 3.0.11 |
| trafgen | I-Netsniff-ng 0.6.6 Izixhobo zokusebenza |
Uvavanyo lweTrafikhi lwe-IXIA
Iseti yokuqala yebenchmarks yokusebenza ye-PTP ye-Intel FPGA PAC N3000 isebenzisa isisombululo se-IXIA* sokuvavanya ukuthotyelwa kwenethiwekhi kunye ne-PTP. Ibhokisi ye-IXIA XGS2 ye-chassis iquka i-IXIA 40 PORT NOVUS-R100GE8Q28 ikhadi kunye ne-IxExplorer ebonelela nge-graphical interface yokuseta i-PTP Grandmaster ebonakalayo kwi-DUT (Intel FPGA PAC N3000) phezu kwe-25 Gbps eyodwa yoqhagamshelwano oluthe ngqo lwe-Ethernet. Umzobo webhloko ongezantsi ubonisa i-topology yokuvavanya ekujoliswe kuyo kwi-IXIA-based benchmarks. Zonke iziphumo zisebenzisa i-IXIA-eveliswe i-traffic yovavanyo lokungena kunye nokusebenzisa isixhobo se-trafgen kwi-Intel FPGA PAC N3000 ibamba kwiimvavanyo zendlela ye-egress, apho i-ingress okanye i-direct direction egress isoloko isuka kwimbono ye-DUT (Intel FPGA PAC N3000 ) umamkeli. Kuzo zombini iimeko, umyinge wezinga le-traffic yi-24 Gbps. Olu cwangciso lovavanyo lubonelela ngophawu olusisiseko lwentsebenzo ye-PTP ye-Intel FPGA PAC N3000 ngomatshini we-T-TC onikwe amandla, kunye nokuwuthelekisa nomfanekiso we-non-TC we-Intel FPGA PAC N3000 wefektri phantsi kwe-ITU-T G.8275.1 PTP profile.
I-Topology ye-Intel FPGA PAC N3000 yovavanyo lweTrafikhi phantsi kwe-IXIA Virtual Grandmaster
Isiphumo soVavanyo lweTrafikhi ye-IXIA
Uhlalutyo olulandelayo lubamba ukusebenza kwe-PTP ye-TC-enabled Intel FPGA PAC N3000 phantsi kweemeko ze-traffic ezingenayo kunye ne-egress. Kweli candelo, i PTP profile I-G.8275.1 yamkelwe kulo lonke uvavanyo lwendlela kunye nokuqokelelwa kwedatha.
Ubungakanani be-Master Offset
Lo mfanekiso ulandelayo ubonisa ubukhulu be-master offset eqatshelwe ngumthengi we-PTP4l wekhoboka le-Intel FPGA PAC N3000 host njengomsebenzi wexesha elidlulileyo phantsi kokungena, i-egress kunye ne-bidirectional traffic (i-avareji ye-24.4Gbps).
Ulibaziseko lweNdlela eLungelwano (MPD)
Lo mzobo ulandelayo ubonisa ukulibaziseka kwendlela, njengoko kubalwe likhoboka le-PTP4 esebenzisa i-Intel FPGA PAC N3000 njengekhadi lojongano lwenethiwekhi, kuvavanyo olufanayo nolo mfanekiso ungentla. Ubude bexesha lovavanyo ngalunye kwezi zintathu zovavanyo lwendlela ubuncinane ziiyure ezili-16.
Le theyibhile ilandelayo idwelisa uhlalutyo lweenkcukacha-manani lweemvavanyo ezintathu zendlela. Ngaphantsi komthwalo we-traffic kufutshane nomthamo wetshaneli, ikhoboka le-PTP4l elisebenzisa i-Intel FPGA PAC N3000 ligcina i-offset yesigaba sayo kwi-IXIA's virtual grandmaster ngaphakathi kwe-53 ns kuzo zonke iimvavanyo zendlela. Ukongezelela, ukuphambuka okusemgangathweni kwe-master offset magnitude ingaphantsi kwe-5 ns.
Iinkcukacha-manani ngokuSebenza kwe-PTP
| G.8275.1 PTP Profile | I-Ingress Traffic (24Gbps) | I-Egress Traffic (24Gbps) | I-Bidirectional Traffic (24Gbps) |
| RMS | 6.35 ns | 8.4 ns | 9.2 ns |
| I-StdDev (ye-abs(max) offset) | 3.68 ns | 3.78 ns | 4.5 ns |
| I-StdDev (yeMPD) | 1.78 ns | 2.1 ns | 2.38 ns |
| Ubukhulu becala | 36 ns | 33 ns | 53 ns |
Amanani alandelayo abonisa ubukhulu be-master offset kunye nokulibaziseka kwendlela yokulibaziseka (MPD), phantsi kweeyure ze-16 ubude be-24 Gbps yovavanyo lwetrafikhi ye-bidirectional ye-encapsulations ye-PTP eyahlukeneyo. Iigrafu ezisekhohlo kula manani zibhekisela kwi-PTP benchmarks phantsi kwe-IPv4 / UDP encapsulation, ngelixa i-PTP yokuthumela imiyalezo yeegrafu ezichanekileyo kwi-L2 (i-Ethernet eluhlaza). Ukusebenza kwekhoboka le-PTP4l kuyafana, eyona nto imbi kakhulu i-master offset magnitude yi-53 ns kunye ne-45 ns ye-IPv4/UDP kunye ne-L2 encapsulation, ngokulandelanayo. Ukutenxa komgangatho we-magnitude offset yi-4.49 ns kunye ne-4.55 ns ye-IPv4/UDP kunye ne-L2 encapsulation, ngokulandelanayo.
Ubungakanani be-Master Offset
Lo mfanekiso ulandelayo ubonisa ubukhulu be-master offset phantsi kwe-24 Gbps traffic bidirectional, IPv4 (ekhohlo) kunye ne-L2 (ekunene) encapsulation, G8275.1 Profile.
Ulibaziseko lweNdlela eLungelwano (MPD)
Lo mzobo ulandelayo ubonisa ukulibaziseka kwendlela ye-Intel FPGA PAC N3000 host PTP4l ikhoboka phantsi kwe-24 Gbps bidirectional traffic, IPv4 (ekhohlo) kunye ne-L2 (ekunene) encapsulation, G8275.1 Profile.
Amanani apheleleyo e-MPD ayibonakalisi ecacileyo yokuhambelana kwe-PTP, njengoko kuxhomekeke kwiintambo zobude, i-data data latency kunye nokunye; nangona kunjalo, ukujonga iinguqu eziphantsi ze-MPD (i-2.381 ns kunye ne-2.377 ns ye-IPv4 kunye ne-L2 case, ngokulandelanayo) yenza kucace ukuba i-PTP MPD yokubala ichanekileyo ngokuqhubekayo kuzo zombini i-encapsulations. Iqinisekisa ukuhambelana kokusebenza kwe-PTP kuzo zonke iindlela zokudibanisa. Utshintsho lwenqanaba kwi-MPD ebaliweyo kwigrafu ye-L2 (kulo mzobo ungentla, igrafu echanekileyo) ngenxa yempembelelo eyongeziweyo yetrafikhi esetyenzisiweyo. Okokuqala, umjelo awusebenzi (i-MPD rms yi-55.3 ns), emva koko i-traffic ingress isetyenzisiweyo (isinyathelo sesibini sokunyuka, i-MPD rms yi-85.44 ns), ilandelwa yi-traffic egress yangexesha elifanayo, okubangela ukubalwa kwe-MPD ye-108.98 ns. La manani alandelayo agqume ubukhulu be-master offset kunye ne-MPD ebalwayo yovavanyo lwetrafikhi oluphindwe kabini olusetyenziswa kuzo zombini ikhoboka le-PTP4l lisebenzisa i-Intel FPGA PAC N3000 ngomatshini we-T-TC, kunye nakwenye esebenzisa i-Intel FPGA PACN3000 ngaphandle kwe-TC. ukusebenza. I-T-TC Intel FPGA PAC N3000 iimvavanyo (orenji) ziqala ukusuka kwixesha elingu-zero, ngelixa uvavanyo lwe-PTP olusebenzisa i-non-TC Intel FPGA PAC N3000 (blue) iqala malunga ne-T = 2300 imizuzwana.
Ubungakanani be-Master Offset
Lo mfanekiso ulandelayo ubonisa ubukhulu be-master offset phantsi kwe-Ingress traffic (24 Gbps), kunye nangaphandle kwenkxaso ye-TTC, G.8275.1 Profile.
Kulo mzobo ungentla, ukusebenza kwe-PTP ye-TC-enabled Intel FPGA PAC N3000 phantsi kwe-traffic ifana ne-non-TC Intel FPGA PAC N3000 kwimizuzwana yokuqala ye-2300. Ukusebenza kwendlela ye-T-TC kwi-Intel FPGA PAC N3000 igxininiswe kwicandelo lovavanyo (emva kwesibini se-2300) apho umthwalo olinganayo wezithuthi usetyenziswa kwi-interfaces zombini amakhadi. Ngokufanayo kumfanekiso ongezantsi, izibalo zeMPD zijongwa ngaphambi nangemva kokusebenzisa i-traffic kwitshaneli. Ukusebenza kwendlela ye-T-TC kugxininiswe ekuhlawuleleni ixesha lokuhlala kwiipakethi okuyi-packet latency ngokusebenzisa indlela ye-FPGA phakathi kwe-25G kunye ne-40G MACs.
Ulibaziseko lweNdlela eLungelwano (MPD)
Lo mfanekiso ulandelayo ubonisa ukulibaziseka kwendlela ye-Intel FPGA PAC N3000 host PTP4l ikhoboka phantsi kwe-Ingress traffic (24 Gbps), kunye nangaphandle kwenkxaso ye-T-TC, G.8275.1 Profile.
La manani abonisa i-algorithm ye-servo ye-PTP4l yekhoboka, ngenxa yokulungiswa kwexesha lokuhlala le-TC, sibona umahluko omncinci kwindlela yokubala yokulibaziseka kwendlela. Ke ngoko, impembelelo yokulibaziseka kokulibaziseka kwi-master offset approximation iyancitshiswa. Le theyibhile ilandelayo idwelisa uhlalutyo lweenkcukacha-manani kwintsebenzo ye-PTP, ebandakanya i-RMS kunye nokutenxa okusemgangathweni kwe-master offset, ukutenxa okusemgangathweni kokulibaziseka kwendlela ephakathi, kunye neyona nto imbi kakhulu ye-master offset ye-Intel FPGA PAC N3000 kunye nangaphandle kwe-T- Inkxaso yeTC.
Iinkcukacha-manani malunga nokuSebenza kwe-PTP phantsi kwe-Ingress Traffic
| I-Ingress Traffic (24Gbps) G.8275.1 PTP Profile | Intel FPGA PAC N3000 kunye T- TC | Intel FPGA PAC N3000 ngaphandle T-TC |
| RMS | 6.34 ns | 40.5 ns |
| I-StdDev (ye-abs(max) offset) | 3.65 ns | 15.5 ns |
| I-StdDev (yeMPD) | 1.79 ns | 18.1 ns |
| Ubukhulu becala | 34 ns | 143 ns |
Uthelekiso oluthe ngqo lwe-Intel FPGA PAC N3000 exhaswa yi-TC kuguqulelo olungelulo lwe-TC
Ibonisa ukuba ukusebenza kwe-PTP yi-4x ukuya kwi-6x esezantsi ngokumalunga naluphi na amanani
iimethrikhi (imeko embi kakhulu, i-RMS okanye ukutenxa okusemgangathweni kwe-master offset). Eyona nto imbi kakhulu
i-master offset ye-G.8275.1 PTP uqwalaselo lwe-T-TC Intel FPGA PAC N3000 yi-34
ns phantsi kweemeko ze-traffic zokungena kumda we-channel bandwidth (24.4Gbps).
Uvavanyo lweTrafikhi lwe-lperf3
Eli candelo lichaza uvavanyo lokulinganisa i-iperf3 yetrafikhi ukuvavanya ngakumbi ukusebenza kwe-PTP ye-Intel FPGA PAC N3000. Isixhobo se-iperf3 sisetyenziselwe ukulinganisa iimeko zendlela esebenzayo. I-topology yenethiwekhi ye-iperf3 yebenchmarks yendlela, eboniswe kumzobo ongezantsi, ibandakanya uqhagamshelwano lweeseva ezimbini, nganye isebenzisa ikhadi le-DUT (Intel FPGA PAC N3000 kunye ne-XXV710), kwi-Cisco Nexus 93180YC FX switch. Ukutshintsha kweCisco kusebenza njengeClock yeMida (T-BC) phakathi kwamakhoboka amabini e-DUT PTP kunye neCalnex Paragon-NEO Grandmaster.
I-Network Topology ye-Intel FPGA PAC N3000 lperf3 Uvavanyo lweTrafikhi
Imveliso ye-PTP4l kwinginginya nganye ye-DUT ibonelela ngemilinganiselo yedatha yokusebenza kwe-PTP kwisixhobo ngasinye sekhoboka ekusekweni (Intel FPGA PAC N3000 kunye ne-XXV710). Kuvavanyo lwetrafikhi iperf3, le miqathango ilandelayo kunye nolungelelwaniso lusebenza kuzo zonke iigrafu kunye nohlalutyo lokusebenza:
- I-17 Gbps i-bandwidth edibeneyo ye-traffic (zombini i-TCP kunye ne-UDP), nokuba i-egress okanye i-ingress okanye i-bidirectional kwi-Intel FPGA PAC N3000.
- IPv4 encapsulation of PTP packets, ngenxa yoqwalaselo umda Cisco Nexus 93180YC-FX switch.
- Izinga lotshintshiselwano lomyalezo we-PTP likhawulelwe kwiipakethi ezi-8/yesibini, ngenxa yokucutha uqwalaselo kwiCisco Nexus 93180YC-FX switch.
perf3 Iziphumo zoVavanyo lweZithuthi
Olu hlalutyo lulandelayo lubamba ukusebenza kwe-Intel FPGA PAC N3000 kunye nekhadi le-XXV710, zombini ngaxeshanye zisebenza njengekhadi lojongano lwenethiwekhi yamakhoboka e-PTP (T-TSC) iCalnex Paragon NEO Grandmaster ngeT-BC Cisco switch.
La manani alandelayo abonisa ubukhulu be-master offset kunye ne-MPD ekuhambeni kwexesha kwiimvavanyo ezintathu zetrafikhi ezahlukeneyo usebenzisa i-Intel FPGA PAC N3000 ene-T-TC kunye ne-XXV710 ikhadi. Kuzo zombini amakhadi, i-traffic ye-bidirectional inempembelelo enkulu ekusebenzeni kwe-PTP4l. Ubude bexesha lovavanyo lwetrafikhi ziiyure ezili-10 ubude. Kula manani alandelayo, umsila wegrafu uphawula inqaku ngexesha apho i-traffic imisa kunye nobukhulu be-PTP master offset yehla ukuya kumanqanaba aphantsi, ngenxa yeshaneli engasebenziyo.
Ubukhulu be-Master Offset ye-Intel FPGA PAC N3000
Lo mfanekiso ulandelayo ubonisa ukulibaziseka kwendlela ye-Intel FPGA PAC N3000 ene-T TC, phantsi kokungena, i-egress kunye ne-bidirectional iperf3 traffic.
ULibaziseko lweNdlela eLithetha (MPD) ye-Intel FPGA PAC N3000
Lo mfanekiso ulandelayo ubonisa ukulibaziseka kwendlela ye-Intel FPGA PAC N3000 ene-T TC, phantsi kokungena, i-egress kunye ne-bidirectional iperf3 traffic.
Ubungakanani be-Master Offset ye-XXV710
Lo mzobo ulandelayo ubonisa ubukhulu be-master offset ye-XXV710, phantsi kwe-ingress, i-egress kunye ne-bidirectional iperf3 traffic.
ULibaziso lweNdlela eNgcono (MPD) yeXXV710
Lo mzobo ulandelayo ubonisa ukulibaziseka kwendlela ye-XXV710, ngaphantsi kokungena, i-egress kunye ne-bidirectional iperf3 traffic.
Ngokumalunga nokusebenza kwe-Intel FPGA PAC N3000 PTP, eyona nto imbi kakhulu i-master offset phantsi kwayo nayiphi na imeko ye-traffic ingaphakathi kwe-90 ns. Ngelixa phantsi kweemeko ezifanayo zetrafikhi, i-RMS ye-Intel FPGA PAC N3000 master offset yi-5.6x engcono kuneyekhadi le-XXV710.
| Intel FPGA PAC N3000 | Ikhadi leXXV710 | |||||
| I-Ingress Traffic10G | I-Egress Traffic 18G | Iindlela ezimbini zeTrafikhi18G | I-Ingress Traffic18G | I-Egress Traffic 10G | Iindlela ezimbini zeTrafikhi18G | |
| RMS | 27.6 ns | 14.2 ns | 27.2 ns | 93.96 ns | 164.2 ns | 154.7 ns |
| I-StdDev(ye-abs(max) offset) | 9.8 ns | 8.7 ns | 14.6 ns | 61.2 ns | 123.8 ns | 100 ns |
| I-StdDev (yeMPD) | 21.6 ns | 9.2 ns | 20.6 ns | 55.58 ns | 55.3 ns | 75.9 ns |
| Ubukhulu becala | 84 ns | 62 ns | 90 ns | 474 ns | 1,106 ns | 958 ns |
Ngokucacileyo, i-master offset ye-Intel FPGA PAC N3000 inomgangatho ophantsi wokutenxa,
ubuncinci i-5x ngaphantsi kwekhadi le-XXV710, lithetha ukuba uqikelelo lwe-PTP
Iwotshi ye-Grandmaster ayikhathali kangako kwi-latency okanye ukwahluka kwengxolo phantsi kwetrafikhi kwi
Intel FPGA PAC N3000.
Xa kuthelekiswa neSiphumo soVavanyo lweNdlela ye-IXIA kwiphepha lesi-5, ubukhulu becala
i-master offset ene-T-TC enikwe amandla i-Intel FPGA PAC N3000 ibonakala iphezulu. Ngaphandle koko
Umahluko kwi-topology yenethiwekhi kunye ne-channel bandwidths, oku kungenxa ye-Intel
I-FPGA PAC N3000 ibanjwe phantsi kwe-G.8275.1 PTP profile (16 Hz sync rate), ngelixa
ireyithi yomyalezo wongqamaniso kulo mzekelo uthintelwe kwiipakethi ezisi-8 ngesekhondi.
Ubungakanani bothelekiso lwe-Master Offset
Lo mzobo ulandelayo ubonisa ubukhulu be-master offset yothelekiso phantsi kwetrafikhi iperf3 ye-bidirectional.
Ulibaziseko lweNdlela eLingeneyo (MPD) Uthelekiso
Lo mzobo ulandelayo ubonisa uthelekiso lokulibaziseka kwendlela phantsi kwetrafikhi iperf3 ye-bidirectional.
Ukusebenza okuphezulu kwe-PTP ye-Intel FPGA PAC N3000, xa kuthelekiswa nekhadi le-XXV710, ikwaxhaswa ngokutenxa okucacileyo okuphezulu kokulibaziseka kwendlela ebaliweyo (MPD) yeXXV710 kunye ne-Intel FPGA PAC N3000 kuvavanyo lwetrafikhi ekujoliswe kulo, kuba umzample ndlela-mbini iperf3 traffic. Ukungahoyi ixabiso eliqhelekileyo kwimeko nganye ye-MPD, enokuthi ihluke ngenxa yezizathu ezininzi, njengeentambo ze-Ethernet ezahlukeneyo kunye ne-latency engundoqo eyahlukileyo. Ukungafani okubonwayo kunye ne-spike kumaxabiso ekhadi le-XXV710 azikho kwi-Intel FPGA PAC N3000.
I-RMS ye-8 elandelelanayo yothelekiso lwe-Master Offset
Ukuqukumbela
Indlela yedatha ye-FPGA phakathi kwe-QSFP28 (25G MAC) kunye ne-Intel XL710 (40G MAC) yongeza i-latency yepakethe eguquguqukayo echaphazela ukuchaneka kokuchaneka kwe-PTP Slave. Ukongeza iClock eNgaphandle (T-TC) inkxaso kwi-FPGA logic ethambileyo ye-Intel FPGA PAC N3000 ibonelela ngembuyekezo yale packet latency ngokufaka ixesha layo lokuhlala kwindawo yokulungisa imiyalezo ye-PTP efihliweyo. Iziphumo ziqinisekisa ukuba indlela ye-T-TC iphucula ukusebenza ngokuchanekileyo kwekhoboka le-PTP4l.
Kwakhona, i-IXIA ye-Traffic Test Result kwiphepha le-5 ibonisa ukuba inkxaso ye-T-TC kwindlela yedatha ye-FPGA iphucula ukusebenza kwe-PTP ubuncinane nge-4x, xa kuthelekiswa ne-Intel FPGA PAC N3000 ngaphandle kwenkxaso ye-T-TC. I-Intel FPGA PAC N3000 ene-T-TC ibonisa i-master offset ye-53 ns phantsi kwe-ingress, i-egress okanye i-bidirectional imithwalo ye-traffic kumda womthamo wesiteshi (25 Gbps). Yiyo loo nto, ngenkxaso ye-T-TC, ukusebenza kwe-Intel FPGA PAC N3000 PTP kuchaneke ngakumbi kwaye akuthandeki kakhulu kwiiyantlukwano zengxolo.
Kuvavanyo lweTrafikhi lwe-lperf3 kwiphepha le-10, ukusebenza kwe-PTP ye-Intel FPGA PAC N3000 ene-T-TC enikwe amandla ithelekiswa nekhadi le-XXV710. Olu vavanyo lubambe idatha ye-PTP4l yazo zombini iiwotshi zekhoboka phantsi kokungena okanye i-traffic egress etshintshiswayo phakathi kweenginginya ezimbini ze-Intel FPGA PAC N3000 kunye ne-XXV710 ikhadi. Eyona nto imbi kakhulu ye-master offset ebonwe kwi-Intel FPGA PAC N3000 ingaphantsi nge-5x ngaphantsi kwekhadi le-XXV710. Kwakhona, ukutenxa okusemgangathweni kwee-offsets ezibanjiweyo kukwangqina ukuba inkxaso ye-T-TC ye-Intel FPGA PAC N3000 ivumela uqikelelo olugudileyo lwewotshi ye-Grandmaster.
Ukuqinisekisa ngakumbi ukusebenza kwe-PTP ye-Intel FPGA PAC N3000, ukhetho olunokubakho lovavanyo lubandakanya:
- Ukuqinisekiswa phantsi kwe-PTP eyahlukileyofiles kunye namaxabiso omyalezo ngaphezulu kwekhonkco elinye le-Ethernet.
- Uvavanyo loVavanyo lweZithuthi lwe-lperf3 kwiphepha le-10 ngotshintsho oluphucukileyo oluvumela amaxabiso aphezulu emiyalezo ye-PTP.
- Ukuvavanywa komsebenzi we-T-SC kunye nokuchaneka kwexesha le-PTP phantsi kwe-G.8273.2 yoVavanyo lokuThotyelwa kweNdlela.
Imbali yoHlaziyo yoXwebhu lwe-IEEE 1588 V2 Test
| Uxwebhu Inguqulelo | Iinguqu |
| 2020.05.30 | Ukukhutshwa kokuqala. |
Amaxwebhu / Izibonelelo
 |
Intel FPGA Programmable Acceleration Card N3000 [pdf] Isikhokelo somsebenzisi FPGA Programmable Acceleration Card, N3000, Programmable Acceleration Card N3000, FPGA Programmable Acceleration Card N3000, FPGA, IEEE 1588 V2 Test |
