Intel FPGA Programmable Acceleration Card N3000 Umhlahlandlela Womsebenzisi
Isingeniso
Ingemuva
I-Intel FPGA Programmable Acceleration Card N3000 kunethiwekhi yokufinyelela yomsakazo (vRAN) idinga ukusekelwa kwe-IEEE1588v2 njenge-Precision Time Protocol (PTP) Telecom Slave Clocks (T-TSC) ukuze ihlele imisebenzi yesofthiwe ngendlela efanele. I-Intel Ethernet Controller XL710 ku-Intel® FPGA PAC N3000 inikeza ukusekelwa kwe-IEEE1588v2. Nokho, indlela yedatha ye-FPGA yethula i-jitter ethinta ukusebenza kwe-PTP. Ukwengeza iwashi elibonisa ngale (T-TC) kuvumela i-Intel FPGA PAC N3000 ukuthi inxephezele ukubambezeleka kwayo kwangaphakathi kwe-FPGA futhi kunciphisa imiphumela ye-jitter, okuvumela i-T-TSC ukuthi ilinganisele Isikhathi Sosuku Se-Grandmaster (ToD) kahle.
Inhloso
Lezi zivivinyo ziqinisekisa ukusetshenziswa kwe-Intel FPGA PAC N3000 njengesigqila se-IEEE1588v2 ku-Open Radio Access Network (O-RAN). Lo mbhalo uchaza:
- Ukusethwa kokuhlola
- Inqubo yokuqinisekisa
- Ukuhlolwa kokusebenza kwendlela yewashi esobala endleleni ye-FPGA ye-Intel FPGA PAC N3000
- Ukusebenza kwe-PTP kwe-Intel FPGA PAC N3000 Ukusebenza kwe-Intel FPGA PAC N3000 esekela iwashi elibonisa ngale
uma kuqhathaniswa ne-Intel FPGA PAC N3000 ngaphandle kwewashi elibonisa ngale kanye nelinye ikhadi le-Ethernet XXV710 ngaphansi kwezimo ezihlukahlukene zethrafikhi nokulungiselelwa kwe-PTP.
Izici Nemikhawulo
Izici nemikhawulo yokuqinisekisa yosekelo lwe-Intel FPGA PAC N3000 IEEE1588v2 imi kanje:
- Isitaki sesofthiwe esisetshenzisiwe: Iphrojekthi ye-Linux PTP (PTP4l)
- Isekela i-telecom pro elandelayofiles:
- 1588v2 (okuzenzakalelayo)
- G. 8265.1
- G. 8275.1
- Isekela iwashi lesigqila le-PTP elinezinyathelo ezimbili.
Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo yesemiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi. *Amanye amagama namabhrendi angafunwa njengempahla yabanye.
- Isekela imodi yokusakaza okuningi ekupheleni ukuya ekupheleni.
- Isekela ukushintshaniswa kwemiyalezo ye-PTP kufika ku-128 Hz.
- Lona umkhawulo wohlelo lokuqinisekisa futhi uqashwe u-Grandmaster. Ukulungiselelwa kwe-PTP okuphezulu kunamaphakethe angu-128 ngomzuzwana wemilayezo ye-PTP kungenzeka.
- Ngenxa yemikhawulo yeswishi ye-Cisco* Nexus* 93180YC-FX esetshenziswe ekusethweni kokuqinisekisa, imiphumela yokusebenza ngaphansi kwezimo zethrafikhi ye-iperf3 ibhekisela esilinganisweni sokushintshana somlayezo we-PTP esingu-8 Hz.
- Ukusekelwa kwe-encapsulation:
- Ezokuthutha nge-L2 (i-Ethernet eluhlaza) ne-L3 (UDP/IPv4/IPv6)
Qaphela: Kulo mbhalo, yonke imiphumela isebenzisa isixhumanisi esisodwa se-Ethernet esingu-25Gbps.
- Ezokuthutha nge-L2 (i-Ethernet eluhlaza) ne-L3 (UDP/IPv4/IPv6)
Amathuluzi Nezinguqulo Zomshayeli
| Amathuluzi | Inguqulo |
| I-BIOS | Intel Server Board S2600WF 00.01.0013 |
| OS | I-CentOS 7.6 |
| I-Kernel | i-kernel-rt-3.10.0-693.2.2.rt56.623.el7.src. |
| I-Data Plane Development Kit (DPDK) | 18.08 |
| I-Intel C Compiler | 19.0.3 |
| I-Intel XL710 Driver (umshayeli we-i40e) | 2.8.432.9.21 |
| I-PTP4l | 2.0 |
| I-IxExplorer | 8.51.1800.7 EA-Patch1 |
| lperf3 | 3.0.11 |
| trafgen | I-Netsniff-ng 0.6.6 Ikhithi yamathuluzi |
Ukuhlolwa Kwethrafikhi kwe-IXIA
Isethi yokuqala yamabhentshimakhi okusebenza e-PTP ye-Intel FPGA PAC N3000 isebenzisa isisombululo se-IXIA* sokuhlola ukuhambisana kwenethiwekhi ne-PTP. Ibhokisi le-chassis le-IXIA XGS2 lihlanganisa ikhadi le-IXIA 40 PORT NOVUS-R100GE8Q28 kanye ne-IxExplorer enikeza isixhumi esibonakalayo sokumisa i-PTP Grandmaster ebonakalayo ku-DUT (Intel FPGA PAC N3000) ngoxhumano olulodwa lwe-Ethernet oluqondile lwe-25 Gbps. Umdwebo webhulokhi ongezansi ubonisa i-topology yokuhlola ehlosiwe yamabhentshimakhi asekelwe ku-IXIA. Yonke imiphumela isebenzisa ithrafikhi ekhiqizwe i-IXIA ekuhlolweni kwethrafikhi ye-ingress futhi isebenzise ithuluzi le-trafgen kumsingathi we-Intel FPGA PAC N3000 ekuhlolweni kwethrafikhi ye-egress, lapho indlela yokungena noma yokuphuma ihlala isuka kumbono we-DUT (Intel FPGA PAC N3000 ) umphathi. Kuzo zombili izimo, isilinganiso somthamo wezimoto singama-24 Gbps. Lokhu kusetha kokuhlola kunikeza ukulinganiswa okuyisisekelo kokusebenza kwe-PTP kwe-Intel FPGA PAC N3000 ngomshini we-T-TC onikwe amandla, kanye nokuwuqhathanisa nesithombe sefekthri okungesona se-TC Intel FPGA PAC N3000 ngaphansi kwe-ITU-T G.8275.1 PTP pro.file.
I-Topology ye-Intel FPGA PAC N3000 Ukuhlolwa Kwethrafikhi ngaphansi kwe-IXIA Virtual Grandmaster
Umphumela Wokuhlolwa Kwethrafikhi we-IXIA
Ukuhlaziywa okulandelayo kuthwebula ukusebenza kwe-PTP kwe-Intel FPGA PAC N3000 enikwe amandla yi-TC ngaphansi kwezimo zethrafikhi zokungena nokuphuma. Kulesi sigaba, i-PTP profile I-G.8275.1 yamukelwe kukho konke ukuhlolwa kwethrafikhi nokuqoqwa kwedatha.
Ubukhulu be-Master Offset
Isibalo esilandelayo sibonisa ubukhulu be-master offset ebonwa iklayenti lesigqila le-PTP4l lomsingathi we-Intel FPGA PAC N3000 njengomsebenzi wesikhathi esidlulile ngaphansi kokungena, ukuphuma nokuhamba kabili kwethrafikhi (isilinganiso sokuphuma kwe-24.4Gbps).
IMean Path Delay (MPD)
Isibalo esilandelayo sibonisa ukubambezeleka kwendlela emaphakathi, njengoba kubalwe yisigqila se-PTP4 esisebenzisa i-Intel FPGA PAC N3000 njengekhadi lesixhumi esibonakalayo senethiwekhi, ekuhlolweni okufanayo nalesi sibalo esingenhla. Isikhathi esiphelele sokuhlolwa ngakunye kokuthathu kwethrafikhi okungenani amahora ayi-16.
Ithebula elilandelayo libala ukuhlaziywa kwezibalo kokuhlolwa kwethrafikhi okuthathu. Ngaphansi komthwalo wethrafikhi oseduze nomthamo wesiteshi, isigqila se-PTP4l esisebenzisa i-Intel FPGA PAC N3000 sigcina isigaba saso sifinyelela kugogo omkhulu we-IXIA phakathi kwama-53 ns kukho konke ukuhlolwa kwethrafikhi. Ngaphezu kwalokho, ukuchezuka okujwayelekile kwe-master offset magnitude kungaphansi kwama-5 ns.
Imininingwane Yezibalo Ngokusebenza kwe-PTP
| G.8275.1 PTP Profile | I-Ingress Traffic (24Gbps) | I-Egress Traffic (24Gbps) | I-Bidirectional Traffic (24Gbps) |
| I-RMS | 6.35 ns | 8.4 ns | 9.2 ns |
| I-StdDev (ye-abs(max) offset) | 3.68 ns | 3.78 ns | 4.5 ns |
| I-StdDev (ye-MPD) | 1.78 ns | 2.1 ns | 2.38 ns |
| I-offset ephezulu | 36 ns | 33 ns | 53 ns |
Izibalo ezilandelayo zimelela ubukhulu be-master offset kanye nokubambezeleka kwendlela ye-mean (MPD), ngaphansi kokuhlolwa kwethrafikhi okuqondiswa kabili kwe-16 Gbps okungamahora angu-24 kokuhlanganisa okuhlukile kwe-PTP. Amagrafu angakwesokunxele kulezi zibalo abhekisela kumabhentshimakhi e-PTP ngaphansi kwe-encapsulation ye-IPv4/UDP, kuyilapho ukufakwa kwemiyalezo ye-PTP yamagrafu angakwesokudla kuku-L2 (i-Ethernet eluhlaza). Ukusebenza kwesigqila se-PTP4l kufana ncamashi, ubukhulu be-master offset obubi kakhulu bungama-53 ns no-45 ns we-IPv4/UDP kanye ne-L2 encapsulation, ngokulandelana. Ukuchezuka okujwayelekile kwe-magnitude offset ngu-4.49 ns no-4.55 ns we-IPv4/UDP kanye ne-L2 encapsulation, ngokulandelanayo.
Ubukhulu be-Master Offset
Isibalo esilandelayo sibonisa ubukhulu be-master offset ngaphansi kwe-24 Gbps bidirectional traffic, IPv4 (kwesokunxele) kanye ne-L2 (kwesokudla) encapsulation, G8275.1 Profile.
IMean Path Delay (MPD)
Isibalo esilandelayo sibonisa ukubambezeleka kwendlela ye-Intel FPGA PAC N3000 ephethe isigqila se-PTP4l ngaphansi kwethrafikhi ye-bidirectional engu-24 Gbps, i-IPv4 (kwesokunxele) kanye ne-L2 (kwesokudla) encapsulation, G8275.1 Profile.
Amanani aphelele we-MPD ayiyona inkomba ecacile yokungaguquguquki kwe-PTP, njengoba kuncike kuzintambo zobude, ukubambezeleka kwendlela yedatha nokunye; kodwa-ke, ukubheka ukuhluka okuphansi kwe-MPD (2.381 ns kanye no-2.377 ns kwecala le-IPv4 kanye ne-L2, ngokulandelanayo) kwenza kube sobala ukuthi ukubala kwe-PTP MPD kunembile ngokuqhubekayo kukho konke kokubili okuhlanganisiwe. Iqinisekisa ukuvumelana kokusebenza kwe-PTP kuzo zonke izindlela ze-encapsulation. Ushintsho lweleveli ku-MPD ebaliwe kugrafu ye-L2 (kumfanekiso ongenhla, igrafu engakwesokudla) kungenxa yomphumela okhulayo wethrafikhi esetshenzisiwe. Okokuqala, isiteshi asisebenzi (i-MPD rms ingu-55.3 ns), bese kusetshenziswa ithrafikhi ye-ingress (isinyathelo sokukhuphuka sesibili, i-MPD rms ingu-85.44 ns), kulandelwa ukugeleza kwethrafikhi ngesikhathi esisodwa, okuholela ku-MPD ebaliwe engu-108.98 ns. Izibalo ezilandelayo zimboza ubukhulu be-master offset kanye ne-MPD ebaliwe yokuhlolwa kwethrafikhi eqondiswa kabili esetshenziswa kuzo zombili izigqila ze-PTP4l kusetshenziswa i-Intel FPGA PAC N3000 enomshini we-T-TC, kanye nakwenye esebenzisa i-Intel FPGA PACN3000 ngaphandle kwe-TC ukusebenza. Ukuhlolwa kwe-T-TC Intel FPGA PAC N3000 (okuwolintshi) kuqala kusukela ku-zero, kuyilapho ukuhlolwa kwe-PTP esebenzisa i-non-TC Intel FPGA PAC N3000 (eluhlaza okwesibhakabhaka) iqala cishe imizuzwana engu-T = 2300.
Ubukhulu be-Master Offset
Isibalo esilandelayo sibonisa ubukhulu be-master offset ngaphansi kwethrafikhi ye-Ingress (24 Gbps), ngosekelo lwe-TTC nangaphandle, G.8275.1 Profile.
Kulesi sibalo esingenhla, ukusebenza kwe-PTP kwe-Intel FPGA PAC N3000 ngaphansi kwethrafikhi enikwe amandla yi-TC kufana ne-non-TC Intel FPGA PAC N3000 imizuzwana yokuqala engu-2300. Ukusebenza komshini we-T-TC ku-Intel FPGA PAC N3000 kugqanyiswe engxenyeni yokuhlola (ngemuva kwesekhondi lama-2300) lapho kufakwa khona umthwalo olinganayo wethrafikhi ezindaweni zokusebenzelana zawo womabili amakhadi. Ngokufanayo esithombeni esingezansi, izibalo ze-MPD zibhekwa ngaphambi nangemva kokusebenzisa ithrafikhi esiteshini. Ukusebenza komshini we-T-TC kugqanyiswe ekunxephezeleni isikhathi sokuhlala samaphakethe okuyi-latency yephakethe ngokusebenzisa indlela ye-FPGA phakathi kwe-25G ne-40G MACs.
IMean Path Delay (MPD)
Isibalo esilandelayo sibonisa ukulibaziseka kwendlela ye-Intel FPGA PAC N3000 host PTP4l isigqila ngaphansi kwethrafikhi ye-Ingress (24 Gbps), ngosekelo lwe-T-TC nangaphandle, G.8275.1 Profile.
Lezi zibalo zibonisa i-algorithm ye-servo yesigqila se-PTP4l, ngenxa yokulungiswa kwesikhathi sokuhlala kwe-TC, sibona umehluko omncane ekubalweni kokulibaziseka kwendlela okumaphakathi. Ngakho-ke, umthelela wokuguquguquka kokulibaziseka ekulinganisweni kwe-master offset uyancishiswa. Ithebula elilandelayo libonisa ukuhlaziywa kwezibalo ekusebenzeni kwe-PTP, okuhlanganisa i-RMS kanye nokuchezuka okujwayelekile kwe-master offset, ukuchezuka okujwayelekile kokulibaziseka kwendlela emaphakathi, kanye ne-master offset embi kakhulu ye-Intel FPGA PAC N3000 ene-T nangaphandle kwayo Ukusekelwa kwe-TC.
Imininingwane Yezibalo Ngokusebenza Kwe-PTP Ngaphansi Kwethrafikhi Ye-Ingress
| I-Ingress Traffic (24Gbps) G.8275.1 PTP Profile | I-Intel FPGA PAC N3000 ene-T-TC | I-Intel FPGA PAC N3000 ngaphandle kwe-T-TC |
| I-RMS | 6.34 ns | 40.5 ns |
| I-StdDev (ye-abs(max) offset) | 3.65 ns | 15.5 ns |
| I-StdDev (ye-MPD) | 1.79 ns | 18.1 ns |
| I-offset ephezulu | 34 ns | 143 ns |
Ukuqhathanisa okuqondile kwe-Intel FPGA PAC N3000 esekelwa yi-TC nenguqulo engeyona eye-TC
Ibonisa ukuthi ukusebenza kwe-PTP kungaphansi ngo-4x ukuya ku-6x ngokuphathelene nanoma yisiphi izibalo
amamethrikhi (okubi kakhulu, i-RMS noma ukuchezuka okujwayelekile kwe-master offset). Icala elibi kakhulu
i-master offset yokucushwa kwe-G.8275.1 PTP ye-T-TC Intel FPGA PAC N3000 ingu-34
ns ngaphansi kwezimo zethrafikhi yokungena emkhawulweni womkhawulokudonsa wesiteshi (24.4Gbps).
I-lperf3 Ukuhlolwa Kwethrafikhi
Lesi sigaba sichaza ukuhlolwa kokulinganisa kwe-iperf3 kwethrafikhi ukuze kuqhutshekwe nokuhlola ukusebenza kwe-PTP kwe-Intel FPGA PAC N3000. Ithuluzi le-iperf3 lisetshenziselwa ukulingisa izimo zethrafikhi ezisebenzayo. I-topology yenethiwekhi ye-iperf3 ye-traffic benchmarks, eboniswe esithombeni esingezansi, ihlanganisa ukuxhumeka kwamaseva amabili, ngayinye isebenzisa ikhadi le-DUT (Intel FPGA PAC N3000 kanye ne-XXV710), kuswishi ye-Cisco Nexus 93180YC FX. Iswishi ye-Cisco isebenza njengewashi Lomngcele (T-BC) phakathi kwezigqila ezimbili ze-DUT PTP kanye ne-Calnex Paragon-NEO Grandmaster.
I-Network Topology ye-Intel FPGA PAC N3000 lperf3 Test Traffic
Okukhiphayo kwe-PTP4l kubasingathi be-DUT ngamunye kunikeza izilinganiso zedatha zokusebenza kwe-PTP kudivayisi ngayinye yesigqila ekusethweni (Intel FPGA PAC N3000 ne-XXV710). Ngokuhlolwa kwethrafikhi ye-iperf3, izimo ezilandelayo nokulungiselelwa kusebenza kuwo wonke amagrafu nokuhlaziywa kokusebenza:
- I-17 Gbps yomkhawulokudonsa ohlanganisiwe wethrafikhi (zombili i-TCP ne-UDP), iphuma noma ingene noma iqondise kabili ku-Intel FPGA PAC N3000.
- I-IPv4 encapsulation yamaphakethe e-PTP, ngenxa yomkhawulo wokucushwa kuswishi ye-Cisco Nexus 93180YC-FX.
- Izinga lokushintshisana komlayezo we-PTP likhawulelwe kumaphakethe angu-8/ngesekhondi, ngenxa yomkhawulo wokucushwa kuswishi ye-Cisco Nexus 93180YC-FX.
perf3 Umphumela Wokuhlolwa Kwethrafikhi
Ukuhlaziywa okulandelayo kuthwebula ukusebenza kwe-Intel FPGA PAC N3000 nekhadi le-XXV710, zombili ngesikhathi esisodwa zisebenza njengekhadi lenethiwekhi yezigqila ze-PTP (T-TSC) i-Calnex Paragon NEO Grandmaster ngokusebenzisa iswishi ye-T-BC Cisco.
Izibalo ezilandelayo zibonisa ubukhulu be-master offset kanye ne-MPD ngokuhamba kwesikhathi ezivivinyweni ezintathu ezahlukene zethrafikhi kusetshenziswa i-Intel FPGA PAC N3000 enekhadi le-T-TC ne-XXV710. Kuwo womabili amakhadi, ithrafikhi ye-bidirectional inomphumela omkhulu kakhulu ekusebenzeni kwe-PTP4l. Ubude besikhathi sokuhlolwa kwethrafikhi amahora angu-10 ubude. Kuzibalo ezilandelayo, umsila wegrafu uphawula iphuzu ngesikhathi lapho ithrafikhi ima khona futhi ubukhulu be-PTP master offset behlela kumazinga aphansi, ngenxa yeshaneli engenzi lutho.
Ubukhulu be-Master Offset ye-Intel FPGA PAC N3000
Isibalo esilandelayo sibonisa indlela yokulibaziseka emaphakathi ye-Intel FPGA PAC N3000 ene-T TC, ngaphansi kwe-ingress, egress kanye ne-bidirectional iperf3 traffic.
Mean Path Delay (MPD) ye-Intel FPGA PAC N3000
Isibalo esilandelayo sibonisa indlela yokulibaziseka emaphakathi ye-Intel FPGA PAC N3000 ene-T TC, ngaphansi kwe-ingress, egress kanye ne-bidirectional iperf3 traffic.
Ubukhulu be-Master Offset ye-XXV710
Isibalo esilandelayo sibonisa ubukhulu be-master offset ye-XXV710, ngaphansi kwe-ingress, i-egress kanye ne-bidirectional iperf3 traffic.
IMean Path Delay (MPD) ye-XXV710
Isibalo esilandelayo sibonisa indlela yokulibaziseka emaphakathi ye-XXV710, ngaphansi kwethrafikhi yokungena, i-egress kanye ne-bidirectional iperf3.
Mayelana nokusebenza kwe-Intel FPGA PAC N3000 PTP, i-master offset embi kakhulu ngaphansi kwanoma yisiphi isimo sethrafikhi ingaphakathi kwama-90 ns. Ngenkathi ingaphansi kwezimo zethrafikhi eziqondiswa kabili, i-RMS ye-Intel FPGA PAC N3000 master offset ingcono ngo-5.6x kunekhadi le-XXV710.
| I-Intel FPGA PAC N3000 | Ikhadi le-XXV710 | |||||
| I-Ingress Traffic10G | I-Egress Traffic 18G | Ithrafikhi ye-Bidirectional18G | I-Ingress Traffic18G | I-Egress Traffic 10G | Ithrafikhi ye-Bidirectional18G | |
| I-RMS | 27.6 ns | 14.2 ns | 27.2 ns | 93.96 ns | 164.2 ns | 154.7 ns |
| I-StdDev(ye-abs(max) offset) | 9.8 ns | 8.7 ns | 14.6 ns | 61.2 ns | 123.8 ns | 100 ns |
| I-StdDev (ye-MPD) | 21.6 ns | 9.2 ns | 20.6 ns | 55.58 ns | 55.3 ns | 75.9 ns |
| I-offset ephezulu | 84 ns | 62 ns | 90 ns | 474 ns | 1,106 ns | 958 ns |
Ngokuphawulekayo, i-master offset ye-Intel FPGA PAC N3000 inokuphambuka okujwayelekile okuphansi,
okungenani izikhathi ezi-5 ngaphansi kwekhadi le-XXV710, kusho ukuthi ukuqagela kwe-PTP
Iwashi le-Grandmaster alizweli kancane ekubambezelekeni noma ezinhlobonhlobo zomsindo ngaphansi kwethrafikhi ku-
I-Intel FPGA PAC N3000.
Uma kuqhathaniswa nomphumela wokuhlolwa kwethrafikhi we-IXIA ekhasini lesi-5, ubukhulu becala elibi kakhulu
i-master offset ene-T-TC enikwe amandla i-Intel FPGA PAC N3000 ibonakala iphakeme. Ngaphandle kwalokho
umehluko we-topology yenethiwekhi kanye nomkhawulokudonsa wesiteshi, lokhu kungenxa ye-Intel
I-FPGA PAC N3000 ithwetshulwa ngaphansi kwe-G.8275.1 PTP profile (16 Hz isilinganiso sokuvumelanisa), ngenkathi
izinga lomlayezo wokuvumelanisa kuleli cala livinjelwe kumaphakethe angu-8 ngomzuzwana.
Ubukhulu bokuqhathaniswa kwe-Master Offset
Isibalo esilandelayo sibonisa ubukhulu bokuqhathaniswa kwe-master offset ngaphansi kwethrafikhi ye-iperf3 ephindwe kabili.
IMean Path Delay (MPD) Ukuqhathanisa
Isibalo esilandelayo sibonisa ukuqhathaniswa kwendlela yokulibaziseka emaphakathi ngaphansi kwethrafikhi ye-iperf3 eqondiswa kabili.
Ukusebenza okuphakeme kwe-PTP kwe-Intel FPGA PAC N3000, uma kuqhathaniswa nekhadi le-XXV710, nakho kusekelwa ukuchezuka okuphezulu okubonakalayo kokulibaziseka kwendlela ebaliwe (MPD) ye-XXV710 kanye ne-Intel FPGA PAC N3000 kusivivinyo ngasinye sethrafikhi eqondisiwe, isbample bidirectional iperf3 traffic. Ziba inani elimaphakathi kukesi ngalinye le-MPD, elingahluka ngenxa yezizathu ezimbalwa, njengamakhebuli e-Ethernet ahlukene kanye nokubambezeleka okuyisisekelo okuhlukile. Umehluko oboniwe kanye ne-spike kumanani wekhadi le-XXV710 akukho ku-Intel FPGA PAC N3000.
I-RMS yokuqhathanisa okungu-8 okulandelanayo okuyi-Master Offset
Isiphetho
Umzila wedatha we-FPGA phakathi kwe-QSFP28 (25G MAC) ne-Intel XL710 (40G MAC) yengeza ukubambezeleka kwephakethe okuguquguqukayo okuthinta ukunemba kokunemba kwe-PTP Slave. Ukwengeza usekelo lwewashi elisobala (i-T-TC) ku-FPGA ethambile ye-Intel FPGA PAC N3000 kunikeza isinxephezelo salokhu ukubambezeleka kwaleli phakethe ngokufaka isikhathi salo sokuhlala emkhakheni wokulungisa wemilayezo ye-PTP ehlanganisiwe. Imiphumela iqinisekisa ukuthi indlela ye-T-TC ithuthukisa ukusebenza ngokunemba kwesigqila se-PTP4l.
Futhi, Umphumela Wokuhlolwa Kwethrafikhi we-IXIA ekhasini lesi-5 ubonisa ukuthi ukusekelwa kwe-T-TC kumzila wedatha we-FPGA kuthuthukisa ukusebenza kwe-PTP okungenani okungu-4x, uma kuqhathaniswa ne-Intel FPGA PAC N3000 ngaphandle kokusekelwa kwe-T-TC. I-Intel FPGA PAC N3000 ene-T-TC iveza i-master offset yesimo esibi kakhulu engu-53 ns ngaphansi kwemithwalo yethrafikhi yokungena, e-egress noma eqondiswa kabili emkhawulweni womthamo wesiteshi (25 Gbps). Ngakho-ke, ngokusekelwa kwe-T-TC, ukusebenza kwe-Intel FPGA PAC N3000 PTP kokubili kunembe kakhudlwana futhi akuthambekele ekuhlukeni komsindo.
Kuhlolo Lwethrafikhi lwe-lperf3 ekhasini le-10, ukusebenza kwe-PTP kwe-Intel FPGA PAC N3000 ene-T-TC enikwe amandla kuqhathaniswa nekhadi le-XXV710. Lokhu kuhlola kuthwebule idatha ye-PTP4l yawo womabili amawashi ezigqila ngaphansi kwethrafikhi ye-ingress noma ye-egress eshintshwa phakathi kwabaphathi ababili be-Intel FPGA PAC N3000 nekhadi le-XXV710. I-master offset embi kakhulu ebonwe ku-Intel FPGA PAC N3000 okungenani ingaphansi ngo-5x kunekhadi le-XXV710. Futhi, ukuchezuka okujwayelekile kwama-offsets athunjiwe kufakazela nokuthi ukusekelwa kwe-T-TC kwe-Intel FPGA PAC N3000 kuvumela ukuqagela okushelelayo kwewashi le-Grandmaster.
Ukuze uqhubeke nokuqinisekisa ukusebenza kwe-PTP kwe-Intel FPGA PAC N3000, izinketho zokuhlola ezingaba khona zifaka:
- Ukuqinisekisa ngaphansi kwe-PTP pro ehlukilefiles kanye namazinga omlayezo wezixhumanisi ze-Ethernet ezingaphezu kweyodwa.
- Ukuhlolwa Kokuhlolwa Kwethrafikhi kwe-lperf3 ekhasini le-10 ngeswishi ethuthuke kakhulu evumela amazinga aphezulu emiyalezo ye-PTP.
- Ukuhlolwa kokusebenza kwe-T-SC kanye nokunemba kwayo kwesikhathi se-PTP ngaphansi kokuhlolwa kokuvumelana kwe-G.8273.2.
Umlando Wokubuyekezwa Kombhalo Wokuhlolwa kwe-IEEE 1588 V2
| Idokhumenti Inguqulo | Izinguquko |
| 2020.05.30 | Ukukhishwa kokuqala. |
Amadokhumenti / Izinsiza
 |
Intel FPGA Programmable Acceleration Card N3000 [pdf] Umhlahlandlela Womsebenzisi I-FPGA Programmable Acceleration Card, N3000, Programmable Acceleration Card N3000, FPGA Programmable Acceleration Card N3000, FPGA, IEEE 1588 V2 Test |
