intel FPGA Programmable Acceleration Card N3000 User Guide

Hoʻolauna

Kāpae

Pono ka Intel FPGA Programmable Acceleration Card N3000 i loko o kahi kikowaena radio access network (vRAN) i kākoʻo no ka IEEE1588v2 ma ke ʻano he Precision Time Protocol (PTP) Telecom Slave Clock (T-TSC) e hoʻonohonoho pono i nā hana lako polokalamu. Hāʻawi ka Intel Ethernet Controller XL710 ma Intel® FPGA PAC N3000 i ke kākoʻo IEEE1588v2. Eia nō naʻe, hoʻokomo ka ala ʻikepili FPGA i ka jitter e pili ana i ka hana PTP. ʻO ka hoʻohui ʻana i kahi kaapuni māmā (T-TC) e hiki ai i ka Intel FPGA PAC N3000 ke hoʻopaʻi no kāna latency kūloko FPGA a hoʻēmi i nā hopena o ka jitter, e hiki ai i ka T-TSC ke hoʻohālikelike i ka manawa o ka Grandmaster's Time of Day (ToD).

Pahuhopu

Hōʻoia kēia mau ho'āʻo i ka hoʻohana ʻana o Intel FPGA PAC N3000 ma ke ʻano he kauā IEEE1588v2 ma Open Radio Access Network (O-RAN). Hōʻike kēia palapala:

• Hoʻonohonoho hoʻāʻo
• Kaʻina hōʻoia
• Ka loiloi hana o ka mīkini uaki akaka ma ke ala FPGA o Intel FPGA PAC N3000
• ʻO ka hana PTP o ka Intel FPGA PAC N3000 ʻO ka hana a ka Intel FPGA PAC N3000 e kākoʻo ana i ka uaki akaka.
  i hoʻohālikelike ʻia me ka Intel FPGA PAC N3000 me ka ʻole o ka uaki akaka a me kahi kāleka Ethernet ʻē aʻe XXV710 ma lalo o nā kūlana kaʻa a me nā hoʻonohonoho PTP.

Nā hiʻohiʻona a me nā palena

ʻO nā hiʻohiʻona a me nā palena hōʻoia no ke kākoʻo Intel FPGA PAC N3000 IEEE1588v2 penei:

• Hoʻohana ʻia ka waihona polokalamu: Linux PTP Project (PTP4l)
• Kākoʻo i ka polokalamu kelepona aʻefiles:
  •  1588v2 (paʻamau)
  • ʻO G.8265.1
  • ʻO G.8275.1
• Kākoʻo i ka uaki kauā PTP ʻelua.

Huina Intel. Ua mālama ʻia nā kuleana āpau. ʻO Intel, ka Intel logo, a me nā hōʻailona Intel ʻē aʻe he mau hōʻailona o Intel Corporation a i ʻole kāna mau lālā. Mālama ʻo Intel i ka hana o kāna mau huahana FPGA a me semiconductor i nā kikoʻī o kēia manawa e like me ka palapala hōʻoia maʻamau o Intel, akā aia ke kuleana e hoʻololi i nā huahana a me nā lawelawe i kēlā me kēia manawa me ka ʻole o ka hoʻolaha. ʻAʻole ʻo Intel i kuleana a i ʻole kuleana e puka mai ana mai ka noi a i ʻole ka hoʻohana ʻana i kekahi ʻike, huahana, a i ʻole lawelawe i wehewehe ʻia ma ʻaneʻi koe wale nō i ʻae ʻia ma ke kākau ʻana e Intel. Manaʻo ʻia nā mea kūʻai aku Intel e loaʻa i ka mana hou o nā kikoʻī o nā hāmeʻa ma mua o ka hilinaʻi ʻana i kekahi ʻike i paʻi ʻia a ma mua o ke kau ʻana i nā kauoha no nā huahana a i ʻole nā ​​​​lawelawe. * Hiki ke koi ʻia nā inoa a me nā hōʻailona ʻē aʻe ma ke ʻano he waiwai o nā poʻe ʻē aʻe.

• Kākoʻo i ke ʻano multicast hope-to-end.
• Kākoʻo ʻo PTP me ka alapine hoʻololi a hiki i 128 Hz.
  • He palena kēia o ka hoʻolālā hōʻoia a me Grandmaster hoʻohana. Hiki i nā hoʻonohonoho PTP ke kiʻekiʻe ma mua o 128 mau ʻeke i kēlā me kēia kekona no nā memo PTP.
• Ma muli o nā palena o ka Cisco* Nexus* 93180YC-FX hoʻololi i hoʻohana ʻia i ka hoʻonohonoho hōʻoia, ʻo nā hopena hana ma lalo o nā kūlana kaʻa iperf3 e pili ana i ka helu hoʻololi o ka memo PTP o 8 Hz.
• Kākoʻo encapsulation:
  • Ka lawe ʻana ma luna o L2 (Ethernet raw) a me L3 (UDP/IPv4/IPv6)
    Nānā: Ma kēia palapala, hoʻohana nā hualoaʻa a pau i hoʻokahi loulou Ethernet 25Gbps.

Nā mea hana a me nā mea hoʻokele

Mea hana	Manao
BIOS	Papa Server Intel S2600WF 00.01.0013
OS	CentOS 7.6
Kino	kernel-rt-3.10.0-693.2.2.rt56.623.el7.src.
ʻIkepili Hoʻolālā Plane Development Kit (DPDK)	18.08
Intel C Compiler	19.0.3
Keaukaha Intel XL710 (mea hoʻokele i40e)	2.8.432.9.21
PTP4l	2.0
IxExplorer	8.51.1800.7 EA-Patch1
lperf3	3.0.11
trafgen	Netsniff-ng 0.6.6 Mea hana

 IXIA Hoao Kaapuni

Hoʻohana ka pūʻulu mua o nā hōʻailona hana PTP no Intel FPGA PAC N3000 i kahi hoʻonā IXIA* no ka hoʻāʻo ʻana i ka pūnaewele a me ka PTP conformance. Aia ka pahu chassis IXIA XGS2 i kahi kāleka IXIA 40 PORT NOVUS-R100GE8Q28 a me IxExplorer e hāʻawi ana i kahi kiʻi kiʻi no ka hoʻonohonoho ʻana i kahi PTP Grandmaster virtual i ka DUT (Intel FPGA PAC N3000) ma luna o kahi pilina Ethernet pololei 25 Gbps. Hōʻike ʻia ke kiʻikuhi poloka ma lalo nei i ka topology hoʻāʻo i manaʻo ʻia no nā pae kuhikuhi IXIA. Hoʻohana nā hualoaʻa a pau i nā kaʻa i hana ʻia e IXIA no ka hoʻāʻo ʻana i ke kaʻa kaʻa a hoʻohana i ka mea hana trafgen ma ka host Intel FPGA PAC N3000 no nā hoʻokolohua egress traffic, kahi e kū mau ai ka ʻaoʻao komo a i ʻole ka egress mai ka manaʻo o ka DUT (Intel FPGA PAC N3000 ) hoʻokipa. I nā hihia ʻelua, ʻo 24 Gbps ka awelika o ka holo kaʻa. Hāʻawi kēia hoʻonohonoho hoʻāʻo i kahi hōʻike kumu o ka hana PTP o Intel FPGA PAC N3000 me ka mīkini T-TC i hoʻohana ʻia, a me ka hoʻohālikelike ʻana i ke kiʻi hale hana non-TC Intel FPGA PAC N3000 ma lalo o ka ITU-T G.8275.1 PTP profile.

Topology no ka Intel FPGA PAC N3000 Nā hoʻāʻo ʻana ma lalo o IXIA Virtual Grandmaster

IXIA Ka hopena hoao

Hoʻopaʻa ʻia ka ʻikepili ma lalo nei i ka hana PTP o ka Intel FPGA PAC N3000 i hoʻohana ʻia e TC ma lalo o nā kūlana kaʻa komo a puka. Ma kēia ʻāpana, ʻo ka PTP profile Ua ʻae ʻia ʻo G.8275.1 no nā hoʻāʻo kaʻa a me ka hōʻiliʻili ʻikepili.

Ka nui o Master Offset

Hōʻike ka helu ma lalo nei i ka nui o ka master offset i ʻike ʻia e ka mea kūʻai aku PTP4l o ka host Intel FPGA PAC N3000 ma ke ʻano he hana o ka manawa i hala ma lalo o ke komo ʻana, egress a me ka bidirectional traffic (average throughput of 24.4Gbps).

Hoʻopaneʻe Ala Kūlana (MPD)

Hōʻike ke kiʻi ma lalo nei i ka lohi o ke ala, e like me ka helu ʻana e ke kauā PTP4 e hoʻohana ana i ka Intel FPGA PAC N3000 ma ke ʻano he kāleka kikowaena pūnaewele, no ka hoʻāʻo like me ka helu ma luna. ʻO ka lōʻihi o kēlā me kēia o nā hoʻokolohua ʻekolu he 16 mau hola.

Hōʻike ka papa ʻaina i ka ʻikepili helu o nā hoʻokolohua ʻekolu. Ma lalo o ke kaʻa kaʻa kokoke i ka mana o ke kahawai, ke kauā PTP4l e hoʻohana ana i ka Intel FPGA PAC N3000 e hoʻomau i ka hoʻokaʻawale ʻana i kona pae i ka IXIA's virtual grandmaster i loko o 53 ns no nā hoʻāʻo kaʻa a pau. Eia kekahi, ʻo ka deviation maʻamau o ka master offset magnitude ma lalo o 5 ns.

Nā kikoʻī helu no ka hana PTP

G.8275.1 PTP Profile	Ke Kaʻa Kaʻa Ingress (24Gbps)	Kaʻa Puka (24Gbps)	Kaʻahele ʻelua (24Gbps)
RMS	6.35 ns	8.4 ns	9.2 ns
StdDev (o abs(max) offset)	3.68 ns	3.78 ns	4.5 ns
StdDev (o MPD)	1.78 ns	2.1 ns	2.38 ns
ʻO ka ʻoi loa	36 ns	33 ns	53 ns

 

Hōʻike nā kiʻi ma lalo nei i ka nui o ka master offset a me ka mean path delay (MPD), ma lalo o 16-hola lōʻihi 24 Gbps bidirectional traffic test no nā PTP encapsulations like ʻole. ʻO nā kiʻi hema i kēia mau kiʻi e pili ana i nā pae PTP ma lalo o IPv4/UDP encapsulation, aʻo ka PTP messaging encapsulation o nā kiʻi pololei ma L2 (raw Ethernet). Ua like like ka hana kauā PTP4l, ʻo ka nui o ka master offset magnitude he 53 ns a me 45 ns no IPv4/UDP a me L2 encapsulation, kēlā me kēia. ʻO ka hoʻokaʻawale maʻamau o ka magnitude offset ʻo 4.49 ns a me 4.55 ns no IPv4/UDP a me L2 encapsulation.

Ka nui o Master Offset

Hōʻike ka kiʻi ma lalo nei i ka nui o ka master offset ma lalo o 24 Gbps bidirectional traffic, IPv4 (hema) a me L2 ('ākau) encapsulation, G8275.1 Profile.

Hoʻopaneʻe Ala Kūlana (MPD)

Hōʻike ke kiʻi ma lalo nei i ke ala lōʻihi o ke kauā ʻo Intel FPGA PAC N3000 host PTP4l ma lalo o 24 Gbps bidirectional traffic, IPv4 (hema) a me L2 (ʻākau) encapsulation, G8275.1 Profile.

ʻAʻole i hōʻike maopopo ʻia nā waiwai paʻa o ka MPD i ka kūlike o ka PTP, no ka mea, pili ia i nā kaula lōʻihi, latency ala ʻikepili a pēlā aku; akā naʻe, ʻo ka nānā ʻana i nā ʻano like ʻole MPD haʻahaʻa (2.381 ns a me 2.377 ns no ka hihia IPv4 a me L2, ʻo ia hoʻi) ʻike maopopo ʻia ka pololei o ka helu ʻana o ka PTP MPD ma nā encapsulation ʻelua. Hōʻoia i ka kūlike o ka hana PTP ma nā ʻano encapsulation ʻelua. ʻO ka hoʻololi ʻana o ka pae i ka MPD i helu ʻia ma ka pakuhi L2 (ma ke kiʻi ma luna, ka pakuhi ʻākau) ma muli o ka hopena hoʻonui o ke kaʻa i noi ʻia. ʻO ka mea mua, ʻaʻohe o ke kahawai (MPD rms he 55.3 ns), a laila hoʻohana ʻia ke kaʻa o ke komo ʻana (ka ʻanuʻu hoʻonui ʻelua, ʻo MPD rms he 85.44 ns), a ukali ʻia e ka huakaʻi egress like, e hopena i kahi MPD helu ʻia o 108.98 ns. Hoʻopili nā kiʻi ma lalo nei i ka nui o ka master offset a me ka MPD i helu ʻia o ka hoʻokolohua bidirectional traffic test i hoʻohana ʻia i kahi kauā PTP4l e hoʻohana ana i ka Intel FPGA PAC N3000 me T-TC mechanical, a me kekahi e hoʻohana ana i ka Intel FPGA PACN3000 me ka ʻole o TC hana hana. Hoʻomaka nā hoʻāʻo T-TC Intel FPGA PAC N3000 (ʻalani) mai ka manawa ʻole, aʻo ka hoʻāʻo PTP e hoʻohana ana i ka TC Intel FPGA PAC N3000 (uliuli) e hoʻomaka a puni T = 2300 kekona.

Ka nui o Master Offset

Hōʻike ke kiʻi ma lalo nei i ka nui o ka haku offset ma lalo o Ingress traffic (24 Gbps), me ke kākoʻo ʻole o TTC, G.8275.1 Profile.

Ma ka helu i luna, ua like ka hana PTP o ka Intel FPGA PAC N3000 i hoʻohana ʻia e TC ma lalo o ke kaʻa me ka Intel FPGA PAC N3000 non-TC no nā kekona 2300 mua. Hōʻike ʻia ka maikaʻi o ka mīkini T-TC ma Intel FPGA PAC N3000 i ka ʻāpana o ka hoʻāʻo (ma hope o ka 2300th kekona) kahi i hoʻopili ʻia ai ka ukana kaʻa like i nā loulou o nā kāleka ʻelua. Ma ke kiʻi ma lalo nei, ʻike ʻia nā helu MPD ma mua a ma hope o ka hoʻohana ʻana i ke kaʻa ma ke kahawai. Hōʻike ʻia ka maikaʻi o ka mīkini T-TC i ka uku ʻana i ka manawa noho o nā ʻeke, ʻo ia ka latency packet ma ke ala FPGA ma waena o 25G a me 40G MAC.

Hoʻopaneʻe Ala Kūlana (MPD)

Hōʻike kēia kiʻi i ke ala lōʻihi o ke kauā ʻo Intel FPGA PAC N3000 host PTP4l ma lalo o Ingress traffic (24 Gbps), me ke kākoʻo ʻole o T-TC, G.8275.1 Pro.file.

Hōʻike kēia mau kiʻi i ka algorithm servo o ke kauā PTP4l, ma muli o ka hoʻoponopono ʻana i ka manawa noho o ka TC, ʻike mākou i nā ʻokoʻa liʻiliʻi i ka helu ʻana o ke ala awelika. No laila, hoʻemi ʻia ka hopena o ka hoʻopaneʻe ʻana i ka master offset approximation. Hōʻike ka papa ma lalo nei i ka ʻikepili helu ma ka hana PTP, ʻo ia hoʻi ka RMS a me ka deviation maʻamau o ka master offset, ka ʻokoʻa maʻamau o ke ala lohi mean, a me ka master offset ʻino loa no ka Intel FPGA PAC N3000 me ka T- Kākoʻo TC.

Nā kikoʻī helu no ka hana PTP ma lalo o ke kaʻa ʻana o Ingress

Ke Kaʻa Kaʻa Ingress (24Gbps) G.8275.1 PTP Profile	Intel FPGA PAC N3000 me T-TC	Intel FPGA PAC N3000 me ka ʻole o T-TC
RMS	6.34 ns	40.5 ns
StdDev (o abs(max) offset)	3.65 ns	15.5 ns
StdDev (o MPD)	1.79 ns	18.1 ns
ʻO ka ʻoi loa	34 ns	143 ns

ʻO kahi hoʻohālikelike pololei i ka Intel FPGA PAC N3000 i kākoʻo ʻia e TC i ka mana non-TC
Hōʻike i ka hana PTP he 4x a 6x haʻahaʻa e pili ana i kekahi o nā helu helu
metrics (ʻino loa, RMS a i ʻole ka hoʻokaʻawale maʻamau o master offset). ʻO ka hihia ʻino loa
haku offset no ka G.8275.1 PTP hoʻonohonoho o T-TC Intel FPGA PAC N3000 he 34
ns ma lalo o nā kūlana kaʻa kaʻa ma ka palena o ka bandwidth channel (24.4Gbps).

lperf3 Hoao Kaahele

Hōʻike kēia ʻāpana i ka hoʻāʻo ʻana i ka iperf3 traffic benchmarking e loiloi hou i ka hana PTP o ka Intel FPGA PAC N3000. Ua hoʻohana ʻia ka mea hana iperf3 e hoʻohālikelike i nā kūlana kaʻa kaʻa. ʻO ka topology pūnaewele o nā mākaʻikaʻi iperf3 traffic, i hōʻike ʻia ma ke kiʻi ma lalo nei, pili i ka pilina o ʻelua mau kikowaena, kēlā me kēia me ka hoʻohana ʻana i kahi kāleka DUT (Intel FPGA PAC N3000 a me XXV710), i ka Cisco Nexus 93180YC FX hoʻololi. Hana ʻia ka Cisco switch ma ke ʻano he Boundary Clock (T-BC) ma waena o nā kauā DUT PTP ʻelua a me ka Calnex Paragon-NEO Grandmaster.

Topology Pūnaewele no Intel FPGA PAC N3000 lperf3 Ho'āʻo Kālepa

Hāʻawi ka PTP4l puka ma kēlā me kēia o nā pūʻali DUT i nā ana ʻikepili o ka hana PTP no kēlā me kēia mea kauā i ka hoʻonohonoho (Intel FPGA PAC N3000 a me XXV710). No ka hoʻāʻo ʻana i ka iperf3, pili nā kūlana a me nā hoʻonohonoho i nā kiʻi āpau a me ka nānā ʻana i ka hana.

• ʻO 17 Gbps ka bandwidth hōʻuluʻulu o nā kaʻa (ʻo TCP a me UDP), i ka puka a i ʻole ke komo ʻana a i ʻole bidirectional i Intel FPGA PAC N3000.
• ʻO IPv4 encapsulation o nā ʻeke PTP, ma muli o ka palena hoʻonohonoho ma ka Cisco Nexus 93180YC-FX hoʻololi.
• Ua kaupalena ʻia ka helu hoʻololi o ka memo PTP i 8 packets/second, ma muli o ka palena hoʻonohonoho i ka hoʻololi Cisco Nexus 93180YC-FX.

perf3 Ka hopena ho'āʻo

Hoʻopaʻa ʻia ka ʻikepili aʻe i ka hana o ka kāleka Intel FPGA PAC N3000 a me XXV710, i ka manawa like e hana like me ke kāleka kikowaena pūnaewele o nā kauā PTP (T-TSC) ka Calnex Paragon NEO Grandmaster ma o ka T-BC Cisco hoʻololi.

Hōʻike nā kiʻi ma lalo nei i ka nui o ka master offset a me ka MPD i ka manawa no nā hoʻokolohua kaʻa like ʻole ʻekolu e hoʻohana ana i ka Intel FPGA PAC N3000 me ke kāleka T-TC a me XXV710. Ma nā kāleka ʻelua, ʻoi aku ka nui o ka hopena bidirectional i ka hana PTP4l. He 10 mau hola ka lōʻihi o ka hoʻāʻo kaʻa. Ma nā kiʻi ma lalo nei, hōʻailona ka huelo o ka pakuhi i kahi kiko i ka manawa e kū ai ke kaʻa a iho ka nui o ka hoʻoneʻe master PTP i kona mau pae haʻahaʻa, ma muli o ke kahawai palaualelo.

Ka nui o Master Offset no Intel FPGA PAC N3000

Hōʻike ke kiʻi ma lalo nei i ke ala lōʻihi no Intel FPGA PAC N3000 me T TC, ma lalo o ke komo ʻana, egress a me ka bidirectional iperf3 traffic.

Hoʻopaneʻe ʻo Mean Path (MPD) no Intel FPGA PAC N3000

Hōʻike ke kiʻi ma lalo nei i ke ala lōʻihi no Intel FPGA PAC N3000 me T TC, ma lalo o ke komo ʻana, egress a me ka bidirectional iperf3 traffic.

Ka nui o Master Offset no XXV710

Hōʻike kēia kiʻi ma lalo nei i ka nui o ka master offset no XXV710, ma lalo o ke komo ʻana, egress a me bidirectional iperf3 traffic.

Hoʻopaneʻe ʻo Mean Path (MPD) no XXV710

Hōʻike ke kiʻi ma lalo nei i ke ala lōʻihi no ka XXV710, ma lalo o ke komo ʻana, puka a me ka huakaʻi iperf3 bidirectional.

E pili ana i ka hana ʻo Intel FPGA PAC N3000 PTP, ʻo ka master offset ʻino loa ma lalo o kekahi kūlana kaʻa i loko o 90 ns. ʻOiai ma lalo o nā kūlana kalepa bidirectional like, ʻo ka RMS o ka Intel FPGA PAC N3000 master offset he 5.6x ʻoi aku ka maikaʻi ma mua o ka kāleka XXV710.

	Intel FPGA PAC N3000			Kāleka XXV710
	Kaʻahele Ingress10G	Egress Traffic 18G	Kaʻahele ʻelua18G	Kaʻahele Ingress18G	Egress Traffic 10G	Kaʻahele ʻelua18G
RMS	27.6 ns	14.2 ns	27.2 ns	93.96 ns	164.2 ns	154.7 ns
StdDev(o abs(max) offset)	9.8 ns	8.7 ns	14.6 ns	61.2 ns	123.8 ns	100 ns
StdDev (o MPD)	21.6 ns	9.2 ns	20.6 ns	55.58 ns	55.3 ns	75.9 ns
ʻO ka ʻoi loa	84 ns	62 ns	90 ns	474 ns	1,106 ns	958 ns

ʻO ka mea nui, ʻo ka master offset o ka Intel FPGA PAC N3000 he haʻahaʻa haʻahaʻa haʻahaʻa,
ma ka liʻiliʻi he 5x ka liʻiliʻi ma mua o ke kāleka XXV710, e hōʻike ana i ka pili PTP o ka
ʻAʻole maʻalahi ka uaki Grandmaster i ka latency a i ʻole ka leo ʻokoʻa ma lalo o ke kaʻa i ka
Intel FPGA PAC N3000.
Ke hoʻohālikelike ʻia me ka IXIA Traffic Test Result ma ka ʻaoʻao 5, ʻo ka nui o ka hihia ʻino loa.
ʻoi aku ka kiʻekiʻe o ka master offset me kahi T-TC i hiki iā Intel FPGA PAC N3000. Ma waho aʻe
nā ʻokoʻa o ka topology pūnaewele a me nā bandwidth channel, no ka Intel
Hopu ʻia ʻo FPGA PAC N3000 ma lalo o kahi G.8275.1 PTP profile (16 Hz sync rate), ʻoiai
ʻO ka helu leka uila i kēia hihia ua kāohi ʻia ma 8 mau ʻeke i kēlā me kēia kekona.

Ka nui o ka hoʻohālikelike hoʻohālikelike kumu

Hōʻike ke kiʻi ma lalo nei i ka nui o ka hoʻohālikelike hoʻohālikelike master ma lalo o ka huakaʻi bidirectional iperf3.

Hoʻohālikelike Mean Path Delay (MPD).

Hōʻike ke kiʻi ma lalo nei i ka hoʻohālikelike ʻana o ke ala lohi ma lalo o ka huakaʻi bidirectional iperf3.

ʻO ka hana PTP maikaʻi loa o ka Intel FPGA PAC N3000, ke hoʻohālikelike ʻia me ke kāleka XXV710, kākoʻo pū ʻia e ka ʻokoʻa kiʻekiʻe o ka hoʻopaneʻe ʻana o ke ala mean ala (MPD) i helu ʻia no XXV710 a me Intel FPGA PAC N3000 i kēlā me kēia o ka hoʻāʻo ʻana i ke kaʻa. example bidirectional iperf3 traffic. E haʻalele i ke kumu waiwai i kēlā me kēia hihia MPD, hiki ke ʻokoʻa ma muli o nā kumu he nui, e like me nā kaula Ethernet ʻokoʻa a me nā latency core ʻokoʻa. ʻAʻole i loaʻa i ka Intel FPGA PAC N710 ka ʻokoʻa ʻike a me ka spike i nā waiwai no ka kāleka XXV3000.

RMS o 8 Kumu Hoʻohālikelike Hoʻohālikelike

Ka hopena

ʻO ke ala ʻikepili FPGA ma waena o QSFP28 (25G MAC) a me Intel XL710 (40G MAC) hoʻohui i kahi latency packet loli e pili ana i ka pololei o ka PTP Slave. ʻO ka hoʻohui ʻana i ke kākoʻo ʻo Transparent Clock (T-TC) i loko o ka FPGA soft logic o Intel FPGA PAC N3000 e hāʻawi i ka uku no kēia latency packet ma ka hoʻopili ʻana i kona manawa noho ma ke kahua hoʻoponopono o nā memo PTP encapsulated. Hōʻoia nā hopena e hoʻomaikaʻi ka mīkini T-TC i ka hana pololei o ke kauā PTP4l.

Eia kekahi, ʻo ka IXIA Traffic Test Result ma ka ʻaoʻao 5 e hōʻike ana i ke kākoʻo T-TC i ke ala ʻikepili FPGA e hoʻonui i ka hana PTP ma ka liʻiliʻi 4x, ke hoʻohālikelike ʻia me ka Intel FPGA PAC N3000 me ke kākoʻo ʻole o T-TC. Hāʻawi ka Intel FPGA PAC N3000 me T-TC i kahi master offset ʻino loa o 53 ns ma lalo o ke komo ʻana, egress a i ʻole nā ​​​​huakaʻi bidirectional ma ka palena o ka hiki ke kahawai (25 Gbps). No laila, me ke kākoʻo T-TC, ʻoi aku ka pololei o ka hana ʻo Intel FPGA PAC N3000 PTP a ʻoi aku ka liʻiliʻi o nā ʻano leo.

Ma lperf3 Traffic Test ma ka ʻaoʻao 10, hoʻohālikelike ʻia ka hana PTP o ka Intel FPGA PAC N3000 me T-TC me kahi kāleka XXV710. Ua kiʻi kēia hoʻāʻo i ka ʻikepili PTP4l no nā uaki kauā ʻelua ma lalo o ke komo ʻana a i ʻole ka puka puka i hoʻololi ʻia ma waena o nā pūʻali ʻelua o Intel FPGA PAC N3000 a me XXV710 kāleka. ʻO ka master offset ʻino loa i ʻike ʻia ma ka Intel FPGA PAC N3000 ma kahi o 5x haʻahaʻa ma mua o ke kāleka XXV710. Eia kekahi, ʻo ka ʻokoʻa maʻamau o nā offset i hoʻopaʻa ʻia e hōʻike ana i ke kākoʻo T-TC o Intel FPGA PAC N3000 e hiki ai ke hoʻohālikelike ʻia i ka uaki o Grandmaster.

No ka hōʻoia hou ʻana i ka hana PTP o Intel FPGA PAC N3000, nā koho hoʻāʻo hiki ke komo:

• ʻO ka hōʻoia ma lalo o nā PTP pro like ʻolefiles a me nā leka uila no nā loulou Ethernet ʻoi aku ma mua o hoʻokahi.
• Ka loiloi o lperf3 Traffic Test ma ka ʻaoʻao 10 me kahi hoʻololi kiʻekiʻe e hiki ai ke kiʻekiʻe aʻe nā helu memo PTP.
• Ka loiloi o ka hana T-SC a me ka pololei o ka manawa PTP ma lalo o G.8273.2 Ho'āʻo Conformance.

Moʻolelo Hoʻoponopono No ka IEEE 1588 V2 Hōʻike

 

Palapala Manao	Nā hoʻololi
2020.05.30	Hoʻokuʻu mua.

 

Palapala / Punawai

intel FPGA Programmable Acceleration Card N3000 [pdf] Ke alakaʻi hoʻohana FPGA Kāleka Hoʻoikaika Hoʻolalelale, N3000, Kāleka Hoʻolalelale Polokalamu N3000, Kāleka Hoʻolalelale Polokalamu FPGA N3000, FPGA, IEEE 1588 V2 Hōʻike.

Nā kuhikuhi

• Palapala Hoʻohana