intel FPGA Programmable Acceleration Card N3000 Jagoran mai amfani

Gabatarwa

Fage

Katin Haɓakawa na Shirin Intel FPGA N3000 a cikin hanyar sadarwar samun damar rediyo mai ƙima (vRAN) yana buƙatar goyan baya ga IEEE1588v2 azaman ƙayyadaddun ƙa'idar Lokaci (PTP) Telecom Slave Clocks (T-TSC) don tsara ayyukan software daidai. Mai sarrafa Intel Ethernet XL710 a cikin Intel® FPGA PAC N3000 yana ba da tallafin IEEE1588v2. Koyaya, hanyar bayanan FPGA tana gabatar da jitter wanda ke shafar aikin PTP. Ƙara da'irar agogo mai haske (T-TC) yana ba da damar Intel FPGA PAC N3000 don ramawa don jinkirin FPGA na ciki kuma yana rage tasirin jitter, wanda ke ba da damar T-TSC don kimanta lokacin Grandmaster's Time of Day (ToD) da kyau.

Manufar

Waɗannan gwaje-gwajen sun tabbatar da amfani da Intel FPGA PAC N3000 a matsayin bawa na IEEE1588v2 a cikin Buɗewar hanyar sadarwa ta Rediyo (O-RAN). Wannan takarda ta bayyana:

• Gwaji saitin
• Tsarin tabbatarwa
• Ƙimar aiki na tsarin agogo na gaskiya a cikin hanyar FPGA na Intel FPGA PAC N3000
• Ayyukan PTP na Intel FPGA PAC N3000 Ayyukan Intel FPGA PAC N3000 da ke goyan bayan agogon gaskiya shine.
  idan aka kwatanta da Intel FPGA PAC N3000 ba tare da agogo na gaskiya ba haka kuma tare da wani katin Ethernet XXV710 a ƙarƙashin yanayin zirga-zirga daban-daban da saitunan PTP.

Siffofin da Iyaka

Siffofin da ƙayyadaddun inganci don tallafin Intel FPGA PAC N3000 IEEE1588v2 sune kamar haka:

• Tarin software da aka yi amfani da shi: Linux PTP Project (PTP4l)
• Yana goyan bayan pro ta hanyar sadarwa mai zuwafiles:
  •  1588v2 (tsoho)
  • G.8265.1
  • G.8275.1
• Yana goyan bayan agogon bawa mataki biyu na PTP.

Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka. *Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.

• Yana goyan bayan ƙarshen-zuwa-ƙarshe yanayin multicast.
• Yana goyan bayan mitar musayar saƙon PTP har zuwa 128 Hz.
  • Wannan ƙayyadaddun tsarin tabbatarwa ne kuma Grandmaster mai aiki. Saitunan PTP sama da fakiti 128 a sakan daya don saƙonnin PTP na iya yiwuwa.
• Saboda iyakoki na Cisco* Nexus* 93180YC-FX sauyawa da aka yi amfani da shi a saitin tabbatarwa, sakamakon aikin a ƙarƙashin yanayin zirga-zirgar iperf3 yana nufin ƙimar musayar saƙon PTP na 8 Hz.
• Taimakon encapsulation:
  • Kai sama da L2 (raw Ethernet) da L3 (UDP/IPv4/IPv6)
    Lura: A cikin wannan takaddar, duk sakamakon yana amfani da hanyar haɗin Ethernet guda 25Gbps.

Kayan aiki da Siffofin Direba

Kayan aiki	Sigar
BIOS	Intel Server Board S2600WF 00.01.0013
OS	CentOS 7.6
Kwaya	kernel-rt-3.10.0-693.2.2.rt56.623.el7.src.
Kit ɗin Ci gaban Jirgin Sama (DPDK)	18.08
Intel C Compiler	19.0.3
Intel XL710 Direba (Direba i40e)	2.8.432.9.21
PTP4l	2.0
IxExplorer	8.51.1800.7 EA-Patch1
shafi 3	3.0.11
trafgen	Netsniff-ng 0.6.6 Kit ɗin Kayan aiki

 IXIA Testing Traffic

Saitin farko na ma'aunin aikin PTP na Intel FPGA PAC N3000 yana amfani da maganin IXIA* don cibiyar sadarwa da gwajin yarda da PTP. Akwatin chassis na IXIA XGS2 ya haɗa da katin IXIA 40 PORT NOVUS-R100GE8Q28 da IxExplorer wanda ke ba da ƙirar hoto don saita babban PTP Grandmaster zuwa DUT (Intel FPGA PAC N3000) akan haɗin Ethernet kai tsaye na 25 Gbps guda ɗaya. Tsarin toshewar da ke ƙasa yana kwatanta yanayin gwajin da aka yi niyya don tushen tushen IXIA. Duk sakamakon suna amfani da zirga-zirgar ababen hawa na IXIA don gwaje-gwajen zirga-zirgar zirga-zirgar ingress kuma suna amfani da kayan aikin trafgen akan Intel FPGA PAC N3000 mai masaukin baki don gwajin zirga-zirgar zirga-zirgar egress, inda hanyar ingress ko egress ta kasance koyaushe daga hangen DUT (Intel FPGA PAC N3000). ) mai masaukin baki. A cikin duka biyun, matsakaicin ƙimar zirga-zirga shine 24 Gbps. Wannan saitin gwajin yana ba da ƙayyadaddun ƙayyadaddun aikin PTP na Intel FPGA PAC N3000 tare da tsarin T-TC da aka kunna, da kuma kwatanta shi da hoton masana'anta wanda ba TC Intel FPGA PAC N3000 ba a ƙarƙashin ITU-T G.8275.1 PTP profile.

Topology don Intel FPGA PAC N3000 Gwajin Traffic karkashin IXIA Virtual Grandmaster

IXIA Sakamakon Gwajin Traffic

Binciken da ke gaba yana ɗaukar aikin PTP na TC-enabled Intel FPGA PAC N3000 a ƙarƙashin ingress da egress yanayin zirga-zirga. A cikin wannan sashe, PTP profile An karɓi G.8275.1 don duk gwajin zirga-zirga da tattara bayanai.

Girman Babban Offset

Hoton da ke biyo baya yana nuna girman babban koma baya wanda abokin aikin bawa na PTP4l na Intel FPGA PAC N3000 mai masaukin baki ya lura a matsayin aikin da ya wuce a karkashin ingress, egress da bidirectional trafic (matsakaicin abin da aka samar na 24.4Gbps).

Ma'anar Jinkirin Hanya (MPD)

Hoton da ke gaba yana nuna ma'anar jinkirin hanya, kamar yadda PTP4 bawan da ke amfani da Intel FPGA PAC N3000 ya ƙidaya a matsayin katin sadarwar cibiyar sadarwa, don gwaji iri ɗaya da adadi na sama. Jimlar tsawon kowane gwajin zirga-zirga guda uku aƙalla sa'o'i 16 ne.

Tebur mai zuwa yana lissafin ƙididdigar ƙididdiga na gwaje-gwajen zirga-zirga guda uku. Ƙarƙashin nauyin zirga-zirga kusa da ƙarfin tashar, PTP4l bawan da ke amfani da Intel FPGA PAC N3000 yana kula da lokacinsa zuwa babban babban malamin IXIA a cikin 53 ns don duk gwajin zirga-zirga. Bugu da kari, madaidaicin karkatar da girman girman maigidan yana ƙasa da 5 ns.

Bayanan ƙididdiga akan Ayyukan PTP

G.8275.1 PTP Profile	Traffic Ingress (24Gbps)	Traffic Egress (24Gbps)	Traffic Bidirectional (24Gbps)
RMS	6.35 ns	8.4 ns	9.2 ns
StdDev (na abs (max) biya diyya)	3.68 ns	3.78 ns	4.5 ns
StdDev (na MPD)	1.78 ns	2.1 ns	2.38 ns
Mafi girman biya	36 ns	33 ns	53 ns

 

Alkaluman da ke biyowa suna wakiltar girman ƙwaƙƙwaran ƙwararru da madaidaicin jinkirin hanya (MPD), ƙarƙashin gwajin zirga-zirgar ababen hawa na tsawon sa'o'i 16 mai tsawon Gbps 24 don ɓangarori daban-daban na PTP. Hotunan hagu a cikin waɗannan alkalumman suna komawa zuwa maƙasudin PTP ƙarƙashin IPV4/UDP encapsulation, yayin da saƙon PTP na jadawali na dama yana cikin L2 (raw Ethernet). Ayyukan bawa na PTP4l yayi kama da haka, mafi munin yanayin babban girman girman girman shine 53 ns da 45 ns don IPV4/UDP da L2 encapsulation, bi da bi. Matsakaicin karkatar da girman girman shine 4.49 ns da 4.55 ns don IPV4/UDP da L2 encapsulation, bi da bi.

Girman Babban Offset

Hoton da ke gaba yana nuna girman babban koma baya a ƙarƙashin 24 Gbps zirga-zirga bidirectional, IPv4 (hagu) da L2 (dama) encapsulation, G8275.1 Profile.

Ma'anar Jinkirin Hanya (MPD)

Adadin da ke biyo baya yana nuna ma'anar jinkirin hanyar Intel FPGA PAC N3000 mai masaukin baki PTP4l bawa a ƙarƙashin 24 Gbps zirga-zirga bidirectional, IPv4 (hagu) da L2 (dama) encapsulation, G8275.1 Profile.

Mahimman ƙimar MPD ba alama ce ta daidaiton PTP ba, saboda ya dogara da tsayin igiyoyi, latency na bayanai da sauransu; duk da haka, duban ƙananan bambance-bambancen MPD (2.381 ns da 2.377 ns don shari'ar IPv4 da L2, bi da bi) ya sa a fili cewa lissafin PTP MPD daidai yake a duk abubuwan da aka tattara. Yana tabbatar da daidaiton aikin PTP a cikin duka hanyoyin ɗaukar hoto. Canjin matakin a cikin MPD mai ƙididdigewa a cikin jadawali na L2 (a cikin adadi na sama, jadawali na dama) ya faru ne saboda ƙara tasirin zirga-zirgar da aka yi amfani da shi. Da farko, tashar ba ta da aiki (MPD rms shine 55.3 ns), sannan ana amfani da zirga-zirgar zirga-zirga (mataki na haɓaka na biyu, MPD rms shine 85.44 ns), tare da zirga-zirgar egress lokaci guda, yana haifar da ƙididdige MPD na 108.98 ns. Hotunan da ke biyowa sun rufe girman girman babban abin biya da MPD da aka ƙididdige na gwajin zirga-zirgar bidirectional da aka yi amfani da su ga bawa PTP4l ta amfani da Intel FPGA PAC N3000 tare da injin T-TC, da kuma wani wanda ke amfani da Intel FPGA PACN3000 ba tare da TC ba. ayyuka. Gwajin T-TC Intel FPGA PAC N3000 (orange) yana farawa daga sifilin lokaci, yayin da gwajin PTP wanda ke amfani da Intel FPGA PAC N3000 (blue) wanda ba TC ba yana farawa a kusa da T = 2300 seconds.

Girman Babban Offset

Hoton da ke biyo baya yana nuna girman babban biya a ƙarƙashin zirga-zirgar Ingress (24 Gbps), tare da ba tare da tallafin TTC ba, G.8275.1 Profile.

A cikin adadi na sama, aikin PTP na TC-enabled Intel FPGA PAC N3000 a ƙarƙashin zirga-zirga yana kama da wanda ba TC Intel FPGA PAC N3000 ba na daƙiƙa 2300 na farko. Ingantacciyar hanyar T-TC a cikin Intel FPGA PAC N3000 an haskaka shi a cikin ɓangaren gwaji (bayan na biyu na 2300) inda ake amfani da nauyin zirga-zirga daidai gwargwado zuwa musaya na katunan biyu. Hakazalika a cikin hoton da ke ƙasa, ana lura da lissafin MPD kafin da kuma bayan amfani da zirga-zirga akan tashar. An nuna tasirin tsarin T-TC a cikin ramawa ga lokacin zama na fakiti wanda shine latency fakiti ta hanyar FPGA tsakanin 25G da 40G MACs.

Ma'anar Jinkirin Hanya (MPD)

Hoto mai zuwa yana nuna ma'anar jinkirin hanyar Intel FPGA PAC N3000 mai masaukin baki PTP4l bawa a ƙarƙashin zirga-zirgar Ingress (24 Gbps), tare da ba tare da tallafin T-TC ba, G.8275.1 Profile.

Waɗannan alkalumman suna nuna servo algorithm na PTP4l, saboda gyare-gyaren lokacin zama na TC, muna ganin ƙananan bambance-bambance a cikin matsakaicin lissafin jinkirin hanya. Sabili da haka, tasirin jinkirin jinkiri a kan ƙimar ƙima ya ragu. Teburin da ke gaba yana lissafin ƙididdigar ƙididdiga akan aikin PTP, wanda ya haɗa da RMS da daidaitaccen karkata na babban biya, daidaitaccen ɓata ma'anar jinkirin hanya, da kuma mafi munin yanayin babban diyya na Intel FPGA PAC N3000 tare da kuma ba tare da T- TC goyon baya.

Cikakkun ƙididdiga akan Ayyukan PTP A Karkashin Traffic Ingress

Traffic Ingress (24Gbps) G.8275.1 PTP Profile	Intel FPGA PAC N3000 tare da T-TC	Intel FPGA PAC N3000 ba tare da T-TC ba
RMS	6.34 ns	40.5 ns
StdDev (na abs (max) biya diyya)	3.65 ns	15.5 ns
StdDev (na MPD)	1.79 ns	18.1 ns
Mafi girman biya	34 ns	143 ns

Kwatanta kai tsaye Intel FPGA PAC N3000 mai goyon bayan TC zuwa nau'in da ba TC ba
Yana nuna cewa aikin PTP yana 4x zuwa 6x ƙasa da kowane ƙididdiga
ma'auni (mafi muni, RMS ko daidaitaccen karkata na babban biya). Mafi munin-harka
babban diyya don tsarin G.8275.1 PTP na T-TC Intel FPGA PAC N3000 shine 34
ns karkashin ingress yanayin zirga-zirga a iyakar bandwidth na tashar (24.4Gbps).

Gwajin Traffic lprf3

Wannan sashe yana bayyana gwajin alamar zirga-zirga na iperf3 don ƙara kimanta aikin PTP na Intel FPGA PAC N3000. An yi amfani da kayan aikin iperf3 don yin koyi da yanayin zirga-zirga. Tsarin hanyar sadarwa na ma'auni na zirga-zirga na iperf3, wanda aka nuna a hoton da ke ƙasa, ya ƙunshi haɗin sabar guda biyu, kowanne yana amfani da katin DUT (Intel FPGA PAC N3000 da XXV710), zuwa Cisco Nexus 93180YC FX sauyawa. Canjin Cisco yana aiki azaman agogon iyaka (T-BC) tsakanin bayin DUT PTP guda biyu da Calnex Paragon-NEO Grandmaster.

Topology na hanyar sadarwa don Intel FPGA PAC N3000 lprf3 Gwajin Traffic

Fitowar PTP4l akan kowace runduna ta DUT tana ba da ma'aunin bayanai na aikin PTP ga kowace na'urar bawa a cikin saitin (Intel FPGA PAC N3000 da XXV710). Don gwajin zirga-zirga na iperf3, sharuɗɗa masu zuwa da jeri suna aiki ga duk jadawali da nazarin aiki:

• 17 Gbps tara bandwidth na zirga-zirga (duka TCP da UDP), ko dai egress ko ingress ko bidirectional zuwa Intel FPGA PAC N3000.
• IPV4 encapsulation na fakitin PTP, saboda ƙayyadaddun ƙayyadaddun ƙayyadaddun bayanai akan Cisco Nexus 93180YC-FX.
• Adadin musayar saƙon PTP yana iyakance ga fakiti 8/daƙiƙa, saboda ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun bayanai akan maɓallin Cisco Nexus 93180YC-FX.

perf3 Sakamakon Gwajin Traffic

Binciken da ke gaba yana ɗaukar aikin Intel FPGA PAC N3000 da katin XXV710, dukansu a lokaci guda suna aiki azaman katin dubawar cibiyar sadarwa na bayin PTP (T-TSC) Calnex Paragon NEO Grandmaster ta hanyar T-BC Cisco switch.

Alkaluman da ke biyowa suna nuna girman babban kashewa da MPD akan lokaci don gwajin zirga-zirga daban-daban guda uku ta amfani da Intel FPGA PAC N3000 tare da katin T-TC da XXV710. A cikin duka katunan biyu, zirga-zirgar zirga-zirgar ababen hawa na da tasiri mafi girma akan aikin PTP4l. Tsawon lokacin gwajin zirga-zirga yana da awoyi 10. A cikin alkaluma masu zuwa, wutsiyar jadawali tana nuna lokaci akan lokaci inda zirga-zirgar ababen hawa ke tsayawa kuma girman PTP master offset ya gangara zuwa ƙananan matakansa, saboda tashar mara aiki.

Girman Babban Offset don Intel FPGA PAC N3000

Hoto mai zuwa yana nuna ma'anar jinkirin hanyar Intel FPGA PAC N3000 tare da T TC, ƙarƙashin ingress, egress da zirga-zirgar iperf3 bidirectional.

Jinkirin Hanya (MPD) don Intel FPGA PAC N3000

Hoto mai zuwa yana nuna ma'anar jinkirin hanyar Intel FPGA PAC N3000 tare da T TC, ƙarƙashin ingress, egress da zirga-zirgar iperf3 bidirectional.

Girman Babban Offset don XXV710

Hoto mai zuwa yana nuna girman babban koma baya na XXV710, ƙarƙashin ingress, egress da bidirectional iperf3.

Ma'anar Jinkirin Hanya (MPD) don XXV710

Hoto mai zuwa yana nuna ma'anar jinkirin hanya don XXV710, ƙarƙashin ingress, egress da bidirectional iperf3.

Game da aikin Intel FPGA PAC N3000 PTP, mafi munin yanayin babban ma'aikaci a ƙarƙashin kowane yanayin zirga-zirga yana tsakanin 90 ns. Yayin da yake ƙarƙashin yanayin zirga-zirga iri ɗaya ɗaya, RMS na Intel FPGA PAC N3000 master offset shine mafi kyawun 5.6x fiye da katin XXV710.

	Intel FPGA PAC N3000			Saukewa: XXV710
	Cigaba Traffic10G	Traffic Egress 18G	Traffic Bidirectional18G	Cigaba Traffic18G	Traffic Egress 10G	Traffic Bidirectional18G
RMS	27.6 ns	14.2 ns	27.2 ns	93.96 ns	164.2 ns	154.7 ns
StdDev (na abs (max) biya diyya)	9.8 ns	8.7 ns	14.6 ns	61.2 ns	123.8 ns	100 ns
StdDev (na MPD)	21.6 ns	9.2 ns	20.6 ns	55.58 ns	55.3 ns	75.9 ns
Mafi girman biya	84 ns	62 ns	90 ns	474 ns	1,106 ns	958 ns

Musamman ma, babban diyya na Intel FPGA PAC N3000 yana da ƙananan ma'auni,
aƙalla 5x ƙasa da katin XXV710, yana nuna cewa ƙimar PTP
Agogon Grandmaster ba shi da hankali ga latency ko bambancin amo a ƙarƙashin zirga-zirga a cikin
Intel FPGA PAC N3000.
Idan aka kwatanta da Sakamakon Gwajin Traffic na IXIA a shafi na 5, mafi munin yanayin girma na
Babban diyya tare da kunna T-TC Intel FPGA PAC N3000 ya bayyana mafi girma. Bayan haka
bambance-bambance a cikin topology na cibiyar sadarwa da bandwidth na tashar, wannan ya faru ne saboda Intel
Ana kama FPGA PAC N3000 a ƙarƙashin G.8275.1 PTP profile (yawan daidaitawa 16 Hz), yayin da
Adadin saƙon daidaitawa a wannan yanayin yana ƙuntatawa a fakiti 8 a sakan daya.

Girman Babban Kwatancen Kaya

Hoto mai zuwa yana nuna girman kwatankwacin babban gyara a ƙarƙashin zirga-zirgar iperf3 na bidirectional.

Ma'anar Jinkirin Tafarki (MPD) Kwatanta

Hoto mai zuwa yana nuna ma'anar kwatankwacin jinkirin hanya ƙarƙashin zirga-zirgar iperf3 na bidirectional.

Mafi girman aikin PTP na Intel FPGA PAC N3000, idan aka kwatanta da katin XXV710, shima yana da goyan bayan mafi girman karkatar da jinkirin hanyar da aka ƙididdige (MPD) don XXV710 da Intel FPGA PAC N3000 a cikin kowane gwajin zirga-zirga da aka yi niyya, don misaliample bidirectional iperf3 zirga-zirga. Yi watsi da ma'anar ƙima a cikin kowane harka na MPD, wanda zai iya bambanta saboda dalilai da yawa, kamar kebul na Ethernet daban-daban da latency daban-daban. Bambance-bambancen da aka lura da haɓakar ƙimar katin XXV710 ba su nan a cikin Intel FPGA PAC N3000.

RMS na Kwatancen Kaya na Jagora guda 8 a jere

Kammalawa

Hanyar bayanan FPGA tsakanin QSFP28 (25G MAC) da Intel XL710 (40G MAC) suna ƙara latency fakiti mai canzawa wanda ke shafar kusan daidaiton Bawan PTP. Ƙara goyon bayan Agogon Mai Bayar (T-TC) a cikin tunani mai laushi na FPGA na Intel FPGA PAC N3000 yana ba da diyya na wannan fakiti ta hanyar ƙara lokacin zama a cikin filin gyara na saƙon PTP. Sakamakon ya tabbatar da cewa tsarin T-TC yana inganta ingantaccen aikin bawan PTP4l.

Hakanan, Sakamakon Gwajin Traffic na IXIA akan shafi na 5 yana nuna cewa tallafin T-TC a cikin hanyar bayanan FPGA yana haɓaka aikin PTP ta aƙalla 4x, idan aka kwatanta da Intel FPGA PAC N3000 ba tare da tallafin T-TC ba. Intel FPGA PAC N3000 tare da T-TC yana gabatar da mafi munin yanayin babban koma baya na 53 ns karkashin ingress, egress ko bidirectional lodin zirga-zirga a iyakar ƙarfin tashar (25 Gbps). Don haka, tare da tallafin T-TC, aikin Intel FPGA PAC N3000 PTP ya fi daidai kuma ba shi da sauƙi ga bambancin amo.

A cikin Gwajin Traffic na lperf3 a shafi na 10, aikin PTP na Intel FPGA PAC N3000 tare da kunna T-TC an kwatanta shi da katin XXV710. Wannan gwajin ya ɗauki bayanan PTP4l na duka agogon bayi a ƙarƙashin zirga-zirgar shiga ko egress wanda ake musayar tsakanin runduna biyu na Intel FPGA PAC N3000 da katin XXV710. Mafi munin yanayin babban abin da aka gani a cikin Intel FPGA PAC N3000 ya kasance aƙalla 5x ƙasa da katin XXV710. Hakanan, madaidaicin karkatawar abubuwan da aka kama shima yana tabbatar da cewa tallafin T-TC na Intel FPGA PAC N3000 yana ba da damar daidaita agogon Grandmaster.

Don ƙara inganta aikin PTP na Intel FPGA PAC N3000, yuwuwar zaɓuɓɓukan gwaji sun haɗa da:

• Tabbatarwa a ƙarƙashin PTP pro daban-dabanfiles da ƙimar saƙo don hanyoyin haɗin Ethernet sama da ɗaya.
• Ƙimar Gwajin Traffic lprf3 a shafi na 10 tare da ƙarin ci gaba wanda ke ba da damar ƙimar saƙon PTP mafi girma.
• Ƙimar ayyukan T-SC da daidaiton lokacin sa na PTP a ƙarƙashin G.8273.2 Gwajin Yarda.

Tarihin Bita na Takardu don Gwajin IEEE 1588 V2

 

Takardu Sigar	Canje-canje
2020.05.30	Sakin farko.

 

Takardu / Albarkatu

intel FPGA Programmable Acceleration Card N3000 [pdf] Jagorar mai amfani FPGA Programmable Acceleration Card, N3000, Programmable Acceleration Card N3000, FPGA Programmable Acceleration Card N3000, FPGA, IEEE 1588 V2 Test

Magana

• Manual mai amfani