Microsemi SmartFusion2 FPGA Fabric DDR njikwa ntuziaka onye ọrụ
Okwu mmalite
SmartFusion2 FPGA nwere njikwa DDR abụọ agbakwunyere - nke a na-enweta site na MSS (MDDR) yana nke ọzọ ezubere maka ịnweta ozugbo site na FPGA Fabric (FDDR). MDR na FDDR abụọ na-achịkwa ebe nchekwa DDR-chip.
Iji hazie onye njikwa Fabric DDR nke ọma ị ga-emerịrị:
- Jiri ihe njikwa nchekwa nchekwa DDR mebere akwa iji hazie DDR Controller, họrọ interface ụgbọ ala datapathpath ya (AXI ma ọ bụ AHBlite), wee họrọ ugboro elekere DDR yana oge elekere data ụzọ akwa.
- Tọọ ụkpụrụ ndekọ aha maka ndebanye aha onye njikwa DDR ka ọ dabara na njirimara ebe nchekwa DDR nke mpụga gị.
- Melite Fabric DDR dị ka akụkụ nke ngwa onye ọrụ wee mee njikọ datapath.
- Jikọọ ihe nhazi nhazi APB nke onye na-ahụ maka DDR dị ka usoro mmalite mmalite nke Peripheral kọwara.
Ihe nhazi nchekwa DDR nke mpụga ákwà
A na-eji Configurator Fabric External Memory DDR (FDDR) hazie ụzọ data n'ozuzu ya na ebe nchekwa DDR mpụga maka Onye njikwa Fabric DDR.
Ọgụgụ 1-1 • FDDR Configurator Overview
Ntọala ebe nchekwa
Jiri Ntọala ebe nchekwa hazie nhọrọ ebe nchekwa gị na MDDR.
- Ụdị ebe nchekwa - LPDDR, DDR2 ma ọ bụ DDR3
- Ogologo data - 32-bit, 16-bit ma ọ bụ 8-bit
- Ugboro elekere - Uru ọ bụla (Decimal/ Fractional) n'etiti 20 MHz ruo 333 MHz
- SECDED agbanyere ECC – Gbanyụọ ma ọ bụ gbanyụọ
- Mapping adreesị - {ROW,BANK,COLUMN},{BANK,ROW,COLUMN}
Ntọala ihu ákwà
FPGA Fabric Interface - Nke a bụ interface data dị n'etiti FDDR na imewe FPGA. N'ihi na FDDR bụ onye na-ahụ maka ebe nchekwa, e bu n'obi ka ọ bụrụ ohu na ụgbọ ala AXI ma ọ bụ AHB. Nna-ukwu nke ụgbọ ala na-amalite azụmahịa ụgbọ ala, nke FDDR tụgharịrị n'aka ya dị ka azụmahịa ebe nchekwa ma gwa ya na ebe nchekwa DDR mgbapụ. FDDR ákwà interface nhọrọ bụ:
- Iji Interface AXI-64 - Otu nna ukwu na-enweta FDDR site na interface 64-bit \ AXI.
- Iji Single AHB-32 Interface - Otu nna ukwu na-enweta FDDR site na otu interface AHB 32-bit.
- Iji abụọ AHB-32 Interfaces - Nna-ukwu abụọ na-enweta FDDR site na iji oghere AHB 32-bit abụọ.
Nkesa elekere FPGA - Na-akọwapụta ọnụọgụ ugboro n'etiti elekere DDR Controller (CLK_FDDR) na elekere na-ejikwa interface ákwà (CLK_FIC64). Ugboro CLK_FIC64 kwesịrị ịha nhata nke usoro AHB/AXI nke ejikọrọ na interface ụgbọ ala FDDR AHB/AXI. Maka examplee, ọ bụrụ na ị nwere DDR RAM na-agba ọsọ na 200 MHz na Fabric/AXI Subsystem gị na-agba ọsọ na 100 MHz, ị ga-ahọrọ onye na-ekesa 2 (Figure 1-2).
Ọgụgụ 1-2 • Ntọala ihu ákwà - AXI Interface na FDDR Clock Divisor Agreement
Jiri ákwà PLL Mkpọchi - Ọ bụrụ CLK_BASE sitere na CCC Fabric, ị nwere ike jikọọ mmepụta CCC LOCK akwa na ntinye FDDR FAB_PLL_LOCK. CLK_BASE anaghị eguzosi ike ruo mgbe mkpuchi CCC akwa. Ya mere, Microsemi na-atụ aro ka ijide FDDR na nrụpụta (ya bụ, kwupụta ntinye CORE_RESET_N) ruo mgbe CLK_BASE kwụsiri ike. Mmepụta LOCK nke Fabric CCC na-egosi na elekere mmepụta nke Fabric CCC kwụsiri ike. Site na ịlele Jiri FAB_PLL_LOCK nhọrọ, ị nwere ike ikpughe FAB_PLL_LOCK ọdụ ụgbọ mmiri nke FDDR. Ị nwere ike jikọọ mmepụta LOCK nke Fabric CCC na ntinye FAB_PLL_LOCK nke FDDR.
Ike IO Drive
Họrọ otu n'ime ike draịva ndị a maka DDR I/O's gị:
- Ọkara Drive Ike
- Ike mbanye zuru oke
Dabere na ụdị ebe nchekwa DDR gị yana ike I/O ị họrọ, Libero SoC na-edobe ọkọlọtọ DDR I/O maka sistemụ FDDR gị dị ka ndị a:
| Ụdị ebe nchekwa DDR | Ọkara Drive Ike | Ike mbanye zuru oke |
| DDR3 | SSTL15I | SSTL15II |
| DDR2 | SSTL18I | SSTL18II |
| LPDDR | LPDRI | LPDRII |
Kwado nkwụsị
FDDR nwere ike iwelite nkwụsịtụ mgbe afọ ụfọdụ ọnọdụ akọpụtarala afọ ojuju. Lelee Kwado nkwụsịtụ na nhazi FDDR ma ọ bụrụ na ịchọrọ iji nkwụsịtụ ndị a na ngwa gị.
Nke a na-ekpughere mgbaama nkwụsịtụ na ihe atụ FDDR. Ị nwere ike jikọọ mgbaàmà nkwụsịtụ ndị a dị ka imewe gị chọrọ. Ihe nrịbama nkwụsịtụ na ihe nkwado ha dị:
- FIC_INT - Emepụtara mgbe enwere mperi na azụmahịa n'etiti Nna-ukwu na FDDR
- IO_CAL_INT - Na-enyere gị aka ịhazigharị DDR I/O site na idegara onye njikwa DDR aha site na nhazi nhazi APB. Mgbe mmezi mmezi, a na-ebulite nkwụsịtụ a. Maka nkọwa gbasara mweghachi I/O, rụtụ aka na ntuziaka ndị ọrụ Microsemi SmartFusion2.
- PLL_LOCK_INT - Na-egosi na FDDR FPLL akpọchiela
- PLL_LOCKLOST_INT - Na-egosi na FDDR FPLL furu efu
- FDDR_ECC_INT - Na-egosi na achọpụtala otu mperi ma ọ bụ abụọ
Ugboro elekere akwa ákwà
Mgbakọ ugboro elekere dabere na ugboro elekere gị ugbu a yana nkesa CLOCK, egosiri na MHz.
Ugboro elekere akwa ákwà (na MHz) = nkesa elekere / elekere
Bandwit ebe nchekwa
Mgbakọ bandwit ebe nchekwa dabere na uru Ugboro elekere gị ugbu a na Mbps.
Bandwit ebe nchekwa (na Mbps) = 2 * Ugboro elekere
Mgbakọta bandwit
Mgbakọ gbakọọ bandwit dabere na ugboro elekere gị ugbu a, obosara data na nkesa elekere, na Mbps.
Mkpokọta bandwit (na Mbps) = (2 * Ugboro elekere * Ogologo data) / Nkesa elekere
Nhazi njikwa FDDR
Mgbe ị na-eji Fabric DDR Controller iji nweta ebe nchekwa DDR mpụga, DDR Controller ga-ahazirịrị n'oge ọ na-agba ọsọ. A na-eme nke a site na ide data nhazi na ndekọ nhazi nhazi DDR raara onwe ya nye. Data nhazi a dabere na njirimara nke ebe nchekwa DDR mpụga yana ngwa gị. Akụkụ a na-akọwa otu esi etinye usoro nhazi ndị a na nhazi njikwa FDDR yana otu esi ejikwa data nhazi dị ka akụkụ nke ngwọta mmalite nke Peripheral. Rụtụ aka na ntuziaka onye ọrụ mmalite mmalite maka ozi zuru oke gbasara ngwọta mmalite mmalite.
Ndị na-edebanye aha DDR Control Fabric
Onye njikwa Fabric DDR nwere ndebanye aha nke achọrọ ka ahazi ya n'oge ọ na-agba ọsọ. Ụkpụrụ nhazi maka ndekọ ndị a na-anọchi anya paramita dị iche iche (maka example, ọnọdụ DDR, obosara PHY, ọnọdụ mgbawa, ECC, wdg). Maka nkọwa gbasara ndekọ nhazi nhazi DDR, rụtụ aka na ntuziaka onye ọrụ Microsemi SmartFusion2.
Nhazi DDR ndị na-edebanye aha ákwà
Jiri taabụ mmalite mmalite (ọgụgụ 2-1) na oge ebe nchekwa (ọgụgụ 2-2) iji tinye paramita kwekọrọ na ebe nchekwa DDR na ngwa gị. A na-asụgharị ụkpụrụ ndị ị tinyere na taabụ ndị a na-akpaghị aka ka ọ bụrụ ụkpụrụ ndebanye aha kwesịrị ekwesị. Mgbe ị pịrị otu paramita a kapịrị ọnụ, a na-akọwa aha ndekọ ya kwekọrọ na mpio nkọwa ndekọ aha (Foto 1-1 na ibe 4).
Ọgụgụ 2-1 • Nhazi FDDR – Tab mmalite ebe nchekwa
Ọgụgụ 2-2 • Nhazi FDDR – Tab oge ebe nchekwa
Na-ebubata nhazi DDR Files
Na mgbakwunye na ịbanye DDR Memory parameters site na iji ebe nchekwa mmalite na oge taabụ, ị nwere ike ibubata ụkpụrụ ndebanye aha DDR site na a. file. Iji mee nke a, pịa bọtịnụ nhazi mbubata wee gaa na ederede file nwere DDR aha na ụkpụrụ. Ọgụgụ 2-3 na-egosi syntax nhazi mbubata.
Ọgụgụ 2-3 • DDR Register Configuration File Syntax
Mara: Ọ bụrụ na ịhọrọ ibubata ụkpụrụ ndekọ aha kama iji GUI tinye ha, ị ga-akọwarịrị ụkpụrụ ndekọ aha niile dị mkpa. Rụtụ aka na ntuziaka onye ọrụ SmartFusion2 maka nkọwa
Na-ebupụ nhazi DDR Files
Ị nwekwara ike mbupụ data nhazi ndekọ aha ugbu a n'ime ederede file. Nke a file ga-enwe ụkpụrụ ndebanye aha nke ị webatara (ma ọ bụrụ na ọ dị) yana nke agbakọrọ site na paramita GUI nke i tinyere n'ime igbe okwu a.
Ọ bụrụ na ịchọrọ imezi mgbanwe ndị i mere na nhazi ndebanye aha DDR, ị nwere ike ime ya site na Weghachite Default. Nke a na-ehichapụ data nhazi ndekọ aha niile ma ị ga-ebubata ma ọ bụ tinyeghachi data a. Atọgharịrị data ahụ na ụkpụrụ nrụpụta ngwaike.
Emepụtara data
Pịa OK ka ịmepụta nhazi ahụ. Dabere na ntinye gị na taabụ General, Oge ebe nchekwa na mmalite mmalite, FDDR Configurator na-agbakọ ụkpụrụ maka ndekọ nhazi DDR niile wee bupụ ụkpụrụ ndị a n'ime ọrụ firmware gị na ịme anwansị. files. Nke mbupụ file egosiri syntax na eserese 2-4.
Ọgụgụ 2-4 • Nhazi ndekọ aha DDR ebupụla File Syntax
Firmware
Mgbe ị na-emepụta SmartDesign, ndị a files na-emepụta na /firmware/ drivers_config/sys_config directory. Ndị a files ka achọrọ maka CMSIS firmware core iji chịkọta nke ọma ma nwee ozi gbasara imewe gị ugbu a, gụnyere data nhazi akụkụ yana ozi nhazi elekere maka MSS. Dezie ihe ndị a files aka, ka a na-emegharị ha oge ọ bụla a na-emegharị mgbọrọgwụ mgbọrọgwụ gị.
- sys_config.c
- sys_config.h
- sys_config_mddr_define.h - data nhazi MDR.
- sys_config_fddr_define.h - data nhazi FDDR.
- sys_config_mss_clocks.h – MSS clocks nhazi nhazi
ịme anwansị
Mgbe ị na-emepụta SmartDesign jikọtara na MSS gị, simulation na-esonụ fileA na-emepụta s na ndekọ ndekọ simulator:
- nwale.bfm - BFM dị elu file nke a na-ebu ụzọ gbuo n'oge ịme anwansị ọ bụla na-eme ihe nhazi SmartFusion2 MSS Cortex-M3. Ọ na-eme peripheral_init.bfm na user.bfm, n'usoro ahụ.
- peripheral_init.bfm - Nwere usoro BFM nke na-eṅomi ọrụ CMSIS :: SystemInit () na-agba ọsọ na Cortex-M3 tupu ịbanye na isi () usoro. Ọ na-eṅomi data nhazi maka akụkụ ọ bụla ejiri mee ihe na nhazi ahụ gaa na ndekọ nhazi mpaghara ziri ezi wee chere ka akụkụ niile dị njikere tupu ị kwupụta na onye ọrụ nwere ike iji ihe ndị a.
- FDDR_init.bfm - Nwere iwu ide BFM nke na-eme ka ọ na-ede nke data ndekọ nhazi Fabric DDR nke ị banyere (iji igbe okwu Dezie ndị na-edebanye aha) n'ime ndekọ DDR Controller.
- onye ọrụ.bfm – Ezubere maka iwu onye ọrụ. Ị nwere ike ịmegharị ụzọ data site na ịgbakwunye iwu BFM nke gị na nke a file. Iwu na nke a file a ga-egbu mgbe peripheral_init.bfm gwụchara.
Iji nke files n'elu, a na-eme ka usoro nhazi ahụ na-akpaghị aka. Naanị ị ga-edezi onye ọrụ.bfm file iji megharịa datapath. Dezie test.bfm, peripheral_init.bfm, ma ọ bụ MDR_init.bfm filedị ka ndị a files na-emegharị oge ọ bụla a na-emezigharị mgbọrọgwụ mgbọrọgwụ gị.
Ụzọ nhazi DDR ákwà
Ngwọta mmalite mmalite nke Peripheral chọrọ na, na mgbakwunye na ịkọwa ụkpụrụ aha nhazi Fabric DDR, ị na-ahazi ụzọ data nhazi APB na MSS (FIC_2). Ọrụ SystemInit() na-ede data na ndekọ nhazi FDDR site na interface FIC_2 APB.
Mara: Ọ bụrụ na ị na-eji Sistemụ Nrụpụta, a na-edozi ụzọ nhazi ma jikọọ ya na-akpaghị aka.
Ọgụgụ 2-5 • FIC_2 Configurator Overview
Iji hazie interface FIC_2:
- Mepee mkparịta ụka nhazi FIC_2 (Foto 2-5) site na nhazi MSS.
- Họrọ ihe mmalite mmalite site na iji nhọrọ Cortex-M3.
- Gbaa mbọ hụ na a na-enyocha MSS DDR, dịkwa ka a na-eme Fabric DDR/SERDES blocks ma ọ bụrụ na ị na-eji ha.
- Pịa OK iji chekwaa ntọala gị. Nke a na-ekpughe ọdụ ụgbọ mmiri nhazi FIC_2 (Oge, Tọgharia, na ebe ụgbọ ala APB), dịka egosiri na eserese 2-6.
- Mepụta MSS. Ọdụ ụgbọ mmiri FIC_2 (FIC_2_APB_MASTER, FIC_2_APB_M_PCLK na FIC_2_APB_M_RESET_N) ekpughere ugbu a na interface MSS ma nwee ike jikọọ ya na CoreSF2Config na CoreSF2Reset dị ka nkọwapụta nkọwa mmalite mmalite nke Peripheral.
Ọgụgụ 2-6 • FIC_2 ọdụ ụgbọ mmiri
Nkọwa Port
FDDR isi ọdụ ụgbọ mmiri
Tebụl 3-1 • FDDR isi ọdụ ụgbọ mmiri
| Aha Port | Ntuziaka | Nkọwa |
| CORE_RESET_N | IN | Ntọgharị njikwa FDDR |
| CLK_BASE | IN | FDDR Fabric elekere |
| FPLL_LOCK | Mpụ | Mkpọchi mkpọchi FDDR PLL - dị elu mgbe akpọchiri FDDR PLL |
| CLK_BASE_PLL_LOCK | IN | Ntinye mkpọchi PLL ákwà. Ntinye a na-ekpughe naanị mgbe ahọpụtara nhọrọ Jiri FAB_PLL_LOCK. |
Ọdụ ụgbọ mmiri kwụsịrị
Otu ọdụ ụgbọ mmiri a na-ekpughe mgbe ị họrọ nhọrọ Kwado nkwụsịtụ.
Tebụl 3-2 • ọdụ ụgbọ mmiri kwụsịrị
| Aha Port | Ntuziaka | Nkọwa |
| PLL_LOCK_INT | Mpụ | Na-ekwupụta mgbe FDDR PLL kpochiri. |
| PLL_LOCKLOST_INT | Mpụ | Na-ekwupụta mgbe mkpọchi FDDR PLL efunahụ. |
| ECC_INT | Mpụ | Na-ekwupụta mgbe emume ECC mere. |
| IO_CALIB_INT | Mpụ | Na-ekwupụta mgbe mmezi I/O zuru. |
| FIC_INT | Mpụ | Na-ekwupụta mgbe enwere mperi na protocol AHB/AXI na interface Fabric. |
Interface nhazi nhazi APB3
Tebụl 3-3 • Interface nhazi nhazi APB3
| Aha Port | Ntuziaka | Nkọwa |
| APB_S_PENABLE | IN | Kwado ohu |
| APB_S_PSEL | IN | Nhọrọ ohu |
| APB_S_PWRITE | IN | Dee Kwado |
| APB_S_PADDR [10:2] | IN | Adreesị |
| APB_S_PWDATA[15:0] | IN | Dee data |
| APB_S_PREADY | Mpụ | Jikere Ohu |
| APB_S_PSLVERR | Mpụ | Njehie ohu |
| APB_S_PRDATA[15:0] | Mpụ | Gụọ data |
| APB_S_PRESET_N | IN | Ntọghari ohu |
| APB_S_PCLK | IN | Elekere |
DDR PHY Interface
Isiokwu 3-4 • DDR PHY Interface
| Aha Port | Ntuziaka | Nkọwa |
| FDDR_CAS_N | Mpụ | DRAM CASN |
| FDDR_CKE | Mpụ | DRAM CKE |
| FDDR_CLK | Mpụ | Elekere, akụkụ P |
| FDDR_CLK_N | Mpụ | Elekere, N akụkụ |
| FDDR_CS_N | Mpụ | DRAM CSN |
| FDDR_ODT | Mpụ | DRAM ODT |
| FDDR_RAS_N | Mpụ | DRAM RASN |
| FDDR_RESET_N | Mpụ | Tọgharia DRAM maka DDR3 |
| FDDR_WE_N | Mpụ | DRAM WEN |
| FDDR_ADDR [15:0] | Mpụ | Iberibe adreesị Dram |
| FDDR_BA[2:0] | Mpụ | Dram Bank Adreesị |
| FDDR_DM_RDQS[4:0] | INOUT | Ihe nkpuchi data Dram |
| FDDR_DQS[4:0] | INOUT | Ntinye/Mpụta Dram Data Strobe – Akụkụ P |
| FDDR_DQS_N [4:0] | INOUT | Ntinye/mmepụta Dram Data Strobe – N akụkụ |
| FDDR_DQ [35:0] | INOUT | Ntinye/mmepụta data DRAM |
| FDDR_FIFO_WE_IN[2:0] | IN | FIFO na mgbama |
| FDDR_FIFO_WE_OUT[2:0] | Mpụ | FIFO pụta ìhè |
| FDDR_DM_RDQS ([3:0]/[1:0]/[0]) | INOUT | Ihe nkpuchi data Dram |
| FDDR_DQS ([3:0]/[1:0]/[0]) | INOUT | Ntinye/Mpụta Dram Data Strobe – Akụkụ P |
| FDDR_DQS_N ([3:0]/[1:0]/[0]) | INOUT | Ntinye/mmepụta Dram Data Strobe – N akụkụ |
| FDDR_DQ ([31:0]/[15:0]/[7:0]) | INOUT | Ntinye/mmepụta data DRAM |
| FDDR_DQS_TMATCH_0_IN | IN | FIFO na mgbama |
| FDDR_DQS_TMATCH_0_OUT | Mpụ | FIFO pụta ìhè |
| FDDR_DQS_TMATCH_1_IN | IN | FIFO na mgbama (naanị 32-bit) |
| FDDR_DQS_TMATCH_1_OUT | Mpụ | Mgbama FIFO (naanị 32-bit) |
| FDDR_DM_RDQS_ECC | INOUT | Ihe nkpuchi data Dram ECC |
| FDDR_DQS_ECC | INOUT | Ntinye/mmepụta Dram ECC Data Strobe – Akụkụ P |
| FDDR_DQS_ECC_N | INOUT | Ntinye/mmepụta Dram ECC Data Strobe – N akụkụ |
| FDDR_DQ_ECC ([3:0]/[1:0]/[0]) | INOUT | Ntinye/mmepụta data DRAM ECC |
| FDDR_DQS_TMATCH_ECC_IN | IN | ECC FIFO na akara ngosi |
| FDDR_DQS_TMATCH_ECC_OUT | Mpụ | ECC FIFO mgbama (naanị 32-bit) |
Mara: Obosara ọdụ ụgbọ mmiri maka ụfọdụ ọdụ ụgbọ mmiri na-agbanwe dabere na nhọrọ nke obosara PHY. A na-eji akara ngosi "[a: 0] / [b: 0] / [c: 0]" pụtara ọdụ ụgbọ mmiri ndị dị otú ahụ, ebe "[a: 0]" na-ezo aka na obosara ọdụ ụgbọ mmiri mgbe ahọpụtara obosara 32-bit PHY. , "[b:0]" dabara na obosara PHY nke 16-bit, na "[c:0]" dabara na obosara PHY nke 8-bit.
Interface ụgbọ ala AXI
Isiokwu 3-5 • AXI ụgbọ ala Interface
| Aha Port | Ntuziaka | Nkọwa |
| AXI_S_AWREADY | Mpụ | Dee adreesị njikere |
| AXI_S_WREADY | Mpụ | Dee adreesị njikere |
| AXI_S_BID[3:0] | Mpụ | NJ nzaghachi |
| AXI_S_BRESP[1:0] | Mpụ | Dee nzaghachi |
| AXI_S_BVALID | Mpụ | Dee nzaghachi bara uru |
| AXI_S_ARREADY | Mpụ | Gụọ adreesị njikere |
| AXI_S_RID[3:0] | Mpụ | Gụọ ID Tag |
| AXI_S_RRESP[1:0] | Mpụ | Gụọ Azịza ya |
| AXI_S_RDATA[63:0] | Mpụ | Gụọ data |
| AXI_S_RLAST | Mpụ | Gụọ Ikpeazụ – Mgbama a na-egosi mbufe ikpeazụ na mgbawa ọgụgụ. |
| AXI_S_RVALID | Mpụ | Gụọ adreesị ziri ezi |
| AXI_S_AWID[3:0] | IN | Dee ID adreesị |
| AXI_S_AWADDR[31:0] | IN | Dee adreesị |
| AXI_S_AWLEN [3:0] | IN | Ogologo mgbawa |
| AXI_S_AWSIZE[1:0] | IN | Nha mgbawa |
| AXI_S_AWBURST[1:0] | IN | Ụdị mgbawa |
| AXI_S_AWLOCK[1:0] | IN | Ụdị mkpọchi - mgbaàmà a na-enye ozi ndị ọzọ gbasara njirimara atọm nke nnyefe. |
| AXI_S_AWVALID | IN | Dee adreesị ziri ezi |
| AXI_S_WID[3:0] | IN | Dee NJ data tag |
| AXI_S_WDATA[63:0] | IN | Dee data |
| AXI_S_WSTRB[7:0] | IN | Dee strobes |
| AXI_S_WLAST | IN | Dee ikpeazụ |
| AXI_S_WVALID | IN | Dee nke ọma |
| AXI_S_BREADY | IN | Dee njikere |
| AXI_S_ARID [3:0] | IN | Gụọ ID adreesị |
| AXI_S_ARADDR[31:0] | IN | Gụọ adreesị |
| AXI_S_ARLEN[3:0] | IN | Ogologo mgbawa |
| AXI_S_ARSIZE[1:0] | IN | Nha mgbawa |
| AXI_S_ARBURST[1:0] | IN | Ụdị mgbawa |
| AXI_S_ARLOCK[1:0] | IN | Ụdị mkpọchi |
| AXI_S_ARVALID | IN | Gụọ adreesị ziri ezi |
| AXI_S_RREADY | IN | Gụọ adreesị njikere |
| Aha Port | Ntuziaka | Nkọwa |
| AXI_S_CORE_RESET_N | IN | Ntọgharị zuru ụwa ọnụ MDR |
| AXI_S_RMW | IN | Na-egosi ma bytes niile nke ụzọ 64-bit dị irè maka nbugharị AXI niile.
|
AHB0 ụgbọ ala interface
Isiokwu 3-6 • AHB0 Ụgbọ ala Interface
| Aha Port | Ntuziaka | Nkọwa |
| AHB0_S_HREADYOUT | Mpụ | AHBL ohu njikere - Mgbe elu maka ederede na-egosi na ohu ahụ dị njikere ịnakwere data na mgbe elu maka ịgụ ihe na-egosi na data dị irè. |
| AHB0_S_HRESP | Mpụ | Ọnọdụ nzaghachi AHBL - Mgbe a na-ebuli elu na njedebe nke azụmahịa na-egosi na azụmahịa ahụ agwụla na njehie. Mgbe chụpụrụ ala na njedebe nke azụmahịa na-egosi na azụmahịa ahụ agwụla nke ọma. |
| AHB0_S_HRDATA[31:0] | Mpụ | AHBL gụọ data - Gụọ data sitere na ohu na nna ukwu |
| AHB0_S_HSEL | IN | AHBL ohu họrọ - Mgbe ekwuputara, ohu ahụ bụ ohu AHBL ahọpụtara ugbu a na bọs AHB. |
| AHB0_S_HADDR[31:0] | IN | Adreesị AHBL – adreesị byte na interface AHBL |
| AHB0_S_HBURST[2:0] | IN | Ogologo ogologo AHBL gbawara |
| AHB0_S_HSIZE[1:0] | IN | Nha mbufe AHBL - Na-egosi nha nke mbufe ugbu a (ịzụ ahịa byte 8/16/32 naanị) |
| AHB0_S_HTRANS[1:0] | IN | Ụdị mbufe AHBL - Na-egosi ụdị nnyefe nke azụmahịa dị ugbu a. |
| AHB0_S_HMASTLOCK | IN | Mkpọchi AHBL - Mgbe ekwuputara na mbufe ugbu a bụ akụkụ nke azụmahịa akpọchiri. |
| AHB0_S_HWRITE | IN | AHBL dee - Mgbe elu na-egosi na azụmahịa ugbu a bụ ederede. Mgbe ala na-egosi na azụmahịa ugbu a bụ ihe na-agụ. |
| AHB0_S_HREADY | IN | AHBL dị njikere - Mgbe elu, na-egosi na ohu ahụ dị njikere ịnakwere azụmahịa ọhụrụ. |
| AHB0_S_HWDATA[31:0] | IN | AHBL dee data - Dee data sitere na nna ukwu nye ohu ahụ |
AHB1 ụgbọ ala interface
Isiokwu 3-7 • AHB1 Ụgbọ ala Interface
| Aha Port | Ntuziaka | Nkọwa |
| AHB1_S_HREADYOUT | Mpụ | AHBL ohu njikere - Mgbe elu maka ederede, na-egosi na ohu ahụ dị njikere ịnakwere data, na mgbe ọ dị elu maka ịgụ ihe, na-egosi na data dị irè. |
| AHB1_S_HRESP | Mpụ | Ọnọdụ nzaghachi AHBL - Mgbe a na-ebuli elu na njedebe nke azụmahịa na-egosi na azụmahịa ahụ agwụla na njehie. Mgbe chụpụrụ ala na njedebe nke azụmahịa, na-egosi na azụmahịa ahụ agwụla nke ọma. |
| AHB1_S_HRDATA[31:0] | Mpụ | AHBL gụọ data - Gụọ data sitere na ohu na nna ukwu |
| AHB1_S_HSEL | IN | AHBL ohu họrọ - Mgbe ekwuputara, ohu ahụ bụ ohu AHBL ahọpụtara ugbu a na bọs AHB. |
| AHB1_S_HADDR[31:0] | IN | Adreesị AHBL – adreesị byte na interface AHBL |
| AHB1_S_HBURST[2:0] | IN | Ogologo ogologo AHBL gbawara |
| AHB1_S_HSIZE[1:0] | IN | Nha mbufe AHBL - Na-egosi nha nke nnyefe ugbu a (azụmahịa 8/16/32 byte naanị). |
| AHB1_S_HTRANS[1:0] | IN | Ụdị mbufe AHBL - Na-egosi ụdị nnyefe nke azụmahịa dị ugbu a. |
| AHB1_S_HMASTLOCK | IN | Mkpọchi AHBL - Mgbe ekwuputara, nnyefe ugbu a bụ akụkụ nke azụmahịa ekpochi. |
| AHB1_S_HWRITE | IN | AHBL dee - Mgbe elu, na-egosi na azụmahịa dị ugbu a bụ ederede. Mgbe ọ dị ala, na-egosi na azụmahịa dị ugbu a bụ agụ. |
| AHB1_S_HREADY | IN | AHBL dị njikere - Mgbe elu, na-egosi na ohu ahụ dị njikere ịnakwere azụmahịa ọhụrụ. |
| AHB1_S_HWDATA[31:0] | IN | AHBL dee data - Dee data sitere na nna ukwu nye ohu ahụ |
Nkwado ngwaahịa
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Websaịtị
Ị nwere ike ịchọgharị ozi dị iche iche nke teknuzu na nke na-abụghị teknụzụ na ibe ụlọ SoC, na www.microsemi.com/soc.
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Okwu m
Ndị ahịa Microsemi SoC Products Group nwere ike nyefee ma soro usoro nka na ntanetị site na ịga na nke m
N'èzí US
Ndị ahịa chọrọ enyemaka na mpụga mpaghara oge US nwere ike ịkpọtụrụ nkwado teknụzụ site na email (soc_tech@microsemi.com) ma ọ bụ kpọtụrụ ụlọ ọrụ ahịa mpaghara. Enwere ike ịchọta ndepụta ụlọ ọrụ ahịa na www.microsemi.com/soc/company/contact/default.aspx.
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Microsemi SmartFusion2 FPGA Fabric DDR Nhazi [pdf] Ntuziaka onye ọrụ SmartFusion2 FPGA Fabric DDR Nhazi, SmartFusion2, FPGA Fabric DDR Nhazi, Nhazi njikwa |
