Microsemi SmartFusion2 FPGA Fabric DDR Controller Configuration Guide Guide

Selelekela

SmartFusion2 FPGA e na le li-control tse peli tse kentsoeng tsa DDR - e 'ngoe e fumaneha ka MSS (MDDR)' me e 'ngoe e reretsoe ho fihlella ka ho toba ho tloha FPGA Fabric (FDDR). MDDR le FDDR ka bobeli li laola mehopolo ea DDR ea off-chip.
Ho hlophisa taolo ea Lesela la DDR ka botlalo o tlameha ho:

1. Sebelisa Fabric External Memory DDR Controller Configurator ho lokisa DDR Controller, khetha sebopeho sa eona sa libese tsa datapath (AXI kapa AHBLite), 'me u khethe maqhubu a oache ea DDR hammoho le maqhubu a oache ea datapath.
2. Beha litekanyetso tsa rejisetara bakeng sa lirejistara tsa molaoli oa DDR ho tsamaisana le litšobotsi tsa hau tsa memori ea DDR tse kantle.
3. Kenya Fabric DDR e le karolo ea ts'ebeliso ea mosebelisi 'me u etse likhokahano tsa datapath.
4. Hokela sehokelo sa APB sa DDR se laolang joalo ka ha se hlalositsoe ke Peripheral Initialization solution.

Lesela la Kantle la Memori DDR Controller Configurator

The Fabric External Memory DDR (FDDR) Configurator e sebelisetsoa ho lokisa datapath ka kakaretso le li-parameter tsa memori tsa DDR tsa ka ntle bakeng sa Fabric DDR Controller.

Setšoantšo sa 1-1 • FDDR Configurator Overview

Litlhophiso tsa memori 

Sebelisa Litlhophiso tsa Memori ho hlophisa likhetho tsa memori ea hau ho MDDR.

• Mofuta oa memori - LPDDR, DDR2, kapa DDR3
• Bophara ba Boitsebiso - 32-bit, 16-bit kapa 8-bit
• Kakaretso ea Clock - Boleng bofe kapa bofe (Decimal / Fractional) ho tloha ho 20 MHz ho isa ho 333 MHz
• SECDED Nobled ECC - HO BUA kapa HO TLOA
• 'Mapa oa Aterese {ROW,BANK,COLUMN},{BANK,ROW,COLUMN}

Litlhophiso tsa Sebopeho sa Lesela 

FPGA Fabric Interface - Ena ke khokahano ea data lipakeng tsa FDDR le moralo oa FPGA. Hobane FDDR ke molaoli oa memori, e reretsoe ho ba lekhoba ka beseng ea AXI kapa AHB. Mong'a bese o qala litšebelisano tsa libese, tseo hape li hlalosoang ke FDDR e le litšebelisano tsa memori mme li fetisetsoa ho off-chip DDR Memory. Likhetho tsa sebopeho sa lesela la FDDR ke:

• Ho sebelisa AXI-64 Interface - Mong'a e mong o fihlella FDDR ka sebopeho sa 64-bit \ AXI.
• Ho sebelisa Sehokelo se le seng sa AHB-32 - Monghali a le mong o fihlella FDDR ka sebopeho se le seng sa 32-bit AHB.
• Ho sebelisa li-interface tse peli tsa AHB-32 - Beng ba babeli ba fihlella FDDR ba sebelisa li-interfaces tse peli tsa 32-bit AHB.

FPGA Oache Karohano - E totobatsa sekhahla sa maqhubu pakeng tsa oache ea DDR Controller (CLK_FDDR) le oache e laolang sebopeho sa masela (CLK_FIC64). Maqhubu a CLK_FIC64 a lokela ho lekana le a AHB/AXI subsystem e hokahaneng le sebopeho sa libese sa FDDR AHB/AXI. Bakeng sa mohlalaample, haeba u na le DDR RAM e sebetsang ho 200 MHz 'me Sesebelisoa sa hau sa Fabric/AXI se sebetsa ho 100 MHz, u tlameha ho khetha karohano ea 2 (Setšoantšo sa 1-2).

Setšoantšo sa 1-2 • Litlhophiso tsa Sebopeho sa Lesela - AXI Interface le Tumellano ea FDDR Clock Divisor

Sebelisa Lesela PLL LEKOA - Haeba CLK_BASE e tsoa ho Fabric CCC, o ka hokela tlhahiso ea lesela la CCC LOCK ho kenyelletso ea FDDR FAB_PLL_LOCK. CLK_BASE ha e tsitsitse ho fihlela Fabric CCC e notlela. Ka hona, Microsemi e khothaletsa hore u tšoare FDDR ha u e seta bocha (ke hore, etsa tlhahiso ea CORE_RESET_N) ho fihlela CLK_BASE e tsitsitse. Tlhahiso ea LOCK ea Fabric CCC e bontša hore lioache tsa tlhahiso ea Fabric CCC li tsitsitse. Ka ho hlahloba khetho ea Sebelisa FAB_PLL_LOCK, u ka pepesa sebaka sa FAB_PLL_LOCK sa FDDR. Joale o ka hokela tlhahiso ea LOCK ea Lesela la CCC ho FAB_PLL_LOCK tlhahiso ea FDDR.

IO Drive Matla 

Khetha e 'ngoe ea matla a latelang a koloi bakeng sa DDR I/O ea hau:

• Half Drive Matla
• Matla a Drive a Felletseng

Ho ipapisitsoe le mofuta oa Memory ea DDR le matla a I/O ao u a khethang, Libero SoC e beha DDR I/O Standard bakeng sa sistimi ea hau ea FDDR ka tsela e latelang:

Mofuta oa memori ea DDR	Half Drive Matla	Matla a Drive a Felletseng
DDR3	SSTL15I	SSTL15II
DDR2	SSTL18I	SSTL18II
LPDDR	LPDRI	LPDRII

Numella Litšitiso 

FDDR e khona ho phahamisa litšitiso ha maemo a itseng a boletsoeng esale pele a khotsofatsoa. Sheba Enable Interrupts ho FDDR configurator haeba u ka rata ho sebelisa litšitiso tsena ts'ebelisong ea hau.
Sena se pepesa matšoao a tšitiso ketsahalong ea FDDR. O ka hokela matshwao ana a sitisang kamoo moralo wa hao o hlokang kateng. Matšoao a latelang a Khatiso le lipehelo tsa ona a teng:

• FIC_INT - E hlahisitsoe ha ho na le phoso khoebong lipakeng tsa Master le FDDR
• IO_CAL_INT - E o nolofalletsa ho nchafatsa DDR I/O's ka ho ngolla lirejistara tsa DDR o sebelisa sebopeho sa APB. Ha tlhahlobo e felile, tšitiso ena e ea phahamisoa. Bakeng sa lintlha tse mabapi le ntlafatso ea I/O, sheba Tataiso ea Basebelisi ba Microsemi SmartFusion2.
• PLL_LOCK_INT - E bontša hore FDDR FPLL e notletsoe
• PLL_LOCKLOST_INT - E bontša hore FDDR FPLL e lahlehetsoe ke senotlolo
• FDDR_ECC_INT - E bontša hore ho fumanoe phoso e le 'ngoe kapa tse peli

Lesela oache Frequency 

Palo ea maqhubu a oache e ipapisitseng le maqhubu a Oache a Oache le karohano ea OACH, e bonts'itsoeng ka MHz.
Lesela oache Frequency (ka MHz) = Clock Frequency / CLOCK divisor

Bandwidth ea memori 

Palo ea bandwidth ea memori e ipapisitseng le boleng ba Clock Frequency ea hau ho Mbps.
Bandwidth ea Memori (ka Mbps) = 2 * Maqhubu a Oache

Kakaretso ea Bandwidth

Kakaretso ea lipalo tsa "bandwidth" e ipapisitseng le "Clock Frequency", "Data Width" le "CLOCK divisor" ho Mbps.
Kakaretso ea Bandwidth (ka Mbps) = (2 * Maqhubu a Oache * Bophara ba Boitsebiso) / CLOCK Divisor

Tlhophiso ea Molaoli oa FDDR

Ha o sebelisa Fabric DDR Controller ho fihlella DDR Memory e kantle, DDR Controller e tlameha ho hlophisoa ka nako ea ts'ebetso. Sena se etsoa ka ho ngola lintlha tsa tlhophiso ho lirejistara tse inehetseng tsa DDR controller. Lintlha tsena tsa tlhophiso li ipapisitse le litšobotsi tsa memori ea kantle ea DDR le ts'ebeliso ea hau. Karolo ena e hlalosa mokhoa oa ho kenya li-parameter tsena tsa tlhophiso ho configurator ea FDDR controller le hore na data ea tlhophiso e laoloa joang e le karolo ea tharollo ea kakaretso ea Peripheral Initialization. Sheba ho Peripheral Initialization User Guide bakeng sa lintlha tse felletseng mabapi le tharollo ea Peripheral Initialization.

Masela a DDR Control Registers 

The Fabric DDR Controller e na le li-registerers tse hlokang ho hlophisoa ka nako ea ho sebetsa. Maemo a tlhophiso bakeng sa lirejiseta tsena a emela liparamente tse fapaneng (bakeng sa mohlalaample, mokhoa oa DDR, bophara ba PHY, mokhoa oa ho phatloha, ECC, joalo-joalo). Bakeng sa lintlha tse mabapi le lirejistara tsa tlhophiso ea taolo ea DDR, sheba Tataiso ea mosebelisi ea Microsemi SmartFusion2.

Lesela DDR Registaras Configuration 

Sebelisa li-tab tsa ho Qala Memori (setšoantšo sa 2-1) le Li-Timing Nako (setšoantšo sa 2-2) ho kenya li-parameter tse tsamaellanang le Memori ea DDR le ts'ebeliso ea hau. Lipalo tseo u li kenyang ho li-tab tsena li fetoleloa ka bo eona ho ea ho litekanyetso tse loketseng tsa rejisetara. Ha o tobetsa parameter e itseng, ngoliso ea eona e lumellanang e hlalositsoe ho Fensetere ea Tlhaloso ea Ngoliso (Setšoantšo sa 1-1 leqepheng la 4).

Setšoantšo sa 2-1 • Tlhophiso ea FDDR - Taba ea ho Qala Memori

Setšoantšo sa 2-2 • Tlhophiso ea FDDR - Taba ea Nako ea Memori

E kenya DDR Configuration Files

Ntle le ho kenya liparamente tsa Memori ea DDR u sebelisa li-tabo tsa Memory Initialization le Nako, o ka kenya boleng ba ngoliso ea DDR ho tsoa ho file. Ho etsa joalo, tobetsa konopo ea Import Configuration ebe u ea ho mongolo file e nang le mabitso a ngoliso ea DDR le boleng. Setšoantšo sa 2-3 se bontša syntax ea tlhophiso ea ho kenya.

Setšoantšo sa 2-3 • Tlhophiso ea Ngoliso ea DDR File Syntax

Hlokomela: Haeba o khetha ho tlisa boleng ba ngoliso ho fapana le ho bo kenya o sebelisa GUI, o tlameha ho hlakisa boleng bohle bo hlokahalang ba ngoliso. Sheba ho SmartFusion2 User Guide bakeng sa lintlha

E romela DDR Configuration Files

U ka boela ua romella lintlha tsa hajoale tsa tlhophiso ea ngoliso ho mongolo file. Sena file e tla ba le litekanyetso tsa ngoliso tseo u li tlisitseng kantle ho naha (haeba li teng) hammoho le tse bakiloeng ho tsoa ho li-parameter tsa GUI tseo u li kentseng lebokoseng lena la puisano.
Haeba u batla ho etsolla liphetoho tseo u li entseng ho tlhophiso ea ngoliso ea DDR, u ka etsa joalo ka Restore Default. Sena se hlakola lintlha tsohle tsa tlhophiso ea ngoliso mme o tlameha ho kenya hape kapa ho kenya data ena hape. Lintlha li seta botjha ho boleng ba ho seta botjha ha hardware.

Lintlha tse hlahisitsoeng 

Tobetsa OK ho etsa tlhophiso. Ho ipapisitsoe le seo u se kentseng ho li-tabo tsa Kakaretso, Nako ea Memori le ho Qala Memori, FDDR Configurator e kopanya boleng ba lirekoto tsohle tsa tlhophiso ea DDR ebe e romela boleng bona ho projeke ea hau ea firmware le papiso. files. E romelloang kantle ho naha file syntax e bontšoa ho Setšoantšo sa 2-4.

Setšoantšo sa 2-4 • Tlhophiso ea Rejistara ea DDR e romelloang kantle File Syntax

Firmware

Ha o hlahisa SmartDesign, tse latelang files li hlahisoa bukeng ea /firmware/drivers_config/sys_config. Tsena files lia hlokahala hore setsi sa firmware sa CMSIS se hlophise hantle 'me se be le leseli mabapi le moetso oa hau oa hajoale, ho kenyeletsoa le data ea tlhophiso ea peripheral le tlhaiso-leseling ea lioache bakeng sa MSS. Se ke oa hlophisa tsena files ka letsoho, ha li ntse li etsoa bocha nako le nako ha moralo oa hau oa motso o nchafatsoa.

• sys_config.c
• sys_config.h
• sys_config_mddr_define.h - MDDR dintlha tsa tlhophiso.
• sys_config_fddr_define.h - data ea tlhophiso ea FDDR.
• sys_config_mss_clocks.h – tlhophiso ea lioache tsa MSS

Ketsiso

Ha o hlahisa SmartDesign e amanang le MSS ea hau, ketsiso e latelang files li hlahisoa bukeng ea /simulation:

• teko.bfm - BFM ea boemo bo holimo file e qala ho etsoa nakong ea papiso efe kapa efe e sebelisang processor ea SmartFusion2 MSS Cortex-M3. E etsa peripheral_init.bfm le user.bfm, ka tatellano eo.
• peripheral_init.bfm - E na le ts'ebetso ea BFM e etsisang CMSIS::SystemInit() ts'ebetso e tsamaisoang ho Cortex-M3 pele o kenya () ts'ebetso. E kopitsa lintlha tsa tlhophiso bakeng sa peripheral efe kapa efe e sebelisitsoeng moahong ho lirejisetara tse nepahetseng tsa tlhophiso ebe e emela hore li-peripheral kaofela li be malala-a-laotsoe pele e tiisa hore mosebelisi a ka sebelisa li-peripherals tsena.
• FDDR_init.bfm - E na le litaelo tsa ho ngola tsa BFM tse etsisang mongolo oa data ea register ea tlhophiso ea Lesela la DDR eo u e kentseng (u sebelisa lebokose la puisano la Edit Registers) lirejiseteng tsa DDR Controller.
• mosebedisi.bfm - E etselitsoe litaelo tsa basebelisi. U ka etsisa datapath ka ho eketsa litaelo tsa hau tsa BFM ho sena file. Litaelo ho sena file e tla etsoa ka mor'a hore peripheral_init.bfm e phethe.

Ho sebelisa the files ka holimo, tsela ea tlhophiso e etsisoa ka bo eona. U hloka feela ho fetola user.bfm file ho etsisa datapath. Se ke oa fetola test.bfm, peripheral_init.bfm, kapa MDDR_init.bfm files joalo ka tsena files li etsoa bocha nako le nako ha moralo oa hau oa metso o nchafatsoa.

Lesela DDR Configuration Tsela 

Pheripheral Initialization tharollo e hloka hore, ntle le ho hlakisa boleng ba rejisetara ea tlhophiso ea Lesela la DDR, o lokise tsela ea data ea tlhophiso ea APB ho MSS (FIC_2). Ts'ebetso ea SystemInit() e ngola lintlha ho lirejistara tsa tlhophiso ea FDDR ka sebopeho sa FIC_2 APB.

Hlokomela: Haeba o sebelisa System Builder, tsela ea tlhophiso e tla beoa ebe e hokahanngoa ka bo eona.

Setšoantšo sa 2-5 • FIC_2 Configurator Overview

Ho lokisa sebopeho sa FIC_2:

1. Bula lebokose la tlhophiso la FIC_2 (setšoantšo sa 2-5) ho tsoa ho setlhophiso sa MSS.
2. Khetha khetho ea Initialize peripherals u sebelisa khetho ea Cortex-M3.
3. Etsa bonnete ba hore MSS DDR e khethiloe, joalo ka li-block tsa Lesela la DDR/SERDES ha u li sebelisa.
4. Tobetsa OK ho boloka litlhophiso tsa hau. Sena se pepesa likou tsa tlhophiso tsa FIC_2 (Clock, Reset, le APB bus interfaces), joalo ka ha ho bonts'itsoe ho Setšoantšo sa 2-6.
5. Hlahisa MSS. Likou tsa FIC_2 (FIC_2_APB_MASTER, FIC_2_APB_M_PCLK le FIC_2_APB_M_RESET_N) li se li pepesitsoe ho MSS interface 'me li ka hokeloa ho CoreSF2Config le CoreSF2Reset ho latela Peripheral Initialization solution.

Setšoantšo sa 2-6 • FIC_2 Boema-kepe

Tlhaloso ea Boema-kepe

FDDR Core Ports 

Letlapa la 3-1 • FDDR Core Ports

Lebitso la Port	Tataiso	Tlhaloso
CORE_RESET_N	IN	Seta hape Selaoli sa FDDR
CLK_BASE	IN	FDDR Fabric Interface Clock
FPLL_LOCK	TSOA	FDDR PLL Lock e hlahisoang - e phahame ha FDDR PLL e notletsoe
CLK_BASE_PLL_LOCK	IN	Lesela PLL Lock Input. Kenyelletso ena e hlaha feela ha ho khethiloe khetho ea Sebelisa FAB_PLL_LOCK.

Khaotsa Maemakepe

Sehlopha sena sa likou sea pepesoa ha u khetha Enable Interrupts kgetho.

Lethathamo la 3-2 • Khaotsa Maemakepe

Lebitso la Port	Tataiso	Tlhaloso
PLL_LOCK_INT	TSOA	E tiisa ha FDDR PLL e notlela.
PLL_LOCKLOST_INT	TSOA	E bolela ha senotlolo sa FDDR PLL se lahlehile.
ECC_INT	TSOA	E bolela ha Ketsahalo ea ECC e etsahala.
IO_CALIB_INT	TSOA	E bolela ha I/O e phethiloe.
FIC_INT	TSOA	E bolela ha ho na le phoso ho protocol ea AHB/AXI ho sebopeho sa Lesela.

APB3 Configuration Interface 

Tafole 3-3 • APB3 Configuration Interface

Lebitso la Port	Tataiso	Tlhaloso
APB_S_PENABLE	IN	Lekhoba Le nolofalletse
APB_S_PSEL	IN	Khetha Makhoba
APB_S_PWRITE	IN	Ngola Thusa
APB_S_PADDR[10:2]	IN	Aterese
APB_S_PWDATA[15:0]	IN	Ngola Lintlha
APB_S_PREADY	TSOA	Lekhoba le Itokisitse
APB_S_PSLVERR	TSOA	Phoso ea Makhoba
APB_S_PRDATA[15:0]	TSOA	Bala Lintlha
APB_S_PRESET_N	IN	Lekhoba Reset
APB_S_PCLK	IN	Tshupanako

DDR PHY Interface 

Lethathamo la 3-4 • DDR PHY Interface 

Lebitso la Port	Tataiso	Tlhaloso
FDDR_CAS_N	TSOA	DRAM CASN
FDDR_CKE	TSOA	DRAM CKE
FDDR_CLK	TSOA	Tshupanako, lehlakore la P
FDDR_CLK_N	TSOA	Tshupanako, N side
FDDR_CS_N	TSOA	DRAM CSN
FDDR_ODT	TSOA	DRAM ODT
FDDR_RAS_N	TSOA	DRAM RASN
FDDR_RESET_N	TSOA	Seta bocha DRAM bakeng sa DDR3
FDDR_WE_N	TSOA	TERAMA WEN
FDDR_ADDR[15:0]	TSOA	Likotoana tsa Aterese ea Dram
FDDR_BA[2:0]	TSOA	Aterese ea Banka ea Dram
FDDR_DM_RDQS[4:0]	LIEKETSENG	Dram Data Mask
FDDR_DQS[4:0]	LIEKETSENG	Dram Data Strobe Input/Output – P Side
FDDR_DQS_N[4:0]	LIEKETSENG	Dram Data Strobe Input/Output – N Side
FDDR_DQ[35:0]	LIEKETSENG	DRAM Data Input/Output
FDDR_FIFO_WE_IN[2:0]	IN	FIFO ka pontšo
FDDR_FIFO_WE_OUT[2:0]	TSOA	FIFO e tsoa letšoao
FDDR_DM_RDQS ([3:0]/[1:0]/[0])	LIEKETSENG	Dram Data Mask
FDDR_DQS ([3:0]/[1:0]/[0])	LIEKETSENG	Dram Data Strobe Input/Output – P Side
FDDR_DQS_N ([3:0]/[1:0]/[0])	LIEKETSENG	Dram Data Strobe Input/Output – N Side
FDDR_DQ ([31:0]/[15:0]/[7:0])	LIEKETSENG	DRAM Data Input/Output
FDDR_DQS_TMATCH_0_IN	IN	FIFO ka pontšo
FDDR_DQS_TMATCH_0_OUT	TSOA	FIFO e tsoa letšoao
FDDR_DQS_TMATCH_1_IN	IN	FIFO ho lets'oao (32-bit feela)
FDDR_DQS_TMATCH_1_OUT	TSOA	Lets'oao la FIFO (32-bit feela)
FDDR_DM_RDQS_ECC	LIEKETSENG	Dram ECC Data Mask
FDDR_DQS_ECC	LIEKETSENG	Dram ECC Data Strobe Input/Output – P Side
FDDR_DQS_ECC_N	LIEKETSENG	Dram ECC Data Strobe Input/Output – N Side
FDDR_DQ_ECC ([3:0]/[1:0]/[0])	LIEKETSENG	DRAM ECC Data Input/Output
FDDR_DQS_TMATCH_ECC_IN	IN	ECC FIFO ka pontšo
FDDR_DQS_TMATCH_ECC_OUT	TSOA	ECC FIFO lets'oao la kantle (32-bit feela)

Hlokomela: Bophahamo ba likou bakeng sa likou tse ling boa fetoha ho latela khetho ea bophara ba PHY. Mantsoe “[a:0]/ [b:0]/[c:0]” a sebelisoa ho supa likou tse joalo, moo “[a:0]” e supang bophara ba kou ha ho khethoa bophara ba 32-bit PHY. , “[b:0]” e tsamaellana le bophara ba 16-bit PHY, le “[c:0]” e tsamaellana le 8-bit PHY bophara.

AXI Bus Interface 

Letlapa la 3-5 • AXI Bus Interface

Lebitso la Port	Tataiso	Tlhaloso
AXI_S_E HLOKOMELA	TSOA	Ngola aterese e lokile
MOLENTSI_S_BOHLOKO	TSOA	Ngola aterese e lokile
AXI_S_BID[3:0]	TSOA	ID ea karabo
AXI_S_BRSP[1:0]	TSOA	Ngola karabo
AXI_S_BVALID	TSOA	Ngola karabo e nepahetse
AXI_S_ARREA	TSOA	Bala aterese e lokile
AXI_S_RID[3:0]	TSOA	Bala ID Tag
AXI_S_RRSP[1:0]	TSOA	Bala Karabo
AXI_S_RDATA[63:0]	TSOA	Bala data
AXI_S_RLAST	TSOA	Bala ho Qetela - Letšoao lena le bontša phetisetso ea ho qetela ka ho phatloha ho hoholo.
AXI_S_RVALID	TSOA	Aterese ea ho bala e nepahetse
AXI_S_AWID[3:0]	IN	Ngola Aterese ID
AXI_S_AWADDR[31:0]	IN	Ngola aterese
AXI_S_AWLEN[3:0]	IN	Bolelele ba ho phatloha
AXI_S_AWSIZE[1:0]	IN	Boholo ba ho phatloha
AXI_S_AWBURST[1:0]	IN	Mofuta oa ho phatloha
AXI_S_AWLOCK[1:0]	IN	Mofuta oa Lock - Letšoao lena le fana ka tlhahisoleseling e eketsehileng mabapi le litšobotsi tsa athomo tsa phetiso.
AXI_S_AWVALID	IN	Ngola aterese e nepahetse
AXI_S_WID[3:0]	IN	Ngola Data ID tag
AXI_S_WDATA[63:0]	IN	Ngola lintlha
AXI_S_WSTRB[7:0]	IN	Ngola strobes
AXI_S_WLAST	IN	Ngola qetellong
AXI_S_WVALID	IN	Ngola e nepahetse
AXI_S_BRETHA	IN	Ngola o itokisitse
AXI_S_ARID[3:0]	IN	Bala ID ea Aterese
AXI_S_ARADDR[31:0]	IN	Bala aterese
AXI_S_ARLEN[3:0]	IN	Bolelele ba ho phatloha
AXI_S_ARSIZE[1:0]	IN	Boholo ba ho phatloha
AXI_S_ARBURST[1:0]	IN	Mofuta oa ho phatloha
AXI_S_ARLOCK[1:0]	IN	Mofuta oa Lock
AXI_S_ARVALID	IN	Aterese ea ho bala e nepahetse
AXI_S_RETHAKILE	IN	Bala aterese e lokile
Lebitso la Port	Tataiso	Tlhaloso
AXI_S_CORE_RESET_N	IN	MDDR Global Reset
AXI_S_RMW	IN	E bontša hore na li-byte tsohle tsa 64-bit lane li nepahetse bakeng sa li-beats tsohle tsa phetisetso ea AXI. E bontša hore li-byte tsohle ho li-beats tsohle li sebetsa ha ho phatloha 'me molaoli o lokela ho lula a ngola litaelo. E bontša hore li-byte tse ling ha li sebetse 'me molaoli o lokela ho latela litaelo tsa RMW. Sena se khethiloe e le lets'oao la lehlakore la AXI la aterese mme le sebetsa ka lets'oao la AWVALID. E sebelisoa feela ha ECC e butse.

AHB0 Bus Interface 

Lethathamo la 3-6 • AHB0 Bus Interface 

Lebitso la Port	Tataiso	Tlhaloso
AHB0_S_HREADYOUT	TSOA	AHBL lekhoba le itokiselitse - Ha e phahame bakeng sa ho ngola e bontša hore lekhoba le se le itokiselitse ho amohela data mme ha le phahame bakeng sa ho bala le bontša hore data e nepahetse.
AHB0_S_HRSP	TSOA	Boemo ba karabo ea AHBL - Ha e tsamaisoa holimo qetellong ea transaction e bontša hore transaction e phethiloe ka liphoso. Ha e tsamaisoa tlase qetellong ea transaction e bontša hore transaction e phethiloe ka katleho.
AHB0_S_HRDATA[31:0]	TSOA	AHBL bala data - Bala data ho tloha ho lekhoba ho ea ho mong'a lona
AHB0_S_HSEL	IN	Khetho ea makhoba a AHBL - Ha ho boleloa, lekhoba ke lekhoba le khethiloeng hajoale la AHBL ka beseng ea AHB.
AHB0_S_HADDR[31:0]	IN	Aterese ea AHBL - aterese ea byte ho sebopeho sa AHBL
AHB0_S_HBURST[2:0]	IN	AHBL Burst Length
AHB0_S_HSIZE[1:0]	IN	Boholo ba phetisetso ea AHBL - E bonts'a boholo ba phetisetso ea hajoale (8/16/32 byte transactions feela)
AHB0_S_HTRANS[1:0]	IN	Mofuta oa phetisetso ea AHBL - E bontša mofuta oa phetisetso ea transaction ea hajoale.
AHB0_S_HMASTLOCK	IN	AHBL Lock - Ha ho boleloa hore phetisetso ea hajoale ke karolo ea khoebo e notletsoeng.
AHB0_S_HWRITE	IN	AHBL ngola - Ha holimo ho bontša hore transaction ea hona joale ke ho ngola. Ha tlase e bontša hore transaction ea hajoale e baloa.
AHB0_S_HARE	IN	AHBL e loketse - Ha e phahame, e bontša hore lekhoba le itokiselitse ho amohela khoebo e ncha.
AHB0_S_HWDATA[31:0]	IN	AHBL ngola lintlha - Ngola lintlha ho tloha ho monghali ho ea ho lekhoba

AHB1 Bus Interface 

Lethathamo la 3-7 • AHB1 Bus Interface

Lebitso la Port	Tataiso	Tlhaloso
AHB1_S_HREADYOUT	TSOA	AHBL lekhoba le itokiselitse - Ha le phahame bakeng sa ho ngola, le bontša hore lekhoba le itokiselitse ho amohela data, 'me ha le phahame bakeng sa ho bala, le bontša hore data e nepahetse.
AHB1_S_HRSP	TSOA	Boemo ba karabo ea AHBL - Ha e tsamaisoa holimo qetellong ea transaction e bontša hore transaction e phethiloe ka liphoso. Ha e theohile qetellong ea transaction, e bontša hore transaction e phethiloe ka katleho.
AHB1_S_HRDATA[31:0]	TSOA	AHBL bala data - Bala data ho tloha ho lekhoba ho ea ho mong'a lona
AHB1_S_HSEL	IN	Khetho ea makhoba a AHBL - Ha ho boleloa, lekhoba ke lekhoba le khethiloeng hajoale la AHBL ka beseng ea AHB.
AHB1_S_HADDR[31:0]	IN	Aterese ea AHBL - aterese ea byte ho sebopeho sa AHBL
AHB1_S_HBURST[2:0]	IN	AHBL Burst Length
AHB1_S_HSIZE[1:0]	IN	Boholo ba phetisetso ea AHBL - E bonts'a boholo ba phetiso ea hajoale (8/16/32 byte transactions feela).
AHB1_S_HTRANS[1:0]	IN	Mofuta oa phetisetso ea AHBL - E bontša mofuta oa phetisetso ea transaction ea hajoale.
AHB1_S_HMASTLOCK	IN	AHBL lock - Ha ho boleloa, phetisetso ea hona joale ke karolo ea transaction e notletsoeng.
AHB1_S_HWRITE	IN	AHBL ngola - Ha e phahame, e bontša hore transaction ea hona joale ke ho ngola. Ha e le tlase, e bontša hore transaction ea hajoale e baloa.
AHB1_S_HARE	IN	AHBL e loketse - Ha e phahame, e bontša hore lekhoba le itokiselitse ho amohela khoebo e ncha.
AHB1_S_HWDATA[31:0]	IN	AHBL ngola lintlha - Ngola lintlha ho tloha ho monghali ho ea ho lekhoba

Tšehetso ea Sehlahisoa

Microsemi SoC Products Group e tšehetsa lihlahisoa tsa eona ka lits'ebeletso tse fapaneng tsa ts'ehetso, ho kenyeletsoa Tšebeletso ea Bareki, Setsi sa Ts'ehetso ea Tekheniki ea Bareki, a websebaka, mangolo a elektroniki, le liofisi tsa thekiso lefatšeng ka bophara. Sehlomathiso sena se na le tlhahisoleseling mabapi le ho ikopanya le Sehlopha sa Lihlahisoa tsa Microsemi SoC le ho sebelisa lits'ebeletso tsena tsa tšehetso.

Tšebeletso ea bareki 

Ikopanye le Tshebeletso ya Bareki bakeng sa tshehetso ya dihlahiswa tseo e seng tsa botekgeniki, jwalo ka ditheko tsa sehlahiswa, dintlafatso tsa sehlahiswa, tlhahisoleseding e ntjhafatsa, boemo ba odara, le tumello.
Ho tsoa Amerika Leboea, letsetsa 800.262.1060
Ho tsoa lefats'eng lohle, letsetsa 650.318.4460
Fax, ho tsoa kae kapa kae lefatšeng, 408.643.6913

Setsi sa Tšehetso ea Theknoloji ea Bareki 

Sehlopha sa Microsemi SoC Products se na le Setsi sa Ts'ehetso sa Bareki sa Theknoloji se nang le lienjiniere tse nang le litsebo tse phahameng tse ka u thusang ho araba lisebelisoa tsa hau tsa thepa, software, le lipotso tsa moralo mabapi le Lihlahisoa tsa Microsemi SoC. The Customer Technical Support Center e qeta nako e ngata e etsa lintlha tsa kopo, likarabo tsa lipotso tse tloaelehileng tsa potoloho ea moralo, litokomane tsa litaba tse tsejoang, le Lipotso tse fapa-fapaneng. Kahoo, pele o ikopanya le rona, ka kopo etela lisebelisoa tsa rona tsa inthanete. Ho ka etsahala hore ebe re se re arabile lipotso tsa hau.

Tšehetso ea tekheniki 

Etela Tšehetso ea Bareki websaete (www.microsemi.com/soc/support/search/default.aspx) bakeng sa tlhaiso-leseling e batsi le tšehetso. Likarabo tse ngata li fumaneha ka mokhoa oa ho batla web lisebelisoa li kenyelletsa litšoantšo, lipapiso, le lihokelo ho lisebelisoa tse ling ho websebaka.

Websebaka

U ka bala lintlha tse fapaneng tsa tekheniki le tseo e seng tsa tekheniki leqepheng la lehae la SoC, ho www.microsemi.com/soc.

Ho ikopanya le Setsi sa Tšehetso ea Theknoloji ea Bareki 

Baenjiniere ba nang le litsebo tse phahameng ba sebetsa Setsing sa Tšehetso sa Tekheniki. Setsi sa Tšehetso ea Tekheniki se ka ikopanya le lengolo-tsoibila kapa ka Sehlopha sa Lihlahisoa tsa Microsemi SoC websebaka.

Email

O ka buisana le lipotso tsa hau tsa tekheniki atereseng ea rona ea lengolo-tsoibila mme oa fumana likarabo ka lengolo-tsoibila, fax kapa mohala. Hape, haeba u na le mathata a moralo, u ka romella moralo oa hau ka lengolo-tsoibila files ho fumana thuso. Re lula re beha leihlo ak'haonte ea lengolo-tsoibila letsatsi lohle. Ha o romella kopo ea hau ho rona, ka kopo etsa bonnete ba hore o kenyelletsa lebitso la hau le felletseng, lebitso la k'hamphani, le tlhaiso-leseling ea hau ea ho ikopanya le rona bakeng sa ts'ebetso e nepahetseng ea kopo ea hau. Aterese ea imeile ea tšehetso ea tekheniki ke soc_tech@microsemi.com.

Linyeoe Tsaka 

Bareki ba Microsemi SoC Products Group ba ka fana ka le ho latela linyeoe tsa tekheniki inthaneteng ka ho ea ho My Case

Ka ntle ho US 

Bareki ba hlokang thuso ka ntle ho libaka tsa nako tsa US ba ka ikopanya le tšehetso ea tekheniki ka lengolo-tsoibila (soc_tech@microsemi.com) kapa ikopanye le ofisi ea thekiso ea lehae. Lethathamo la liofisi tsa thekiso li ka fumanoa ho www.microsemi.com/soc/company/contact/default.aspx.

ITAR Tšehetso ea Theknoloji

Bakeng sa tšehetso ea tekheniki ho RH le RT FPGAs tse laoloang ke International Traffic in Arms Regulations (ITAR), ikopanye le rona ka soc_tech_itar@microsemi.com. Ntle le moo, ka har'a Maemo a Ka, khetha E, lethathamong la ho theoha ha ITAR. Bakeng sa lenane le felletseng la li-FPGA tsa Microsemi tse laoloang ke ITAR, etela ITAR web leqephe.

Microsemi Corporation (NASDAQ: MSCC) e fana ka mosebetsi o pharaletseng oa tharollo ea semiconductor bakeng sa: sefofane, tšireletso le tšireletso; khoebo le lipuisano; le limmaraka tsa liindasteri le mefuta e meng ea matla. Lihlahisoa li kenyelletsa lisebelisoa tse phahameng tsa ts'ebetso, li-analog tse tšepahalang haholo le lisebelisoa tsa RF, lets'oao le tsoakiloeng le li-circuits tse kopaneng tsa RF, li-SoCs tse ikhethileng, li-FPGA, le li-subsystems tse felletseng. Microsemi e ikarabella ho Aliso Viejo, Calif. Ithute haholoanyane ho www.microsemi.com.

© 2014 Microsemi Corporation. Litokelo tsohle li sirelelitsoe. Microsemi le logo ea Microsemi ke matšoao a khoebo a Microsemi Corporation. Matshwao a mang kaofela a kgwebo le matshwao a ditshebeletso ke thepa ya beng ba ona ka ho fapana.

Ntlo-khōlō ea Khoebo ea Microsemi
Khoebo e le 'ngoe, Aliso Viejo CA 92656 USA
Ka hare ho USA: +1 949-380-6100
Lithekiso: +1 949-380-6136
Fax: +1 949-215-4996

Litokomane / Lisebelisoa

Microsemi SmartFusion2 FPGA Fabric DDR Controller Configuration [pdf] Bukana ea Mosebelisi Sebopeho sa SmartFusion2 FPGA Fabric DDR Controller Configuration, SmartFusion2, FPGA Fabric DDR Controller Configuration, Controller Configuration

Litšupiso

• Bukana ea Mosebelisi