Microsemi SmartFusion2 FPGA Fabric DDR Adarí User iṣeto ni

Ọrọ Iṣaaju

SmartFusion2 FPGA ni awọn olutona DDR meji ti a fi sinu - ọkan wa nipasẹ MSS (MDDR) ati ekeji ti a pinnu fun iraye si taara lati FPGA Fabric (FDDR). MDR ati FDDR mejeeji ṣakoso awọn iranti DDR ni pipa-chip.
Lati tunto ni kikun oluṣakoso Fabric DDR o gbọdọ:

1. Lo awọn Fabric Ita Memory DDR Adarí Configurator to a tunto DDR Adarí, yan awọn oniwe-datapath akero ni wiwo (AXI tabi AHBlite), ki o si yan DDR aago igbohunsafẹfẹ bi daradara bi fabric datapath aago igbohunsafẹfẹ.
2. Ṣeto awọn iye iforukọsilẹ fun awọn iforukọsilẹ oluṣakoso DDR lati baamu awọn abuda iranti DDR ita rẹ.
3. Ṣe agbekalẹ DDR Fabric gẹgẹbi apakan ti ohun elo olumulo kan ki o ṣe awọn asopọ datapath.
4. So DDR adarí APB ni wiwo iṣeto ni bi asọye nipa Agbeegbe Initialization ojutu.

Fabric Ita Memory DDR Adarí Configurator

Oluṣeto Ibi-ipamọ Ita Ita Fabric DDR (FDDR) ni a lo lati tunto ọna data gbogbogbo ati awọn aye iranti DDR ita fun Alakoso Fabric DDR.

olusin 1-1 • FDDR Configurator Overview

Eto iranti 

Lo Eto Iranti lati tunto awọn aṣayan iranti rẹ ni MDDR.

• Iranti Iru - LPDDR, DDR2, tabi DDR3
• Iwọn Data - 32-bit, 16-bit tabi 8-bit
• Aago igbohunsafẹfẹ - Eyikeyi iye (Decimal/Ipin) ni sakani 20 MHz si 333 MHz
• SECDED Ṣiṣẹ ECC – TAN tabi PA
• Iyatọ adirẹsi – {ROW,BANK,COLUMN},{BANK,ROW,COLUMN}

Aso Interface Eto 

FPGA Fabric Interface - Eyi ni wiwo data laarin FDDR ati apẹrẹ FPGA. Nitori FDDR jẹ oludari iranti, o ti pinnu lati jẹ ẹrú lori ọkọ akero AXI tabi AHB. Titunto si ti bosi pilẹṣẹ akero lẹkọ, eyi ti o wa ni Tan tumo nipasẹ awọn FDDR bi iranti lẹkọ ati ki o mimq si pa-ërún DDR Memory. Awọn aṣayan wiwo aṣọ FDDR jẹ:

• Lilo wiwo AXI-64 – Titunto si iwọle si FDDR nipasẹ wiwo 64-bit \ AXI kan.
• Lilo Interface AHB-32 Nikan - Titunto si iwọle si FDDR nipasẹ wiwo AHB 32-bit kan ṣoṣo.
• Lilo Awọn atọkun AHB-32 Meji - Awọn oluwa meji wọle si FDDR ni lilo awọn atọkun AHB 32-bit meji.

FPGA Aago Divisor - Ni pato ipin igbohunsafẹfẹ laarin aago Alakoso DDR (CLK_FDDR) ati aago ti n ṣakoso wiwo aṣọ (CLK_FIC64). Igbohunsafẹfẹ CLK_FIC64 yẹ ki o dọgba si ti AHB/AXI subsystem ti o ni asopọ si wiwo ọkọ akero FDDR AHB/AXI. Fun example, ti o ba ti o ba ni a DDR Ramu nṣiṣẹ ni 200 MHz ati awọn rẹ Fabric / AXI Subsystem nṣiṣẹ ni 100 MHz, o gbọdọ yan a pin 2 (olusin 1-2).

Ṣe nọmba 1-2 • Awọn Eto Ibaraẹnisọrọ Aṣọ - Ibaraẹnisọrọ AXI ati Adehun Pipin Aago FDDR

Lo Aṣọ PLL Titiipa - Ti CLK_BASE ba wa lati inu CCC Fabric kan, o le so iṣelọpọ CCC LOCK aṣọ si titẹ sii FDDR FAB_PLL_LOCK. CLK_BASE ko duro titi ti Aṣọ CCC tilekun. Nitorinaa, Microsemi ṣeduro pe ki o di FDDR mu ni atunto (ie, sọ titẹ sii CORE_RESET_N) titi CLK_BASE yoo fi duro. Ijade LOCK ti Fabric CCC tọkasi pe awọn aago iṣelọpọ Fabric CCC jẹ iduroṣinṣin. Nipa ṣiṣe ayẹwo Lo FAB_PLL_LOCK aṣayan, o le fi FAB_PLL_LOCK ibudo titẹ sii ti FDDR han. Lẹhinna o le so iṣelọpọ LOCK ti Fabric CCC pọ si igbewọle FAB_PLL_LOCK ti FDDR.

IO wakọ Agbara 

Yan ọkan ninu awọn agbara awakọ wọnyi fun DDR I/O's rẹ:

• Idaji wakọ Agbara
• Kikun wakọ Agbara

Ti o da lori iru iranti DDR rẹ ati I / O Agbara ti o yan, Libero SoC ṣeto Ipele I/O DDR fun eto FDDR rẹ gẹgẹbi atẹle:

DDR Memory Iru	Idaji wakọ Agbara	Kikun wakọ Agbara
DDR3	SSTL15I	SSTL15II
DDR2	SSTL18I	SSTL18II
LPDDR	LPDRI	LPDRII

Mu Awọn Idilọwọ ṣiṣẹ 

FDDR ni agbara lati gbe awọn idalọwọduro dide nigbati awọn ipo asọye tẹlẹ ni itẹlọrun. Ṣayẹwo Mu Awọn Idilọwọ ṣiṣẹ ni atunto FDDR ti o ba fẹ lati lo awọn idalọwọduro wọnyi ninu ohun elo rẹ.
Eyi ṣafihan awọn ifihan agbara idalọwọduro lori apẹẹrẹ FDDR. O le so awọn ifihan agbara idalọwọduro wọnyi pọ bi apẹrẹ rẹ ṣe nilo. Awọn ifihan agbara Idilọwọ atẹle ati awọn ipo iṣaaju wọn wa:

• FIC_INT – Ti ipilẹṣẹ nigbati aṣiṣe ba wa ninu idunadura laarin Titunto si ati FDDR
• IO_CAL_INT – N jẹ ki o tun ṣe atunṣe DDR I/O nipa kikọ si awọn iforukọsilẹ oludari DDR nipasẹ wiwo iṣeto ni APB. Nigbati isọdọtun ba ti pari, idalọwọduro yii yoo dide. Fun alaye nipa I/O recalibration, tọkasi Microsemi SmartFusion2 Awọn olumulo Itọsọna.
• PLL_LOCK_INT – Tọkasi pe FDDR FPLL ti ni titiipa
• PLL_LOCKLOST_INT – Tọkasi pe FDDR FPLL ti padanu titiipa
• FDDR_ECC_INT – Tọkasi ẹyọkan tabi aṣiṣe-bit meji ti a ti rii

Aago Aṣọ Igbohunsafẹfẹ 

Iṣiro igbohunsafẹfẹ aago ti o da lori igbohunsafẹfẹ aago lọwọlọwọ rẹ ati alapin Aago, ti o han ni MHz.
Igbohunsafẹfẹ Aṣọ Aṣọ (ni MHz) = Aago Igbohunsafẹfẹ / Aago pin

Bandiwidi iranti 

Iṣiro bandiwidi iranti ti o da lori iye Igbohunsafẹfẹ Aago lọwọlọwọ rẹ ni Mbps.
Bandiwidi iranti (ni Mbps) = 2 * Igbohunsafẹfẹ aago

Lapapọ bandiwidi

Lapapọ iṣiro bandiwidi ti o da lori Igbohunsafẹfẹ Aago lọwọlọwọ rẹ, Iwọn data ati alapin Aago, ni Mbps.
Lapapọ bandiwidi (ni Mbps) = (2 * Igbohunsafẹfẹ aago * Iwọn data) / Aago Pipin

FDDR Adarí iṣeto ni

Nigbati o ba lo Oluṣakoso DDR Fabric lati wọle si iranti DDR ita, Adarí DDR gbọdọ wa ni tunto ni akoko asiko. Eyi ni a ṣe nipa kikọ data atunto si awọn iforukọsilẹ iṣeto oluṣakoso DDR igbẹhin. Yi data iṣeto ni da lori awọn abuda kan ti awọn ita DDR iranti ati ohun elo rẹ. Abala yii ṣapejuwe bii o ṣe le tẹ awọn aye atunto wọnyi sinu oluṣeto oluṣakoso FDDR ati bii data iṣeto ni a ṣe ṣakoso gẹgẹ bi apakan ti ojutu Ibẹrẹ Agbeegbe gbogbogbo. Tọkasi Itọsọna Olumulo Ibẹrẹ Agbeegbe fun alaye alaye nipa ojutu Ibẹrẹ Agbeegbe.

Fabric DDR Iṣakoso registers 

Adarí DDR Fabric ni ṣeto awọn iforukọsilẹ ti o nilo lati tunto ni akoko asiko. Awọn iye atunto fun awọn iforukọsilẹ wọnyi ṣe aṣoju awọn aye oriṣiriṣi (fun example, DDR mode, PHY iwọn, ti nwaye mode, ECC, ati be be lo). Fun awọn alaye nipa awọn iforukọsilẹ iṣeto oluṣakoso DDR, tọka si Itọsọna Olumulo Microsemi SmartFusion2.

Fabric DDR Registers iṣeto ni 

Lo awọn taabu Initialization Memory (olusin 2-1) ati Memory Time (Figure 2-2) lati tẹ awọn paramita ti o badọgba lati rẹ DDR Memory ati ohun elo. Awọn iye ti o tẹ sinu awọn taabu wọnyi ni a tumọ laifọwọyi si awọn iye iforukọsilẹ ti o yẹ. Nigbati o ba tẹ paramita kan pato, iforukọsilẹ ti o baamu jẹ apejuwe ninu Ferese Apejuwe Iforukọsilẹ (Aworan 1-1 ni oju-iwe 4).

Olusin 2-1 • Iṣeto FDDR - Taabu Ibẹrẹ Iranti

Olusin 2-2 • Iṣeto FDDR – Taabu aago iranti

Gbigbe DDR iṣeto ni Files

Ni afikun si titẹ awọn aye iranti DDR ni lilo Ibẹrẹ Iranti ati awọn taabu akoko, o le gbe awọn iye iforukọsilẹ DDR wọle lati inu kan file. Lati ṣe bẹ, tẹ bọtini Iṣeto Wọle ki o lọ kiri si ọrọ naa file ti o ni awọn orukọ DDR forukọsilẹ ati iye. olusin 2-3 fihan agbewọle iṣeto ni sintasi.

olusin 2-3 • DDR Forukọsilẹ iṣeto ni File Sintasi

Akiyesi: Ti o ba yan lati gbe awọn iye iforukọsilẹ wọle kuku ju titẹ wọn sii nipa lilo GUI, o gbọdọ pato gbogbo awọn iye iforukọsilẹ pataki. Tọkasi Itọsọna olumulo SmartFusion2 fun awọn alaye

Okeere DDR iṣeto ni Files

O tun le okeere data iṣeto ni iforukọsilẹ lọwọlọwọ sinu ọrọ kan file. Eyi file yoo ni awọn iye iforukọsilẹ ti o gbe wọle (ti o ba jẹ eyikeyi) ati awọn ti a ṣe iṣiro lati awọn aye GUI ti o tẹ sinu apoti ibaraẹnisọrọ yii.
Ti o ba fẹ mu awọn ayipada pada ti o ti ṣe si iṣeto iforukọsilẹ DDR, o le ṣe pẹlu Iyipada Mu pada. Eyi npa gbogbo data iṣeto ni iforukọsilẹ rẹ ati pe o gbọdọ tun gbe wọle tabi tun data yii wọle. A tunto data naa si awọn iye atunto hardware.

Ti ipilẹṣẹ Data 

Tẹ Dara lati ṣe ina iṣeto ni. Da lori igbewọle rẹ ni Gbogbogbo, Akoko Iranti ati awọn taabu Ibẹrẹ Iranti, FDDR Configurator ṣe iṣiro awọn iye fun gbogbo awọn iforukọsilẹ iṣeto ni DDR ati gbejade awọn iye wọnyi si okeere si iṣẹ akanṣe famuwia rẹ ati kikopa files. Awọn okeere file sintasi han ni Figure 2-4.

olusin 2-4 • Exported DDR Forukọsilẹ iṣeto ni File Sintasi

Firmware

Nigbati o ba ṣe ina SmartDesign, atẹle naa files ti wa ni ipilẹṣẹ ni / famuwia / drivers_config/sys_config liana. Awọn wọnyi files nilo fun ipilẹ famuwia CMSIS lati ṣajọ daradara ati ni alaye ninu nipa apẹrẹ rẹ lọwọlọwọ, pẹlu data atunto agbeegbe ati alaye iṣeto aago fun MSS. Maṣe ṣatunkọ awọn wọnyi files pẹlu ọwọ, bi wọn ṣe tun ṣe ni gbogbo igba ti apẹrẹ root rẹ jẹ atunbi.

• sys_config.c
• sys_config.h
• sys_config_mddr_define.h - data iṣeto ni MDR.
• sys_config_fddr_define.h - data iṣeto ni FDDR.
• sys_config_mss_clocks.h – MSS titobi iṣeto ni

Afọwọṣe

Nigbati o ba ṣe ina SmartDesign ti o ni nkan ṣe pẹlu MSS rẹ, simulation atẹle files ti wa ni ti ipilẹṣẹ ninu / kikopa liana:

• idanwo.bfm BFM ti o ga julọ file ti o ti wa ni akọkọ executed nigba eyikeyi kikopa ti o idaraya SmartFusion2 MSS Cortex-M3 isise. O ṣiṣẹ peripheral_init.bfm ati user.bfm, ni ibere.
• peripheral_init.bfm - Ni awọn ilana BFM ti o fara wé CMSIS :: SystemInit () iṣẹ ṣiṣe lori Cortex-M3 ṣaaju ki o to tẹ akọkọ () ilana. O daakọ data iṣeto ni fun eyikeyi agbeegbe ti a lo ninu apẹrẹ si awọn iforukọsilẹ atunto agbeegbe ti o pe ati lẹhinna duro fun gbogbo awọn agbeegbe lati wa ni imurasilẹ ṣaaju iṣeduro pe olumulo le lo awọn agbeegbe wọnyi.
• FDDR_init.bfm - Ni awọn aṣẹ kikọ BFM ti o ṣedasilẹ kọwe ti data iforukọsilẹ Fabric DDR iṣeto ni ti o ti tẹ (lilo apoti ajọṣọ Ṣatunkọ Awọn iforukọsilẹ) sinu awọn iforukọsilẹ Alakoso DDR.
• olumulo.bfm - Ti pinnu fun awọn aṣẹ olumulo. O le ṣe afiwe ọna data nipa fifi awọn aṣẹ BFM tirẹ kun ni eyi file. Awọn aṣẹ ni eyi file yoo ṣiṣẹ lẹhin peripheral_init.bfm ti pari.

Lilo awọn files loke, awọn iṣeto ni ona ti wa ni labeabo laifọwọyi. O nilo lati ṣatunkọ olumulo.bfm nikan file lati ṣedasilẹ ọna data. Maṣe ṣatunkọ test.bfm, peripheral_init.bfm, tabi MDR_init.bfm files bi awọn wọnyi files ti wa ni atunda ni gbogbo igba ti rẹ root oniru ti wa ni atunbi.

Fabric DDR iṣeto ni Ona 

Ojutu Initialization Agbeegbe nbeere pe, ni afikun si sisọ awọn iye iforukọsilẹ iṣeto ni Fabric DDR, o tunto ọna data iṣeto ni APB ni MSS (FIC_2). Iṣẹ SystemInit () kọ data naa si awọn iforukọsilẹ iṣeto ni FDDR nipasẹ wiwo FIC_2 APB.

Akiyesi: Ti o ba nlo Akole System ọna iṣeto ni a ṣeto ati ti sopọ laifọwọyi.

Olusin 2-5 • FIC_2 Configurator Overview

Lati tunto wiwo FIC_2:

1. Ṣii ifọrọwerọ atunto FIC_2 (Aworan 2-5) lati ọdọ atunto MSS.
2. Yan Ibẹrẹ awọn agbeegbe nipa lilo aṣayan Cortex-M3.
3. Rii daju pe MSS DDR ti ṣayẹwo, gẹgẹ bi awọn bulọọki Fabric DDR/SERDES ti o ba nlo wọn.
4. Tẹ O DARA lati fi awọn eto rẹ pamọ. Eyi ṣafihan awọn ibudo iṣeto FIC_2 (Aago, Tunto, ati awọn atọkun ọkọ akero APB), bi o ṣe han ni Nọmba 2-6.
5. Ṣẹda MSS. Awọn ebute oko oju omi FIC_2 (FIC_2_APB_MASTER, FIC_2_APB_M_PCLK ati FIC_2_APB_M_RESET_N) ti farahan ni wiwo MSS ati pe o le sopọ si CoreSF2Config ati CoreSF2Reset gẹgẹbi fun sipesifikesonu Ibẹrẹ Ibẹrẹ Agbeegbe

olusin 2-6 • FIC_2 Ports

Port Apejuwe

FDDR mojuto Ports 

Table 3-1 • FDDR mojuto Ports

Orukọ Port	Itọsọna	Apejuwe
CORE_RESET_N	IN	FDDR Adarí Tun
CLK_BASE	IN	FDDR Fabric Aago
FPLL_LOCK	Jade	Titiipa Titiipa FDDR PLL - giga nigbati FDDR PLL wa ni titiipa
CLK_BASE_PLL_LOCK	IN	Aṣọ PLL Titiipa Input. Iṣagbewọle yii farahan nigbati o ba yan aṣayan Lo FAB_PLL_LOCK.

Idilọwọ Awọn ibudo

Ẹgbẹ yii ti awọn ebute oko oju omi ti han nigbati o yan aṣayan Mu Awọn idilọwọ ṣiṣẹ.

Table 3-2 • Idilọwọ Ports

Orukọ Port	Itọsọna	Apejuwe
PLL_LOCK_INT	Jade	Awọn ifisilẹ nigbati FDDR PLL titii.
PLL_LOCKLOST_INT	Jade	Awọn ifisilẹ nigbati FDDR PLL titiipa ti sọnu.
ECC_INT	Jade	Awọn ifisilẹ nigbati iṣẹlẹ ECC waye.
IO_CALIB_INT	Jade	Awọn ifisilẹ nigbati isọdọtun I/O ti pari.
FIC_INT	Jade	Awọn ifisilẹ nigbati aṣiṣe ba wa ninu ilana AHB/AXI lori wiwo Aṣọ.

APB3 Iṣeto ni wiwo 

Table 3-3 • APB3 Iṣeto ni wiwo

Orukọ Port	Itọsọna	Apejuwe
APB_S_PENABLE	IN	Ẹrú Jeki
APB_S_PSEL	IN	Ẹrú Select
APB_S_PWRITE	IN	Kọ Mu ṣiṣẹ
APB_S_PADDR[10:2]	IN	Adirẹsi
APB_S_PWDATA[15:0]	IN	Kọ Data
APB_S_PRADY	Jade	Ẹrú Ṣetan
APB_S_PSLVERR	Jade	Aṣiṣe Ẹrú
APB_S_PRDATA[15:0]	Jade	Ka Data
APB_S_PRESET_N	IN	Ẹrú Tunto
APB_S_PCLK	IN	Aago

DDR PHY Interface 

Table 3-4 • DDR PHY Interface 

Orukọ Port	Itọsọna	Apejuwe
FDDR_CAS_N	Jade	DRAM CASN
FDDR_CKE	Jade	DRAM CKE
FDDR_CLK	Jade	Aago, P ẹgbẹ
FDDR_CLK_N	Jade	Aago, N ẹgbẹ
FDDR_CS_N	Jade	DRAM CSN
FDDR_ODT	Jade	DRAM ODT
FDDR_RAS_N	Jade	DRAM RASN
FDDR_RESET_N	Jade	DRAM Tun fun DDR3
FDDR_WE_N	Jade	DRAM WEN
FDDR_ADDR[15:0]	Jade	Dram Adirẹsi die-die
FDDR_BA[2:0]	Jade	Dram Bank adirẹsi
FDDR_DM_RDQS[4:0]	INOUT	Dram Data Boju
FDDR_DQS[4:0]	INOUT	Dram Data Strobe Input / o wu - P Side
FDDR_DQS_N [4:0]	INOUT	Dram Data Strobe Input / O wu - N Side
FDDR_DQ[35:0]	INOUT	DRAM Data Input / o wu
FDDR_FIFO_WE_IN[2:0]	IN	FIFO ni ifihan agbara
FDDR_FIFO_WE_OUT[2:0]	Jade	FIFO jade ifihan agbara
FDDR_DM_RDQS ([3:0]/[1:0]/[0])	INOUT	Dram Data Boju
FDDR_DQS ([3:0]/[1:0]/[0])	INOUT	Dram Data Strobe Input / o wu - P Side
FDDR_DQS_N ([3:0]/[1:0]/[0])	INOUT	Dram Data Strobe Input / O wu - N Side
FDDR_DQ ([31:0]/[15:0]/[7:0])	INOUT	DRAM Data Input / o wu
FDDR_DQS_TMATCH_0_IN	IN	FIFO ni ifihan agbara
FDDR_DQS_TMATCH_0_OUT	Jade	FIFO jade ifihan agbara
FDDR_DQS_TMATCH_1_IN	IN	FIFO ni ifihan (32-bit nikan)
FDDR_DQS_TMATCH_1_OUT	Jade	Ifihan FIFO jade (32-bit nikan)
FDDR_DM_RDQS_ECC	INOUT	Dram ECC Data boju
FDDR_DQS_ECC	INOUT	Dram ECC Data Strobe Input / o wu - P Side
FDDR_DQS_ECC_N	INOUT	Dram ECC Data Strobe Input / O wu - N Side
FDDR_DQ_ECC ([3:0]/[1:0]/[0])	INOUT	DRAM ECC Data Input / o wu
FDDR_DQS_TMATCH_ECC_IN	IN	ECC FIFO ni ifihan agbara
FDDR_DQS_TMATCH_ECC_OUT	Jade	ECC FIFO ifihan agbara (32-bit nikan)

Akiyesi: Awọn iwọn ibudo fun diẹ ninu awọn ebute oko oju omi yipada da lori yiyan ti iwọn PHY. A lo akiyesi "[a: 0] / [b: 0] / [c: 0]" lati ṣe afihan iru awọn ebute oko oju omi, nibiti "[a: 0]" n tọka si iwọn ibudo nigbati a yan iwọn 32-bit PHY , "[b:0]" ni ibamu pẹlu iwọn 16-bit PHY, ati "[c: 0]" ni ibamu pẹlu iwọn 8-bit PHY kan.

AXI Bus Interface 

Table 3-5 • AXI Bus Interface

Orukọ Port	Itọsọna	Apejuwe
AXI_S_AWREADY	Jade	Kọ adirẹsi setan
AXI_S_WREADY	Jade	Kọ adirẹsi setan
AXI_S_BID[3:0]	Jade	Idahun ID
AXI_S_BRESP[1:0]	Jade	Kọ esi
AXI_S_BVALID	Jade	Kọ esi wulo
AXI_S_ARREADY	Jade	Ka adirẹsi setan
AXI_S_RID[3:0]	Jade	Ka ID Tag
AXI_S_RRESP[1:0]	Jade	Ka Idahun
AXI_S_RDATA[63:0]	Jade	Ka data
AXI_S_RLAST	Jade	Ka Kẹhin – Ifihan agbara yii tọkasi gbigbe to kẹhin ninu igbafọ kika.
AXI_S_RVALID	Jade	Ka adirẹsi wulo
AXI_S_AWID[3:0]	IN	Kọ ID adirẹsi
AXI_S_AWADDR[31:0]	IN	Kọ adirẹsi
AXI_S_AWLEN[3:0]	IN	Fonkaakiri ipari
AXI_S_AWSIZE[1:0]	IN	Ti nwaye iwọn
AXI_S_AWBURST[1:0]	IN	Ti nwaye iru
AXI_S_AWLOCK[1:0]	IN	Titiipa Iru – Ifihan agbara yii n pese alaye ni afikun nipa awọn abuda atomiki ti gbigbe.
AXI_S_AWVALID	IN	Kọ adirẹsi wulo
AXI_S_WID[3:0]	IN	Kọ ID ID tag
AXI_S_WDATA[63:0]	IN	Kọ data
AXI_S_WSTRB[7:0]	IN	Kọ strobes
AXI_S_WLAST	IN	Kọ kẹhin
AXI_S_WVALID	IN	Kọ wulo
AXI_S_BREADY	IN	Kọ setan
AXI_S_ARID[3:0]	IN	Ka ID adirẹsi
AXI_S_ARADDR[31:0]	IN	Ka adirẹsi
AXI_S_ARLEN[3:0]	IN	Fonkaakiri ipari
AXI_S_ARSIZE[1:0]	IN	Ti nwaye iwọn
AXI_S_ARBURST[1:0]	IN	Ti nwaye iru
AXI_S_ARLOCK[1:0]	IN	Titiipa Iru
AXI_S_ARVALID	IN	Ka adirẹsi wulo
AXI_S_RREADY	IN	Ka adirẹsi setan
Orukọ Port	Itọsọna	Apejuwe
AXI_S_CORE_RESET_N	IN	MDR Agbaye Tun
AXI_S_RMW	IN	Tọkasi boya gbogbo awọn baiti ti ọna 64-bit kan wulo fun gbogbo awọn lilu ti gbigbe AXI kan. Tọkasi pe gbogbo awọn baiti ni gbogbo awọn lu ni o wulo ni ti nwaye ati oludari yẹ ki o aiyipada lati kọ awọn aṣẹ. Tọkasi pe diẹ ninu awọn baiti ko wulo ati pe oludari yẹ ki o aiyipada si awọn aṣẹ RMW. Eyi jẹ ipin bi AXI kikọ adirẹsi ikanni sideband ifihan agbara ati pe o wulo pẹlu ifihan AWVALID. Nikan lo nigbati ECC ti ṣiṣẹ.

AHB0 Bus Interface 

Table 3-6 • AHB0 Bus Interface 

Orukọ Port	Itọsọna	Apejuwe
AHB0_S_HREADYOUT	Jade	AHBL ẹrú setan - Nigba ti o ga fun a Kọ tọkasi ẹrú ti šetan lati gba data ati nigbati ga fun a kika tọkasi wipe data jẹ wulo.
AHB0_S_HRESP	Jade	Ipo idahun AHBL - Nigbati o ba gbe ga ni opin idunadura kan tọkasi pe idunadura naa ti pari pẹlu awọn aṣiṣe. Nigbati o ba lọ silẹ ni opin idunadura kan tọkasi pe idunadura naa ti pari ni aṣeyọri.
AHB0_S_HRDATA[31:0]	Jade	AHBL kika data - Ka data lati ẹrú si oluwa
AHB0_S_HSEL	IN	Ẹrú AHBL yan - Nigbati o ba fi idi rẹ mulẹ, ẹrú naa jẹ ẹrú AHBL ti a yan lọwọlọwọ lori ọkọ akero AHB.
AHB0_S_HADDR[31:0]	IN	AHBL adirẹsi – baiti adirẹsi lori AHBL ni wiwo
AHB0_S_HBURST[2:0]	IN	AHBL Fonkaakiri Ipari
AHB0_S_HSIZE[1:0]	IN	Iwọn gbigbe AHBL - Tọkasi iwọn ti gbigbe lọwọlọwọ (awọn iṣowo baiti 8/16/32 nikan)
AHB0_S_HTRANS[1:0]	IN	Iru gbigbe AHBL - Ṣe afihan iru gbigbe ti iṣowo lọwọlọwọ.
AHB0_S_HMASTLOCK	IN	Titiipa AHBL - Nigbati o ba fi idi rẹ mulẹ gbigbe lọwọlọwọ jẹ apakan ti idunadura titiipa.
AHB0_S_HWRITE	IN	AHBL kọ - Nigbati giga ba tọka si pe idunadura lọwọlọwọ jẹ kikọ. Nigbati kekere tọkasi pe idunadura lọwọlọwọ jẹ kika.
AHB0_S_HREADY	IN	AHBL setan - Nigbati o ga, tọkasi pe ẹrú ti šetan lati gba idunadura titun kan.
AHB0_S_HWDATA[31:0]	IN	AHBL kọ data - Kọ data lati ọdọ oluwa si ẹrú naa

AHB1 Bus Interface 

Table 3-7 • AHB1 Bus Interface

Orukọ Port	Itọsọna	Apejuwe
AHB1_S_HREADYOUT	Jade	AHBL ẹrú setan - Nigbati ga fun a Kọ, tọkasi awọn ẹrú ti šetan lati gba data, ati nigbati o ga fun a kika, tọkasi wipe data jẹ wulo.
AHB1_S_HRESP	Jade	Ipo idahun AHBL - Nigbati o ba gbe ga ni opin idunadura kan tọkasi pe idunadura naa ti pari pẹlu awọn aṣiṣe. Nigbati o ba lọ silẹ ni opin idunadura kan, tọkasi pe idunadura naa ti pari ni aṣeyọri.
AHB1_S_HRDATA[31:0]	Jade	AHBL kika data - Ka data lati ẹrú si oluwa
AHB1_S_HSEL	IN	Ẹrú AHBL yan - Nigbati o ba fi idi rẹ mulẹ, ẹrú naa jẹ ẹrú AHBL ti a yan lọwọlọwọ lori ọkọ akero AHB.
AHB1_S_HADDR[31:0]	IN	AHBL adirẹsi – baiti adirẹsi lori AHBL ni wiwo
AHB1_S_HBURST[2:0]	IN	AHBL Fonkaakiri Ipari
AHB1_S_HSIZE[1:0]	IN	Iwọn gbigbe AHBL - Ṣe afihan iwọn ti gbigbe lọwọlọwọ (8/16/32 awọn iṣowo baiti nikan).
AHB1_S_HTRANS[1:0]	IN	Iru gbigbe AHBL - Ṣe afihan iru gbigbe ti iṣowo lọwọlọwọ.
AHB1_S_HMASTLOCK	IN	Titiipa AHBL - Nigbati o ba fi idi rẹ mulẹ, gbigbe lọwọlọwọ jẹ apakan ti idunadura titiipa.
AHB1_S_HWRITE	IN	AHBL kọ - Nigbati o ga, tọkasi pe idunadura lọwọlọwọ jẹ kikọ. Nigbati o ba lọ silẹ, tọkasi pe idunadura lọwọlọwọ jẹ kika.
AHB1_S_HREADY	IN	AHBL setan - Nigbati o ga, tọkasi pe ẹrú ti šetan lati gba idunadura titun kan.
AHB1_S_HWDATA[31:0]	IN	AHBL kọ data - Kọ data lati ọdọ oluwa si ẹrú naa

Ọja Support

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Oluranlowo lati tun nkan se 

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Webojula

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Ita awọn US 

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Fun atilẹyin imọ ẹrọ lori awọn RH ati RT FPGA ti o jẹ ilana nipasẹ International Traffic in Arms Regulations (ITAR), kan si wa nipasẹ soc_tech_itar@microsemi.com. Ni omiiran, laarin Awọn ọran Mi, yan Bẹẹni ninu atokọ jabọ-silẹ ITAR. Fun atokọ pipe ti Awọn FPGA Microsemi ti ITAR ti ṣe ilana, ṣabẹwo si ITAR web oju-iwe.

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