Microsemi IGLOO2 HPMS DDR njikwa nhazi

Okwu mmalite

IGLOO2 HPMS nwere ihe njikwa DDR agbakwunyere (HPMS DDR). Ihe njikwa DDR a bu n'obi jikwaa ebe nchekwa DDR na-apụ apụ. Enwere ike ịnweta onye njikwa HPMS DDR site na HPMS (iji HPDMA) yana site na akwa FPGA.
Mgbe ị na-eji Sistemụ Nrụpụta Ihe iji wuo ngọngọ sistemu nke gụnyere HPMS DDR, Onye nrụpụta sistemụ na-ahazi gị onye njikwa HPMS DDR dabere na ntinye na nhọrọ gị.
Enweghị nhazi HPMS DDR dị iche iche nke onye ọrụ chọrọ. Maka nkọwapụta, biko rụtụ aka na ntuziaka Onye Nrụpụta Sistemu IGLOO2.
Onye nrụpụta sistemụ

Onye nrụpụta sistemụ

Na em Builder iji hazie HPMS DDR na-akpaghị aka.

1.  Na taabụ Njirimara Ngwaọrụ nke Onye Nrụpụta Sistemu, lelee HPMS Mpụga DDR Ebe nchekwa (HPMS DDR).
2. Na taabụ Ncheta, họrọ ụdị ebe nchekwa DDR:
   • DDR2
   •  DDR3
   • LPDDR
3. Họrọ obosara nke ebe nchekwa DDR: 8, 16 ma ọ bụ 32
4. Lelee ECC ma ọ bụrụ na ịchọrọ ịnweta ECC maka DDR.
5. Tinye oge nhazi ebe nchekwa DDR. Nke a bụ oge ebe nchekwa DDR chọrọ ịmalite.
6. Pịa Nhazi nhazi mbubata ka ibubata ụkpụrụ ndekọ aha maka FDDR site na ederede dị file nwere ụkpụrụ ndekọ aha. Lee Tebụl 1 maka nhazi ndekọ aha file syntax.
   Libero na-echekwa data nhazi a na-akpaghị aka na eNVM. Mgbe nrụpụta FPGA, a ga-eṅomi data nhazi a na-akpaghị aka na HPMS DDR.

Ọgụgụ 1 • Sistemụ Nrụpụta na HPMS DDR

Tebụl 1 • Nhazi aha File Syntax

• ddrc_dyn_soft_reset_CR 0x00 ;
• ddrc_dyn_refresh_1_CR 0x27DE ;
• ddrc_dyn_refresh_2_CR 0x30F ;
• ddrc_dyn_powerdown_CR 0x02 ;
• ddrc_dyn_debug_CR 0x00 ;
• ddrc_ecc_data_mask_CR 0x0000 ;
• ddrc_addr_map_col_1_CR 0x3333 ;

Nhazi njikwa HPMS DDR

Mgbe ị na-eji HPMS DDR Controller iji nweta ebe nchekwa DDR dị n'èzí, DDR Controller ga-amalite ịmalite n'oge ọ na-agba ọsọ. A na-eme nke a site na ide data nhazi na ndekọ nhazi nhazi DDR raara onwe ya nye. Na IGLOO2, eNVM na-echekwa data nhazi ndekọ aha na mgbe FPGA tọgharịa, a na-eṅomi data nhazi site na eNVM gaa na ndebanye aha nke HPMS DDR maka ibido.

HPMS DDR Njikwa ndekọ
Onye njikwa HPMS DDR nwere ndebanye aha nke kwesịrị ịhazi n'oge ọ na-agba ọsọ. Ụkpụrụ nhazi maka ndekọ ndị a na-anọchi anya paramita dị iche iche, dị ka ọnọdụ DDR, obosara PHY, ọnọdụ mgbawa, na ECC. Maka nkọwa zuru ezu gbasara ndekọ nhazi njikwa DDR biko rụtụ aka na ntuziaka onye ọrụ Microsemi IGLOO2
Nhazi ndebanye aha HPMS MDR

Iji kọwapụta ụkpụrụ ndebanye aha DDR:

1. Jiri ndezi ederede na mpụga Libero SoC, kwado ederede file nwere aha na ụkpụrụ ndekọ aha, dịka na eserese 1-1.
2. Site System Nrụpụta's ebe nchekwa taabụ, click Import Register Configuration.
3. Gaa na ebe ederede nhazi ndebanye aha file Ị kwadola na Nzọụkwụ 1 wee họrọ nke file mbubata.

Ọgụgụ 1-1 • Data nhazi aha - Ụdị ederede

HPMS DDR mmalite
A na-ebuba data nhazi ndekọ aha ị na-ebubata maka HPMS DDR n'ime eNVM wee depụta ya na ndekọ nhazi HPMS DDR na nrụpụta FPGA. Ọ nweghị ihe onye ọrụ chọrọ iji malite HPMS DDR n'oge ọ na-agba ọsọ. A na-ahazikwa mmalite mmalite a akpaghị aka na simulation.

Nkọwa Port

DDR PHY Interface
A na-ekpughe ọdụ ụgbọ mmiri ndị a n'ogo dị elu nke ngọngọ nke mepụtara Sistemụ Nrụpụta. Maka nkọwa, gaa na ntuziaka onye nrụpụta Sistemu IGLOO2. Jikọọ ọdụ ụgbọ mmiri ndị a na ebe nchekwa DDR gị.

Isiokwu 2-1 • DDR PHY Interface

Aha Port	Ntuziaka	Nkọwa
MDR_CAS_N	Mpụ	DRAM CASN
MDR_CKE	Mpụ	DRAM CKE
MDR_CLK	Mpụ	Elekere, akụkụ P
MDR_CLK_N	Mpụ	Elekere, N akụkụ
MDR_CS_N	Mpụ	DRAM CSN
MDR_ODT	Mpụ	DRAM ODT
MDR_RAS_N	Mpụ	DRAM RASN
MDR_RESET_N	Mpụ	Tọgharia DRAM maka DDR3
MDR_WE_N	Mpụ	DRAM WEN
MDR_ADDR[15:0]	Mpụ	Iberibe adreesị Dram
MDR_BA[2:0]	Mpụ	Dram Bank Adreesị
MDDR_DM_RDQS ([3:0]/[1:0]/[0])	INOUT	Ihe nkpuchi data Dram
MDDR_DQS ([3:0]/[1:0]/[0])	INOUT	Ntinye/Mpụta Dram Data Strobe – Akụkụ P
MDDR_DQS_N ([3:0]/[1:0]/[0])	INOUT	Ntinye/mmepụta Dram Data Strobe – N akụkụ
MDDR_DQ ([31:0]/[15:0]/[7:0])	INOUT	Ntinye/mmepụta data DRAM
MDR_DQS_TMATCH_0_IN	IN	FIFO na mgbama
MDR_DQS_TMATCH_0_OUT	Mpụ	FIFO pụta ìhè
MDR_DQS_TMATCH_1_IN	IN	FIFO na mgbama (naanị 32-bit)
MDR_DQS_TMATCH_1_OUT	Mpụ	Mgbama FIFO (naanị 32-bit)
MDR_DM_RDQS_ECC	INOUT	Ihe nkpuchi data Dram ECC
MDR_DQS_ECC	INOUT	Ntinye/mmepụta Dram ECC Data Strobe – Akụkụ P
MDR_DQS_ECC_N	INOUT	Ntinye/mmepụta Dram ECC Data Strobe – N akụkụ
MDDR_DQ_ECC ([3:0]/[1:0]/[0])	INOUT	Ntinye/mmepụta data DRAM ECC
MDR_DQS_TMATCH_ECC_IN	IN	ECC FIFO na akara ngosi
MDR_DQS_TMATCH_ECC_OUT	Mpụ	ECC FIFO mgbama (naanị 32-bit)

Ogologo ọdụ ụgbọ mmiri maka ụfọdụ ọdụ ụgbọ mmiri na-agbanwe dabere na nhọrọ nke obosara PHY. A na-eji akara “[a:0]/[b:0]/[c:0]” gosi ọdụ ụgbọ mmiri ndị dị otú ahụ, ebe “[a:0]” na-ezo aka na obosara ọdụ ụgbọ mmiri mgbe ahọpụtara obosara 32-bit PHY, “[b:0]” dabara na obosara PHY 16-bit, yana “[c:0]” dabara na obosara PHY 8.

Nkwado ngwaahịa

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Okwu m
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Microsemi IGLOO2 HPMS DDR njikwa nhazi [pdf] Ntuziaka onye ọrụ IGLOO2 HPMS DDR nhazi nhazi, IGLOO2, HPMS DDR njikwa nhazi, DDR njikwa nhazi, nhazi

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