Microsemi SmartFusion2 FPGA Fabric DDR Controller Configuration User Guide
Nhanganyaya
Iyo SmartFusion2 FPGA ine maviri akamisikidzwa DDR anodzora - imwe inowanikwa kuburikidza neMSS (MDDR) uye imwe inoitirwa kuwana yakananga kubva kuFPGA Fabric (FDDR). Iyo MDDR neFDDR ese ari maviri anodzora off-chip DDR ndangariro.
Kuti unyatso gadzirisa iyo Fabric DDR controller unofanirwa:
- Shandisa iyo Fabric External Memory DDR Controller Configurator kugadzirisa iyo DDR Controller, sarudza iyo datapath bhazi interface (AXI kana AHBLite), uye sarudza iyo DDR wachi frequency pamwe nemucheka datapath wachi frequency.
- Seta marejista emhando dzeDDR controller marejista kuti aenderane neako ekunze DDR ndangariro maitiro.
- Isa iyo Fabric DDR sechikamu chemushandisi application uye ita datapath yekubatanidza.
- Batanidza iyo DDR controller's APB yekumisikidza interface sekutsanangurwa kwazvinoitwa nePeripheral Initialization solution.
Mucheka Wekunze Memory DDR Controller Configurator
Iyo Fabric External Memory DDR (FDDR) Configurator inoshandiswa kugadzirisa iyo yakazara datapath uye yekunze DDR memory paramita yeFabric DDR Controller.
Mufananidzo 1-1 • FDDR Configurator Overview
Memory Settings
Shandisa Memory Settings kugadzirisa sarudzo dzako dzendangariro muMDDR.
- Memory Type - LPDDR, DDR2, kana DDR3
- Data Width - 32-bit, 16-bit kana 8-bit
- Clock Kakawanda - Chero kukosha (Decimal / Fractional) muhuwandu hwe20 MHz kusvika 333 MHz
- SECDED Inogonesa ECC - VAKA kana VAKA
- Kero Mapping - {MUROW,BHANGI,COLUMN},{BHANGI,MUROW,COLUMN}
Fabric Interface Settings
FPGA Fabric Interface -Iyi ndiyo data interface pakati peFDDR neFPGA dhizaini. Nekuti iyo FDDR inodzora ndangariro, inoitirwa kuve muranda paAXI kana AHB bhazi. Iye Tenzi webhazi anotanga kutengeserana kwebhazi, izvo zvinozodudzirwa neFDDR senge ndangariro kutengeserana uye kuziviswa kune iyo off-chip DDR Memory. FDDR fabric interface sarudzo ndeidzi:
- Uchishandisa AXI-64 Interface - Imwe tenzi inowana iyo FDDR kuburikidza ne64-bit \ AXI interface.
- Uchishandisa Imwe AHB-32 Interface - Imwe tenzi inowana iyo FDDR kuburikidza neiyo imwe chete 32-bit AHB interface.
- Kushandisa maviri AHB-32 Interfaces - Vatenzi vaviri vanowana iyo FDDR vachishandisa maviri 32-bit AHB nzvimbo.
FPGA Clock Divisor - Inodoma frequency reshiyo pakati peDDR Controller wachi (CLK_FDDR) uye wachi inodzora jira remachira (CLK_FIC64). Iyo CLK_FIC64 frequency inofanirwa kuenzana neyeiyo AHB/AXI subsystem yakabatana neFDDR AHB/AXI bhazi interface. For exampuye, kana uine DDR RAM inomhanya pa200 MHz uye yako Fabric/AXI Subsystem inomhanya pa100 MHz, unofanirwa kusarudza divisor ye2 (Mufananidzo 1-2).
Mufananidzo 1-2 • Fabric Interface Settings - AXI Interface uye FDDR Clock Divisor Agreement
Shandisa Fabric PLL LOCK - Kana CLK_BASE yakatorwa kubva kuFabric CCC, unogona kubatanidza jira reCCC LOCK rinobuda kune FDDR FAB_PLL_LOCK yekuisa. CLK_BASE haina kugadzikana kusvika Fabric CCC yakiya. Naizvozvo, Microsemi inokurudzira kuti ubate iyo FDDR mukugadzirisa (kureva, taura CORE_RESET_N yekuisa) kusvika CLK_BASE yagadzikana. Iyo LOCK yakabuda yeFabric CCC inoratidza kuti Iyo Fabric CCC yekubuda wachi yakagadzikana. Nekutarisa iyo Shandisa FAB_PLL_LOCK sarudzo, unogona kufumura iyo FAB_PLL_LOCK yekuisa port yeFDDR. Unogona kubatanidza LOCK yakabuda yeFabric CCC kune iyo FAB_PLL_LOCK yekuisa yeFDDR.
IO Drive Simba
Sarudza imwe yeanotevera simba rekutyaira kune yako DDR I/O's:
- Half Drive Simba
- Full Drive Simba
Zvichienderana neDDR Memory yako uye I/O Simba raunosarudza, Libero SoC inoisa iyo DDR I/O Standard yeFDDR system yako seizvi:
| DDR Memory Type | Half Drive Simba | Full Drive Simba |
| DDR3 | SSTL15I | SSTL15II |
| DDR2 | SSTL18I | SSTL18II |
| LPDDR | LPDRI | LPDRII |
Bvumira Kupindira
Iyo FDDR inokwanisa kusimudza zvinokanganisa kana mamwe mamiriro akatemerwa agutsikana. Tarisa Bvumira Kuvhiringidza muFDDR configurator kana iwe uchida kushandisa izvi zvinokanganisa mukushandisa kwako.
Izvi zvinofumura masaini ekukanganisa pane iyo FDDR muenzaniso. Unogona kubatanidza aya masaini masaini sekuda kwedhizaini yako. Aya anotevera Kuvhiringidza masaini uye preconditions yawo anowanikwa:
- FIC_INT - Inogadzirwa kana paine chikanganiso mukutengeserana pakati paTenzi neFDDR
- IO_CAL_INT - Inokugonesa kuti udzokorore maDDR I/O's nekunyorera kuDDR controller marejista kuburikidza neiyo APB yekumisikidza interface. Kana kuenzanisa kwapera, kukanganisa uku kunosimudzwa. Kuti uwane ruzivo nezve I / O recalibration, tarisa iyo Microsemi SmartFusion2 Users Guide.
- PLL_LOCK_INT - Inoratidza kuti FDDR FPLL yakakiyiwa
- PLL_LOCKLOST_INT - Inoratidza kuti FDDR FPLL yarasa kukiya
- FDDR_ECC_INT - Inoratidza kukanganisa kumwe chete kana maviri-bit kwaonekwa
Fabric Clock Frequency
Clock frequency calculation zvichienderana neyazvino Clock frequency uye CLOCK divisor, inoratidzwa muMHz.
Fabric Clock Frequency (muMHz) = Clock Frequency / Clock divisor
Memory Bandwidth
Memory bandwidth kuverenga zvichibva pane yako ikozvino Clock Frequency kukosha muMbps.
Memory Bandwidth (muMbps) = 2 * Clock Frequency
Total Bandwidth
Yese bandwidth kuverenga zvichibva pane yako yazvino Clock Frequency, Data Width uye CLOCK divisor, muMbps.
Total Bandwidth (muMbps) = (2 * Clock Frequency * Data Width) / CLOCK Divisor
FDDR Controller Configuration
Paunoshandisa Fabric DDR Controller kuti uwane yekunze DDR Memory, iyo DDR Controller inofanira kugadzirwa panguva yekumhanya. Izvi zvinoitwa nekunyora dhizaini yekumisikidza kune yakatsaurwa DDR controller kumisikidzwa marejista. Iyi data yekumisikidza inoenderana nehunhu hweyekunze DDR ndangariro uye application yako. Ichi chikamu chinotsanangura maitiro ekuisa aya magadzirirwo maparamita muFDDR controller configurator uye kuti iyo data yekumisikidza inofambiswa sei sechikamu cheiyo yese Peripheral Initialization solution. Tarisa kune Peripheral Initialization User Guide kuti uwane ruzivo rwakakwana nezve Peripheral Initialization solution.
Fabric DDR Control Registers
Iyo Fabric DDR Controller ine seti yemarejista inoda kugadzirwa panguva yekumhanya. Magadzirirwo emhando dzemarejista aya anomiririra akasiyana paramita (yeexample, DDR modhi, PHY hupamhi, kuputika modhi, ECC, nezvimwewo). Kuti uwane rumwe ruzivo nezve DDR controller kumisikidza marejista, tarisa iyo Microsemi SmartFusion2 Mushandisi's Guide.
Fabric DDR Registers Configuration
Shandisa Memory Initialization (Mufananidzo 2-1) uye Memory Nguva (Mufananidzo 2-2) ma tabo kuti uise maparameter anoenderana neDDR Memory yako uye kushandiswa. Hwaro dzaunopinda mumatabu aya dzinoshandurudzwa otomatiki kune dzakakodzera rejista kukosha. Paunodzvanya imwe parameter, rejista yayo inoenderana inotsanangurwa muRejista Tsanangudzo Window (Mufananidzo 1-1 papeji 4).
Mufananidzo 2-1 • FDDR Configuration - Memory Initialization Tab
Mufananidzo 2-2 • FDDR Configuration - Memory Timing Tab
Kupinza DDR Configuration Files
Pamusoro pekupinda DDR Memory paramita uchishandisa Memory Initialization uye Timing tabo, unogona kuendesa DDR rejista hunhu kubva kune file. Kuti uite kudaro, tinya bhatani reImport Configuration uye enda kune zvinyorwa file ine DDR mazita ekunyoresa uye kukosha. Mufananidzo 2-3 inoratidza syntax yekumisikidzwa kwekunze.
Mufananidzo 2-3 • DDR Rejista Configuration File Syntax
Cherechedza: Kana ukasarudza kupinza marejitari maitiro pane kuapinda uchishandisa iyo GUI, iwe unofanirwa kutsanangura ese anodiwa marejitari kukosha. Tarisa kune SmartFusion2 Mushandisi Gwaro kuti uwane ruzivo
Kutumira kunze DDR Configuration Files
Iwe unogona zvakare kutumira iyo yazvino rejista yekumisikidza data mune chinyorwa file. Izvi file ichange iine maregisheni emhando dzawakaunza kunze kwenyika (kana iripo) pamwe neayo akaverengerwa kubva kuGUI paramita yawakaisa mubhokisi rehurukuro.
Kana iwe uchida kugadzirisa shanduko yawakaita kune DDR rejisita kumisikidza, unogona kuzviita neDzosera Default. Izvi zvinodzima data rese redhijitari yekumisikidza uye unofanirwa kuendesa kunze kana kuisa iyi data. Iyo data inoiswa patsva kune hardware reset kukosha.
Yakagadzirwa Data
Dzvanya OK kuti uite zvigadziriso. Zvichienderana nezvawaisa muGeneral, Memory Nguva uye Memory Initialization tabo, iyo FDDR Configurator inokokorodza kukosha kune ese DDR kumisikidzwa marejista uye inotumira kunze ukoshi uhwu muchirongwa chako chefirmware uye simulation. files. The exported file Syntax inoratidzwa mumufananidzo 2-4.
Mufananidzo 2-4 • Exported DDR Register Configuration File Syntax
Firmware
Paunogadzira iyo SmartDesign, inotevera files inogadzirwa mu /firmware/ drivers_config/sys_config dhairekitori. Izvi files inodiwa kuti CMSIS firmware core iunganidzwe zvakanaka uye iine ruzivo maererano nedhizaini yako yazvino, kusanganisira peripheral configuration data uye wachi yekumisikidza ruzivo rweMSS. Usagadzirise izvi files nemaoko, sezvavanogadzirwazve pese pese paunogadzira midzi yako patsva.
- sys_config.c
- sys_config.h
- sys_config_mddr_define.h - MDDR configuration data.
- sys_config_fddr_define.h - FDDR kugadzirisa data.
- sys_config_mss_clocks.h – MSS wachi configuration
Simulation
Paunogadzira iyo SmartDesign yakabatana neMSS yako, inotevera simulation files inogadzirwa mu / simulation dhairekitori:
- test.bfm – Yepamusoro-nhanho BFM file iyo inotanga kuurayiwa panguva chero yekufungidzira inoshandisa SmartFusion2 MSS Cortex-M3 processor. Inoita peripheral_init.bfm uye user.bfm, nenzira iyoyo.
- peripheral_init.bfm -Ine maitiro eBFM anotevedzera CMSIS ::SystemInit () basa rinomhanya paCortex-M3 usati wapinda main() maitiro. Inokopa data yekumisikidza yechero peripheral inoshandiswa mudhizaini kune iyo chaiyo peripheral configuration marejista yobva yamirira kuti maperipherals ese agadzirire asati ataura kuti mushandisi anogona kushandisa aya maperipheral.
- FDDR_init.bfm -Ine BFM yekunyora mirairo inoteedzera zvinyorwa zveFabric DDR kumisikidza regista data yawakaisa (uchishandisa Rongedza Rejista dialog box) muDDR Controller marejista.
- user.bfm - Yakagadzirirwa mirairo yemushandisi. Iwe unogona kutevedzera iyo datapath nekuwedzera yako BFM mirairo mune izvi file. Mirairo mune izvi file ichaitwa mushure mekunge peripheral_init.bfm yapera.
Kushandisa the files pamusoro, nzira yekumisikidza inoteedzerwa otomatiki. Unongoda kugadzirisa mushandisi.bfm file kutevedzera iyo datapath. Usagadzirise test.bfm, peripheral_init.bfm, kana MDDR_init.bfm files seizvi files inogadzirwazve pese pese paunogadzira midzi yako patsva.
Fabric DDR Configuration Path
Iyo Peripheral Initialization mhinduro inoda kuti, pamusoro pekutsanangudza Mucheka DDR kumisikidza rejista kukosha, iwe unogadzirisa iyo APB yekumisikidza data nzira muMSS (FIC_2). Iyo SystemInit () basa inonyora iyo data kuFDDR dhizaini yekumisikidza kuburikidza neFIC_2 APB interface.
Cherechedza: Kana iwe uri kushandisa System Builder nzira yekumisikidza inoiswa uye yakabatana otomatiki.
Mufananidzo 2-5 • FIC_2 Configurator Overview
Kugadzirisa iyo FIC_2 interface:
- Vhura iyo FIC_2 configurator dialog (Mufananidzo 2-5) kubva kuMSS configurator.
- Sarudza iyo Initialize peripherals uchishandisa Cortex-M3 sarudzo.
- Ita shuwa kuti MSS DDR yakatariswa, sezvakaita Fabric DDR/SERDES blocks kana uri kuishandisa.
- Dzvanya OK kuchengetedza marongero ako. Izvi zvinofumura FIC_2 configuration ports (Clock, Reset, uye APB mabhazi interfaces), sezvinoratidzwa mumufananidzo 2-6.
- Gadzira iyo MSS. FIC_2 ports (FIC_2_APB_MASTER, FIC_2_APB_M_PCLK neFIC_2_APB_M_RESET_N) dzave pachena paMSS interface uye dzinogona kubatana neCoreSF2Config neCoreSF2Reset sekuenderana nePeripheral Initialization solution
Mufananidzo 2-6 • FIC_2 Ports
Port Description
FDDR Core Ports
Tafura 3-1 • FDDR Core Ports
| Port Name | Direction | Tsanangudzo |
| CORE_RESET_N | IN | FDDR Controller Reset |
| CLK_BASE | IN | FDDR Fabric Interface Clock |
| FPLL_LOCK | OUT | FDDR PLL Kiya kubuda - yakakwirira kana FDDR PLL yakavharwa |
| CLK_BASE_PLL_LOCK | IN | Fabric PLL Lock Input. Kupinza uku kunoburitswa chete kana kushandisa FAB_PLL_LOCK sarudzo yasarudzwa. |
Kuvhiringidza Ports
Iri boka rezvikepe rinoburitswa kana ukasarudza iyo Inogonesa Kuvhiringidza sarudzo.
Tafura 3-2 • Kuvhiringidza Zviteshi
| Port Name | Direction | Tsanangudzo |
| PLL_LOCK_INT | OUT | Inosimbisa kana FDDR PLL ichikiya. |
| PLL_LOCKLOST_INT | OUT | Asserts kana FDDR PLL kiyi yarasika. |
| ECC_INT | OUT | Inosimbisa kana ECC Chiitiko chikaitika. |
| IO_CALIB_INT | OUT | Inosimbisa kana I/O kuenzanisa kwapera. |
| FIC_INT | OUT | Inoti kana paine chikanganiso muAHB/AXI protocol paFabric interface. |
APB3 Configuration Interface
Tafura 3-3 • APB3 Configuration Interface
| Port Name | Direction | Tsanangudzo |
| APB_S_PENABLE | IN | Muranda Enable |
| APB_S_PSEL | IN | Muranda Sarudza |
| APB_S_PWRITE | IN | Nyora Enable |
| APB_S_PADDR[10:2] | IN | Kero |
| APB_S_PWDATA[15:0] | IN | Nyora Data |
| APB_S_PREADY | OUT | Muranda Akagadzirira |
| APB_S_PSLVERR | OUT | Muranda Error |
| APB_S_PRDATA[15:0] | OUT | Read Data |
| APB_S_PRESET_N | IN | Muranda Reset |
| APB_S_PCLK | IN | Clock |
DDR PHY Interface
Tafura 3-4 • DDR PHY Interface
| Port Name | Direction | Tsanangudzo |
| FDDR_CAS_N | OUT | DRAM CASN |
| FDDR_CKE | OUT | DRAM CKE |
| FDDR_CLK | OUT | Clock, P side |
| FDDR_CLK_N | OUT | Clock, N side |
| FDDR_CS_N | OUT | DRAM CSN |
| FDDR_ODT | OUT | DRAM ODT |
| FDDR_RAS_N | OUT | DRAM RASN |
| FDDR_RESET_N | OUT | DRAM Reset yeDDR3 |
| FDDR_WE_N | OUT | DRAM WEN |
| FDDR_ADDR[15:0] | OUT | Dram Kero bits |
| FDDR_BA[2:0] | OUT | Dram Bank Kero |
| FDDR_DM_RDQS[4:0] | INOUT | Dram Data Mask |
| FDDR_DQS[4:0] | INOUT | Dram Data Strobe Input/Output – P Side |
| FDDR_DQS_N[4:0] | INOUT | Dram Data Strobe Input/Output – N Side |
| FDDR_DQ[35:0] | INOUT | DRAM Data Input/Output |
| FDDR_FIFO_WE_IN[2:0] | IN | FIFO muchiratidzo |
| FDDR_FIFO_WE_OUT[2:0] | OUT | FIFO kunze chiratidzo |
| FDDR_DM_RDQS ([3:0]/[1:0]/[0]) | INOUT | Dram Data Mask |
| FDDR_DQS ([3:0]/[1:0]/[0]) | INOUT | Dram Data Strobe Input/Output – P Side |
| FDDR_DQS_N ([3:0]/[1:0]/[0]) | INOUT | Dram Data Strobe Input/Output – N Side |
| FDDR_DQ ([31:0]/[15:0]/[7:0]) | INOUT | DRAM Data Input/Output |
| FDDR_DQS_TMATCH_0_IN | IN | FIFO muchiratidzo |
| FDDR_DQS_TMATCH_0_OUT | OUT | FIFO kunze chiratidzo |
| FDDR_DQS_TMATCH_1_IN | IN | FIFO muchiratidzo (32-bit chete) |
| FDDR_DQS_TMATCH_1_OUT | OUT | FIFO kunze chiratidzo (32-bit chete) |
| FDDR_DM_RDQS_ECC | INOUT | Dram ECC Data Mask |
| FDDR_DQS_ECC | INOUT | Dram ECC Data Strobe Input/Output – P Side |
| FDDR_DQS_ECC_N | INOUT | Dram ECC Data Strobe Input/Output – N Side |
| FDDR_DQ_ECC ([3:0]/[1:0]/[0]) | INOUT | DRAM ECC Data Input/Output |
| FDDR_DQS_TMATCH_ECC_IN | IN | ECC FIFO muchiratidzo |
| FDDR_DQS_TMATCH_ECC_OUT | OUT | ECC FIFO kunze chiratidzo (32-bit chete) |
Cherechedza: Port wides kune mamwe madoko anoshanduka zvichienderana nekusarudzwa kwehupamhi hwePHY. Chiratidzo "[a:0]/ [b:0]/[c:0]" chinoshandiswa kuratidza zviteshi zvakadaro, apo "[a:0]" inoreva hupamhi hwechiteshi kana 32-bit PHY upamhi hwasarudzwa. , “[b:0]” inofambirana nehupamhi hwe16-bit PHY, uye “[c:0]” inofambirana nehupamhi hwe8-bit PHY.
AXI Bhazi Interface
Tafura 3-5 • AXI Bus Interface
| Port Name | Direction | Tsanangudzo |
| AXI_S_AWREADY | OUT | Nyora kero yakagadzirira |
| AXI_S_WREADY | OUT | Nyora kero yakagadzirira |
| AXI_S_BID[3:0] | OUT | Mhinduro ID |
| AXI_S_BRSP[1:0] | OUT | Nyora mhinduro |
| AXI_S_BVALID | OUT | Nyora mhinduro inoshanda |
| AXI_S_ARREADY | OUT | Verenga kero yagadzirira |
| AXI_S_RID[3:0] | OUT | Verenga ID Tag |
| AXI_S_RRSP[1:0] | OUT | Verenga Mhinduro |
| AXI_S_RDATA[63:0] | OUT | Verenga data |
| AXI_S_RLAST | OUT | Verenga Pakupedzisira - Ichi chiratidzo chinoratidza kuchinjisa kwekupedzisira mukuverenga kuputika. |
| AXI_S_RVALID | OUT | Verenga kero inoshanda |
| AXI_S_AWID[3:0] | IN | Nyora Kero ID |
| AXI_S_AWADDR[31:0] | IN | Nyora kero |
| AXI_S_AWLEN[3:0] | IN | Kuputika kureba |
| AXI_S_AWSIZE[1:0] | IN | Kuputika saizi |
| AXI_S_AWBURST[1:0] | IN | Burst type |
| AXI_S_AWLOCK[1:0] | IN | Kiya mhando - Ichi chiratidzo chinopa rumwe ruzivo nezve maatomu maitiro ekutamisa. |
| AXI_S_AWVALID | IN | Nyora kero inoshanda |
| AXI_S_WID[3:0] | IN | Nyora Data ID tag |
| AXI_S_WDATA[63:0] | IN | Nyora data |
| AXI_S_WSTRB[7:0] | IN | Nyora strobes |
| AXI_S_WLAST | IN | Nyora kwekupedzisira |
| AXI_S_WVALID | IN | Nyora zvinoshanda |
| AXI_S_BREADY | IN | Nyora wakagadzirira |
| AXI_S_ARID[3:0] | IN | Verenga Kero ID |
| AXI_S_ARADDR[31:0] | IN | Verenga kero |
| AXI_S_ARLEN[3:0] | IN | Kuputika kureba |
| AXI_S_ARSIZE[1:0] | IN | Kuputika saizi |
| AXI_S_ARBURST[1:0] | IN | Burst type |
| AXI_S_ARLOCK[1:0] | IN | Kiya Type |
| AXI_S_ARVALID | IN | Verenga kero inoshanda |
| AXI_S_RREADY | IN | Verenga kero yagadzirira |
| Port Name | Direction | Tsanangudzo |
| AXI_S_CORE_RESET_N | IN | MDDR Global Reset |
| AXI_S_RMW | IN | Inoratidza kana mabhayiti ese e64-bit nzira ariko kune ese mabhiti eAXI kutamiswa.
|
AHB0 Bhazi Interface
Tafura 3-6 • AHB0 Bus Interface
| Port Name | Direction | Tsanangudzo |
| AHB0_S_HREADYOUT | OUT | AHBL muranda akagadzirira - Kana yakakwira yekunyora inoratidza kuti muranda akagadzirira kugamuchira data uye kana yakakwira yekuverenga inoratidza kuti data inoshanda. |
| AHB0_S_HRSP | OUT | AHBL mamiriro ekupindura - Kana ichityairwa kumusoro pakupera kwekutengeserana inoratidza kuti kutengeserana kwapera nezvikanganiso. Kana inofambiswa yakaderera pakupera kwekutengeserana inoratidza kuti kutengeserana kwapera zvinobudirira. |
| AHB0_S_HRDATA[31:0] | OUT | AHBL verenga data - Verenga data kubva kumuranda kuenda kuna tenzi |
| AHB0_S_HSEL | IN | AHBL muranda sarudza - Kana zvichinzi, muranda ndiye akasarudzwa iye zvino muranda weAHBL mubhazi reAHB. |
| AHB0_S_HADDR[31:0] | IN | AHBL kero - byte kero pane iyo AHBL interface |
| AHB0_S_HBURST[2:0] | IN | AHBL Burst Length |
| AHB0_S_HSIZE[1:0] | IN | Saizi yekufambisa yeAHBL - Inoratidza saizi yekutamisa kwazvino (8/16/32 byte transactions chete) |
| AHB0_S_HTRANS[1:0] | IN | AHBL yekufambisa mhando - Inoratidza mhando yekuchinjisa yeazvino transaction. |
| AHB0_S_HMASTLOCK | IN | AHBL kukiya - Kana ichinzi kuendesa kwazvino chikamu cheakakiyiwa kutengeserana. |
| AHB0_S_HWRITE | IN | AHBL nyora - Kana yakakwirira inoratidza kuti ikozvino kutengeserana kunyora. Kana yakaderera inoratidza kuti kutengeserana kwazvino kunoverengwa. |
| AHB0_S_HREADY | IN | AHBL yakagadzirira - Kana yakakwira, inoratidza kuti muranda akagadzirira kugamuchira kutengeserana kutsva. |
| AHB0_S_HWDATA[31:0] | IN | AHBL nyora data - Nyora data kubva kuna tenzi kuenda kumuranda |
AHB1 Bhazi Interface
Tafura 3-7 • AHB1 Bus Interface
| Port Name | Direction | Tsanangudzo |
| AHB1_S_HREADYOUT | OUT | AHBL muranda akagadzirira - Kana yakakwira yekunyora, inoratidza kuti muranda akagadzirira kugamuchira data, uye kana yakakwirira kuverenga, inoratidza kuti data inoshanda. |
| AHB1_S_HRSP | OUT | AHBL mamiriro ekupindura - Kana ichityairwa kumusoro pakupera kwekutengeserana inoratidza kuti kutengeserana kwapera nezvikanganiso. Kana yadzikiswa yakaderera pakupera kwekutengeserana, inoratidza kuti kutengeserana kwapera zvinobudirira. |
| AHB1_S_HRDATA[31:0] | OUT | AHBL verenga data - Verenga data kubva kumuranda kuenda kuna tenzi |
| AHB1_S_HSEL | IN | AHBL muranda sarudza - Kana zvichinzi, muranda ndiye akasarudzwa iye zvino muranda weAHBL mubhazi reAHB. |
| AHB1_S_HADDR[31:0] | IN | AHBL kero - byte kero pane iyo AHBL interface |
| AHB1_S_HBURST[2:0] | IN | AHBL Burst Length |
| AHB1_S_HSIZE[1:0] | IN | Saizi yekufambisa yeAHBL - Inoratidza saizi yekuchinjisa ikozvino (8/16/32 byte transactions chete). |
| AHB1_S_HTRANS[1:0] | IN | AHBL yekufambisa mhando - Inoratidza mhando yekuchinjisa yeazvino transaction. |
| AHB1_S_HMASTLOCK | IN | AHBL kukiya - Kana yakasimbiswa, iko kutamisa kwazvino chikamu cheakakiyiwa kutengeserana. |
| AHB1_S_HWRITE | IN | AHBL nyora - Kana yakakwirira, inoratidza kuti ikozvino kutengeserana kunyora. Kana yakaderera, inoratidza kuti kutengeserana kwazvino kunoverengwa. |
| AHB1_S_HREADY | IN | AHBL yakagadzirira - Kana yakakwira, inoratidza kuti muranda akagadzirira kugamuchira kutengeserana kutsva. |
| AHB1_S_HWDATA[31:0] | IN | AHBL nyora data - Nyora data kubva kuna tenzi kuenda kumuranda |
Product Support
Microsemi SoC Zvigadzirwa Boka inodzosera zvigadzirwa zvayo neakasiyana masevhisi ekutsigira, anosanganisira Mutengi Sevhisi, Mutengi Unyanzvi Tsigiro Center, a websaiti, tsamba dzemagetsi, uye mahofisi ekutengesa pasi rese. Apendikisi iyi ine ruzivo rwekubata Microsemi SoC Zvigadzirwa Boka uye kushandisa aya masevhisi ekutsigira.
Mabatiro evatengi
Bata Mutengi Sevhisi kune isiri-tekinoroji yechigadzirwa rutsigiro, semitengo yechigadzirwa, kukwidziridzwa kwechigadzirwa, ruzivo rwekuvandudza, mamiriro eodha, uye mvumo.
Kubva kuNorth America, fonera 800.262.1060
Kubva kune dzimwe nyika, fonera 650.318.4460
Fax, kubva kupi zvako munyika, 408.643.6913
Mutengi Technical Support Center
Microsemi SoC Zvigadzirwa Boka tsvimbo yayo Mutengi Unyanzvi Tsigiro Center ine mainjiniya ane hunyanzvi anogona kubatsira kupindura Hardware yako, software, uye dhizaini mibvunzo nezve Microsemi SoC Zvigadzirwa. Mutengi Unyanzvi Wetsigiro Center inopedza nguva yakawanda ichigadzira zvinyorwa zvekushandisa, mhinduro kumibvunzo yakajairwa dhizaini kutenderera, zvinyorwa zvenyaya dzinozivikanwa, uye akasiyana maFAQ. Saka, usati watibata, ndapota shanyira yedu online zviwanikwa. Zvingangodaro kuti isu takatopindura mibvunzo yako.
Technical Support
Shanyira Rutsigiro rweMutengi websaiti (www.microsemi.com/soc/support/search/default.aspx) kuti uwane rumwe ruzivo nerutsigiro. Mhinduro dzakawanda dziripo pane zvinotsvakwa web resource inosanganisira dhayagiramu, mifananidzo, uye zvinongedzo kune zvimwe zviwanikwa pa website.
Website
Unogona kutarisa akasiyana siyana ehunyanzvi uye asiri-tekinoroji ruzivo pane iyo SoC peji repamba, pa www.microsemi.com/soc.
Kubata neCustomer Technical Support Center
Mainjiniya vane hunyanzvi vanoshanda muTechnical Support Center. Iyo Technical Support Center inogona kufonerwa neemail kana kuburikidza neMicrosemi SoC Zvigadzirwa Boka website.
Unogona kutaurira mibvunzo yako yehunyanzvi kukero yedu yeemail uye wogashira mhinduro neemail, fax, kana foni. Zvakare, kana uine matambudziko ekugadzira, unogona kutumira email dhizaini yako files kuwana rubatsiro. Isu tinogara tichitarisa iyo email account zuva rese. Paunenge uchitumira chikumbiro chako kwatiri, ndapota iva nechokwadi chekuisa zita rako rizere, zita rekambani, uye ruzivo rwako rwekufonera kuti unyatso kugadzirisa chikumbiro chako. Iyo tekinoroji yekutsigira email kero ndeye soc_tech@microsemi.com.
Nyaya dzangu
Microsemi SoC Zvigadzirwa Boka vatengi vanogona kuendesa uye kuteedzera matekiniki makesi online nekuenda kuNyaya Yangu
Kunze kweUS
Vatengi vanoda rubatsiro kunze kwenzvimbo dzenguva dzeUS vanogona kubata rubatsiro rwehunyanzvi kuburikidza neemail (soc_tech@microsemi.com) kana kubata hofisi yekutengesa yemuno. Sales office zvinyorwa zvinogona kuwanikwa pa www.microsemi.com/soc/company/contact/default.aspx.
ITAR Technical Support
Kuti uwane rutsigiro rwehunyanzvi paRH uye RT FPGAs dzinodzorwa neInternational Traffic muArms Regulations (ITAR), taura nesu kuburikidza soc_tech_itar@microsemi.com. Neimwe nzira, mukati meNyaya Dzangu, sarudza Hongu mune ITAR yekudonha-pasi runyorwa. Kuti uwane runyorwa rwakakwana rweITAR-yakadzorwa Microsemi FPGAs, shanyira ITAR web peji.
Microsemi Corporation (NASDAQ: MSCC) inopa ruzivo rwakakwana rwezvigadziriso zve semiconductor zve: aerospace, kudzivirira uye kuchengeteka; bhizinesi uye kutaurirana; uye maindasitiri uye mamwe magetsi misika. Zvigadzirwa zvinosanganisira kuita kwepamusoro-soro, kuvimbika kwepamusoro analog uye RF zvishandiso, siginecha yakasanganiswa uye RF yakasanganiswa maseketi, customizable SoCs, FPGAs, uye yakakwana subsystems. Microsemi inotungamirwa muAliso Viejo, Calif. Dzidza zvakawanda pa www.microsemi.com.
© 2014 Microsemi Corporation. Kodzero dzese dzakachengetwa. Microsemi uye iyo Microsemi logo zviratidzo zveMicrosemi Corporation. Mamwe matrademark ese uye masevhisi mamaki zvinhu zvevaridzi vazvo.
Microsemi Corporate Headquarters
Imwe Enterprise, Aliso Viejo CA 92656 USA
Mukati meUSA: +1 949-380-6100
Sales: +1 949-380-6136
Fax: +1 949-215-4996
Zvinyorwa / Zvishandiso
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