SmartFusion2 MSS
Nhazi njikwa DDR
Libero SoC v11.6 na mgbe e mesịrị
Okwu mmalite
SmartFusion2 MSS nwere ihe njikwa DDR agbakwunyere. Ihe njikwa DDR a bu n'obi jikwaa ebe nchekwa DDR na-apụ apụ. Enwere ike ịnweta onye njikwa MDDR site na MSS yana site na akwa FPGA. Na mgbakwunye, enwere ike ịfefe onye njikwa DDR, na-enye mgbakwunye mgbakwunye na akwa FPGA (Mode Controller Mode (SMC)).
Iji hazie onye njikwa MSS DDR nke ọma, ị ga-emerịrị:
- Họrọ ụzọ data site na iji MDR Configurator.
- Tọọ ụkpụrụ ndekọ aha maka ndebanye aha onye njikwa DDR.
- Họrọ ugboro elekere DDR ebe nchekwa na akwa FPGA na nha elekere MDR (ọ bụrụ na achọrọ ya) site na iji MSS CCC Configurator.
- Jikọọ interface nhazi APB nke onye njikwa dịka ngwọta mmalite mmalite nke Peripheral kọwara. Maka sekit initialization MDR nke Sistemụ Nrụpụta wuru, rụtụ aka na “Ụzọ nhazi nhazi MSS DDR” na ibe 13 na eserese 2-7.
Ị nwekwara ike wuo sekit mmalite mmalite nke gị site na iji guzoro (ọ bụghị site na Onye Nrụpụta Sistemụ) Mbido Mkpebi. Rụtụ aka na ntuziaka onye ọrụ mmalite SmartFusion2 Standalone Peripheral.
Onye nhazi MDR
A na-eji MDR Configurator hazie ụzọ data n'ozuzu ya yana ebe nchekwa DDR mpụga maka onye njikwa MSS DDR.
Taabụ Ozuruọnụ na-edobe ntọala ebe nchekwa na akwa ákwà gị (Foto 1-1).
Ntọala ebe nchekwa
Tinye oge nhazi ebe nchekwa DDR. Nke a bụ oge ebe nchekwa DDR chọrọ ịmalite. Uru ndabara bụ 200 anyị. Rụtụ aka na mpempe akwụkwọ data ebe nchekwa DDR gị maka uru ziri ezi ịbanye.
Jiri Ntọala ebe nchekwa hazie nhọrọ ebe nchekwa gị na MDDR.
- Ụdị ebe nchekwa - LPDDR, DDR2, ma ọ bụ DDR3
- Ogologo data - 32-bit, 16-bit ma ọ bụ 8-bit
- SECDED agbanyere ECC - Gbanye ma ọ bụ gbanyụọ
- Atụmatụ ikpe ikpe - Ụdị-0, Ụdị -1, Ụdị-2, Ụdị-3
- NJ Kachasịsịsịsịsịsịsịsịsịsịsịsịsịsịsịsịsịsịsịsịsịnụ 0 ruo 15
- Obosara adreesị (bits) - Rụtụ aka na mpempe akwụkwọ data ebe nchekwa DDR gị maka ọnụọgụ ahịrị ahịrị, ụlọ akụ, na ibebe adreesị kọlụm maka ebe nchekwa LPDDR/DDR2/DDR3 ị na-eji. họrọ menu ndọda ka ịhọrọ uru ziri ezi maka ahịrị/ụlọ akụ/ogidi dịka mpempe data nke ebe nchekwa LPDDR/DDR2/DDR3 si dị.
Mara: Ọnụọgụ dị na listi mgbada na-ezo aka na ọnụọgụ nke ibe n'ibe adreesị, ọ bụghị ọnụọgụ zuru oke nke ahịrị / ụlọ akụ / ogidi. Maka exampỌ bụrụ na ebe nchekwa DDR gị nwere ụlọ akụ 4, họrọ 2 (2 ² = 4) maka ụlọ akụ. Ọ bụrụ na ebe nchekwa DDR gị nwere ụlọ akụ 8, họrọ 3 (2³ = 8) maka ụlọ akụ.
Ntọala ihu ákwà
Site na ndabara, edoziri ihe nrụpụta Cortex-M3 siri ike iji nweta DDR Controller. Ị nwekwara ike ikwe ka Master akwa nweta DDR Controller site n'ịkwado igbe nrịbama nke Interface Setting. N'okwu a, ị nwere ike ịhọrọ otu n'ime nhọrọ ndị a:
- Jiri Interface AXI - Master akwa na-enweta DDR Controller site na interface 64-bit AXI.
- Jiri Interface AHBlite Single - Master akwa na-enweta DDR Controller site na otu interface AHB 32-bit.
- Jiri interface AHBlite abụọ - Masters akwa abụọ na-enweta DDR Controller site na iji oghere AHB 32-bit abụọ.
Nhazi view (Foto 1-1) na-emelite dị ka nhọrọ Fabric Interface gị siri dị.
I/O Drive Ike (DDR2 na DDR3 naanị)
Họrọ otu n'ime ike draịva ndị a maka DDR I/Os gị:
- Ọkara Drive Ike
- Ike mbanye zuru oke
Libero SoC na-edobe ọkọlọtọ DDR I/O maka sistemụ MDDr gị dabere na ụdị ebe nchekwa DDR gị yana ike I/O Drive (dị ka egosiri na Tab le 1-1).
Tebụl 1-1 • I/O Drive Strength na DDR Memory Type
| Ụdị ebe nchekwa DDR | Ọkara Ike Drive | Mbanye ike zuru oke |
| DDR3 | SSTL15I | SSTL15II |
| DDR2 | SSTL18I | SSTL18II |
| LPDDR | LPDRI | LPDRII |
Standard IO (LPDDR naanị)
Họrọ otu n'ime nhọrọ ndị a:
- LVCMOS18 (Ike kacha ala) maka ọkọlọtọ LVCMOS 1.8V IO. Ejiri ya na ngwa LPDDR1.
- Mara LPDDRI: Tupu ịhọrọ ọkọlọtọ a, gbaa mbọ hụ na bọọdụ gị kwadoro ọkọlọtọ a. Ị ga-eji nhọrọ a mgbe ị na-achọ M2S-EVAL-KIT ma ọ bụ bọọdụ SF2-STARTER-KIT. Ụkpụrụ LPDDRI IO chọrọ ka etinyere IMP_CALIB resistor na bọọdụ.
IO calibration (LPDDR naanị)
Họrọ otu n'ime nhọrọ ndị a mgbe ị na-eji ọkọlọtọ LVCMOS18 IO:
- On
- Gbanyụọ (Ọkachamara)
Calibration ON na Gbanyụọ na nhọrọ na-achịkwa iji ngọngọ calibration IO nke na-eme ka ndị ọkwọ ụgbọala IO gaa na resistor mpụga. Mgbe agbanyụrụ, ngwaọrụ ahụ na-eji nhazi IO ọkwọ ụgbọ ala nke atọrọ.
Mgbe ONYE, nke a chọrọ 150-ohm IMP_CALIB resistor ka etinyere na PCB.
A na-eji nke a iji mezie IO na njirimara PCB. Agbanyeghị, mgbe atọrọ na ON, ekwesịrị itinye resistor ma ọ bụ njikwa ebe nchekwa agaghị ebido.
Maka ozi ndị ọzọ, rụtụ aka na AC393-SmartFusion2 na IGLOO2 Board Design Guidelines Application
Rịba ama yana ntuziaka onye ọrụ SmartFusion2 SoC FPGA High Speed DDR Interfaces.
Nhazi onye njikwa MDR
Mgbe ị na-eji MSS DDR Controller iji nweta ebe nchekwa DDR mpụga, DDR Controller ga-ahazirịrị n'oge ọ na-agba ọsọ. A na-eme nke a site na ide data nhazi na ndekọ nhazi nhazi DDR raara onwe ya nye. Data nhazi a dabere na njirimara nke ebe nchekwa DDR mpụga yana ngwa gị. Akụkụ a na-akọwa otu esi etinye usoro nhazi ndị a na nhazi njikwa MSS DDR yana otu esi ejikwa data nhazi ahụ dị ka akụkụ nke ngwọta mmalite nke Peripheral n'ozuzu ya.
Ndị ndebanye aha njikwa MSS DDR
Onye njikwa MSS DDR nwere ndebanye aha nke kwesịrị ịhazi n'oge ọ na-agba ọsọ. Ụkpụrụ nhazi maka ndekọ ndị a na-anọchi anya paramita dị iche iche, dị ka ọnọdụ DDR, obosara PHY, ọnọdụ mgbawa, na ECC. Maka nkọwa zuru ezu gbasara ndekọ nhazi njikwa DDR, rụtụ aka na ntuziaka onye ọrụ SmartFusion2 SoC FPGA High Speed DDR Interfaces.
Nhazi nhazi nke MDR
Jiri mmalite mmalite ebe nchekwa (ọgụgụ 2-1, eserese 2-2, na eserese 2-3) na oge ebe nchekwa (ọgụgụ 2-4) iji tinye paramita kwekọrọ na ebe nchekwa DDR na ngwa gị. A na-asụgharị ụkpụrụ ndị ị tinyere na taabụ ndị a na-akpaghị aka ka ọ bụrụ ụkpụrụ ndebanye aha kwesịrị ekwesị. Mgbe ị pịrị otu paramita a kapịrị ọnụ, a na-akọwa ndekọ aha ya kwekọrọ na pane Description Description (akụkụ dị ala na foto 1-1 na ibe 4).
Mmalite ebe nchekwa
Taabụ mmalite mmalite ebe nchekwa na-enye gị ohere ịhazi ụzọ ịchọrọ ibido ncheta LPDDR/DDR2/DDR3 gị. Nchịkọta na nhọrọ dị na taabụ mmalite mmalite ebe nchekwa dị iche na ụdị ebe nchekwa DDR (LPDDR/DDR2/DDR3) ị na-eji. Rụtụ aka na mpempe akwụkwọ data ebe nchekwa DDR gị mgbe ị haziri nhọrọ. Mgbe ị gbanwere ma ọ bụ tinye uru, pane nkọwa ndekọ aha na-enye gị aha aha na aha aha aha nke emelitere. Akpọrọ ụkpụrụ ezighi ezi dị ka ịdọ aka ná ntị. Ọgụgụ 2-1, eserese 2-2, na eserese 2-3 na-egosi taabụ mmalite maka LPDDR, DDR2 na DDR3, n'otu n'otu.
- Ụdị oge – Họrọ 1T ma ọ bụ 2T ọnọdụ oge. Na 1T (ọnọdụ ndabara), onye na-ahụ maka DDR nwere ike ịnye iwu ọhụrụ na okirikiri elekere ọ bụla. Na ọnọdụ oge 2T, onye na-ahụ maka DDR na-ejide adreesị na ụgbọ ala iwu dị irè maka okirikiri elekere abụọ. Nke a na-ebelata arụmọrụ ụgbọ ala na otu iwu kwa elekere abụọ, mana ọ na-abawanye ọnụọgụ nhazi na oge ijide okpukpu abụọ.
- Nwee ume ọhụrụ nke akụkụ-array (naanị LPDDR). Njirimara a bụ maka ịchekwa ike maka LPDDR.
Họrọ otu n'ime ihe ndị a maka onye njikwa iji mee ka ọnụọgụ ebe nchekwa dị ọhụrụ mgbe ị na-enwe ume ọhụrụ:
- Ngwakọta zuru oke: ụlọ akụ 0, 1,2, na 3
- Ọkara n'usoro: Banks 0 na 1
- Usoro nkeji iri na ise: Bank 0
– Otu ụzọ n'usoro nke asatọ: Bank 0 nwere adreesị ahiri MSB=0
– Otu ụzọ na iri na isii: Bank 0 nwere adreesị ahiri MSB na MSB-1 ha abụọ hà 0.
Maka nhọrọ ndị ọzọ niile, rụtụ aka na mpempe akwụkwọ data ebe nchekwa DDR gị mgbe ị haziri nhọrọ.
Oge ebe nchekwa
Nke a taabụ na-enye gị ohere ịhazi paramita oge ebe nchekwa. Rụtụ aka na mpempe akwụkwọ data nke ebe nchekwa LPDDR/ DDR2/DDR3 gị mgbe ị na-ahazi paramita oge ebe nchekwa.
Mgbe ị gbanwere ma ọ bụ tinye uru, pane nkọwa ndekọ aha na-enye gị aha aha na aha aha aha emelitere. Akpọrọ ụkpụrụ ezighi ezi dị ka ịdọ aka ná ntị.
Na-ebubata nhazi DDR Files
Na mgbakwunye na ịbanye DDR Memory parameters site na iji ebe nchekwa initialization na Timeing, ị nwere ike ibubata ụkpụrụ ndebanye aha DDR site na a. file. Iji mee nke a, pịa bọtịnụ nhazi mbubata wee gaa na ederede file nwere DDR aha na ụkpụrụ. Ọgụgụ 2-5 na-egosi syntax nhazi mbubata.
Mara: Ọ bụrụ na ịhọrọ ibubata ụkpụrụ ndekọ aha kama iji GUI tinye ha, ị ga-akọwarịrị ụkpụrụ ndekọ aha niile dị mkpa. Rụtụ aka na SmartFusion2 SoC FPGA High Speed DDR Interfaces ntuziaka onye ọrụ maka nkọwa.
Na-ebupụ nhazi DDR Files
Ị nwekwara ike mbupụ data nhazi ndekọ aha ugbu a n'ime ederede file. Nke a file ga-enwe ụkpụrụ ndebanye aha nke ị webatara (ma ọ bụrụ na ọ dị) yana nke agbakọrọ site na paramita GUI ị banyere na mkparịta ụka a.
Ọ bụrụ na ịchọrọ imezi mgbanwe ndị i mere na nhazi ndebanye aha DDR, ị nwere ike ime ya site na Weghachite Default. Mara na nke a na-ehichapụ data nhazi ndekọ aha niile na ị ga-ebubata ma ọ bụ tinyeghachi data a. Atọgharịrị data ahụ na ụkpụrụ nrụpụta ngwaike.
Emepụtara data
Pịa OK ka ịmepụta nhazi ahụ. Dabere na ntinye gị na taabụ General, Oge ebe nchekwa na mmalite mmalite, MDR Configurator na-agbakọ ụkpụrụ maka ndekọ nhazi DDR niile wee bupụ ụkpụrụ ndị a n'ime ọrụ firmware gị na simulation. files. Nke mbupụ file egosiri syntax na eserese 2-6.
Firmware
Mgbe ị na-emepụta SmartDesign, ndị a files na-eme na /firmware/ drivers_config/sys_config ndekọ. Ndị a files ka achọrọ ka CMSIS firmware core chịkọta nke ọma ma nwee ozi gbasara imewe gị ugbu a gụnyere data nhazi mpaghara yana ozi nhazi elekere maka MSS. Dezie ihe ndị a files aka ka a na-emepụtaghachi ha oge ọ bụla a na-emepụta mgbọrọgwụ mgbọrọgwụ gị.
- sys_config.c
- sys_config.h
- sys_config_mddr_define.h - data nhazi MDR.
- Sys_config_fddr_define.h - data nhazi FDDR.
- sys_config_mss_clocks.h – MSS clocks nhazi nhazi
ịme anwansị
Mgbe ị na-emepụta SmartDesign jikọtara na MSS gị, simulation na-esonụ files na-eme na / ndekọ ndekọ:
- test.bfm – BFM dị elu file nke a na-ebu ụzọ "mere" n'oge ịme anwansị ọ bụla na-eme SmartFusion2 MSS' Cortex-M3 processor. Ọ na-eme peripheral_init.bfm na user.bfm, n'usoro ahụ.
- peripheral_init.bfm - Nwere usoro BFM nke na-eṅomi ọrụ CMSIS :: SystemInit () na-agba ọsọ na Cortex-M3 tupu ịbanye na isi () usoro. Ọ na-eṅomi data nhazi maka akụkụ ọ bụla ejiri na nhazi ahụ gaa na ndekọ nhazi mpaghara ziri ezi wee chere ka akụkụ niile dị njikere tupu ị kwupụta na onye ọrụ nwere ike iji ihe ndị a.
- MDR_init.bfm - Nwere iwu ide BFM nke na-eme ka ọ na-ede nke data ndebanye aha nhazi MSS DDR nke ị banyere (iji dialog Dezie n'elu) n'ime ndekọ nchịkwa DDR.
- user.bfm – Ezubere maka iwu onye ọrụ. Ị nwere ike ịmegharị ụzọ data site na ịgbakwunye iwu BFM nke gị na nke a file. Iwu na nke a file a ga-emecha "peripheral_init.bfm" emechara.
Iji nke files n'elu, a na-eme ka usoro nhazi ahụ na-akpaghị aka. Naanị ị ga-edezi user.bfm file iji megharịa datapath. Dezie test.bfm, peripheral_init.bfm, ma ọ bụ MDR_init.bfm filedị ka ndị a files na-mere ọzọ oge ọ bụla a na-emepụta mgbọrọgwụ mgbọrọgwụ gị.
Ụzọ nhazi MSS DDR
Ngwọta mmalite mmalite nke Peripheral chọrọ na, na mgbakwunye na ịkọwa ụkpụrụ ndekọ aha nhazi MSS DDR, ị na-ahazi ụzọ data nhazi APB na MSS (FIC_2). Ọrụ SystemInit() na-ede data na ndekọ nhazi nke MDDR site na interface FIC_2 APB.
Mara: Ọ bụrụ na ị na-eji Sistemụ Nrụpụta, a na-edozi ụzọ nhazi ma jikọọ ya na-akpaghị aka.
Iji hazie interface FIC_2:
- Mepee mkparịta ụka nhazi FIC_2 (Foto 2-7) site na nhazi MSS.
- Họrọ ihe mmalite mmalite site na iji nhọrọ Cortex-M3.
- Gbaa mbọ hụ na a na-enyocha MSS DDR, dịkwa ka a na-eme Fabric DDR/SERDES blocks ma ọ bụrụ na ị na-eji ha.
- Pịa OK iji chekwaa ntọala gị. Nke a ga-ekpughe ọdụ ụgbọ mmiri nhazi FIC_2 (Oge, Tọgharia, na ebe ụgbọ ala APB), dịka egosiri na eserese 2-8.
- Mepụta MSS. Ọdụ ụgbọ mmiri FIC_2 (FIC_2_APB_MASTER, FIC_2_APB_M_PCLK na FIC_2_APB_M_RESET_N) ka ekpughere ugbu a na interface MSS ma nwee ike jikọọ ya na CoreConfigP na CoreResetP dịka nkọwapụta nkọwapụta mmalite mmalite nke Peripheral.
Maka nkọwa zuru ezu na nhazi na ijikọ CoreConfigP na CoreResetP cores, rụtụ aka na ntuziaka onye ọrụ mmalite nke Peripheral.
Nkọwa Port
DDR PHY Interface
Isiokwu 3-1 • DDR PHY Interface
| Aha Port | Ntuziaka | Nkọwa |
| MDR_CAS_N | Mpụ | DRAM CASN |
| MDR_CKE | Mpụ | DRAM CKE |
| MDR_CLK | Mpụ | Elekere, akụkụ P |
| MDR_CLK_N | Mpụ | Elekere, N akụkụ |
| MDR_CS_N | Mpụ | DRAM CSN |
| MDR_ODT | Mpụ | DRAM ODT |
| MDR_RAS_N | Mpụ | DRAM RASN |
| MDR_RESET_N | Mpụ | Tọgharia DRAM maka DDR3. Ileghara mgbama a maka LPDDR na DDR2 Interfaces. Kaa ya akara na ejighi ya maka LPDDR na DDR2 Interfaces. |
| MDR_WE_N | Mpụ | DRAM WEN |
| MDR_ADDR[15:0] | Mpụ | Iberibe adreesị Dram |
| MDR_BA[2:0] | Mpụ | Dram Bank Adreesị |
| MDDR_DM_RDQS ([3:0]/[1:0]/[0]) | INOUT | Ihe nkpuchi data Dram |
| MDDR_DQS ([3:0]/[1:0]/[0]) | INOUT | Ntinye/Mpụta Dram Data Strobe – Akụkụ P |
| MDDR_DQS_N ([3:0]/[1:0]/[0]) | INOUT | Ntinye/mmepụta Dram Data Strobe – N akụkụ |
| MDDR_DQ ([31:0]/[15:0]/[7:0]) | INOUT | Ntinye/mmepụta data DRAM |
| MDR_DQS_TMATCH_0_IN | IN | FIFO na mgbama |
| MDR_DQS_TMATCH_0_OUT | Mpụ | FIFO pụta ìhè |
| MDR_DQS_TMATCH_1_IN | IN | FIFO na mgbama (naanị 32-bit) |
| MDR_DQS_TMATCH_1_OUT | Mpụ | Mgbama FIFO (naanị 32-bit) |
| MDR_DM_RDQS_ECC | INOUT | Ihe nkpuchi data Dram ECC |
| MDR_DQS_ECC | INOUT | Ntinye/mmepụta Dram ECC Data Strobe – Akụkụ P |
| MDR_DQS_ECC_N | INOUT | Ntinye/mmepụta Dram ECC Data Strobe – N akụkụ |
| MDDR_DQ_ECC ([3:0]/[1:0]/[0]) | INOUT | Ntinye/mmepụta data DRAM ECC |
| MDR_DQS_TMATCH_ECC_IN | IN | ECC FIFO na akara ngosi |
| MDR_DQS_TMATCH_ECC_OUT | Mpụ | ECC FIFO mgbama (naanị 32-bit) |
Mara: Obosara ọdụ ụgbọ mmiri maka ụfọdụ ọdụ ụgbọ mmiri na-agbanwe dabere na nhọrọ nke obosara PHY. A na-eji akara ngosi "[a: 0] / [b: 0] / [c: 0]" pụtara ọdụ ụgbọ mmiri ndị dị otú ahụ, ebe "[a: 0]" na-ezo aka na obosara ọdụ ụgbọ mmiri mgbe ahọpụtara obosara 32-bit PHY. , "[b:0]" dabara na obosara PHY nke 16-bit, na "[c:0]" dabara na obosara PHY nke 8-bit.
Fabric Master AXI Bus Interface
Tebụl 3-2 • Fabric Master AXI Bus Interface
| Aha Port | Ntuziaka | Nkọwa |
| DDR_AXI_S_AWREADY | Mpụ | Dee adreesị njikere |
| DDR_AXI_S_WREADY | Mpụ | Dee adreesị njikere |
| DDR_AXI_S_BID[3:0] | Mpụ | NJ nzaghachi |
| DDR_AXI_S_BRESP[1:0] | Mpụ | Dee nzaghachi |
| DDR_AXI_S_BVALID | Mpụ | Dee nzaghachi bara uru |
| DDR_AXI_S_ARREADY | Mpụ | Gụọ adreesị njikere |
| DDR_AXI_S_RID[3:0] | Mpụ | Gụọ ID Tag |
| DDR_AXI_S_RRESP[1:0] | Mpụ | Gụọ Azịza ya |
| DDR_AXI_S_RDATA[63:0] | Mpụ | Gụọ data |
| DDR_AXI_S_RLAST | Mpụ | Gụọ Nke Ikpeazụ Mgbama a na-egosi mbufe ikpeazụ na mgbawa ọgụgụ |
| DDR_AXI_S_RVALID | Mpụ | Gụọ adreesị ziri ezi |
| DDR_AXI_S_AWID[3:0] | IN | Dee ID adreesị |
| DDR_AXI_S_AWADDR[31:0] | IN | Dee adreesị |
| DDR_AXI_S_AWLEN[3:0] | IN | Ogologo mgbawa |
| DDR_AXI_S_AWSIZE[1:0] | IN | Nha mgbawa |
| DDR_AXI_S_AWBURST[1:0] | IN | Ụdị mgbawa |
| DDR_AXI_S_AWLOCK[1:0] | IN | Ụdị mkpọchi mgbama a na-enye ozi ndị ọzọ gbasara njirimara atomic nke mbufe |
| DDR_AXI_S_AWVALID | IN | Dee adreesị ziri ezi |
| DDR_AXI_S_WID[3:0] | IN | Dee NJ data tag |
| DDR_AXI_S_WDATA[63:0] | IN | Dee data |
| DDR_AXI_S_WSTRB[7:0] | IN | Dee strobes |
| DDR_AXI_S_WLAST | IN | Dee ikpeazụ |
| DDR_AXI_S_WVALID | IN | Dee nke ọma |
| DDR_AXI_S_BREADY | IN | Dee njikere |
| DDR_AXI_S_ARID[3:0] | IN | Gụọ ID adreesị |
| DDR_AXI_S_ARADDR[31:0] | IN | Gụọ adreesị |
| DDR_AXI_S_ARLEN[3:0] | IN | Ogologo mgbawa |
| DDR_AXI_S_ARSIZE[1:0] | IN | Nha mgbawa |
| DDR_AXI_S_ARBURST[1:0] | IN | Ụdị mgbawa |
| DDR_AXI_S_ARLOCK[1:0] | IN | Ụdị mkpọchi |
| DDR_AXI_S_ARVALID | IN | Gụọ adreesị ziri ezi |
| DDR_AXI_S_RREADY | IN | Gụọ adreesị njikere |
Tebụl 3-2 • Fabric Master AXI Bus Interface (na-aga n'ihu)
| Aha Port | Ntuziaka | Nkọwa |
| DDR_AXI_S_CORE_RESET_N | IN | Ntọgharị zuru ụwa ọnụ MDR |
| DDR_AXI_S_RMW | IN | Na-egosi ma bytes niile nke ụzọ 64-bit dị irè maka nfefe AXI niile. 0: Na-egosi na bytes niile dị n'ọkpụkpụ niile dị irè na mgbawa na onye njikwa kwesịrị ịdaba ide iwu. 1: Na-egosi na ụfọdụ bytes abaghị uru na onye njikwa kwesịrị ịdaba na iwu RMW Nke a bụ nkewa dị ka akara ngosi AXI dee adreesị ọwa sideband yana ọ dabara na mgbama AWVALID. A na-eji naanị mgbe agbanyere ECC. |
Fabric Master AHB0 Bus Interface
Tebụl 3-3 • Fabric Master AHB0 Interface ụgbọ ala
| Aha Port | Ntuziaka | Nkọwa |
| DDR_AHB0_SHREADYOUT | Mpụ | AHBL ohu dị njikere - Mgbe elu maka ederede na-egosi MDDR dị njikere ịnakwere data na mgbe elu maka ịgụ na-egosi na data dị irè. |
| DDR_AHB0_SHRESP | Mpụ | Ọnọdụ nzaghachi AHBL - Mgbe a na-ebuli elu na njedebe nke azụmahịa na-egosi na azụmahịa ahụ agwụla na njehie. Mgbe chụpụrụ ala na njedebe nke azụmahịa na-egosi na azụmahịa ahụ agwụla nke ọma. |
| DDR_AHB0_SHrdATA[31:0] | Mpụ | AHBL na-agụ data - Gụọ data sitere na ohu MDR gaa na nna ukwu akwa |
| DDR_AHB0_SHSEL | IN | AHBL ohu họrọ - Mgbe ekwuputara, MDR bụ ohu AHBL ahọpụtara ugbu a na ụgbọ ala AHB akwa |
| DDR_AHB0_SHADDR[31:0] | IN | Adreesị AHBL – adreesị byte na interface AHBL |
| DDR_AHB0_SHBURST[2:0] | IN | Ogologo ogologo AHBL gbawara |
| DDR_AHB0_SHSIZE[1:0] | IN | Nha mbufe AHBL - Na-egosi nha nke mbufe ugbu a (ịzụ ahịa byte 8/16/32 naanị) |
| DDR_AHB0_SHTRANS[1:0] | IN | Ụdị mbufe AHBL - Na-egosi ụdị nnyefe nke azụmahịa dị ugbu a |
| DDR_AHB0_SHMASTLOCK | IN | Mkpọchi AHBL - Mgbe ekwuputara na mbufe ugbu a bụ akụkụ nke azụmahịa akpọchiri |
| DDR_AHB0_SHWRITE | IN | AHBL dee - Mgbe elu na-egosi na azụmahịa ugbu a bụ ederede. Mgbe ala na-egosi na azụmahịa ugbu a bụ ihe na-agụ |
| DDR_AHB0_S_HREADY | IN | AHBL dị njikere - Mgbe elu, na-egosi na MDR dị njikere ịnakwere azụmahịa ọhụrụ |
| DDR_AHB0_S_HWDATA[31:0] | IN | AHBL dee data - Dee data sitere na nna ukwu akwa gaa na MDDr |
Fabric Master AHB1 Bus Interface
Tebụl 3-4 • Fabric Master AHB1 Interface ụgbọ ala
| Aha Port | Ntuziaka | Nkọwa |
| DDR_AHB1_SHREADYOUT | Mpụ | AHBL ohu dị njikere - Mgbe elu maka ederede na-egosi MDDR dị njikere ịnakwere data na mgbe elu maka ịgụ na-egosi na data dị irè. |
| DDR_AHB1_SHRESP | Mpụ | Ọnọdụ nzaghachi AHBL - Mgbe a na-ebuli elu na njedebe nke azụmahịa na-egosi na azụmahịa ahụ agwụla na njehie. Mgbe chụpụrụ ala na njedebe nke azụmahịa na-egosi na azụmahịa ahụ agwụla nke ọma. |
| DDR_AHB1_SHrdATA[31:0] | Mpụ | AHBL na-agụ data - Gụọ data sitere na ohu MDR gaa na nna ukwu akwa |
| DDR_AHB1_SHSEL | IN | AHBL ohu họrọ - Mgbe ekwuputara, MDR bụ ohu AHBL ahọpụtara ugbu a na ụgbọ ala AHB akwa |
| DDR_AHB1_SHADDR[31:0] | IN | Adreesị AHBL – adreesị byte na interface AHBL |
| DDR_AHB1_SHBURST[2:0] | IN | Ogologo ogologo AHBL gbawara |
| DDR_AHB1_SHSIZE[1:0] | IN | Nha mbufe AHBL - Na-egosi nha nke mbufe ugbu a (ịzụ ahịa byte 8/16/32 naanị) |
| DDR_AHB1_SHTRANS[1:0] | IN | Ụdị mbufe AHBL - Na-egosi ụdị nnyefe nke azụmahịa dị ugbu a |
| DDR_AHB1_SHMASTLOCK | IN | Mkpọchi AHBL - Mgbe ekwuputara na mbufe ugbu a bụ akụkụ nke azụmahịa akpọchiri |
| DDR_AHB1_SHWRITE | IN | AHBL dee - Mgbe elu na-egosi na azụmahịa ugbu a bụ ederede. Mgbe ala na-egosi na azụmahịa ugbu a bụ ihe na-agụ. |
| DDR_AHB1_SHREADY | IN | AHBL dị njikere - Mgbe elu, na-egosi na MDR dị njikere ịnakwere azụmahịa ọhụrụ |
| DDR_AHB1_SHWDATA[31:0] | IN | AHBL dee data - Dee data sitere na nna ukwu akwa gaa na MDDr |
Ọnọdụ ebe nchekwa dị nro AXI Bus Interface
Tebụl 3-5 • Ọnọdụ ebe nchekwa dị nro AXI Bus Interface
| Aha Port | Ntuziaka | Nkọwa |
| SMC_AXI_M_WLAST | Mpụ | Dee ikpeazụ |
| SMC_AXI_M_WVALID | Mpụ | Dee nke ọma |
| SMC_AXI_M_AWLEN[3:0] | Mpụ | Ogologo mgbawa |
| SMC_AXI_M_AWBURST[1:0] | Mpụ | Ụdị mgbawa |
| SMC_AXI_M_BREADY | Mpụ | Azịza dị njikere |
| SMC_AXI_M_AWVALID | Mpụ | Dee adreesị bara uru |
| SMC_AXI_M_AWID[3:0] | Mpụ | Dee ID adreesị |
| SMC_AXI_M_WDATA[63:0] | Mpụ | Dee data |
| SMC_AXI_M_ARVALID | Mpụ | Gụọ adreesị ziri ezi |
| SMC_AXI_M_WID[3:0] | Mpụ | Dee NJ data tag |
| SMC_AXI_M_WSTRB[7:0] | Mpụ | Dee strobes |
| SMC_AXI_M_ARID[3:0] | Mpụ | Gụọ ID adreesị |
| SMC_AXI_M_ARADDR[31:0] | Mpụ | Gụọ adreesị |
| SMC_AXI_M_ARLEN[3:0] | Mpụ | Ogologo mgbawa |
| SMC_AXI_M_ARSIZE[1:0] | Mpụ | Nha mgbawa |
| SMC_AXI_M_ARBURST[1:0] | Mpụ | Ụdị mgbawa |
| SMC_AXI_M_AWADDR[31:0] | Mpụ | Dee adreesị |
| SMC_AXI_M_RREADY | Mpụ | Gụọ adreesị njikere |
| SMC_AXI_M_AWSIZE[1:0] | Mpụ | Nha mgbawa |
| SMC_AXI_M_AWLOCK[1:0] | Mpụ | Ụdị mkpọchi mgbama a na-enye ozi ndị ọzọ gbasara njirimara atomic nke mbufe |
| SMC_AXI_M_ARLOCK[1:0] | Mpụ | Ụdị mkpọchi |
| SMC_AXI_M_BID[3:0] | IN | NJ nzaghachi |
| SMC_AXI_M_RID[3:0] | IN | Gụọ ID Tag |
| SMC_AXI_M_RRESP[1:0] | IN | Gụọ Azịza ya |
| SMC_AXI_M_BRESP[1:0] | IN | Dee nzaghachi |
| SMC_AXI_M_AWREADY | IN | Dee adreesị njikere |
| SMC_AXI_M_RDATA[63:0] | IN | Gụọ data |
| SMC_AXI_M_WREADY | IN | Dee njikere |
| SMC_AXI_M_BVALID | IN | Dee nzaghachi bara uru |
| SMC_AXI_M_ARREADY | IN | Gụọ adreesị njikere |
| SMC_AXI_M_RLAST | IN | Gụọ Nke Ikpeazụ Mgbama a na-egosi mbufe ikpeazụ na mgbawa ọgụgụ |
| SMC_AXI_M_RVALID | IN | Gụọ nke ọma |
Ọnọdụ ebe nchekwa dị nro AHB0 Interface ụgbọ ala
Tebụl 3-6 • Ọnọdụ ebe nchekwa dị nro AHB0 Interface ụgbọ ala
| Aha Port | Ntuziaka | Nkọwa |
| SMC_AHB_M_HBURST[1:0] | Mpụ | Ogologo ogologo AHBL gbawara |
| SMC_AHB_M_HTRANS[1:0] | Mpụ | Ụdị mbufe AHBL - Na-egosi ụdị nnyefe nke azụmahịa dị ugbu a. |
| SMC_AHB_M_HMASTLOCK | Mpụ | Mkpọchi AHBL - Mgbe ekwuputara na mbufe ugbu a bụ akụkụ nke azụmahịa akpọchiri |
| SMC_AHB_M_HWRITE | Mpụ | AHBL dee - Mgbe elu na-egosi na azụmahịa ugbu a bụ dee. Mgbe ala na-egosi na azụmahịa ugbu a bụ ihe na-agụ |
| SMC_AHB_M_HSIZE[1:0] | Mpụ | Nha mbufe AHBL - Na-egosi nha nke mbufe ugbu a (ịzụ ahịa byte 8/16/32 naanị) |
| SMC_AHB_M_HWDATA[31:0] | Mpụ | AHBL dee data - Dee data sitere na nna ukwu MSS gaa na njikwa ebe nchekwa dị nro |
| SMC_AHB_M_HADDR[31:0] | Mpụ | Adreesị AHBL – adreesị byte na interface AHBL |
| SMC_AHB_M_HRESP | IN | Ọnọdụ nzaghachi AHBL - Mgbe a na-ebuli elu na njedebe nke azụmahịa na-egosi na azụmahịa ahụ agwụla na njehie. Mgbe chụpụrụ ala na njedebe nke azụmahịa na-egosi na azụmahịa ahụ agwụla nke ọma |
| SMC_AHB_M_HRDATA[31:0] | IN | AHBL na-agụ data - Gụọ data sitere na njikwa ebe nchekwa dị nro gaa na nna ukwu MSS |
| SMC_AHB_M_HREADY | IN | AHBL dị njikere - Elu na-egosi na ụgbọ ala AHBL dị njikere ịnakwere azụmahịa ọhụrụ |
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Okwu m
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