Microsemi SmartFusion2 FPGA Npuag DDR Controller Configuration User Guide

Microsemi SmartFusion2 FPGA Npuag DDR Controller Configuration User Guide

Cov ntsiab lus zais

1 Taw qhia

2 Npuag Sab Nraud Memory DDR Controller Configurator

3 FDDR Controller Configuration

4 Chaw nres nkoj piav qhia

5 Khoom txhawb

6 Cov ntaub ntawv / Cov ntaub ntawv

6.1 Cov ntaub ntawv

7 Related Posts

Taw qhia

Lub SmartFusion2 FPGA muaj ob lub cim DDR tswj - ib qho nkag tau los ntawm MSS (MDDR) thiab lwm qhov npaj rau kev nkag ncaj qha los ntawm FPGA Fabric (FDDR). MDDR thiab FDDR ob leeg tswj tawm-chip DDR nco.
Txhawm rau txhim kho Fabric DDR maub los koj yuav tsum:

Siv Fabric External Memory DDR Controller Configurator los teeb tsa DDR Controller, xaiv nws cov datapath bus interface (AXI lossis AHBLite), thiab xaiv DDR moos zaus nrog rau cov ntaub datapath moos zaus.

Teem tus nqi sau npe rau DDR maub los sau npe kom phim koj cov yam ntxwv ntawm DDR sab nraud.
Instantiate Fabric DDR ua ib feem ntawm daim ntawv thov siv thiab ua cov ntaub ntawv sib txuas.

Txuas DDR maub los's APB configuration interface raws li tau hais los ntawm Peripheral Initialization tov.

Npuag Sab Nraud Memory DDR Controller Configurator

Fabric External Memory DDR (FDDR) Configurator yog siv los teeb tsa cov ntaub ntawv tag nrho thiab sab nraud DDR nco tsis tau rau Fabric DDR Controller.

Daim duab 1-1 • FDDR Configurator Tshajview

Memory Settings

Siv Memory Settings los teeb tsa koj cov kev xaiv nco hauv MDDR.

Hom Nco - LPDDR, DDR2, lossis DDR3

Cov ntaub ntawv dav - 32-ntsis, 16-ntsis lossis 8-ntsis
Moos Tsaus - Txhua tus nqi (Decimal / Fractional) nyob rau hauv thaj tsam ntawm 20 MHz txog 333 MHz

SECDED Enabled ECC - ON los yog OFF
Chaw nyob Mapping - {ROW,BANK,COLUMN},{BANK,ROW,COLUMN}

Fabric Interface Settings

FPGA Fabric Interface - Qhov no yog cov ntaub ntawv sib cuam tshuam ntawm FDDR thiab FPGA tsim. Vim tias FDDR yog lub cim xeeb tswj, nws yog npaj los ua qhev ntawm AXI lossis AHB tsheb npav. Tus Xib Hwb ntawm lub tsheb npav pib kev lag luam tsheb npav, uas tau txhais los ntawm FDDR raws li kev hloov pauv kev nco thiab sib txuas lus mus rau off-chip DDR Memory. FDDR npuag interface xaiv yog:

Siv AXI-64 Interface - Ib tus tswv nkag mus rau FDDR los ntawm 64-ntsis \ AXI interface.
Siv Ib Leeg AHB-32 Interface - Ib tus tswv nkag mus rau FDDR los ntawm ib qho 32-ntsis AHB interface.

Siv Ob Lub AHB-32 Interfaces - Ob tus tswv nkag mus rau FDDR siv ob 32-ntsis AHB interfaces.

FPGA CLOCK Divisor - Qhia meej qhov sib piv ntawm DDR Controller moos (CLK_FDDR) thiab lub moos tswj cov ntaub interface (CLK_FIC64). CLK_FIC64 zaus yuav tsum sib npaug ntawm AHB / AXI subsystem uas txuas nrog FDDR AHB / AXI tsheb npav interface. Rau example, yog tias koj muaj DDR RAM khiav ntawm 200 MHz thiab koj Fabric / AXI Subsystem khiav ntawm 100 MHz, koj yuav tsum xaiv qhov sib faib ntawm 2 (Daim duab 1-2).

Daim duab 1-2 • Fabric Interface Settings – AXI Interface thiab FDDR Clock Divisor Daim Ntawv Pom Zoo

Siv ntaub PLL LOCK - Yog tias CLK_BASE tau txais los ntawm Fabric CCC, koj tuaj yeem txuas cov ntaub ntawv CCC LOCK tso tawm rau FDDR FAB_PLL_LOCK cov tswv yim. CLK_BASE tsis ruaj khov kom txog thaum Fabric CCC xauv. Yog li ntawd, Microsemi xav kom koj tuav FDDR hauv kev pib dua (piv txwv li, lees paub CORE_RESET_N cov tswv yim) kom txog thaum CLK_BASE ruaj khov. Lub LOCK tso zis ntawm Npuag CCC qhia tias Fabric CCC tso zis moos ruaj khov. Los ntawm kev txheeb xyuas qhov Siv FAB_PLL_LOCK kev xaiv, koj tuaj yeem nthuav tawm FAB_PLL_LOCK input chaw nres nkoj ntawm FDDR. Tom qab ntawd koj tuaj yeem txuas lub LOCK tso tawm ntawm Fabric CCC rau FAB_PLL_LOCK cov tswv yim ntawm FDDR.

IO Tsav zog

Xaiv ib qho ntawm lub zog tsav hauv qab no rau koj DDR I/O's:

Ib nrab Tsav Zog
Tag Nrho Tsav Zog

Nyob ntawm koj hom DDR Memory thiab I/O Strength koj xaiv, Libero SoC teeb tsa DDR I/O Standard rau koj FDDR system raws li hauv qab no:

DDR Nco Hom	Ib nrab Tsav Zog	Tag Nrho Tsav Zog
DDR 3	SSTL15I	TIAB SA 15 II
DDR 2	SSTL18I	TIAB SA 18 II
LPDDR	LPDRI	LPDRII

Ua kom muaj kev cuam tshuam

FDDR muaj peev xwm txhawb nqa kev cuam tshuam thaum qee yam kev cai ua ntej tau txaus siab. Tshawb xyuas Enable Interrupts hauv FDDR configurator yog tias koj xav siv cov kev cuam tshuam no hauv koj daim ntawv thov.
Qhov no nthuav tawm cov teeb liab cuam tshuam ntawm FDDR piv txwv. Koj tuaj yeem txuas cov teeb liab cuam tshuam no raws li koj tus qauv xav tau. Cov teeb liab cuam tshuam hauv qab no thiab lawv cov xwm txheej ua ntej muaj:

FIC_INT – Tsim thaum muaj qhov yuam kev hauv kev sib pauv ntawm tus tswv thiab FDDR

IO_CAL_INT – Pab kom koj rov qab kho DDR I / O's los ntawm kev sau ntawv rau DDR tus tswj hwm sau npe ntawm APB teeb tsa interface. Thaum calibration tiav, qhov kev cuam tshuam no tau tsa. Yog xav paub meej txog I/O recalibration, xa mus rau Microsemi SmartFusion2 Cov Neeg Siv Khoom Qhia.
PLL_LOCK_INT – Qhia tias FDDR FPLL tau kaw lawm
PLL_LOCKLOST_INT – Qhia tias FDDR FPLL tau poob xauv
FDDR_ECC_INT – Qhia tau tias muaj qhov yuam kev ib los yog ob-ntsis tau kuaj pom

Npuag moos zaus

Kev xam moos zaus raws li koj lub moos zaus tam sim no thiab CLOCK divisor, tso tawm hauv MHz.
Npuag moos zaus (hauv MHz) = Clock Frequency / CLOCK divisor

Nco Bandwidth

Kev suav bandwidth nco raws li koj lub moos zaus tam sim no hauv Mbps.
Nco Bandwidth (hauv Mbps) = 2 * moos zaus

Tag nrho Bandwidth

Kev suav tag nrho bandwidth raws li koj lub moos zaus tam sim no, Cov Ntaub Ntawv Dav thiab CLOCK divisor, hauv Mbps.
Tag nrho Bandwidth (hauv Mbps) = (2 * moos zaus * Cov ntaub ntawv dav) / CLOCK Divisor

FDDR Controller Configuration

Thaum koj siv Fabric DDR Controller kom nkag mus rau sab nraud DDR Nco, DDR Controller yuav tsum tau teeb tsa thaum lub sijhawm ua haujlwm. Qhov no yog ua los ntawm kev sau cov ntaub ntawv teeb tsa rau DDR kev tswj hwm kev teeb tsa kev sau npe. Cov ntaub ntawv teeb tsa no yog nyob ntawm tus yam ntxwv ntawm lub cim xeeb sab nraud DDR thiab koj daim ntawv thov. Tshooj lus no piav qhia txog yuav ua li cas nkag mus rau cov kev teeb tsa no hauv FDDR tus tswj hwm tus tswj hwm thiab yuav ua li cas cov ntaub ntawv teeb tsa tau tswj hwm raws li ib feem ntawm tag nrho Peripheral Initialization daws. Xa mus rau Peripheral Initialization User Guide rau cov ncauj lus kom ntxaws txog cov tshuaj Peripheral Initialization.

Npuag DDR Control Registers

Fabric DDR Controller muaj cov txheej txheem sau npe uas yuav tsum tau teeb tsa thaum lub sijhawm ua haujlwm. Cov nqi kev teeb tsa rau cov ntawv sau npe no sawv cev rau qhov sib txawv (example, DDR hom, PHY dav, tawg hom, ECC, thiab lwm yam). Yog xav paub meej txog DDR tswj kev teeb tsa kev sau npe, xa mus rau Microsemi SmartFusion2 Tus Neeg Siv Khoom Qhia.

Fabric DDR Registers Configuration

Siv lub cim xeeb Initialization (Daim duab 2-1) thiab Lub Sijhawm Nco (Daim duab 2-2) tab kom nkag mus rau qhov tsis sib xws rau koj lub cim xeeb DDR thiab daim ntawv thov. Cov txiaj ntsig koj nkag rau hauv cov tab no tau muab txhais ua qhov tsim nyog rau npe. Thaum koj nyem ib qho kev txwv tshwj xeeb, nws cov ntawv sau npe sib raug tau piav qhia nyob rau hauv Daim Ntawv Teev Npe Qhov rai (Daim duab 1-1 ntawm nplooj ntawv 4).

Daim duab 2-1 • FDDR Configuration – Memory Initialization Tab

Daim duab 2-2 • FDDR Configuration – Memory Timing Tab

Importing DDR Configuration Files

Ntxiv rau kev nkag mus rau DDR Memory tsis siv lub cim xeeb pib thiab Lub Sijhawm tab, koj tuaj yeem import DDR cov nqi sau npe los ntawm ib qho file. Txhawm rau ua li ntawd, nyem qhov Ntshuam Configuration khawm thiab mus rau cov ntawv nyeem file muaj DDR sau npe thiab cov nqi. Daim duab 2-3 qhia tau hais tias ntshuam configuration syntax.

Daim duab 2-3 • DDR Register Configuration File Syntax

Nco tseg: Yog tias koj xaiv import cov nqi sau npe ntau dua li nkag mus rau lawv siv GUI, koj yuav tsum qhia tag nrho cov nqi sau npe tsim nyog. Saib rau SmartFusion2 Tus Neeg Siv Qhia kom paub meej

Exporting DDR Configuration Files

Koj tseem tuaj yeem xa cov ntaub ntawv sau npe tam sim no rau hauv cov ntawv nyeem file. Qhov no file yuav muaj cov nqi sau npe uas koj tau xa tuaj (yog tias muaj) nrog rau cov uas tau suav los ntawm GUI tsis tau koj nkag rau hauv lub thawv no.
Yog tias koj xav thim rov qab cov kev hloov pauv uas koj tau ua rau DDR rau npe teeb tsa, koj tuaj yeem ua li ntawd nrog Restore Default. Qhov no tshem tawm tag nrho cov ntaub ntawv teev npe configuration thiab koj yuav tsum rov ntshuam lossis rov sau cov ntaub ntawv no. Cov ntaub ntawv rov pib dua rau qhov kho vajtse rov pib dua qhov tseem ceeb.

Cov ntaub ntawv tsim tawm

Nyem OK los tsim cov kev teeb tsa. Raws li koj cov tswv yim hauv General, Memory Timing thiab Memory Initialization tabs, FDDR Configurator suav cov txiaj ntsig rau tag nrho DDR teeb tsa kev sau npe thiab xa tawm cov txiaj ntsig no rau hauv koj qhov project firmware thiab simulation. files. Cov exported file syntax muaj nyob rau hauv daim duab 2-4.

Daim duab 2-4 • Exported DDR Register Configuration File Syntax

Firmware

Thaum koj tsim SmartDesign, cov hauv qab no files tau tsim nyob rau hauv /firmware/ drivers_config/sys_config directory. Cov no files yuav tsum tau rau CMSIS firmware core kom muab tso ua ke kom raug thiab muaj cov ntaub ntawv hais txog koj tus qauv tsim tam sim no, suav nrog cov ntaub ntawv teeb tsa peripheral thiab cov ntaub ntawv teev teev rau MSS. Tsis txhob hloov cov no files manually, raws li lawv yog recreated txhua txhua lub sij hawm koj lub hauv paus tsim yog regenerated.

sys_config.c
sys_config.h

sys_config_mddr_define.h – MDDR configuration data.
sys_config_fddr_define.h – FDDR configuration data.
sys_config_mss_clocks.h – MSS moos configuration

Kev simulation

Thaum koj tsim SmartDesign cuam tshuam nrog koj MSS, simulation hauv qab no files yog tsim nyob rau hauv / simulation directory:

tes bfm - Sab saum toj BFM file uas yog thawj zaug tua thaum lub sijhawm simulation uas ua haujlwm ntawm SmartFusion2 MSS Cortex-M3 processor. Nws ua haujlwm peripheral_init.bfm thiab user.bfm, hauv qhov kev txiav txim ntawd.

peripheral_init.bfm - Muaj cov txheej txheem BFM uas emulates CMSIS::SystemInit() muaj nuj nqi khiav ntawm Cortex-M3 ua ntej koj nkag mus rau lub ntsiab() txheej txheem. Nws luam tawm cov ntaub ntawv teeb tsa rau ib qho khoom siv peripheral uas siv rau hauv kev tsim kom raug peripheral configuration registers thiab tom qab ntawd tos kom tag nrho cov peripherals npaj ua ntej lees tias tus neeg siv tuaj yeem siv cov khoom siv no.
FDDR_init.bfm - Muaj BFM sau cov lus txib uas simulate sau ntawm Fabric DDR teeb tsa cov ntaub ntawv sau npe koj tau nkag (siv lub Edit Registers dialog box) rau hauv DDR Controller sau npe.
siv bfm - Npaj rau cov neeg siv cov lus txib. Koj tuaj yeem simulate datapath los ntawm kev ntxiv koj tus kheej BFM cov lus txib hauv qhov no file. Cov lus txib hauv qhov no file yuav raug tua tom qab peripheral_init.bfm ua tiav.

Siv cov files saum toj no, txoj kev configuration yog simulated txiav. Koj tsuas yog yuav tsum hloov kho user.bfm file los simulate datapath. Tsis txhob hloov qhov test.bfm, peripheral_init.bfm, lossis MDDR_init.bfm files as cov files yog recreated txhua zaus koj lub hauv paus tsim yog regenerated.

Fabric DDR Configuration Path

Kev daws teeb meem Peripheral Initialization yuav tsum tau hais tias, ntxiv rau qhov qhia meej txog Fabric DDR teeb tsa kev sau npe qhov tseem ceeb, koj teeb tsa APB teeb tsa cov ntaub ntawv kab hauv MSS (FIC_2). Qhov SystemInit() muaj nuj nqi sau cov ntaub ntawv mus rau FDDR teeb tsa kev sau npe ntawm FIC_2 APB interface.

Nco tseg: Yog tias koj siv System Builder txoj kev teeb tsa tau teeb tsa thiab txuas nrog txiav.

Daim duab 2-5 • FIC_2 Configurator Tshajview

Txhawm rau teeb tsa FIC_2 interface:

Qhib FIC_2 configurator dialog (Daim duab 2-5) los ntawm MSS configurator.
Xaiv qhov Initialize peripherals siv Cortex-M3 kev xaiv.
Nco ntsoov tias MSS DDR raug kuaj xyuas, zoo li Fabric DDR / SERDES thaiv yog tias koj siv lawv.

Nyem OK kom txuag koj qhov chaw. Qhov no nthuav tawm FIC_2 configuration ports (Clock, Reset, thiab APB bus interfaces), raws li qhia hauv daim duab 2-6.
Tsim MSS. Lub FIC_2 chaw nres nkoj (FIC_2_APB_MASTER, FIC_2_APB_M_PCLK thiab FIC_2_APB_M_RESET_N) tam sim no nthuav tawm ntawm MSS interface thiab tuaj yeem txuas nrog CoreSF2Config thiab CoreSF2Reset raws li Peripheral Initialization tov specification.

Daim duab 2-6 • FIC_2 Ports

Chaw nres nkoj piav qhia

FDDR Core Ports

Table 3-1 • FDDR Core Ports

Chaw nres nkoj npe	Kev taw qhia	Kev piav qhia
CORE_RESET_N	IN	FDDR Controller pib dua
CLK_BASE	IN	FDDR Npuag Interface Clock
FPLL_LOCK	Tawm	FDDR PLL Xauv tso zis - siab thaum FDDR PLL raug kaw
CLK_BASE_PLL_LOCK	IN	Npuag PLL Lock Input. Cov tswv yim no tsuas yog nthuav tawm thaum siv FAB_PLL_LOCK xaiv.

Interrupt Ports

Cov pab pawg ntawm cov chaw nres nkoj no raug nthuav tawm thaum koj xaiv qhov Enable Interrupts xaiv.

Table 3-2 • Interrupt Ports

Chaw nres nkoj npe	Kev taw qhia	Kev piav qhia
PLL_LOCK_INT	Tawm	Asserts thaum FDDR PLL xauv.
PLL_LOCKLOST_INT	Tawm	Asserts thaum FDDR PLL xauv lawm.
ECC_INT	Tawm	Kev lees paub thaum muaj xwm txheej ECC tshwm sim.
IO_CALIB_INT	Tawm	Asserts thaum I/O calibration tiav.
FIC_INT	Tawm	Asserts thaum muaj qhov yuam kev hauv AHB / AXI raws tu qauv ntawm Fabric interface.

APB3 Configuration Interface

Table 3-3 • APB3 Configuration Interface

Chaw nres nkoj npe	Kev taw qhia	Kev piav qhia
APB_S_PENABLE	IN	qhev Enable
APB_S_PSEL	IN	qhev xaiv
APB_S_PWRITE	IN	Sau Enable
APB_S_PADDR[10:2]	IN	Chaw nyob
APB_S_PWDATA[15:0]	IN	Sau cov ntaub ntawv
APB_S_PREADY	Tawm	qhev npaj
APB_S_PSLVERR	Tawm	qhev yuam kev
PAB_S_PRDATA[15:0]	Tawm	Nyeem cov ntaub ntawv
APB_S_PRESET_N	IN	Tus qhev rov pib dua
APB_S_PCLK	IN	moos

DDR PHY Interface

Table 3-4 • DDR PHY Interface

Chaw nres nkoj npe	Kev taw qhia	Kev piav qhia
FDDR_CAS_N	Tawm	DRAM CASN
FDDR_CKE	Tawm	DRAM CKE
FDDR_CLK	Tawm	moos, P sab
FDDR_CLK_N	Tawm	moos, N sab
FDDR_CS_N	Tawm	DRAM CSN
FDDR_ODT	Tawm	DRAM ODT
FDDR_RAS_N	Tawm	DRAM RASN
FDDR_RESET_N	Tawm	DRAM Reset rau DDR3
FDDR_WE_N	Tawm	DRAM WEN
FDDR_ADDR[15:0]	Tawm	Dram Address bits
FDDR_BA[2:0]	Tawm	Dram Bank Chaw Nyob
FDDR_DM_RDQS[4:0]	NCO	Dram Data Mask
FDDR_DQS[4:0]	NCO	Dram Data Strobe Input/Output – P Sab
FDDR_DQS_N[4:0]	NCO	Dram Data Strobe Input/Output – N Sab
FDDR_DQ[35:0]	NCO	DRAM Cov ntaub ntawv nkag / tawm
FDDR_FIFO_WE_IN[2:0]	IN	FIFO hauv teeb liab
FDDR_FIFO_WE_OUT[2:0]	Tawm	FIFO tawm signal
FDDR_DM_RDQS ([3:0]/[1:0]/[0])	NCO	Dram Data Mask
FDDR_DQS ([3:0]/[1:0]/[0])	NCO	Dram Data Strobe Input/Output – P Sab
FDDR_DQS_N ([3:0]/[1:0]/[0])	NCO	Dram Data Strobe Input/Output – N Sab
FDDR_DQ ([31:0]/[15:0]/[7:0])	NCO	DRAM Cov ntaub ntawv nkag / tawm
FDDR_DQS_TMATCH_0_IN	IN	FIFO hauv teeb liab
FDDR_DQS_TMATCH_0_OUT	Tawm	FIFO tawm signal
FDDR_DQS_TMATCH_1_IN	IN	FIFO hauv teeb liab (32-ntsis nkaus xwb)
FDDR_DQS_TMATCH_1_OUT	Tawm	FIFO tawm teeb liab (32-ntsis nkaus xwb)
FDDR_DM_RDQS_ECC	NCO	Dram ECC Data Mask
FDDR_DQS_ECC	NCO	Dram ECC Data Strobe Input/Output – P Sab
FDDR_DQS_ECC_N	NCO	Dram ECC Data Strobe Input/Output – N Sab
FDDR_DQ_ECC ([3:0]/[1:0]/[0])	NCO	DRAM ECC Cov ntaub ntawv nkag / tawm
FDDR_DQS_TMATCH_ECC_IN	IN	ECC FIFO hauv teeb liab
FDDR_DQS_TMATCH_ECC_OUT	Tawm	ECC FIFO tawm teeb liab (32-ntsis nkaus xwb)

Nco tseg: Qhov dav ntawm qhov chaw nres nkoj rau qee qhov chaw nres nkoj hloov raws li kev xaiv ntawm PHY dav. Cov cim "[a:0]/ [b:0]/[c:0]" yog siv los qhia cov chaw nres nkoj, qhov twg "[a:0]" yog hais txog qhov chaw nres nkoj dav thaum xaiv 32-ntsis PHY dav. , "[b:0]" sib raug rau 16-ntsis PHY dav, thiab "[c:0]" sib raug rau 8-ntsis PHY dav.

AXI Bus Interface

Table 3-5 • AXI Bus Interface

Chaw nres nkoj npe	Kev taw qhia	Kev piav qhia
AXI_S_AWREADY	Tawm	Sau chaw nyob npaj txhij
AXI_S_WREADY	Tawm	Sau chaw nyob npaj txhij
AXI_S_BID[3:0] UA	Tawm	Teb ID
AXI_S_BRESP[1:0] UA	Tawm	Sau cov lus teb
AXI_S_BVALID	Tawm	Sau cov lus teb siv tau
AXI_S_ARREADY	Tawm	Nyeem qhov chaw nyob npaj
AXI_S_RID[3:0] ib	Tawm	Nyeem ID Tag
AXI_S_RRESP[1:0]	Tawm	Nyeem Teb
AXI_S_RDATA[63:0] TSI	Tawm	Nyeem cov ntaub ntawv
AXI_S_RLAST	Tawm	Nyeem Kawg - Qhov teeb liab no qhia txog kev hloov pauv zaum kawg hauv kev nyeem ntawv tawg.
AXI_S_RVALID	Tawm	Nyeem qhov chaw nyob siv tau
AXI_S_AWID[3:0]	IN	Sau ID Chaw Nyob
AXI_S_AWADDR[31:0]	IN	Sau chaw nyob
AXI_S_AWLEN[3:0]	IN	tawg ntev
AXI_S_AWSIZE[1:0]	IN	tawg loj
AXI_S_AWBURST[1:0]	IN	Hom tawg
AXI_S_AWLOCK[1:0]	IN	Xauv hom - Cov teeb liab no muab cov ntaub ntawv ntxiv txog cov yam ntxwv atomic ntawm kev hloov pauv.
AXI_S_AWVALID	IN	Sau qhov chaw nyob siv tau
AXI_S_WID [3:0]	IN	Sau cov ntaub ntawv ID tag
AXI_S_WDATA[63:0]	IN	Sau cov ntaub ntawv
AXI_S_WSTRB[7:0]	IN	Sau strobes
AXI_S_WLAST	IN	Sau ntawv kawg
AXI_S_WVALID	IN	Sau siv tau
AXI_S_BREADY	IN	Sau ntawv npaj txhij
AXI_S_ARID[3:0] UA	IN	Nyeem Qhov Chaw Nyob ID
AXI_S_ARADDR[31:0]	IN	Nyeem qhov chaw nyob
AXI_S_ARLEN[3:0] UA	IN	tawg ntev
AXI_S_ARSIZE [1:0]	IN	tawg loj
AXI_S_ARBUST[1:0] UA	IN	Hom tawg
AXI_S_ARLOCK[1:0] UA	IN	Hom xauv
AXI_S_ARVALID	IN	Nyeem qhov chaw nyob siv tau
AXI_S_RREADY	IN	Nyeem qhov chaw nyob npaj
Chaw nres nkoj npe	Kev taw qhia	Kev piav qhia
AXI_S_CORE_RESET_N	IN	MDDR Ntiaj teb no Reset
AXI_S_WM	IN	Qhia seb tag nrho cov bytes ntawm txoj kab 64-ntsis siv tau rau txhua qhov kev sib tw ntawm AXI hloov chaw. Qhia tias tag nrho cov bytes hauv txhua tus neeg ntaus yeej siv tau hauv qhov tawg thiab tus maub los yuav tsum ua raws li sau cov lus txib. Qhia tias qee cov bytes tsis raug thiab tus maub los yuav tsum ua raws li RMW cov lus txib. Qhov no yog classed raws li AXI sau chaw nyob channel sideband teeb liab thiab siv tau nrog AWVALID teeb liab.Tsuas yog siv thaum ECC qhib.

AHB0 Bus Interface

Table 3-6 • AHB0 Bus Interface

Chaw nres nkoj npe	Kev taw qhia	Kev piav qhia
AHB0_S_HREADYOUT	Tawm	AHBL qhev npaj - Thaum siab rau kev sau ntawv qhia tias tus qhev npaj tau txais cov ntaub ntawv thiab thaum siab nyeem ntawv qhia tias cov ntaub ntawv siv tau.
AHB0_S_HRESP	Tawm	AHBL cov xwm txheej teb - Thaum tsav siab thaum kawg ntawm kev sib pauv qhia tias kev hloov pauv tau ua tiav nrog qhov yuam kev. Thaum tsav qis thaum kawg ntawm kev sib pauv qhia tias qhov kev sib pauv tau ua tiav tiav.
HHB0_S_HRDATA[31:0]	Tawm	AHBL nyeem cov ntaub ntawv - Nyeem cov ntaub ntawv los ntawm tus qhev rau tus tswv
AHB0_S_HSEL	IN	AHBL qhev xaiv - Thaum lees paub, tus qhev yog tam sim no xaiv AHBL qhev ntawm lub npav AHB.
AHB0_S_HADDR[31:0]	IN	AHBL chaw nyob - byte chaw nyob ntawm AHBL interface
AHB0_S_HBURST[2:0] UA	IN	AHBL tawg Length
AHB0_S_HSIZE[1:0]	IN	AHBL hloov pauv loj - Qhia qhov loj ntawm kev hloov pauv tam sim no (8/16/32 byte kev lag luam nkaus xwb)
AHB0_S_HTRANS[1:0] UA	IN	AHBL hloov hom - Qhia txog hom kev hloov pauv ntawm kev hloov pauv tam sim no.
AHB0_S_HMASTLOCK	IN	AHBL xauv - Thaum lees paub qhov kev hloov pauv tam sim no yog ib feem ntawm kev lag luam xauv.
AHB0_S_HWRITE	IN	AHBL sau - Thaum siab qhia tias kev hloov pauv tam sim no yog sau. Thaum qis qhia tias qhov kev hloov pauv tam sim no yog nyeem.
AHB0_S_HREADY	IN	AHBL npaj - Thaum siab, qhia tias tus qhev npaj tau txais kev hloov pauv tshiab.
AHB0_S_HWDATA[31:0]	IN	AHBL sau cov ntaub ntawv - Sau cov ntaub ntawv los ntawm tus tswv mus rau tus qhev

AHB1 Bus Interface

Table 3-7 • AHB1 Bus Interface

Chaw nres nkoj npe	Kev taw qhia	Kev piav qhia
AHB1_S_HREADYOUT	Tawm	AHBL qhev npaj - Thaum siab rau kev sau ntawv, qhia tias tus qhev npaj tau txais cov ntaub ntawv, thiab thaum siab nyeem ntawv, qhia tias cov ntaub ntawv siv tau.
AHB1_S_HRESP	Tawm	AHBL cov xwm txheej teb - Thaum tsav siab thaum kawg ntawm kev sib pauv qhia tias kev hloov pauv tau ua tiav nrog qhov yuam kev. Thaum tsav qis thaum kawg ntawm kev sib pauv, qhia tias qhov kev sib pauv tau ua tiav tiav.
HHB1_S_HRDATA[31:0]	Tawm	AHBL nyeem cov ntaub ntawv - Nyeem cov ntaub ntawv los ntawm tus qhev rau tus tswv
AHB1_S_HSEL	IN	AHBL qhev xaiv - Thaum lees paub, tus qhev yog tam sim no xaiv AHBL qhev ntawm lub npav AHB.
AHB1_S_HADDR[31:0]	IN	AHBL chaw nyob - byte chaw nyob ntawm AHBL interface
AHB1_S_HBURST[2:0] UA	IN	AHBL tawg Length
AHB1_S_HSIZE[1:0]	IN	AHBL hloov pauv loj - Qhia qhov loj ntawm kev hloov pauv tam sim no (8/16/32 byte kev lag luam nkaus xwb).
AHB1_S_HTRANS[1:0] UA	IN	AHBL hloov hom - Qhia txog hom kev hloov pauv ntawm kev hloov pauv tam sim no.
AHB1_S_HMASTLOCK	IN	AHBL xauv - Thaum tau lees paub, kev hloov pauv tam sim no yog ib feem ntawm kev lag luam xauv.
AHB1_S_HWRITE	IN	AHBL sau - Thaum siab, qhia tias kev hloov pauv tam sim no yog sau. Thaum qis, qhia tias qhov kev hloov pauv tam sim no yog nyeem.
AHB1_S_HREADY	IN	AHBL npaj - Thaum siab, qhia tias tus qhev npaj tau txais kev hloov pauv tshiab.
AHB1_S_HWDATA[31:0]	IN	AHBL sau cov ntaub ntawv - Sau cov ntaub ntawv los ntawm tus tswv mus rau tus qhev

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