Intel 50G àjọlò Design Example User Itọsọna

Awọn akoonu tọju

1 Intel 50G àjọlò Design Example

2 50GbE Quick Bẹrẹ Itọsọna

3 Apẹrẹ Example Directory Be

4 Simulation Design Example irinše

5 Ti o npese awọn Design Example

6 Simulating 50GbE Oniru Example Testbench

7 Apẹrẹ Example Apejuwe

8 50GbE Oniru Example Awọn iforukọsilẹ

9 Awọn iwe aṣẹ / Awọn orisun

9.1 Awọn itọkasi

10 jẹmọ Posts

Intel 50G àjọlò Design Example

50GbE Quick Bẹrẹ Itọsọna

50GbE IP mojuto n pese idanwo kikopa ati apẹrẹ ohun elo kan example ti o atilẹyin akopo ati hardware igbeyewo. Nigbati o ba ṣe ina apẹrẹ example, paramita olootu laifọwọyi ṣẹda awọn files pataki lati ṣe simulate, ṣajọ, ati idanwo apẹrẹ ni hardware. O le ṣe igbasilẹ apẹrẹ ohun elo ti a ṣajọpọ si ẹrọ Arria 10 GT kan.

Akiyesi: Apẹrẹ yii example fojusi ẹrọ Arria 10 GT ati pe o nilo ifẹhinti 25G kan. Jọwọ kan si aṣoju Intel FPGA rẹ lati beere nipa iru ẹrọ ti o yẹ lati ṣiṣe ohun elo ohun elo yiiample. Ni awọn igba miiran awin ti ohun elo ti o yẹ le wa. Ni afikun, Intel pese akopọ-nikan example ise agbese ti o le lo lati ni kiakia siro IP mojuto agbegbe ati ìlà.

olusin 1. Design Example Lilo

Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn aami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ṣiṣe ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ. * Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.

Apẹrẹ Example Directory Be

olusin 2. 50GbE Design Example Directory Be

Awọn hardware iṣeto ni ati igbeyewo files (apẹrẹ hardware example) wa ninuample_dir>/hardware_test_design. Simulation naa files (testbench fun kikopa nikan) wa ninuample_dir>/ example_testbench.The akopo-nikan oniru example wa ni be niample_dir>/ akopo_test_design.

Simulation Design Example irinše

olusin 3. 50GbE Simulation Design Example Àkọsílẹ aworan atọka

Simulation example design oke-ipele igbeyewo file jẹ basic_avl_tb_top.sv Eleyi file instantiates ati ki o so ohun ATX PLL. O pẹlu iṣẹ-ṣiṣe kan, send_packets_50g_avl, lati firanṣẹ ati gba awọn apo-iwe 10.

Table 1. 50GbE IP mojuto Testbench File Awọn apejuwe

File Oruko	Apejuwe
Testbench ati Simulation Files
ipilẹ_avl_tb_top.sv	Igbeyewo ipele oke file. Testbench naa ṣe imudara DUT ati ṣiṣe awọn iṣẹ ṣiṣe Verilog HDL lati ṣe ina ati gba awọn apo-iwe.
Awọn iwe afọwọkọ Testbench
run_vsim.do	Iwe afọwọkọ ModelSim lati ṣiṣe testbench.
run_vcs.sh	Awọn Synopsys VCS iwe afọwọkọ lati ṣiṣe awọn testbench.
run_ncsim.sh	Iwe afọwọkọ Cadence NCSim lati ṣiṣẹ testbench.
run_xcelium.sh	Iwe afọwọkọ Cadence Xcelium * lati ṣiṣe testbench naa.

rdware Design Example irinše

olusin 4. 50GbE Hardware Design Example High Ipele Block aworan atọka

Awọn 50GbE hardware oniru example pẹlu awọn wọnyi irinše

50GbE IP mojuto.
Onibara kannaa ti o ipoidojuko siseto ti IP mojuto ati soso iran.

ATX PLL lati wakọ awọn ikanni transceiver ẹrọ.
IOPLL lati ṣe agbejade aago 100 MHz lati aago titẹ sii 50 MHz si apẹrẹ ohun elo example.

JTAG oludari ti o ibasọrọ pẹlu awọn System Console. O ṣe ibasọrọ pẹlu ọgbọn alabara nipasẹ ẹrọ Console System.

Table 2. 50GbE IP mojuto Hardware Design Eksample File Awọn apejuwe

File Awọn orukọ	Apejuwe
eth_ex_50g.qpf	Quartus NOMBA ise agbese file
eth_ex_50g.qsf	Awọn eto ise agbese Quartus file
eth_ex_50g.sdc	Synopsys Design inira file. O le daakọ ati tunṣe eyi file fun ara rẹ 50GbE oniru.
*tesiwaju…*

50GbE Quick Bẹrẹ Itọsọna

File Awọn orukọ	Apejuwe
eth_ex_50g.v	Oke-ipele Verilog HDL oniru example file
wọpọ/	Hardware oniru example ṣe atilẹyin files
hwtest/main.tcl	Akọkọ file fun wiwọle System Console

Ti o npese awọn Design Example

olusin 5. Ilana

Aworan 6. Eksample Design Tab ni 50GbE Parameter Olootu

Tẹle awọn igbesẹ wọnyi lati ṣe ina apẹrẹ hardware example ati testbench

Da lori boya o nlo sọfitiwia Intel Quartus® Prime Pro Edition tabi sọfitiwia Intel Quartus Prime Standard Edition, ṣe ọkan ninu awọn iṣe wọnyi: Ninu Intel Quartus Prime Pro Edition, tẹ File ➤ Oluṣeto Iṣẹ Tuntun lati ṣẹda iṣẹ akanṣe Quartus Prime tuntun, tabi File ➤ Ṣii Project lati ṣii iṣẹ akanṣe Quartus Prime ti o wa tẹlẹ. Oluṣeto naa ta ọ lati pato ẹrọ kan. Ninu sọfitiwia Ipele Ipele Intel Quartus Prime, ninu Katalogi IP (Awọn irinṣẹ IP Catalog), yan idile ẹrọ ibi-afẹde Arria 10.
Ninu Katalogi IP, wa ko si yan 50G Ethernet. Ferese Iyipada IP Tuntun yoo han.

Pato orukọ ipele oke kan fun iyatọ IP rẹ ki o tẹ O DARA. Olootu paramita ṣe afikun .qsys oke-ipele (ni Intel Quartus Prime Standard Edition) tabi .ip (ni Intel Quartus Prime Pro Edition) file si awọn ti isiyi ise agbese laifọwọyi. Ti o ba ti ṣetan lati fi ọwọ kun .qsys tabi .ip file si ise agbese, tẹ Project ➤ Fikun-un / Yọ Files ni Project lati fi awọn file.
Ni Intel Quartus Prime Standard Edition sọfitiwia, o gbọdọ yan ohun elo Arria 10 kan pato ni aaye Ẹrọ, tabi tọju ẹrọ aifọwọyi ti sọfitiwia Quartus Prime ni imọran.
Akiyesi: Apẹrẹ hardware example ìkọlélórí yiyan pẹlu awọn ẹrọ lori afojusun ọkọ. O pato awọn afojusun ọkọ lati awọn akojọ ti oniru example awọn aṣayan ninu awọn Example Design taabu (Igbese 8).

Tẹ O DARA. Olootu paramita yoo han.
Lori IP taabu, pato awọn paramita fun iyatọ ipilẹ IP rẹ.

Lori Example Design taabu, fun Example Apẹrẹ Files, yan aṣayan Simulation lati ṣe ina testbench, ki o yan aṣayan Synthesis lati ṣe ipilẹṣẹ apẹrẹ ohun elo example. Nikan Verilog HDL files ti wa ni ipilẹṣẹ.
Akiyesi: Kokoro IP VHDL ti n ṣiṣẹ ko si. Pato Verilog HDL nikan, fun apẹrẹ ipilẹ IP rẹ example.
Fun Hardware Board yan Arria 10 GX Transceiver Signal Integrity Development Apo.
Akiyesi: Kan si aṣoju Intel FPGA rẹ fun alaye nipa iru ẹrọ ti o yẹ lati ṣiṣẹ ohun elo yii example.

Tẹ Ina Example Design bọtini. Awọn Yan Example Design Directory window han.
Ti o ba fẹ lati yi awọn oniru exampọna itọsọna tabi orukọ lati awọn aṣiṣe ti o han (alt_e50_0_example_design), lọ kiri si ọna tuntun ki o tẹ apẹrẹ tuntun example orukọ liana (ample_dir>).
Tẹ O DARA.
Tọkasi Idahun KDB Bawo ni MO ṣe sanpada fun jitter ti PLL cascading tabi ọna aago ti kii ṣe igbẹhin fun aago itọkasi Arria 10 PLL? fun a workaround o yẹ ki o waye ninu hardware_test_design liana ni .sdc file.

Akiyesi: O gbọdọ kan si Idahun KDB yii nitori pe ọna RX ni 50GbE IP mojuto pẹlu awọn PLL ti o kasikedi. Nitorinaa, awọn aago ipilẹ IP le ni iriri jitter afikun ni awọn ẹrọ Arria 10. Idahun KDB yii ṣe alaye awọn idasilẹ sọfitiwia ninu eyiti iṣẹ ṣiṣe jẹ pataki.

Alaye ti o jọmọ
Idahun KDB: Bawo ni MO ṣe sanpada fun jitter ti PLL cascading tabi ọna aago ti kii ṣe igbẹhin fun aago itọkasi Arria 10 PLL?

Simulating 50GbE Oniru Example Testbench

olusin 7. Ilana

Tẹle awọn igbesẹ wọnyi lati ṣe simulate testbench

Yi pada si testbench kikopa lianaample_dir>/ example_testbench.
Ṣiṣe awọn iwe afọwọkọ kikopa fun atilẹyin iṣeṣiro ti o fẹ. Awọn akosile akopọ ati ki o nṣiṣẹ testbench ni labeabo. Tọkasi tabili “Awọn Igbesẹ lati ṣe Simulate Testbench”.
Ṣe itupalẹ awọn abajade. Aṣeyọri testbench firanṣẹ awọn apo-iwe mẹwa, gba awọn apo-iwe mẹwa, ati ṣafihan “Testbench ti pari.”

Table 3. Igbesẹ lati Simulate awọn Testbench

Simulator	Awọn ilana
AwoṣeSim	Ninu laini aṣẹ, tẹ vsim -do run_vsim.do Ti o ba fẹ lati ṣe adaṣe lai mu ModelSim GUI soke, tẹ vsim -c -do run_vsim.do Akiyesi: AwoṣeSim* – Simulator Edition Intel FPGA ko ni agbara lati ṣe afarawe ipilẹ IP yii. O gbọdọ lo afọwọṣe ModelSim atilẹyin miiran gẹgẹbi ModelSim SE.
NCSim	Ninu laini aṣẹ, tẹ sh run_ncsim.sh
VCS	Ninu laini aṣẹ, tẹ sh run_vcs.sh
Xcelium	Ninu laini aṣẹ, tẹ sh run_xcelium.sh

Ṣiṣe idanwo aṣeyọri ṣe afihan iṣelọpọ ti o jẹrisi ihuwasi atẹle

Nduro fun aago RX lati yanju
Titẹ sita ipo PHY
Fifiranṣẹ awọn apo-iwe 10
Gbigba awọn apo-iwe 10

Ṣe afihan “Testbench ti pari.”

Awọn atẹle sample o wu sapejuwe a aseyori kikopa igbeyewo run

Aago Ref jẹ ṣiṣe ni 625 MHz nitorina gbogbo awọn nọmba le lo fun gbogbo awọn akoko aago.

# Pupọ awọn igbohunsafẹfẹ ijabọ nipasẹ 33/32 lati gba awọn igbohunsafẹfẹ aago gangan.
# Nduro fun titete RX
#RX deskew titii pa

# RX titete ọna titii pa
#TX ṣiṣẹ
#* Fifiranṣẹ Packet 1…

#* Fifiranṣẹ Packet 2…
#* Fifiranṣẹ Packet 3…
#* Fifiranṣẹ Packet 4…

#* Fifiranṣẹ Packet 5…
#* Fifiranṣẹ Packet 6…
#* Fifiranṣẹ Packet 7…

#**Packet 1 ti o gba…
#* Fifiranṣẹ Packet 8…
#**Packet 2 ti o gba…

#* Fifiranṣẹ Packet 9…
#**Packet 3 ti o gba…
#* Fifiranṣẹ Packet 10…

#**Packet 4 ti o gba…
#**Packet 5 ti o gba…
#**Packet 6 ti o gba…

#**Packet 7 ti o gba…
#**Packet 8 ti o gba…
#**Packet 9 ti o gba…

#**Packet 10 ti o gba…
#**
#** Testbench ti pari.

#**
*************************************

Iṣakojọpọ ati Ṣiṣeto Oniru Example ni Hardware

Lati sakojo awọn hardware oniru example ki o tunto lori ẹrọ Arria 10 GT rẹ, tẹle awọn igbesẹ wọnyi

Rii daju hardware oniru example iran jẹ pari.
Ninu sọfitiwia Intel Quartus Prime, ṣii iṣẹ akanṣe Intel Quartus Primeample_dir>/hardware_test_design/eth_ex_50g.qpf.

Ṣaaju ki o to ṣajọ, rii daju pe o ti ṣe imuse iṣẹ-ṣiṣe lati Idahun KDB Bawo ni MO ṣe sanpada fun jitter ti PLL cascading tabi ọna aago ti kii ṣe igbẹhin fun aago itọkasi Arria 10 PLL? ti o ba wulo fun itusilẹ sọfitiwia rẹ.
Lori awọn Processing akojọ, tẹ Bẹrẹ akopo.
Lẹhin ti o ṣe ina ohun SRAM file .sof, tẹle awọn igbesẹ wọnyi lati ṣe eto apẹrẹ hardware example lori ẹrọ Arria 10:

Lori awọn Irinṣẹ akojọ, tẹ Programmer.
Ni awọn Programmer, tẹ Hardware Setup.
Yan ẹrọ siseto.

Yan ki o ṣafikun igbimọ Arria 10 GT pẹlu 25G retimer si igba Intel Quartus Prime rẹ.
Rii daju pe Ipo ti ṣeto si JTAG.
Yan ẹrọ Arria 10 ki o tẹ Fi ẹrọ kun. Awọn pirogirama ṣe afihan aworan atọka Àkọsílẹ ti awọn asopọ laarin awọn ẹrọ lori igbimọ rẹ.

Ni ila pẹlu .sof rẹ, ṣayẹwo apoti fun .sof.
Ṣayẹwo apoti ti o wa ninu iwe Eto / Tunto.
Tẹ Bẹrẹ

Akiyesi: Apẹrẹ yii example fojusi Arria 10 GT ẹrọ. Jọwọ kan si aṣoju Intel FPGA rẹ lati beere nipa iru ẹrọ ti o yẹ lati ṣiṣẹ tẹlẹ hardware yiiample

Alaye ti o jọmọ

Idahun KDB: Bawo ni MO ṣe sanpada fun jitter ti PLL cascading tabi ọna aago aiṣedeede fun aago itọkasi Arria 10 PLL?

Akopọ Ipilẹṣẹ fun Iṣagbekalẹ ati Apẹrẹ Ipilẹ Ẹgbẹ
Siseto Intel FPGA Devices

Idanwo 50GbE Hardware Design Example

Lẹhin ti o ṣe akopọ 50GbE IP core design example ati tunto rẹ lori ẹrọ Arria 10 GT rẹ, o le lo Console System lati ṣe eto ipilẹ IP ati awọn iforukọsilẹ Native PHY IP mojuto rẹ. Lati tan-an Console System ati idanwo apẹrẹ hardware example, tẹle awọn igbesẹ wọnyi:

Lẹhin ti hardware oniru example jẹ tunto lori ẹrọ Arria 10, ninu sọfitiwia Intel Quartus Prime, lori akojọ Awọn irinṣẹ, tẹ Awọn irinṣẹ N ṣatunṣe aṣiṣe System ➤ System Console.
Ninu iwe Tcl Console, tẹ cd hwest lati yi ilana pada siample_dir>/hardware_test_design/hwtest.

Tẹ orisun main.tcl lati ṣii asopọ si JTAG oluwa.

O le ṣe eto ipilẹ IP pẹlu apẹrẹ atẹle yii example paṣẹ

chkphy_status: Ṣe afihan awọn igbohunsafẹfẹ aago ati ipo titiipa PHY.

start_pkt_gen: Bẹrẹ olupilẹṣẹ apo.
stop_pkt_gen: Duro monomono soso.
loop_on: Tan-an ti abẹnu loopback ni tẹlentẹle

loop_off: Pa ti abẹnu loopback ni tẹlentẹle.
reg_read : Pada awọn IP mojuto Forukọsilẹ iye ni .
reg_write : Kọ si iforukọsilẹ mojuto IP ni adirẹsi .

Alaye ti o jọmọ

50GbE Oniru Example Forukọsilẹ loju iwe 13 Forukọsilẹ map fun hardware oniru example.
Ṣiṣayẹwo ati Awọn apẹrẹ N ṣatunṣe aṣiṣe pẹlu Eto Console

Apẹrẹ Example Apejuwe

Apẹrẹ example ṣe afihan awọn iṣẹ ti mojuto 50GbE pẹlu wiwo transceiver ti o ni ibamu pẹlu IEEE 802.3ba boṣewa CAUI-4 sipesifikesonu. O le ṣe ina apẹrẹ lati Example Design taabu ni 50GbE paramita olootu. Lati ṣe ina apẹrẹ exampNitorina, o gbọdọ kọkọ ṣeto awọn iye paramita fun iyatọ ipilẹ IP ti o pinnu lati ṣe ina ni ọja ipari rẹ. Ti o npese awọn oniru example ṣẹda ẹda ti ipilẹ IP; testbench ati hardware design example lo iyatọ yii bi DUT. Ti o ko ba ṣeto awọn iye paramita fun DUT lati baamu awọn iye paramita ninu ọja ipari rẹ, apẹrẹ apẹẹrẹample o se ina ko idaraya IP mojuto iyatọ ti o pinnu.

Akiyesi: Testbench ṣe afihan idanwo ipilẹ ti ipilẹ IP. Ko ṣe ipinnu lati jẹ aropo fun agbegbe ijẹrisi ni kikun. O gbọdọ ṣe ijerisi gigun diẹ sii ti apẹrẹ 50GbE tirẹ ni simulation ati ni ohun elo.

Alaye ti o jọmọ
Intel Arria® 10 50Gbps àjọlò IP mojuto olumulo Itọsọna

Apẹrẹ Example Iwa
Testbench firanṣẹ ijabọ nipasẹ mojuto IP, ṣiṣe adaṣe ẹgbẹ atagba ati gba ẹgbẹ ti mojuto IP. Ni hardware oniru exampLe, o le eto awọn IP mojuto ni ti abẹnu ni tẹlentẹle loopback mode ati ina ijabọ lori awọn atagba ẹgbẹ ti o losiwajulosehin pada nipasẹ awọn gba ẹgbẹ.

Apẹrẹ Example Interface Awọn ifihan agbara
50GbE testbench jẹ ti ara ẹni ati pe ko nilo ki o wakọ eyikeyi awọn ifihan agbara titẹ sii.

Table 4. 50GbE Hardware Design Eksample Interface Awọn ifihan agbara

Ifihan agbara	Itọsọna	Comments
clk50	Iṣawọle	Wakọ ni 50 MHz. Idi naa ni lati wakọ eyi lati oscillator 50 Mhz lori igbimọ.
clk_ref	Iṣawọle	Wakọ ni 644.53125 MHz.
cpu_resetn	Iṣawọle	Tun IP mojuto. Ti nṣiṣe lọwọ kekere. Ṣe awakọ atunto lile agbaye csr_reset_n si ipilẹ IP.
*tesiwaju…*

Ifihan agbara	Itọsọna	Comments
tx_serial[1:0]	Abajade	Transceiver PHY o wu data ni tẹlentẹle.
rx_serial [1:0]	Iṣawọle	Transceiver PHY igbewọle data ni tẹlentẹle.
olumulo_led[7:0]	Abajade	Awọn ifihan agbara ipo. Apẹrẹ hardware example so awọn die-die wọnyi pọ lati wakọ awọn LED lori igbimọ ibi-afẹde. Awọn die-die kọọkan ṣe afihan awọn iye ifihan agbara atẹle ati ihuwasi aago: • [0]: Ifihan agbara atunto akọkọ si IP mojuto • [1]: Pipin version of clk_ref • [2]: Pipin version of clk50 • [3]: Pipin version of 100 MHz ipo aago • [4]: tx_lanes_stable • [5]: rx_block_lock • [6]: rx_am_lock • [7]: rx_pcs_ready

Alaye ti o jọmọ
Awọn atọkun ati Awọn apejuwe Ifihan Pese awọn apejuwe alaye ti awọn ifihan agbara 50GbE IP ati awọn atọkun ti wọn jẹ.

50GbE Oniru Example Awọn iforukọsilẹ

Table 5. 50GbE Hardware Design Eksample Forukọsilẹ Map
Awọn atokọ ti awọn sakani iforukọsilẹ ti o ya aworan iranti fun apẹrẹ hardware example. O wọle si awọn iforukọsilẹ wọnyi pẹlu awọn iṣẹ reg_read ati reg_write ninu Eto Console.

Aiṣedeede Ọrọ	Forukọsilẹ Ẹka
0x300–0x5FF	50GbE IP mojuto awọn iforukọsilẹ.
0x4000–0x4C00	Arria 10 ìmúdàgba reconfiguration awọn iforukọsilẹ. Adirẹsi ipilẹ iforukọsilẹ jẹ 0x4000 fun Lane 0 ati 0x4400 fun Lane 1.

Alaye ti o jọmọ

Idanwo 50GbE Hardware Design Example loju iwe 11 System Console pase lati wọle si ipilẹ IP ati awọn iforukọsilẹ PHY abinibi.
Iṣakoso 50GbE ati Awọn apejuwe Iforukọsilẹ Ipo Ṣe apejuwe awọn iforukọsilẹ mojuto IP 50GbE.

Iwe Itan Atunyẹwo

Table 6. 50G àjọlò Design Eksample User Itọsọna Àtúnyẹwò History

Ọjọ	Tu silẹ	Awọn iyipada
2019.04.03	17.0	Ṣafikun aṣẹ lati ṣiṣẹ awọn iṣeṣiro Xcelium.
2017.11.08	17.0	Ọna asopọ ti a ṣafikun si Idahun KDB ti o pese ibi-iṣẹ fun jitter ti o pọju lori awọn ẹrọ Intel Arria® 10 nitori sisọ awọn ATX PLLs ni ipilẹ IP. Tọkasi si Ti o npese awọn Design Example loju iwe 7 ati Iṣakojọpọ ati Iṣeto ni Oniru Example ni Hardware loju iwe 10. Apẹrẹ yii example olumulo guide ti ko ti ni imudojuiwọn lati fi irisi Akiyesi: awọn ayipada kekere ni iran apẹrẹ ni awọn idasilẹ Intel Quartus Prime nigbamii ju itusilẹ sọfitiwia Intel Quartus Prime v17.0.
2017.05.08	17.0	Itusilẹ gbangba akọkọ.

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