Intel 50G Ethernet Dhizaini Example

50GbE Quick Start Guide

Iyo 50GbE IP musimboti inopa simulation testbench uye hardware dhizaini example iyo inotsigira kuunganidza uye kuyedza hardware. Paunogadzira iyo dhizaini example, iyo parameter editor inogadzira iyo fileinodiwa kutevedzera, kuunganidza, uye kuyedza dhizaini muhardware. Unogona kudhawunirodha yakaunganidzwa hardware dhizaini kune Arria 10 GT mudziyo.

Cherechedza: Iyi dhizaini example inotarisa Arria 10 GT mudziyo uye inoda 25G retimer. Ndokumbira ubate mumiriri wako weIntel FPGA kuti ubvunze nezve chikuva chakakodzera kumhanyisa iyi hardware example. Mune zvimwe zviitiko chikwereti chehardware chakakodzera chingave chiripo. Mukuwedzera, Intel inopa yekubatanidza-chete example purojekiti yaunogona kushandisa kukurumidza kufungidzira IP musimboti nzvimbo uye nguva.

Mufananidzo 1. Dhizaini Example Usage

Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi. *Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.

Design Example Directory Structure

Mufananidzo 2. 50GbE Dhizaini Example Directory Structure

Iyo hardware kumisikidza uye bvunzo files (iyo hardware dhizaini example) vari mukatiample_dir>/hardware_test_design. The simulation files (testbench yekufananidza chete) iri mukatiample_dir>/ example_testbench.The compilation-chete dhizaini example iri muample_dir>/compilation_test_design.

Simulation Dhizaini Example Components

Mufananidzo 3. 50GbE Simulation Design Exampuye Block Diagram

The simulation example design yepamusoro-level test file is basic_avl_tb_top.sv This file inosimbisa uye inobatanidza ATX PLL. Zvinosanganisira basa, send_packets_50g_avl, kutumira uye kugamuchira mapaketi gumi.

Tafura 1. 50GbE IP Core Testbench File Tsanangudzo

File Zita	Tsanangudzo
Testbench uye Simulation Files
basic_avl_tb_top.sv	Top-level testbench file. Testbench inosimbisa iyo DUT uye inomhanyisa Verilog HDL mabasa kugadzira uye kugamuchira mapaketi.
Testbench Scripts
run_vsim.do	Iyo ModelSim script yekumhanyisa testbench.
run_vcs.sh	Iyo Synopsys VCS script yekumhanyisa testbench.
run_ncsim.sh	Iyo cadence NCSim script yekumhanyisa testbench.
run_xcelium.sh	Iyo cadence Xcelium* script yekumhanyisa testbench.

rdware Dhizaini Example Components

Mufananidzo 4. 50GbE Hardware Design Exampuye High Level Block Diagram

Iyo 50GbE hardware dhizaini example rinosanganisira zvinotevera zvinoriumba

• 50GbE IP musimboti.
• Mutengi logic inoronga hurongwa hweiyo IP musimboti uye packet chizvarwa.
• ATX PLL kutyaira mudziyo transceiver chiteshi.
• IOPLL kugadzira 100 MHz wachi kubva pa50 MHz yekuisa wachi kuenda kune hardware dhizaini ex.ample.
• JTAG controller inotaurirana neSystem Console. Iwe unotaurirana nemutengi logic kuburikidza neSystem Console.

Tafura 2. 50GbE IP Core Hardware Dhizaini Example File Tsanangudzo

File Mazita	Tsanangudzo
eth_ex_50g.qpf	Quartus Prime project file
eth_ex_50g.qsf	Quartus purojekiti marongero file
eth_ex_50g.sdc	Synopsys Design Constraints file. Unogona kukopa uye kugadzirisa izvi file kune yako wega 50GbE dhizaini.
akaenderera…

50GbE Quick Start Guide

File Mazita	Tsanangudzo
eth_ex_50g.v	Yepamusoro-chikamu Verilog HDL dhizaini example file
zvakajairika/	Hardware design example support files
hwtest/main.tcl	Main file yekuwana System Console

Kugadzira iyo Dhizaini Example

Mufananidzo 5. Maitiro

Mufananidzo 6. Exampuye Dhizaina Tab mu50GbE Parameter Mharidzo

Tevedza nhanho idzi kugadzira iyo hardware dhizaini example uye testbench

1. Zvichienderana nekuti uri kushandisa Intel Quartus® Prime Pro Edition software kana Intel Quartus Prime Standard Edition software, ita chimwe chezviito zvinotevera: MuIntel Quartus Prime Pro Edition, tinya. File ➤ New Project Wizard kugadzira itsva Quartus Prime project, kana File ➤ Vhura Project kuvhura iripo Quartus Prime project. Iyo wizard inokukurudzira kuti utaure mudziyo. MuIntel Quartus Prime Standard Edition software, muIP Catalog (Zvishandiso IP Catalog), sarudza iyo Arria gumi yakananga mudziyo mhuri.
2. Mune IP Catalog, tsvaga uye sarudza 50G Ethernet. The New IP Variation hwindo rinoonekwa.
3. Rondedzera zita repamusoro-soro reiyo IP musiyano uye tinya OK. Iyo parameter mupepeti inowedzera yepamusoro-level .qsys (muIntel Quartus Prime Standard Edition) kana .ip (muIntel Quartus Prime Pro Edition) file kune purojekiti yazvino otomatiki. Kana ukakumbirwa kuti uwedzere nemaoko .qsys kana .ip file kuchirongwa, tinya Chirongwa ➤ Wedzera/Bvisa Files muProjekti yekuwedzera iyo file.
4. MuIntel Quartus Prime Standard Edition software, iwe unofanirwa kusarudza chaiyo Arria 10 mudziyo mumudziyo weChishandiso, kana chengetedza mudziyo wakasarudzika uyo Quartus Prime software inokurudzira.
   Cherechedza: Iyo hardware dhizaini example anonyora kusarudzwa nemudziyo pabhodhi rinotarisirwa. Iwe unotsanangura bhodhi rinonangwa kubva kumenyu yedhizaini exampsarudzo mune Example Dhizaini tab (Chikamu 8).
5. Dzvanya OK. Iyo parameter editor inooneka.
6. PaI IP tab, tsanangura maparamita eiyo IP yako musimboti musiyano.
7. Pamusoro peExample Dhizaini tab, yeExample Dhizaini Files, sarudza iyo Simulation sarudzo yekugadzira testbench, uye sarudza iyo Synthesis sarudzo yekugadzira iyo hardware dhizaini ex.ample. Verilog HDL chete files inogadzirwa.
   Cherechedza: Iyo inoshanda VHDL IP musimboti haisi kuwanikwa. Nyora Verilog HDL chete, kune yako IP musimboti dhizaini example.
8. Ye Hardware Board sarudza iyo Arria 10 GX Transceiver Signal Kutendeseka Kwekuvandudza Kit.
   Cherechedza: Bata mumiriri wako weIntel FPGA kuti uwane ruzivo nezve chikuva chakakodzera kumhanyisa iyi hardware example.
9. Dzvanya iyo Gadzira Example Dhizaini bhatani. Sarudza Example Dhizaini Dhairekitori hwindo rinoonekwa.
10. Kana iwe uchida kugadzirisa iyo dhizaini example dhairekitori nzira kana zita kubva kune defaults inoratidzwa (alt_e50_0_example_design), tsvaga kunzira nyowani uye nyora iyo nyowani dhizaini exampzita rezita (ample_dir>).
11. Dzvanya OK.
12. Tarisa kuKDB Mhinduro Ndinoripira sei jitter yePLL inodonha kana isina-yakatsaurirwa wachi nzira yeArria 10 PLL referensi wachi? kuti ugadzirise kushanda unofanira kuisa muhardware_test_design directory mu.sdc file.

Cherechedza: Iwe unofanirwa kubvunza iyi KDB Mhinduro nekuti iyo RX nzira iri mu50GbE IP musimboti inosanganisira cascaded PLL. Naizvozvo, iyo IP yakakosha wachi inogona kuwana yakawedzera jitter muArria 10 zvishandiso. Iyi KDB Mhinduro inojekesa iyo software inoburitswa mune iyo workaround inodiwa.

Related Information
KDB Mhinduro: Ini ndinotsiva sei iyo jitter yePLL inodonha kana isina-yakatsaurirwa wachi nzira yeArria 10 PLL referensi wachi?

Kutevedzera iyo 50GbE Dhizaini Example Testbench

Mufananidzo 7. Maitiro

Tevera matanho aya kutevedzera testbench

1. Shandura kune testbench simulation dhairekitoriample_dir>/ example_testbench.
2. Mhanya iyo simulation script yeiyo inotsigirwa simulator yesarudzo yako. Iyo script inounganidza uye inomhanyisa testbench mune simulator. Tarisa kune tafura "Matanho ekutevedzera Testbench".
3. Ongorora zvabuda. Testbench yakabudirira inotumira mapaketi gumi, inogamuchira mapaketi gumi, uye inoratidza "Testbench yakakwana."

Tafura 3. Matanho ekutevedzera Testbench

Simulator	Mirayiridzo
ModelSim	Mumutsara wekuraira, nyora vsim -do run_vsim.do Kana ukasarudza kutevedzera pasina kuunza ModelSim GUI, nyora vsim -c -do run_vsim.do Cherechedza: Iyo ModelSim * - Intel FPGA Edition simulator haina kugona kutevedzera iyi IP musimboti. Iwe unofanirwa kushandisa imwe inotsigirwa ModelSim simulator seModelSim SE.
NCSim	Mumutsara wekuraira, nyora sh run_ncsim.sh
VCS	Mumutsara wekuraira, nyora sh run_vcs.sh
Xcelium	Mumutsara wekuraira, nyora sh run_xcelium.sh

Iyo yakabudirira bvunzo kumhanya inoratidza inobuda inosimbisa inotevera maitiro

1. Kumirira RX wachi kuti igadzirise
2. Kudhinda PHY chimiro
3. Kutumira 10 mapaketi
4. Kugamuchira 10 mapaketi
5. Kuratidza "Testbench yakakwana."

Inotevera sample output inoratidza yakabudirira simulation test run

• #Ref wachi inomhanya pa625 MHz saka nhamba dzese dzinogona kushandiswa kune ese wachi.
• #Multiply yakashuma mafrequency na33/32 kuti uwane chaiwo wachi.
• #Kumirira kurongeka kweRX
• #RX deskew yakakiyiwa
• #RX nzira yekurongeka yakavharwa
• #TX yakagoneswa
• #**Kutumira Pakiti 1…
• #**Kutumira Pakiti 2…
• #**Kutumira Pakiti 3…
• #**Kutumira Pakiti 4…
• #**Kutumira Pakiti 5…
• #**Kutumira Pakiti 6…
• #**Kutumira Pakiti 7…
• #**Yakagamuchirwa Pakiti 1…
• #**Kutumira Pakiti 8…
• #**Yakagamuchirwa Pakiti 2…
• #**Kutumira Pakiti 9…
• #**Yakagamuchirwa Pakiti 3…
• #**Kutumira Pakiti 10…
• #**Yakagamuchirwa Pakiti 4…
• #**Yakagamuchirwa Pakiti 5…
• #**Yakagamuchirwa Pakiti 6…
• #**Yakagamuchirwa Pakiti 7…
• #**Yakagamuchirwa Pakiti 8…
• #**Yakagamuchirwa Pakiti 9…
• #**Yakagamuchirwa Pakiti 10…
• #**
• #** Testbench yakakwana.
• #**
• ****************************************

Kunyora uye Kugadzirisa Dhizaini Example mu Hardware

Kuunganidza iyo hardware dhizaini example uye gadzirisa pane yako Arria 10 GT mudziyo, tevera matanho aya

1. Ita shuwa kuti hardware dhizaini example generation yapera.
2. MuIntel Quartus Prime software, vhura iyo Intel Quartus Prime projectample_dir>/hardware_test_design/eth_ex_50g.qpf.
3. Usati wagadzira, ita shuwa kuti waita workaround kubva kuKDB Mhinduro Ndinoripira sei jitter yePLL cascading kana isina-yakatsaurirwa wachi nzira yeArria 10 PLL referensi wachi? kana yakakodzera kune yako software kuburitswa.
4. Pane iyo Processing menyu, tinya Start Compilation.
5. Mushure mekugadzira chinhu cheSRAM file .sof, tevera matanho aya kuronga hardware design examppane iyo Arria 10 mudziyo:

• PaZvishandiso menyu, tinya Programmer.
• MuPurogiramu, tinya Hardware Setup.
• Sarudza chigadzirwa chepurogiramu.
• Sarudza uye wedzera iyo Arria 10 GT bhodhi ine 25G retimer kune yako Intel Quartus Prime chikamu.
• Ita shuwa kuti Mode yakaiswa kuna JTAG.
• Sarudza iyo Arria 10 mudziyo uye tinya Wedzera Chishandiso. Iyo Programmer inoratidza dhizaini yebhuroka yekubatana pakati pemidziyo iri pabhodhi rako.
• Mumutsara ne .sof yako, tarisa bhokisi re .sof.
• Tarisa bhokisi riri muPurogiramu/Gadzirisa column.
• Click Start

Cherechedza: Iyi dhizaini example inotarisa iyo Arria 10 GT mudziyo. Ndokumbira ubate mumiriri wako weIntel FPGA kuti ubvunze nezve chikuva chakakodzera kumhanyisa iyi yehardware example

Related Information

• KDB Mhinduro: Ini ndinotsiva sei iyo jitter yePLL inodonha kana isina kupihwa wachi nzira yeArria 10 PLL referensi wachi?
• Kuwedzera Kuunganidzwa kweHierarchical uye Team-Yakavakirwa Dhizaini
• Kuronga Intel FPGA Zvishandiso

Kuedza iyo 50GbE Hardware Dhizaini Example

Mushure mekunyora iyo 50GbE IP musimboti dhizaini example uye gadzirisa pane yako Arria 10 GT mudziyo, unogona kushandisa iyo System Console kuronga iyo IP musimboti uye yakamisikidzwa Native PHY IP epakati marejista. Kuvhura iyo System Console uye kuyedza iyo hardware dhizaini example, tevera matanho aya:

1. Mushure meiyo hardware dhizaini exampiyo inogadziriswa paArria 10 mudziyo, muIntel Quartus Prime software, pane Zvishandiso menyu, tinya System Debugging Zvishandiso ➤ System Console.
2. MuTcl Console pane, nyora cd hwtest kuti uchinje dhairekitori kutiample_dir>/hardware_test_design/hwtest.
3. Type source main.tcl kuti uvhure chinongedzo kuJTAG master.

Iwe unogona kuronga iyo IP musimboti neinotevera dhizaini example commands

• chkphy_status: Inoratidza wachi frequency uye PHY kukiya mamiriro.
• start_pkt_gen: Inotanga jenareta yepakiti.
• stop_pkt_gen: Inomisa jenareta yepakiti.
• loop_on: Inobatidza yemukati serial loopback
• loop_off: Inodzima yemukati serial loopback.
• reg_read : Inodzosa iyo IP yepakati rejisita kukosha pa .
• reg_write : Anonyora kune iyo IP core register pakero .

Related Information

• 50GbE Dhizaini Example Registers papeji 13 Nyora mepu yehardware dhizaini example.
• Kuongorora uye Kugadzirisa Dhizaini neSystem Console

Design Example Description

Iyo yakagadzirwa example inoratidza mashandiro eiyo 50GbE core ine transceiver interface inoenderana neIEEE 802.3ba standard CAUI-4 yakatarwa. Iwe unogona kugadzira dhizaini kubva kuExample Dhizaini tebhu mune 50GbE parameter mupepeti. Kugadzira iyo dhizaini exampuye, iwe unofanirwa kutanga waisa iyo parameter kukosha kweiyo IP musimboti mutsauko waunoda kugadzira mune yako yekupedzisira chigadzirwa. Kugadzira iyo dhizaini example inogadzira kopi yeiyo IP core; iyo testbench uye hardware dhizaini exampndinoshandisa shanduko iyi seDUT. Kana iwe ukasaisa iyo parameter kukosha kweDUT kuti ienderane neiyo parameter kukosha mune yako yekupedzisira chigadzirwa, dhizaini ex.ampiyo iwe yaunogadzira haishandisi iyo IP musimboti musiyano waunoda.

Cherechedza: Iyo testbench inoratidza bvunzo yekutanga yeiyo IP core. Haina kuitirwa kutsiva nzvimbo yechokwadi yakazara. Iwe unofanirwa kuita yakawedzera ongororo yeako wega 50GbE dhizaini mukuenzanisa uye muhardware.

Related Information
Intel Arria® 10 50Gbps Ethernet IP Core User Guide

Design Example Behavior
Iyo testbench inotumira traffic kuburikidza neiyo IP musimboti, ichiita yekufambisa divi uye inogashira divi reiyo IP musimboti. Mukugadzirwa kwehardware example, unogona kuronga iyo IP musimboti mune yemukati serial loopback modhi uye kugadzira traffic padivi rekutumira iro rinodzokera kumashure kuburikidza nedivi rekugamuchira.

Design Example Interface Signals
Iyo 50GbE testbench inozvimiririra uye haidi kuti iwe utyaire chero masaini ekuisa.

Tafura 4. 50GbE Hardware Dhizaini Example Interface Signals

Signal	Direction	Comments
clk50	Input	Dhiraivha pa50 MHz. Chinangwa ndechekutyaira izvi kubva kune 50 Mhz oscillator pabhodhi.
clk_ref	Input	Dhiraivha pa644.53125 MHz.
cpu_resetn	Input	Inogadzirisa zvakare IP core. Active low. Inotyaira iyo yepasirese yakaoma reset csr_reset_n kune IP musimboti.
akaenderera…

Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi. *Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.

Signal	Direction	Comments
tx_serial[1:0]	Output	Transceiver PHY yakabuda serial data.
rx_serial[1:0]	Input	Transceiver PHY inopinza serial data.
user_led[7:0]	Output	Status zviratidzo. Iyo hardware dhizaini example inobatanidza mabheti aya kutyaira ma LED pane bhodhi rinotarisirwa. Mabhiti ega ega anoratidza anotevera masiginecha maitiro uye wachi maitiro: • [0]: Chiratidzo chikuru chekugadzirisa kuIP core • [1]: Yakakamurwa shanduro ye clk_ref • [2]: Yakakamurwa shanduro ye clk50 • [3]: Yakakamurwa shanduro ye100 MHz mamiriro wachi • [4]: ​​tx_lanes_stable • [5]: rx_block_lock • [6]: rx_am_lock • [7]: rx_pcs_ready

Related Information
Interfaces uye Signal Tsananguro Inopa tsananguro yakadzama ye50GbE IP musimboti masaini uye mainterfaces kwaanogara.

50GbE Dhizaini Example Registers

Tafura 5. 50GbE Hardware Dhizaini Example Register Mepu
Inodonongodza marejisteri akamepurwa ndangariro yehardware dhizaini example. Iwe unowana aya marejista neiyo reg_read uye reg_write mabasa muSystem Console.

Shoko Offset	Register Category
0x300–0x5FF	50GbE IP musimboti marejista.
0x4000–0x4C00	Arria 10 dynamic reconfiguration registers. Register base kero ndeye 0x4000 yeLane 0 uye 0x4400 yeLane 1.

Related Information

• Kuedza iyo 50GbE Hardware Dhizaini Example papeji 11 System Console inoraira kuwana iyo IP musimboti uye Native PHY marejista.
• 50GbE Kudzora uye Status Rejista Tsananguro Inotsanangura iyo 50GbE IP marejista epakati.

Document Revision History

Tafura 6. 50G Ethernet Dhizaini Example User Guide Revision History

Date	Kusunungurwa	Kuchinja
2019.04.03	17.0	Yakawedzera murairo wekumhanyisa Xcelium simulations.
2017.11.08	17.0	Yakawedzerwa chinongedzo kuKDB Mhinduro inopa workaround yeinogona jitter paIntel Arria® 10 zvishandiso nekuda kwekudonha kweATX PLL muIP musimboti. Tarisa kune Kugadzira iyo Dhizaini Example papeji 7 uye Kuunganidza uye Kugadzirisa Dhizaini Example mu Hardware papeji 10. Iyi dhizaini exampLe user guide haina kuvandudzwa kuratidza Cherechedza: shanduko diki mukugadzira dhizaini muIntel Quartus Prime inoburitswa gare gare kupfuura iyo Intel Quartus Prime software kuburitswa v17.0.
2017.05.08	17.0	Kutanga kuburitswa pachena.

Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi. *Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.

Zvinyorwa / Zvishandiso

Intel 50G Ethernet Dhizaini Example [pdf] Bhuku reMushandisi 50G Ethernet Dhizaini Example, 50G, Ethernet Dhizaini Example, Dhizaini Example

References

• User Manual