Intel 50G Ethernet Design Example

50GbE Quick Start Guide

50GbE IP pachimake imapereka testbench yoyeserera komanso kapangidwe kazinthu kakaleample yomwe imathandizira kusonkhanitsa ndi kuyesa kwa hardware. Mukapanga zojambula zakaleampndi, mkonzi wa parameter amangopanga files zofunika kuyerekezera, kusonkhanitsa, ndi kuyesa mapangidwe mu hardware. Mutha kutsitsa kapangidwe ka Hardware kachipangizo ka Arria 10 GT.

Zindikirani: Mapangidwe awa example imayang'ana chipangizo cha Arria 10 GT ndipo imafuna 25G retimer. Chonde funsani woimira Intel FPGA wanu kuti akufunseni za pulatifomu yoyenera kuyendetsa zinthu zakaleziample. Nthawi zina ngongole ya hardware yoyenera ingakhalepo. Kuphatikiza apo, Intel imapereka chophatikizira chokhachoample pulojekiti yomwe mungagwiritse ntchito kuyerekeza mwachangu malo oyambira a IP ndi nthawi yake.

Chithunzi 1. Design Exampndi Kugwiritsa

Malingaliro a kampani Intel Corporation Maumwini onse ndi otetezedwa. Intel, logo ya Intel, ndi zizindikiro zina za Intel ndi zizindikiro za Intel Corporation kapena mabungwe ake. Intel imatsimikizira kugwira ntchito kwa FPGA yake ndi zida za semiconductor malinga ndi zomwe zili pano malinga ndi chitsimikizo cha Intel, koma ili ndi ufulu wosintha zinthu ndi ntchito zilizonse nthawi iliyonse popanda kuzindikira. Intel sakhala ndi udindo kapena udindo chifukwa chakugwiritsa ntchito kapena kugwiritsa ntchito zidziwitso zilizonse, malonda, kapena ntchito zomwe zafotokozedwa pano kupatula monga momwe Intel adavomerezera momveka bwino. Makasitomala a Intel amalangizidwa kuti apeze mtundu waposachedwa kwambiri wamakina a chipangizocho asanadalire zidziwitso zilizonse zosindikizidwa komanso asanayike maoda azinthu kapena ntchito. *Mayina ena ndi mtundu zitha kunenedwa kuti ndi za ena.

Design Exampndi Kapangidwe ka Directory

Chithunzi 2. 50GbE Design Exampndi Kapangidwe ka Directory

Kukonzekera kwa hardware ndi kuyesa files (kapangidwe ka hardware example) zili muample_dir>/hardware_test_design. Kayeseleledwe files (testbench for simulation only) ali mkatiample_dir>/example_testbench.Kuphatikizika kokha kamangidwe kakaleample ili muample_dir>/compilation_test_design.

Simulation Design Exampndi Components

Chithunzi 3. 50GbE Simulation Design Exampndi Block Diagram

Kayeseleledwe example design mayeso apamwamba file ndi basic_avl_tb_top.sv Izi file imakhazikitsa ndikulumikiza ATX PLL. Zimaphatikizapo ntchito, send_packets_50g_avl, kutumiza ndi kulandira mapaketi 10.

Table 1. 50GbE IP Core Testbench File Kufotokozera

File Dzina	Kufotokozera
Testbench ndi Simulation Files
basic_avl_tb_top.sv	Testbench yapamwamba kwambiri file. Testbench imayambitsa DUT ndikuyendetsa ntchito za Verilog HDL kuti apange ndi kuvomereza mapaketi.
Zolemba za Testbench
run_vsim.do	The ModelSim script kuyendetsa testbench.
run_vcs.sh	Synopsys VCS script yoyendetsa testbench.
run_ncsim.sh	The Cadence NCSim script kuyendetsa testbench.
run_xcelium.sh	Cholemba cha Cadence Xcelium* kuti muyendetse testbench.

rdware Design Exampndi Components

Chithunzi 4. 50GbE Hardware Design Exampndi High Level Block Diagram

Mapangidwe a hardware a 50GbE example likuphatikizapo zigawo zotsatirazi

• 50GbE IP core.
• Lingaliro la kasitomala lomwe limagwirizanitsa mapulogalamu a IP core ndi kupanga paketi.
• ATX PLL kuyendetsa ma transceiver a chipangizo.
• IOPLL kuti ipange wotchi ya 100 MHz kuchokera pa wotchi yolowera ya 50 MHz kupita ku kapangidwe kazinthu zakale.ample.
• JTAG woyang'anira yemwe amalumikizana ndi System Console. Mumalumikizana ndi malingaliro a kasitomala kudzera mu System Console.

Table 2. 50GbE IP Core Hardware Design Example File Kufotokozera

File Mayina	Kufotokozera
eth_ex_50g.qpf	Quartus Prime Project file
eth_ex_50g.qsf	Zokonda za polojekiti ya Quartus file
eth_ex_50g.sdc	Zolepheretsa Zopanga za Synopsys file. Mutha kukopera ndikusintha izi file pakupanga kwanu kwa 50GbE.
anapitiriza…

50GbE Quick Start Guide

File Mayina	Kufotokozera
eth_ex_50g.v	Mapangidwe apamwamba a Verilog HDL example file
wamba/	Mapangidwe a Hardware exampndi support files
hwtest/main.tcl	Chachikulu file kuti mupeze System Console

Kupanga Design Example

Chithunzi 5. Ndondomeko

Chithunzi 6. Example Design Tab mu 50GbE Parameter Editor

Tsatirani izi kuti mupange mawonekedwe a Hardware example ndi testbench

1. Kutengera ngati mukugwiritsa ntchito pulogalamu ya Intel Quartus® Prime Pro Edition kapena pulogalamu ya Intel Quartus Prime Standard Edition, chitani chimodzi mwazinthu izi: Mu Intel Quartus Prime Pro Edition, dinani File ➤ Project Wizard Watsopano kuti apange polojekiti yatsopano ya Quartus Prime, kapena File ➤ Tsegulani Project kuti mutsegule pulojekiti yomwe ilipo ya Quartus Prime. Wizard imakulimbikitsani kuti mutchule chipangizo. Mu pulogalamu ya Intel Quartus Prime Standard Edition, mu IP Catalog (Zida za IP Catalog), sankhani banja la zida za Arria 10.
2. Mu IP Catalog, pezani ndikusankha 50G Ethernet. Zenera la New IP Variation likuwonekera.
3. Tchulani dzina lapamwamba la IP yanu ndipo dinani OK. Mkonzi wa parameter amawonjezera .qsys yapamwamba (mu Intel Quartus Prime Standard Edition) kapena .ip (mu Intel Quartus Prime Pro Edition) file ku polojekiti yamakono basi. Ngati mwapemphedwa kuti muwonjezere pamanja .qsys kapena .ip file ku polojekitiyo, dinani Ntchito ➤ Onjezani/Chotsani Files mu Project kuwonjezera ma file.
4. Mu pulogalamu ya Intel Quartus Prime Standard Edition, muyenera kusankha chipangizo china cha Arria 10 pagawo la Chipangizo, kapena kusunga chipangizo chokhazikika chomwe pulogalamu ya Quartus Prime ikufuna.
   Zindikirani: Mapangidwe a hardware example overwrites kusankha ndi chipangizo pa chandamale bolodi. Mumatchula bolodi lomwe mukufuna kuchokera pamenyu ya kapangidwe kakaleample options mu Example Design tabu (Gawo 8).
5. Dinani Chabwino. The parameter editor ikuwonekera.
6. Pa tabu ya IP, tchulani magawo akusintha kwanu kwa IP.
7. Pa Eksample Design tabu, ya Eksampndi Design Files, sankhani njira yoyeserera kuti mupange testbench, ndikusankha njira ya kaphatikizidwe kuti mupange kapangidwe ka Hardware ex.ample. Verilog HDL yokha files amapangidwa.
   Zindikirani: IP yogwira ntchito ya VHDL IP palibe. Tchulani Verilog HDL yokha, ya IP core design example.
8. Kwa Hardware Board sankhani Arria 10 GX Transceiver Signal Integrity Development Kit.
   Zindikirani: Lumikizanani ndi woimira Intel FPGA wanu kuti mudziwe zambiri za nsanja yoyenera kugwiritsa ntchito chipangizochiample.
9. Dinani Pangani Exampndi Design batani. Sankhani Exampzenera la Design Directory likuwonekera.
10. Ngati mukufuna kusintha kapangidwe example chikwatu njira kapena dzina kuchokera zosasintha zomwe zikuwonetsedwa (alt_e50_0_example_design), sakatulani njira yatsopano ndikulemba mawonekedwe atsopanoample directory name (ample_dir>).
11. Dinani Chabwino.
12. Onani ku Yankho la KDB Kodi ndimabwezera bwanji jitter ya PLL yotuluka kapena njira yosadzipatulira ya wotchi ya Arria 10 PLL? kuti mugwiritse ntchito muyenera kuyika mu hardware_test_design directory mu .sdc file.

Zindikirani: Muyenera kufunsa Yankho la KDB ili chifukwa njira ya RX mu 50GbE IP pachimake imaphatikizapo ma PLL otsika. Chifukwa chake, mawotchi apakati a IP amatha kukhala ndi jitter yowonjezera pazida za Arria 10. Yankho la KDB ili limamveketsa bwino za mapulogalamu omwe amafunikira ntchito.

Zambiri Zogwirizana
Yankho la KDB: Kodi ndimalipira bwanji jitter ya PLL yotayika kapena njira yosadzipatulira ya wotchi ya Arria 10 PLL?

Kutengera 50GbE Design Exampndi Testbench

Chithunzi 7. Ndondomeko

Tsatirani izi kuti muyesere testbench

1. Sinthani ku chikwatu choyeserera cha testbenchample_dir>/example_testbench.
2. Yendetsani script yoyeserera ya simulator yothandizidwa yomwe mungasankhe. Zolembazo zimaphatikiza ndikuyendetsa testbench mu simulator. Onani pa tebulo "Masitepe Otengera Testbench".
3. Unikani zotsatira. Testbench yopambana imatumiza mapaketi khumi, imalandira mapaketi khumi, ndikuwonetsa "Testbench yathunthu."

Table 3. Njira Zotsanzira Testbench

Woyeserera	Malangizo
ModelSim	Mu mzere wolamula, lembani vsim -do run_vsim.do Ngati mukufuna kutsanzira popanda kubweretsa ModelSim GUI, lembani vsim -c -do run_vsim.do Zindikirani: ModelSim * - Intel FPGA Edition simulator ilibe kuthekera kotengera maziko a IP awa. Muyenera kugwiritsa ntchito simulator ina yothandizidwa ya ModelSim monga ModelSim SE.
NCSim	Mu mzere wolamula, lembani sh run_ncsim.sh
Zithunzi za VCS	Mu mzere wolamula, lembani sh run_vcs.sh
Xcelium	Mu mzere wolamula, lembani sh run_xcelium.sh

Kuthamanga kochita bwino kumawonetsa zotuluka zomwe zimatsimikizira izi

1. Kudikirira wotchi ya RX kuti ikhazikike
2. Kusindikiza mawonekedwe a PHY
3. Kutumiza mapaketi 10
4. Kulandira mapaketi 10
5. Kuwonetsa "Testbench yatha."

Zotsatirazi sample output ikuwonetsa kuyesa koyeserera kopambana

• #Ref wotchi imayendetsedwa pa 625 MHz kotero manambala athunthu amatha kugwiritsidwa ntchito nthawi zonse.
• #Multiply ma frequency adanenedwa pofika 33/32 kuti mupeze ma frequency enieni.
• #Kudikirira ma RX
• #RX deskew yotsekedwa
• #RX njira yolumikizira yotsekedwa
• #TX yathandizidwa
• #**Kutumiza Phukusi 1…
• #**Kutumiza Phukusi 2…
• #**Kutumiza Phukusi 3…
• #**Kutumiza Phukusi 4…
• #**Kutumiza Phukusi 5…
• #**Kutumiza Phukusi 6…
• #**Kutumiza Phukusi 7…
• #**Paketi Yolandila 1…
• #**Kutumiza Phukusi 8…
• #**Paketi Yolandila 2…
• #**Kutumiza Phukusi 9…
• #**Paketi Yolandila 3…
• #**Kutumiza Phukusi 10…
• #**Paketi Yolandila 4…
• #**Paketi Yolandila 5…
• #**Paketi Yolandila 6…
• #**Paketi Yolandila 7…
• #**Paketi Yolandila 8…
• #**Paketi Yolandila 9…
• #**Paketi Yolandila 10…
• #**
• #** Testbench yatha.
• #**
• *****************************************

Kupanga ndi Kukonza Design Exampndi mu Hardware

Kupanga kapangidwe ka hardware example ndikuikonza pa chipangizo chanu cha Arria 10 GT, tsatirani izi

1. Onetsetsani kuti hardware kapangidwe example generation yatha.
2. Mu pulogalamu ya Intel Quartus Prime, tsegulani polojekiti ya Intel Quartus Primeample_dir>/hardware_test_design/eth_ex_50g.qpf.
3. Musanasambe, onetsetsani kuti mwagwiritsa ntchito njira yochokera ku KDB Yankho Kodi ndimalipira bwanji jitter ya PLL cascading kapena njira yosadzipatulira ya wotchi ya Arria 10 PLL? ngati ndizofunikira pakumasulidwa kwa pulogalamu yanu.
4. Pa Processing menyu, dinani Start Compilation.
5. Mukapanga chinthu cha SRAM file .sof, tsatirani izi kuti mupange mawonekedwe a hardware example pa chipangizo cha Arria 10:

• Pa Zida menyu, dinani Programmer.
• Mu Programmer, dinani Hardware Setup.
• Sankhani chipangizo chokonzera.
• Sankhani ndikuwonjezera bolodi ya Arria 10 GT yokhala ndi 25G retimer ku gawo lanu la Intel Quartus Prime.
• Onetsetsani kuti Mode yakhazikitsidwa ku JTAG.
• Sankhani chipangizo cha Arria 10 ndikudina Add Chipangizo. The Programmer akuwonetsa chithunzi cholumikizira cha kulumikizana pakati pa zida pa bolodi lanu.
• Mu mzere ndi .sof yanu, fufuzani bokosi la .sof.
• Chongani bokosi mu gawo la Pulogalamu/Sinthani.
• Dinani Yambani

Zindikirani: Mapangidwe awa example amalimbana ndi chipangizo cha Arria 10 GT. Chonde funsani woimira Intel FPGA wanu kuti akufunseni za pulatifomu yoyenera kuyendetsa zinthu zakaleziample

Zambiri Zogwirizana

• Yankho la KDB: Kodi ndimalipiritsa bwanji jitter ya PLL yotayika kapena njira yosadziwika ya wotchi ya Arria 10 PLL?
• Kuphatikizika Kwakukulu kwa Mapangidwe a Hierarchical ndi Team-based Design
• Mapulogalamu a Intel FPGA Devices

Kuyesa 50GbE Hardware Design Example

Mukapanga 50GbE IP core design example ndikuikonza pa chipangizo chanu cha Arria 10 GT, mutha kugwiritsa ntchito System Console kukonza IP core ndi zolembetsa zake za Native PHY IP. Kuti muyatse System Console ndikuyesa kapangidwe ka Hardware example, tsatirani izi:

1. Pambuyo pa mapangidwe a hardware example yakhazikitsidwa pa chipangizo cha Arria 10, mu pulogalamu ya Intel Quartus Prime, pa Zida menyu, dinani Zida Zowonongeka pa System ➤ System Console.
2. Pagawo la Tcl Console, lembani cd hwtest kuti musinthe chikwatuample_dir>/hardware_test_design/hwtest.
3. Lembani source main.tcl kuti mutsegule kulumikiza ku JTAG mbuye.

Mutha kukonza IP pachimake ndi mawonekedwe otsatirawaample commands

• chkphy_status: Imawonetsa ma frequency a wotchi ndi mawonekedwe a PHY loko.
• start_pkt_gen: Imayambitsa jenereta ya paketi.
• stop_pkt_gen: Imayimitsa jenereta ya paketi.
• loop_on: Kuyatsa serial loopback yamkati
• loop_off: Izimitsa serial loopback yamkati.
• reg_werengani : Ikubweza mtengo wa kaundula wa IP pa .
• reg_lemba : Amalemba kupita ku registry ya IP pa adilesi .

Zambiri Zogwirizana

• 50GbE Design Example Registers patsamba 13 Lembani mapu a hardware design example.
• Kusanthula ndi Kuthetsa Mapangidwe ndi System Console

Design Example Kufotokozera

Mapangidwe example akuwonetsa ntchito za 50GbE pachimake ndi mawonekedwe a transceiver ogwirizana ndi IEEE 802.3ba muyezo wa CAUI-4. Mutha kupanga mapangidwe kuchokera ku Example Design tabu mu 50GbE parameter editor. Kupanga kapangidwe exampLero, muyenera kukhazikitsa kaye magawo amitundu yosiyanasiyana ya IP yomwe mukufuna kupanga pomaliza. Kupanga kapangidwe example imapanga kopi ya IP core; testbench ndi hardware design exampndigwiritsa ntchito kusinthaku ngati DUT. Ngati simukuyika ma parameter a DUT kuti agwirizane ndi zomwe zili patsamba lanu, kapangidwe kakaleampzomwe mumapanga sizigwiritsa ntchito kusintha kwa IP komwe mukufuna.

Zindikirani: Testbench ikuwonetsa kuyesa koyambira kwa IP core. Sichikupangidwa kuti chilowe m'malo mwa malo otsimikizira. Muyenera kutsimikiziranso zambiri za kapangidwe kanu ka 50GbE poyerekezera ndi mu hardware.

Zambiri Zogwirizana
Intel Arria® 10 50Gbps Ethernet IP Core User Guide

Design Exampndi Behaviour
Testbench imatumiza magalimoto kupyola IP core, imagwiritsa ntchito mbali yotumizira ndikulandira mbali ya IP core. Mu kapangidwe ka hardware example, mutha kukonza IP pachimake mkati mwa serial loopback mode ndikupanga kuchuluka kwa magalimoto kumbali yotumizira yomwe imabwerera kumbuyo kunjira yolandila.

Design Exampndi Interface Signals
Testbench ya 50GbE ndi yodziyimira yokha ndipo sikutanthauza kuti muyendetse zizindikiro zilizonse zolowetsa.

Table 4. 50GbE Hardware Design Exampndi Interface Signals

Chizindikiro	Mayendedwe	Ndemanga
clk50	Zolowetsa	Kuthamanga pa 50 MHz. Cholinga ndikuyendetsa izi kuchokera pa oscillator ya 50 Mhz pa bolodi.
clk_ref	Zolowetsa	Yendetsani pa 644.53125 MHz.
cpu_resetn	Zolowetsa	Imakhazikitsanso IP core. Yogwira otsika. Imayendetsa kukonzanso kolimba kwapadziko lonse csr_reset_n ku IP core.
anapitiriza…

Malingaliro a kampani Intel Corporation Maumwini onse ndi otetezedwa. Intel, logo ya Intel, ndi zizindikiro zina za Intel ndi zizindikiro za Intel Corporation kapena mabungwe ake. Intel imatsimikizira kugwira ntchito kwa FPGA yake ndi zida za semiconductor malinga ndi zomwe zili pano malinga ndi chitsimikizo cha Intel, koma ili ndi ufulu wosintha zinthu ndi ntchito zilizonse nthawi iliyonse popanda kuzindikira. Intel sakhala ndi udindo kapena udindo chifukwa chakugwiritsa ntchito kapena kugwiritsa ntchito zidziwitso zilizonse, malonda, kapena ntchito zomwe zafotokozedwa pano kupatula monga momwe Intel adavomerezera momveka bwino. Makasitomala a Intel amalangizidwa kuti apeze mtundu waposachedwa kwambiri wamakina a chipangizocho asanadalire zidziwitso zilizonse zosindikizidwa komanso asanayike maoda azinthu kapena ntchito. *Mayina ena ndi mtundu zitha kunenedwa kuti ndi za ena.

Chizindikiro	Mayendedwe	Ndemanga
tx_serial[1:0]	Zotulutsa	Transceiver PHY linanena bungwe deta siriyo.
rx_serial[1:0]	Zolowetsa	Transceiver PHY yolowetsa data.
ogwiritsa_wotsogolera[7:0]	Zotulutsa	Zizindikiro za chikhalidwe. Mapangidwe a hardware example amalumikiza ma bits awa kuti ayendetse ma LED pa bolodi lomwe mukufuna. Mabiti pawokha amawonetsa ma siginali awa ndi machitidwe a wotchi: • [0]: Kusintha kwakukulu chizindikiro ku IP core • [1]: Mtundu wogawika wa clk_ref • [2]: Mtundu wogawidwa wa clk50 • [3]: Mtundu wogawanika wa 100 MHz status wotchi • [4]: ​​tx_lanes_stable • [5]: rx_block_lock • [6]: rx_am_lock • [7]: rx_pcs_ready

Zambiri Zogwirizana
Ma Interfaces ndi Signal Description Amapereka mafotokozedwe atsatanetsatane azizindikiro zapakati za 50GbE IP ndi mawonekedwe omwe ali.

50GbE Design Exampndi Registers

Table 5. 50GbE Hardware Design Exampndi Register Mapu
Imatchula mndandanda wa kaundula wa mapu a ma hardware design example. Mumapeza zolembetsa izi ndi reg_read ndi reg_write ntchito mu System Console.

Mawu Offset	Register Category
0x300–0x5FF	50GbE IP core registry.
0x4000–0x4C00	Arria 10 dynamic reconfiguration registry. Adilesi yoyambira yolembetsa ndi 0x4000 ya Lane 0 ndi 0x4400 ya Lane 1.

Zambiri Zogwirizana

• Kuyesa 50GbE Hardware Design Example patsamba 11 System Console imalamula kuti mupeze ma IP core ndi Native PHY registry.
• Mafotokozedwe a 50GbE Control and Status Registry Amafotokoza 50GbE IP core registry.

Document Revision History

Table 6. 50G Ethernet Design Exampndi Mbiri Yokonzanso Buku Logwiritsa Ntchito

Tsiku	Kumasula	Zosintha
2019.04.03	17.0	Anawonjezera lamulo kuti mugwiritse ntchito zoyeserera za Xcelium.
2017.11.08	17.0	Ulalo wowonjezedwa ku KDB Yankho lomwe limapereka njira yopangira jitter pazida za Intel Arria® 10 chifukwa chakuchulukira kwa ma ATX PLL pakatikati pa IP. Onani ku Kupanga Design Example patsamba 7 ndi Kupanga ndi Kukonza Design Exampndi mu Hardware patsamba 10. Mapangidwe awa example user guide sinasinthidwe kuti iwonetsere Zindikirani: zosintha zazing'ono pamapangidwe a Intel Quartus Prime zimatulutsidwa pambuyo pa Intel Quartus Prime software kutulutsidwa v17.0.
2017.05.08	17.0	Kutulutsidwa koyamba kwa anthu.

Malingaliro a kampani Intel Corporation Maumwini onse ndi otetezedwa. Intel, logo ya Intel, ndi zizindikiro zina za Intel ndi zizindikiro za Intel Corporation kapena mabungwe ake. Intel imatsimikizira kugwira ntchito kwa FPGA yake ndi zida za semiconductor malinga ndi zomwe zili pano malinga ndi chitsimikizo cha Intel, koma ili ndi ufulu wosintha zinthu ndi ntchito zilizonse nthawi iliyonse popanda kuzindikira. Intel sakhala ndi udindo kapena udindo chifukwa cha kugwiritsa ntchito kapena kugwiritsa ntchito zidziwitso zilizonse, malonda, kapena ntchito zomwe zafotokozedwa pano kupatula monga momwe Intel adavomerezera momveka bwino. Makasitomala a Intel amalangizidwa kuti apeze mtundu waposachedwa kwambiri wamakina a chipangizocho asanadalire zidziwitso zilizonse zosindikizidwa komanso asanayike maoda azinthu kapena ntchito. *Mayina ena ndi mtundu zitha kunenedwa kuti ndi za ena.

Zolemba / Zothandizira

Intel 50G Ethernet Design Example [pdf] Buku Logwiritsa Ntchito 50G Ethernet Design Example, 50G, Ethernet Design Exampndi, Design Example

Maumboni

• Buku Logwiritsa Ntchito