Intel 50G Ethernet Design Example
Jagorar Fara Saurin 50GbE
50GbE IP core yana ba da gwajin simulation da ƙirar ƙirar kayan aiki exampwanda ke goyan bayan haɗawa da gwajin kayan aiki. Lokacin da ka samar da zane exampHar ila yau, editan siga yana ƙirƙirar ta atomatik fileya zama dole don kwaikwaya, tarawa, da gwada ƙira a cikin kayan masarufi. Kuna iya zazzage ƙirar kayan masarufi da aka haɗa zuwa na'urar Arria 10 GT.
Lura: Wannan zane example ya kai hari kan na'urar Arria 10 GT kuma yana buƙatar mai karɓar 25G. Da fatan za a tuntuɓi wakilin ku na Intel FPGA don tambaya game da dandalin da ya dace don gudanar da wannan tsohon kayan aikinample. A wasu lokuta ana iya samun lamunin kayan aikin da ya dace. Bugu da kari, Intel yana ba da tarin-kawai exampaikin da za ku iya amfani da shi don kimanta yankin ainihin IP da lokaci da sauri.
Hoto 1. Zane Exampda Amfani
Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka. *Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.
Zane Exampda Tsarin Jagora
Hoto 2. 50GbE Zane Exampda Tsarin Jagora
Tsarin hardware da gwaji files (ƙirar kayan masarufi example) suna cikinample_dir>/hardware_test_design. Simulation files (testbench don kwaikwayo kawai) suna cikinample_dir>/ misaliample_testbench.Kira-kawai ƙira example is located inample_dir>/compilation_test_design.
Tsarin Simulators ExampAbubuwan da aka gyara
Hoto 3. 50GbE Simulations Design Exampda Block zane
Simulation example zane saman-matakin gwajin file shine basic_avl_tb_top.sv Wannan file nan take kuma yana haɗa ATX PLL. Ya ƙunshi ɗawainiya, send_packets_50g_avl, don aikawa da karɓar fakiti 10.
Tebur 1. 50GbE IP Core Testbench File Bayani
| File Suna | Bayani |
| Testbench da Simulation Files | |
| Basic_avl_tb_top.sv | Babban matakin gwajin benci file. Testbench yana ƙaddamar da DUT kuma yana gudanar da ayyukan Verilog HDL don samarwa da karɓar fakiti. |
| Rubutun Testbench | |
| run_vsim.do | Rubutun ModelSim don gudanar da gwajin benci. |
| run_vcs.sh | Rubutun Synopsys VCS don gudanar da gwajin benci. |
| run_ncsim.sh | Rubutun Cadence NCsim don gudanar da testbench. |
| run_xcelium.sh | Rubutun Cadence Xcelium* don gudanar da testbench. |
rdware Design ExampAbubuwan da aka gyara
Hoto 4. 50GbE Hardware Design Example High Level Block zane
50GbE kayan aikin ƙirar example ya ƙunshi abubuwa masu zuwa
- 50GbE IP core.
- Hankalin abokin ciniki wanda ke daidaita shirye-shiryen tushen IP da tsara fakiti.
- ATX PLL don fitar da tashoshin transceiver na'urar.
- IOPLL don samar da agogon 100 MHz daga agogon shigarwar 50 MHz zuwa ƙirar kayan masarufi.ample.
- JTAG mai sarrafawa wanda ke sadarwa tare da Console System. Kuna sadarwa tare da dabarun abokin ciniki ta hanyar Console System.
Tebur 2. 50GbE IP Core Hardware Design Example File Bayani
| File Sunaye | Bayani |
| eth_ex_50g.qpf | Quartus Prime aikin file |
| eth_ex_50g.qsf | Saitunan aikin Quartus file |
| eth_ex_50g.sdc | Ƙuntataccen Ƙira na Synopsys file. Kuna iya kwafa da gyara wannan file don ƙirar 50GbE na ku. |
| ci gaba… | |
Jagorar Fara Saurin 50GbE
| File Sunaye | Bayani |
| eth_ex_50g.v | Babban matakin ƙirar Verilog HDL example file |
| gama gari/ | Hardware zane exampda goyon baya files |
| hwtest/main.tcl | Babban file don samun damar System Console |
Samar da Zane Example
Hoto 5. Tsari
Hoto 6. ExampLe Design Tab a cikin 50GbE Parameter Editan
Bi waɗannan matakan don samar da ƙirar kayan masarufi example da testbench
- Dangane da ko kana amfani da software na Intel Quartus® Prime Pro Edition ko kuma Intel Quartus Prime Standard Edition software, yi ɗaya daga cikin waɗannan ayyuka: A cikin Intel Quartus Prime Pro Edition, danna. File ➤ Sabon Project Wizard don ƙirƙirar sabon aikin Quartus Prime, ko File ➤ Bude Project don buɗe aikin Quartus Prime da ke akwai. Mayen yana tambayarka don saka na'ura. A cikin Intel Quartus Prime Standard Edition software, a cikin IP Catalog (Tools IP Catalog), zaɓi dangin na'urar manufa ta Arria 10.
- A cikin IP Catalog, gano wuri kuma zaɓi 50G Ethernet. Sabuwar taga Bambancin IP yana bayyana.
- Saka sunan babban matakin don bambancin IP ɗin ku kuma danna Ok. Editan siga yana ƙara babban matakin .qsys (a cikin Intel Quartus Prime Standard Edition) ko .ip (a cikin Intel Quartus Prime Pro Edition) file zuwa aikin na yanzu ta atomatik. Idan an sa ka ƙara .qsys ko .ip da hannu file zuwa aikin, danna Project ➤ Ƙara / Cire Files a cikin Project don ƙara da file.
- A cikin software na Intel Quartus Prime Standard Edition, dole ne ka zaɓi takamaiman na'urar Arria 10 a cikin filin Na'ura, ko kiyaye tsohuwar na'urar da Quartus Prime software ke bayarwa.
Lura: Kayan aikin hardware example overwrites zabin da na'urar a kan manufa jirgin. Kuna saka allon manufa daga menu na ƙira exampzažužžukan a cikin Example Design tab (Mataki na 8). - Danna Ok. Editan siga ya bayyana.
- A shafin IP, ƙididdige sigogi don ainihin bambancin IP ɗin ku.
- A kan Example Design tab, don Exampda Design Files, zaɓi zaɓin Simulation don samar da testbench, kuma zaɓi zaɓi na Synthesis don samar da ƙirar ƙirar kayan aiki.ample. Verilog HDL kawai files suna haifarwa.
Lura: Ba a samuwa VHDL IP core mai aiki. Ƙayyade Verilog HDL kawai, don ƙirar ainihin IP ɗin kuample. - Don Hukumar Hardware zaɓi Arria 10 GX Transceiver Signal Integrity Development Kit.
Lura: Tuntuɓi wakilin ku na Intel FPGA don bayani game da dandamalin da ya dace don gudanar da wannan tsohuwar kayan masarufiample. - Danna Generate Example Design button. Zaɓi ExampTagar Zane Directory ya bayyana.
- Idan kuna son gyara ƙirar ƙirar examphanyar shugabanci ko suna daga abubuwan da aka nuna (alt_e50_0_example_design), bincika zuwa sabuwar hanya kuma rubuta sabon ƙira exampsunan directory (ample_dir>).
- Danna Ok.
- Koma zuwa Amsar KDB Ta yaya zan rama jitter na PLL cascading ko marar sadaukar da hanyar agogo don agogon tunani na Arria 10 PLL? don aikin da za a yi amfani da shi a cikin hardware_test_design directory a cikin .sdc file.
Lura: Dole ne ku tuntubi wannan Amsar KDB saboda hanyar RX a cikin 50GbE IP core ya haɗa da PLLs. Don haka, agogon ainihin IP na iya samun ƙarin jitter a cikin na'urorin Arria 10. Wannan Amsar KDB tana fayyace fitar da software wanda a cikinsa ya zama dole.
Bayanai masu alaƙa
Amsa KDB: Ta yaya zan rama jitter na PLL cascading ko marar sadaukarwar agogon agogon Aria 10 PLL?
Simulating da 50GbE Design Exampda Testbench
Hoto 7. Tsari
Bi waɗannan matakan don kwaikwayi gwajin benci
- Canza zuwa kundin jagorar simintin gwajin gwajiample_dir>/ misaliample_testbench.
- Gudanar da rubutun simintin don goyan bayan na'urar kwaikwayo na zaɓinku. Rubutun yana tattarawa kuma yana gudanar da testbench a cikin na'urar kwaikwayo. Koma zuwa teburin "Mataki don Kwaikwayi Testbench".
- Yi nazarin sakamakon. Gwajin gwaji mai nasara yana aika fakiti goma, yana karɓar fakiti goma, kuma yana nuna "Testbench cikakke."
Tebur 3. Matakai don Kwaikwayi Testbench
| Na'urar kwaikwayo | Umarni |
| ModelSim | A cikin layin umarni, rubuta vsim -do run_vsim.do
Idan kun fi son yin kwaikwayo ba tare da kawo ModelSim GUI ba, rubuta vsim -c -do run_vsim.do Lura: ModelSim* - Intel FPGA Edition na'urar kwaikwayo ba shi da ikon yin kwatankwacin wannan ainihin IP. Dole ne ku yi amfani da wani goyan bayan ModelSim na'urar kwaikwayo kamar ModelSim SE. |
| NCsim | A cikin layin umarni, rubuta sh run_ncsim.sh |
| VCS | A cikin layin umarni, rubuta sh run_vcs.sh |
| Xcelium | A cikin layin umarni, rubuta sh run_xcelium.sh |
Gudun gwajin nasara yana nuna fitarwa mai tabbatar da halaye masu zuwa
- Ana jira agogon RX ya daidaita
- Buga halin PHY
- Ana aika fakiti 10
- Ana karɓar fakiti 10
- Nuna "Testbench cikakke."
Mai zuwa sampLe fitarwa yana kwatanta nasarar gwajin simulation
- Ana gudanar da agogon #Ref a 625 MHz don haka ana iya amfani da lambobi duka don duk lokutan agogo.
- #Yawaita rahotannin mitoci da 33/32 don samun ainihin mitocin agogo.
- # Jiran daidaita RX
- #RX deskew a kulle
- An kulle layin #RX
- An kunna #TX
- #**Aika Fakiti 1…
- #**Aika Fakiti 2…
- #**Aika Fakiti 3…
- #**Aika Fakiti 4…
- #**Aika Fakiti 5…
- #**Aika Fakiti 6…
- #**Aika Fakiti 7…
- #**An Karɓi Fakiti 1…
- #**Aika Fakiti 8…
- #**An Karɓi Fakiti 2…
- #**Aika Fakiti 9…
- #**An Karɓi Fakiti 3…
- #**Aika Fakiti 10…
- #**An Karɓi Fakiti 4…
- #**An Karɓi Fakiti 5…
- #**An Karɓi Fakiti 6…
- #**An Karɓi Fakiti 7…
- #**An Karɓi Fakiti 8…
- #**An Karɓi Fakiti 9…
- #**An Karɓi Fakiti 10…
- #**
- #** Testbench ya cika.
- #**
- *********************************
Ƙirƙirar da Ƙaddamar da Zane Exampa cikin Hardware
Don haɗa kayan ƙirar kayan aiki example kuma saita shi akan na'urar Arria 10 GT, bi waɗannan matakan
- Tabbatar da ƙirar hardware example tsara ya cika.
- A cikin Intel Quartus Prime software, buɗe aikin Intel Quartus Primeample_dir>/hardware_test_design/eth_ex_50g.qpf.
- Kafin hadawa, tabbatar da kun aiwatar da yanayin aiki daga Amsar KDB Ta yaya zan rama jitter na cascading PLL ko hanyar agogo mara sadaukar don agogon tunani na Arria 10 PLL? idan ya dace don sakin software naku.
- A cikin menu na sarrafawa, danna Fara Tari.
- Bayan kun ƙirƙiri abin SRAM file .sof, bi waɗannan matakan don tsara kayan ƙirar kayan aikin exampa kan na'urar Arria 10:
- A cikin Tools menu, danna Programmer.
- A cikin Programmer, danna Saitin Hardware.
- Zaɓi na'urar shirye-shirye.
- Zaɓi kuma ƙara allon Arria 10 GT tare da 25G mai ritaya zuwa zaman ku na Intel Quartus Prime.
- Tabbatar cewa an saita Yanayin zuwa JTAG.
- Zaɓi na'urar Arria 10 kuma danna Ƙara Na'ura. Mai Shirya shirye-shirye yana nuna zanen toshewar haɗin kai tsakanin na'urorin da ke kan allo.
- A cikin jere tare da sof ɗinku, duba akwatin don .sof.
- Duba akwatin da ke cikin ginshiƙin Shirin/Sanya.
- Danna Fara
Lura: Wannan zane example hari da na'urar Arria 10 GT. Da fatan za a tuntuɓi wakilin ku na Intel FPGA don tambaya game da dandamali da ya dace don gudanar da wannan tsohon kayan aikinample
Bayanai masu alaƙa
- Amsa KDB: Ta yaya zan rama jitter na PLL cascading ko hanyar agogon da ba a keɓe don agogon tunani na Arria 10 PLL?
- Ƙirƙirar Ƙarfafa don Tsari da Ƙirar Ƙungiya
- Shirye-shiryen na'urorin Intel FPGA
Gwajin 50GbE Hardware Design Example
Bayan kun hada 50GbE IP core design exampsannan ka saita ta akan na'urarka ta Arria 10 GT, zaka iya amfani da System Console don tsara ainihin IP da maƙallan Native PHY IP core rajista. Don kunna System Console da gwada ƙirar kayan masarufi exampko, bi waɗannan matakan:
- Bayan hardware zane example an saita a kan na'urar Arria 10, a cikin Intel Quartus Prime software, akan menu na Kayan aiki, danna Kayan aikin Debugging System ➤ System Console.
- A cikin rukunin Tcl Console, rubuta cd hwtest don canza shugabanci zuwaample_dir>/hardware_test_design/hwtest.
- Buga tushen main.tcl don buɗe haɗi zuwa JTAG maigida.
Kuna iya tsara tushen IP tare da zane mai zuwaampda umarni
- chkphy_status: Yana Nuna mitocin agogo da matsayin kulle PHY.
- start_pkt_gen: Yana fara janareta fakiti.
- stop_pkt_gen: Yana dakatar da janareta na fakiti.
- loop_on: Yana kunna madauki na ciki
- loop_off: Yana kashe madauki na ciki.
- reg_karatu : Yana mayar da ƙimar rajistar ainihin IP a .
- reg_rubutu : ya rubuta zuwa IP core rajista a adireshin .
Bayanai masu alaƙa
- 50GbE Zane ExampYi rijista a shafi na 13 Yi rijistar taswira don ƙirar kayan masarufiample.
- Nazari da Gyara Zane-zane tare da Console System
Zane Example Bayanin
Zane example yana nuna ayyuka na 50GbE core tare da transceiver interface mai dacewa tare da ƙayyadaddun IEEE 802.3ba daidaitaccen CAUI-4. Kuna iya samar da zane daga ExampLe Design tab a cikin editan sigar 50GbE. Don samar da zane exampDon haka, dole ne ka fara saita ƙimar sigina don bambancin ainihin IP ɗin da kake son samarwa a ƙarshen samfurinka. Samar da ƙira example ƙirƙirar kwafin tushen IP; da testbench da hardware design exampYi amfani da wannan bambancin azaman DUT. Idan baku saita ma'auni don DUT don dacewa da ma'auni a cikin samfurin ƙarshenku ba, ƙirar ƙirar.ampda ka ƙirƙira baya motsa jiki da IP core bambancin da kuke nufi.
Lura: Testbench yana nuna gwajin asali na ainihin IP. Ba a nufin ya zama madadin cikakken yanayin tabbatarwa ba. Dole ne ku yi ƙarin tabbaci na ƙirar 50GbE na ku a cikin siminti da a cikin kayan aiki.
Bayanai masu alaƙa
Intel Arria® 10 50Gbps Ethernet IP Core User Guide
Zane Exampda Halaye
The testbench aika zirga-zirga ta hanyar IP core, motsa jiki da watsa gefe da karɓar gefen IP core. A cikin kayan aikin hardware exampHar ila yau, za ku iya tsara ainihin IP a cikin yanayin madauki na ciki da kuma samar da zirga-zirga a gefen watsawa wanda ke dawowa ta hanyar karɓa.
Zane Exampda Alamar Interface
50GbE testbench yana ƙunshe da kansa kuma baya buƙatar ku fitar da kowane siginar shigarwa.
Tebur 4. 50GbE Hardware Design Exampda Alamar Interface
| Sigina | Hanyar | Sharhi |
|
klk50 |
Shigarwa |
Tuba a 50 MHz. Manufar ita ce fitar da wannan daga oscillator 50Mhz a kan allo. |
| clk_ref | Shigarwa | Tuba a 644.53125 MHz. |
|
cpu_sake saitin |
Shigarwa |
Yana sake saita ainihin IP. Ƙananan aiki. Yana fitar da sake saiti mai wuya na duniya csr_reset_n zuwa ainihin IP. |
| ci gaba… | ||
Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka. *Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.
| Sigina | Hanyar | Sharhi |
| tx_serial[1:0] | Fitowa | Serial bayanan fitarwa na Transceiver PHY. |
| rx_serial[1:0] | Shigarwa | Serial bayanan shigar da Transceiver PHY. |
|
mai amfani_led[7:0] |
Fitowa |
Alamun matsayi. Tsarin kayan masarufi exampLe ya haɗa waɗannan ragowa don fitar da LEDs akan allon da aka yi niyya. Rago ɗaya ɗaya yana nuna ƙimar sigina masu zuwa da halayen agogo:
• [0]: Babban siginar sake saiti zuwa ainihin IP • [1]: Rarraba sigar clk_ref • [2]: Rarraba sigar clk50 • [3]: Rarraba nau'in agogon matsayi na 100 MHz • [4]: tx_lanes_stable • [5]: rx_block_lock • [6]: rx_am_lock • [7]: rx_pcs_ready |
Bayanai masu alaƙa
Hanyoyin sadarwa da Bayanin Siginar Yana ba da cikakkun bayanai na siginar siginar IP na 50GbE da mu'amalar da suke ciki.
50GbE Zane Exampda Rajista
Tebur 5. 50GbE Hardware Design Exampda Rajista taswira
Ya lissafa jeri na rijistar taswirar žwažwalwar ajiya don ƙirar kayan masarufiample. Kuna samun damar waɗannan rajistar tare da ayyukan reg_read da reg_write a cikin Tsarin Console.
| Kashe Magana | Yi rijista Category |
| 0x300-0x5FF | 50GbE IP core rajista. |
| 0x4000–0x4C00 | Arria 10 Rajista na sake fasalin tsauri. Adireshin tushe na rajista shine 0x4000 don Lane 0 da 0x4400 don Lane 1. |
Bayanai masu alaƙa
- Gwajin 50GbE Hardware Design ExampLe a shafi na 11 Tsarin Console yana ba da umarni don samun dama ga ainihin IP da rijistar PHY na asali.
- 50GbE Sarrafa da Bayanin Rijista Matsayi Yana Siffanta ainihin rijistar 50GbE IP.
Tarihin Bita daftarin aiki
Tebur 6. 50G Ethernet Design ExampTarihin Bita Jagoran Mai Amfani
| Kwanan wata | Saki | Canje-canje |
| 2019.04.03 | 17.0 | Ƙara umarni don gudanar da simintin Xcelium. |
|
2017.11.08 |
17.0 |
Ƙara hanyar haɗi zuwa Amsar KDB wanda ke ba da mafita don yuwuwar jitter akan na'urorin Intel Arria® 10 saboda cascading ATX PLLs a cikin ainihin IP.
Koma zuwa Samar da Zane Example a shafi na 7 da Hadawa da Saita Zane Exampa cikin Hardware shafi na 10. Wannan zane exampba a sabunta jagorar mai amfani don yin tunani ba Lura: ƙananan canje-canje a cikin tsara ƙira a cikin Intel Quartus Prime fitowa daga baya fiye da sakin software na Intel Quartus Prime v17.0. |
| 2017.05.08 | 17.0 | Farkon sakin jama'a. |
Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka. *Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.
Takardu / Albarkatu
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Intel 50G Ethernet Design Example [pdf] Jagorar mai amfani 50G Ethernet Design Example, 50G, Ethernet Design Example, Design Example |
