intel 50G Ethernet Design Example

Ntuziaka mmalite ngwa ngwa 50GbE

50GbE IP isi na-enye testbench simulation na ngwaike imewe example nke na-akwado mkpokọta na nyocha ngwaike. Mgbe ị na-emepụta imewe example, paramita nchịkọta akụkọ na-akpaghị aka na-emepụta filedị mkpa iji megharịa, chịkọta, na nwalee imewe na ngwaike. Ị nwere ike budata nhazi ngwaike achịkọtara na ngwaọrụ Arria 10 GT.

Mara: Nke a imewe examplekwasịrị anya na ngwaọrụ Arria 10 GT ma chọọ onye ezumike nka 25G. Biko kpọtụrụ onye nnọchi anya Intel FPGA gị ka ị jụọ maka ikpo okwu dabara adaba iji mee ngwaike aample. N'ọnọdụ ụfọdụ, mbinye nke ngwaike kwesịrị ekwesị nwere ike ịdị. Na mgbakwunye, Intel na-enye mkpokọta-naanị example oru ngo nke ị nwere ike iji mee atụmatụ ngwa ngwa IP isi mpaghara na oge.

Ọgụgụ 1. Imepụta Example ojiji

Ụlọ ọrụ Intel. Ikike niile echekwabara. Intel, akara Intel, na akara Intel ndị ọzọ bụ ụghalaahịa nke Intel Corporation ma ọ bụ ndị enyemaka ya. Intel nyere ikike ịrụ ọrụ nke FPGA na ngwaahịa semiconductor na nkọwapụta ugbu a dịka akwụkwọ ikike ọkọlọtọ Intel siri dị, mana nwere ikike ịme mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Intel anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Intel kwetara na ederede. A dụrụ ndị ahịa Intel ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ. * Enwere ike ịzọrọ aha na akara ndị ọzọ dị ka ihe onwunwe nke ndị ọzọ.

Imepụta Exampn'akwụkwọ ndekọ aha Structure

Ọgụgụ 2. 50GbE Kere Exampn'akwụkwọ ndekọ aha Structure

Nhazi ngwaike na ule files (ihe nhazi ngwaike example) dị naample_dir>/hardware_test_design. The ịme anwansị files (testbench maka ịme anwansị naanị) dị naample_dir>/ example_testbench.Nchịkọta-naanị imewe example dị naample_dir>/compilation_test_design.

Imepụta ihe ngosi Exampna akụrụngwa

Ọgụgụ 3. 50GbE Simulation Design Example Block eserese

Simulation example imewe elu-larịị ule file bụ basic_avl_tb_top.sv Nke a file na-ewepụta ma jikọọ ATX PLL. Ọ gụnyere ọrụ, send_packets_50g_avl, izipu na ịnata ngwugwu 10.

Tebụl 1. 50GbE IP Core Testbench File Nkọwa

File Aha	Nkọwa
Testbench na Simulation Files
basic_avl_tb_top.sv	testbench dị elu file. Testbench na-ewepụta DUT ma na-arụ ọrụ Verilog HDL iji mepụta na ịnakwere ngwugwu.
Ederede Testbench
run_vsim.do	Ederede ModelSim ka ọ na-agba testbench.
ọsọ_vcs.sh	Edemede Synopsys VCS iji mee testbench.
run_ncsim.sh	Edemede Cadence NCsim iji mee testbench.
run_xcelium.sh	Edemede Cadence Xcelium* iji mee testbench.

rdware Design Exampna akụrụngwa

Ọgụgụ 4. 50GbE Akụrụngwa Kere Example Elu Ọkwa Block Eserese

Ihe nhazi ngwaike 50GbE example gụnyere ihe ndị a

• 50GbE IP isi.
• Echiche ndị ahịa nke na-ahazi mmemme nke isi IP na ọgbọ ngwugwu.
• ATX PLL iji chụba ọwa transceiver ngwaọrụ.
• IOPLL iji wepụta elekere 100 MHz site na elekere ntinye 50 MHz na nhazi ngwaike ex.ample.
• JTAG njikwa na-ekwurịta okwu na Sistemu Console. Ị na-ekwurịta okwu na mgbagha onye ahịa site na Sistemu Console.

Tebụl 2. 50GbE IP Core Hardware Design Example File Nkọwa

File Aha	Nkọwa
eth_ex_50g.qpf	Quartus Prime oru ngo file
eth_ex_50g.qsf	Ntọala ọrụ Quartus file
eth_ex_50g.sdc	Synopsys imewe mmachi file. Ị nwere ike idetuo ma gbanwee nke a file maka imewe 50GbE nke gị.
gara n'ihu…

Ntuziaka mmalite ngwa ngwa 50GbE

File Aha	Nkọwa
eth_ex_50g.v	Verilog HDL imewe nke kachasị eluample file
nkịtị/	Nhazi ngwaike example nkwado files
hwtest/main.tcl	Isi file maka ịnweta Sistemu Console

Na-emepụta ihe osise Example

Ọgụgụ 5. Usoro

Nyocha 6. ỌpụampMepụta Tab na 50GbE Parameter Editor

Soro usoro ndị a ka ịmepụta ngwaike imewe example na testbench

1. Dabere ma ị na-eji sọftụwia Intel Quartus® Prime Pro Edition ma ọ bụ sọftụwia Intel Quartus Prime Standard Edition, mee otu n'ime omume ndị a: Na Intel Quartus Prime Pro Edition, pịa. File ➤ Ọkachamara Project ọhụrụ iji mepụta ọrụ Quartus Prime ọhụrụ, ma ọ bụ File ➤ Mepee Project ka imepe ọrụ Quartus Prime dị. Ọkachamara na-akpali gị ezipụta ngwaọrụ. N'ime sọftụwia Intel Quartus Prime Standard Edition, na katalọgụ IP (Ngwaọrụ IP katalọgụ), họrọ ezinụlọ ngwaọrụ ebumnuche Arria 10.
2. Na katalọgụ IP, chọta ma họrọ 50G Ethernet. Window mgbanwe IP ọhụrụ na-egosi.
3. Ezipụta aha ọkwa dị elu maka ụdị IP gị wee pịa OK. Onye nchịkọta akụkọ paramita na-agbakwụnye .qsys dị elu (na Intel Quartus Prime Standard Edition) ma ọ bụ .ip (na Intel Quartus Prime Pro Edition) file na oru ngo nke ugbu a na-akpaghị aka. Ọ bụrụ na a kpaliri gị iji aka tinye .qsys ma ọ bụ .ip file na oru ngo, pịa Project ➤ Tinye/Wepụ Files na Project ịgbakwunye ihe file.
4. N'ime sọftụwia Intel Quartus Prime Standard Edition, ị ga-ahọrọrịrị ngwaọrụ Arria 10 n'ọhịa ngwaọrụ, ma ọ bụ debe ngwaọrụ ndabara nke Quartus Prime ngwanro tụpụtara.
   Mara: Nhazi ngwaike example overwrites nhọrọ na ngwaọrụ na iche osisi. Ị na-akọwapụta bọọdụ ebumnuche site na menu nke imewe exampnhọrọ na Example Design tab (Nzọụkwụ 8).
5. Pịa OK. Ihe ndezi paramita na-egosi.
6. Na taabụ IP, ezipụta paramita maka mgbanwe isi IP gị.
7. Na Example Kere tab, maka Example Design Files, họrọ nhọrọ Simulation iji mepụta testbench, wee họrọ nhọrọ Synthesis iji mepụta ngwaike imewe ex.ample. Naanị Verilog HDL files na-emepụta.
   Mara: Isi VHDL IP na-arụ ọrụ adịghị. Ezipụta Verilog HDL naanị, maka nhazi IP isi gị example.
8. Maka Board Hardware họrọ Arria 10 GX Transceiver Signal Integrity Development Kit.
   Mara: Kpọtụrụ onye nnọchi anya Intel FPGA maka ozi gbasara ikpo okwu dabara adaba iji rụọ ngwa ngwa a bụbuample.
9. Pịa n'ịwa Example Design bọtịnụ. Họrọ Example Imepụta windo ndekọ na-egosi.
10. Ọ bụrụ na-ịchọrọ ị gbanwee imewe exampụzọ ndekọ aha ma ọ bụ aha sitere na ndabara egosiri (alt_e50_0_example_design), chọgharịa n'ụzọ ọhụrụ wee pịnye ihe ọhụrụ ahụ exampaha ndekọ aha (ample_dir>).
11. Pịa OK.
12. Rụtụ aka na Azịza KDB Kedu ka m ga-esi kwụọ ụgwọ maka jitter nke PLL cascading ma ọ bụ ụzọ elekere anaghị arara onwe ya maka elekere Aria 10 PLL? maka ebe a na-arụ ọrụ ị ga-etinye na akwụkwọ ndekọ hardware_test_design na .sdc file.

Mara: Ị ga-enyocha azịza KDB a n'ihi na ụzọ RX dị na 50GbE IP core gụnyere PLLs cascaded. Ya mere, clocks isi IP nwere ike nweta ihe jitter ọzọ na ngwaọrụ Arria 10. Azịza KDB a na-akọwapụta mwepụta sọftụwia nke ebe a na-arụ ọrụ dị mkpa.

Ozi metụtara
Azịza KDB: Kedu ka m ga-esi kwụọ ụgwọ maka jitter nke PLL cascading ma ọ bụ ụzọ elekere na-abụghị nke raara onwe ya nye maka elekere Aria 10 PLL?

Ịmepụta 50GbE Design Exampna Testbench

Ọgụgụ 7. Usoro

Soro usoro ndị a ka ịmee testbench

1. Gbanwee na ndekọ ndekọ simulation testbenchample_dir>/ example_testbench.
2. Gbaa script simulation maka simulator akwadoro nke nhọrọ gị. Edemede ahụ na-achịkọta ma na-agba testbench na simulator. Rụtụ aka na tebụl "Nzọụkwụ iji simulate the Testbench".
3. Nyochaa nsonaazụ ya. Testbench na-aga nke ọma na-eziga ngwugwu iri, nata ngwugwu iri, ma gosipụta "Testbench zuru ezu."

Tebụl 3. Nzọụkwụ iji mee ka Testbench

Simulator	Ntuziaka
ModelSim	N'ahịrị iwu, pịnye vsim -do run_vsim.do Ọ bụrụ na-amasị gị ịme simulate na-ebuliteghị ModelSim GUI, pịnye vsim -c -do run_vsim.do Mara: ModelSim* – Intel FPGA Edition simulator enweghị ikike ịme emume nke isi IP a. Ị ga-ejiri simulator ModelSim ọzọ akwadoro dị ka ModelSim SE.
NCSim	N'ahịrị iwu, pịnye sh run_ncsim.sh
VCS	N'ahịrị iwu, pịnye sh run_vcs.sh
Xcelium	N'ahịrị iwu, pịnye sh run_xcelium.sh

Nnwale na-aga nke ọma na-egosipụta mmepụta na-akwado omume ndị a

1. Na-eche ka elekere RX dozie
2. Ọkwa PHY na-ebi akwụkwọ
3. Na-eziga ngwugwu 10
4. Ịnata ngwugwu 10
5. Na-egosi "Testbench zuru ezu."

Ndị na-esonụ sample mmepụta na-egosi ọsọ ule ịme anwansị na-aga nke ọma

• A na-agba ọsọ elekere #Ref na 625 MHz ka enwere ike iji ọnụọgụ niile maka oge elekere niile.
• # Tinyegharịa ugboro ugboro site na 33/32 iji nweta ugboro ugboro n'ezie.
• # Na-eche nhazi RX
• #RX deskew akpọchiri
• # Akpọchiri n'usoro ụzọ RX
• #TX agbanyere
• #** Na-eziga ngwugwu 1…
• #** Na-eziga ngwugwu 2…
• #** Na-eziga ngwugwu 3…
• #** Na-eziga ngwugwu 4…
• #** Na-eziga ngwugwu 5…
• #** Na-eziga ngwugwu 6…
• #** Na-eziga ngwugwu 7…
• #** Ngwungwu 1 enwetara…
• #** Na-eziga ngwugwu 8…
• #** Ngwungwu 2 enwetara…
• #** Na-eziga ngwugwu 9…
• #** Ngwungwu 3 enwetara…
• #** Na-eziga ngwugwu 10…
• #** Ngwungwu 4 enwetara…
• #** Ngwungwu 5 enwetara…
• #** Ngwungwu 6 enwetara…
• #** Ngwungwu 7 enwetara…
• #** Ngwungwu 8 enwetara…
• #** Ngwungwu 9 enwetara…
• #** Ngwungwu 10 enwetara…
• #**
• #** Testbench zuru ezu.
• #**
• *****************************

Ịchịkọta na Hazie Nhazi Exampna Hardware

Iji chịkọta nhazi ngwaike example ma hazie ya na ngwaọrụ Arria 10 GT gị, soro usoro ndị a

1. Gbaa mbọ hụ na imepụta ngwaike example ọgbọ agwụla.
2. Na ngwa Intel Quartus Prime, mepee ọrụ Intel Quartus Primeample_dir>/hardware_test_design/eth_ex_50g.qpf.
3. Tupu achịkọta, hụ na i mejuputala workaround si na KDB Azịza Kedu ka m ga-esi kwụọ ụgwọ maka jitter nke PLL cascading ma ọ bụ na-abụghị raara onwe ya nye elekere elekere maka Arria 10 PLL? ọ bụrụ na ọ dị mkpa maka mwepụta ngwanrọ gị.
4. Na nhazi menu, pịa Malite Nchịkọta.
5. Mgbe ịmepụtara ihe SRAM file .sof, soro usoro ndị a iji hazie ngwaike imewe example na ngwaọrụ Arria 10:

• Na Ngwaọrụ menu, pịa Programmer.
• Na Programmer, pịa Hardware Mbido.
• Họrọ ngwaọrụ mmemme.
• Họrọ ma tinye bọọdụ Arria 10 GT nwere 25G retimer na nnọkọ Intel Quartus Prime gị.
• Gbaa mbọ hụ na edobere ọnọdụ na JTAG.
• Họrọ Arria 10 ngwaọrụ wee pịa Tinye Ngwaọrụ. Onye mmemme na-egosiputa eserese mgbochi nke njikọ dị n'etiti ngwaọrụ dị na bọọdụ gị.
• N'ahịrị na .sof gị, lelee igbe maka .sof.
• Lelee igbe dị na kọlụm Mmemme/Hazie.
• Pịa Malite

Mara: Nke a imewe example lekwasịrị anya na ngwaọrụ Arria 10 GT. Biko kpọtụrụ onye nnọchi anya Intel FPGA gị ka ị jụọ maka ikpo okwu dabara adaba iji mee ngwaike aample

Ozi metụtara

• Azịza KDB: Kedu ka m ga-esi kwụọ ụgwọ maka jitter nke PLL cascading ma ọ bụ ụzọ elekere anaghị ewepụta maka elekere Arria 10 PLL?
• Mgbakwunye Mgbakwunye maka Nhazi usoro na otu dabere
• Ngwa ngwa Intel FPGA na-eme mmemme

Na-anwale 50GbE Hardware Design Example

Mgbe ị chịkọtara 50GbE IP core design exampma hazie ya na ngwaọrụ Arria 10 GT gị, ị nwere ike iji Sistemu Console iji hazie IP core yana ndebanye aha Native PHY IP agbakwunyere ya. Ka ịgbanwuo Console Sistemu wee nwalee nhazi ngwaike example, soro usoro ndị a:

1. Mgbe ngwaike imewe example na-ahazi na Arria 10 ngwaọrụ, na Intel Quartus Prime software, na Tools menu, pịa System Debugging Tools ➤ System Console.
2. Na pane Tcl Console, pịnye cd hwtest iji gbanwee ndekọ ka ọ bụrụample_dir>/hardware_test_design/hwtest.
3. Pịnye isi iyi main.tcl ka imepe njikọ na JTAG nna ukwu.

Ị nwere ike hazie IP core na ndị a imewe example iwu

• chkphy_status: Na-egosiputa ugboro elekere yana ọkwa mkpọchi PHY.
• start_pkt_gen: Na-amalite generator nke ngwugwu.
• stop_pkt_gen: Kwụsị generator nke ngwugwu.
• loop_on: Na-agbanye n'ime serial loopback
• loop_off: Gbanyụọ loopback nke ime.
• reg_agụ : Weghachite uru ndekọ aha IP isi na .
• reg_write : Na-ede gaa na ndekọ isi IP na adreesị .

Ozi metụtara

• 50GbE imewe Example Ndị debanyere aha na ibe 13 Debanye aha maapụ maka imepụta ngwaike example.
• Iji Sistemụ Console nyochaa na imegharị atụmatụ

Imepụta Example Nkọwa

Imewe example na-egosipụta ọrụ nke 50GbE isi na transceiver interface kwekọrọ na IEEE 802.3ba ọkọlọtọ CAUI-4 nkọwa. Ị nwere ike ịmepụta imewe site na Example Kere taabụ na 50GbE paramita nchịkọta akụkọ. Iji mepụta imewe exampYa mere, ị ga-ebu ụzọ tọọ ụkpụrụ paramita maka mgbanwe isi IP nke ịchọrọ ịmepụta na ngwaahịa njedebe gị. Na-emepụta imewe example emepụta oyiri nke IP isi; the testbench and hardware design exampwere mgbanwe a dị ka DUT. Ọ bụrụ na ịtọghị ụkpụrụ paramita maka DUT ka ọ dakọba na ụkpụrụ paramita dị na ngwaahịa njedebe gị, imewe ex.ampka ị na-emepụta adịghị egosipụta IP isi mgbanwe ị bu n'obi.

Mara: Testbench na-egosiputa ule bụ isi nke isi IP. Ebubeghi ya ka ọ bụrụ nnọchi maka gburugburu nkwenye zuru oke. Ị ga-emerịrị nkwenye sara mbara nke imewe 50GbE nke gị na simulation na ngwaike.

Ozi metụtara
Intel Arria® 10 50Gbps Ethernet IP isi ntuziaka onye ọrụ

Imepụta Example Omume
The testbench na-eziga okporo ụzọ site na IP isi, na-emega ahụ n'akụkụ na-enweta akụkụ nke IP isi. Na ngwaike imewe exampYa mere, ị nwere ike mmemme nke IP isi na esịtidem serial loopback mode na n'ịwa okporo ụzọ na-ebufe n'akụkụ na loops azụ site na-anata n'akụkụ.

Imepụta Exampna akara ngosi interface
Testbench 50GbE nwere onwe ya na ọ chọghị ka ị kwọọ akara ntinye ọ bụla.

Tebụl 4. 50GbE Akụrụngwa Kere Exampna akara ngosi interface

Signal	Ntuziaka	Okwu
klk50	Ntinye	Ụgbọ ala na 50 MHz. Ebumnuche bụ ịchụpụ nke a site na oscillator 50Mhz na bọọdụ.
clk_ref	Ntinye	Ụgbọ ala na 644.53125 MHz.
cpu_resetn	Ntinye	Na-atọgharịa isi IP. Na-arụ ọrụ dị ala. Na-ebugharị nrụpụta ike zuru ụwa ọnụ csr_reset_n na isi IP.
gara n'ihu…

Ụlọ ọrụ Intel. Ikike niile echekwabara. Intel, akara Intel, na akara Intel ndị ọzọ bụ ụghalaahịa nke Intel Corporation ma ọ bụ ndị enyemaka ya. Intel nyere ikike ịrụ ọrụ nke FPGA na ngwaahịa semiconductor na nkọwapụta ugbu a dịka akwụkwọ ikike ọkọlọtọ Intel siri dị, mana nwere ikike ịme mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Intel anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Intel kwetara na ederede. A dụrụ ndị ahịa Intel ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ. * Enwere ike ịzọrọ aha na akara ndị ọzọ dị ka ihe onwunwe nke ndị ọzọ.

Signal	Ntuziaka	Okwu
tx_usoro [1:0]	Mpụta	Oghere Usoro mmepụta PHY transceiver.
rx_serial [1:0]	Ntinye	Ntinye data nsonye transceiver PHY.
onye ọrụ_led[7:0]	Mpụta	Ọkwa ọkwa. Nhazi ngwaike example ejikọta ndị a ibe n'ibe ka ụgbọala LEDs na lekwasịrị osisi. Bits n'otu n'otu na-egosipụta ụkpụrụ mgbama na omume elekere: • [0]: Mgbama nrụpụta isi na isi IP • [1]: Ụdị nke clk_ref • [2]: Ụdị nke clk50 kewara • [3]: Ụdị nkewa nke 100 MHz ọkwa elekere • [4]: ​​tx_lanes_stable • [5]: rx_block_lock • [6]: rx_am_lock • [7]: rx_pcs_ready

Ozi metụtara
Ntugharị na nkọwa akara ngosi na-enye nkọwa zuru ezu nke akara isi 50GbE IP na oghere nke ha nwere.

50GbE imewe Exampna Ndebanye aha

Tebụl 5. 50GbE Akụrụngwa Kere Exampna Deba aha Map
Na-edepụta aha ndekọ aha mapụtara ebe nchekwa maka nhazi ngwaike example. Ị na-eji ọrụ reg_read na reg_write nweta ndekọ ndị a na Sistemu Console.

Mwepu okwu	Deba aha otu
0x300-0x5FF	50GbE IP isi ndekọ.
0x4000–0x4C00	Aria 10 dynamic reconfiguration ndekọ. Adreesị ntọala ndebanye aha bụ 0x4000 maka Lane 0 yana 0x4400 maka Lane 1.

Ozi metụtara

• Na-anwale 50GbE Hardware Design Exampna ibe 11 Sistemụ njikwa na-enye iwu ka ịnweta ndekọ IP core na Native PHY.
• 50GbE njikwa na ọkwa ndekọ nkọwa nkọwa nke 50GbE IP isi ndekọ.

Akụkọ ngbanwe akwụkwọ

Tebụl 6. 50G Ethernet Design ExampAkụkọ Nduzi Nduzi

Ụbọchị	Hapụ	Mgbanwe
2019.04.03	17.0	Agbakwunyere iwu iji mee ihe ngosi Xcelium.
2017.11.08	17.0	Agbakwunyere njikọ na Azịza KDB nke na-enye mgbanaka maka ike jitter na ngwaọrụ Intel Arria® 10 n'ihi ịkwanye ATX PLL na isi IP. Tụtụ aka na Na-emepụta ihe osise Example na ibe 7 na Ịchịkọta na Na-ahazi Design Exampna Hardware na ibe 10. Nke a imewe exampemelitebeghị ntuziaka onye ọrụ iji tụgharịa uche Mara: obere mgbanwe na ọgbọ imewe na Intel Quartus Prime ewepụtara ma emechaa karịa ntọhapụ sọftụwia Intel Quartus Prime v17.0.
2017.05.08	17.0	Ntọhapụ ọha mbụ.

Ụlọ ọrụ Intel. Ikike niile echekwabara. Intel, akara Intel, na akara Intel ndị ọzọ bụ ụghalaahịa nke Intel Corporation ma ọ bụ ndị enyemaka ya. Intel nyere ikike ịrụ ọrụ nke FPGA na ngwaahịa semiconductor na nkọwapụta ugbu a dịka akwụkwọ ikike ọkọlọtọ Intel siri dị, mana nwere ikike ịme mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Intel anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Intel kwetara na ederede. A dụrụ ndị ahịa Intel ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ. * Enwere ike ịzọrọ aha na akara ndị ọzọ dị ka ihe onwunwe nke ndị ọzọ.

Akwụkwọ / akụrụngwa

intel 50G Ethernet Design Example [pdf] Ntuziaka onye ọrụ 50G Ethernet Design Example, 50G, Ethernet Design Example, Imepụta Example

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