intel 50G Ethernet Design Example

50GbE Ta'iala Amata vave

O le 50GbE IP autu e maua ai se suʻega faʻataʻitaʻiga ma se faʻataʻitaʻiga meafaigaluegaampe lagolagoina le tu'ufa'atasiga ma su'ega meafaigaluega. A e gaosia le mamanu example, e otometi lava ona fatuina e le faatonu parameter le files e manaʻomia e faʻataʻitaʻi, faʻapipiʻi, ma suʻe le mamanu i meafaigaluega. E mafai ona e siiina le mamanu faʻapipiʻi meafaigaluega i se masini Arria 10 GT.

Fa'aaliga: O lenei mamanu exampLe faʻamoemoeina le Arria 10 GT masini ma manaʻomia se 25G retimer. Fa'amolemole fa'afeso'ota'i lou sui o le Intel FPGA e su'esu'e e uiga i se fa'avae e talafeagai e fa'agaioi ai lenei meafaigaluega fa'amuaample. I nisi tulaga e mafai ona maua se nonogatupe o meafaigaluega talafeagai. E le gata i lea, ua saunia e Intel se tuʻufaʻatasiga-naʻo example poloketi e mafai ona e faʻaogaina e faʻatatau vave ai le vaega autu o le IP ma le taimi.

Ata 1. Fuafuaga Example Fa'aaogaina

Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie fa'aalia i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel e maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua. *O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.

Design Example Fa'atonuga Fa'atonu

Ata 2. 50GbE Design Example Fa'atonuga Fa'atonu

Le faʻatulagaina o meafaigaluega ma suʻega files (le mamanu meafaigaluega example) o loʻo i totonuample_dir>/hardware_test_design. Le fa'ata'ita'iga files (testbench mo na o faʻataʻitaʻiga) o loʻo i totonuample_dir>/ example_testbench.O le tuufaatasia-na'o le mamanu example o loʻo i totonuample_dir>/compilation_test_design.

Fuafuaga Fa'ata'ita'iga Example Vaega

Ata 3. 50GbE Simulation Design Example Ata poloka

O le fa'ata'ita'iga example mamanu su'ega pito i luga file o le basic_avl_tb_top.sv Lenei file vave ma fa'afeso'ota'i se ATX PLL. E aofia ai se galuega, send_packets_50g_avl, e lafo ma maua 10 pepa.

Laulau 1. 50GbE IP Core Testbench File Fa'amatalaga

File Igoa	Fa'amatalaga
Testbench ma Simulation Files
basic_avl_tb_top.sv	Tulaga maualuga su'ega file. O le su'ega su'esu'e e fa'atino le DUT ma fa'atino galuega a le Verilog HDL e fa'atupu ma talia fa'aputu.
Testbench Scripts
run_vsim.do	O le ModelSim script e faʻatautaia le suʻega suʻega.
run_vcs.sh	Le Synopsys VCS script e faʻatautaia le suʻega suʻega.
run_ncsim.sh	Le Cadence NCSim script e faʻatautaia le suʻega suʻega.
run_xcelium.sh	Le Cadence Xcelium * tusitusiga e faʻatautaia le suʻega suʻega.

rdware Design Example Vaega

Ata 4. 50GbE Hardware Design Example High Level Block Diagram

Le 50GbE meafaigaluega mamanu example aofia ai vaega nei

• 50GbE IP autu.
• Fa'amatalaga a le aufaipisinisi e fa'amaopoopoina le polokalame o le IP ma le fa'atupuina o pusa.
• ATX PLL e faʻauluina le masini transceiver auala.
• IOPLL e fa'atupuina se uati 100 MHz mai se uati fa'aoga 50 MHz i le fa'ailoga meafaigaluegaample.
• JTAG pule e feso'ota'i ma le System Console. E te fa'afeso'ota'i ma le tagata o tausia e ala i le System Console.

Laulau 2. 50GbE IP Core Hardware Design Example File Fa'amatalaga

File Igoa	Fa'amatalaga
eth_ex_50g.qpf	Poloketi Quartus Prime file
eth_ex_50g.qsf	Fa'atonuga o galuega faatino a Quartus file
eth_ex_50g.sdc	Synopsys Design Constraints file. E mafai ona e kopiina ma suia lenei mea file mo lau lava mamanu 50GbE.
faaauau…

50GbE Ta'iala Amata vave

File Igoa	Fa'amatalaga
eth_ex_50g.v	Tulaga maualuga Verilog HDL mamanu example file
masani/	Fuafuaga meafaigaluega example lagolago files
hwtest/main.tcl	Autu file mo le mauaina o le System Console

Fausiaina o le Design Example

Ata 5. Taualumaga

Ata 6. Esample Design Tab i le 50GbE Parameter Editor

Mulimuli i laasaga nei e fa'atupuina ai le fa'atulagaina o meafaigaluega e iaiample ma le laulau su'esu'e

1. Fa'alagolago pe o lo'o e fa'aogaina le Intel Quartus® Prime Pro Edition software po'o le Intel Quartus Prime Standard Edition software, fai se tasi o gaioiga nei: I le Intel Quartus Prime Pro Edition, kiliki. File ➤ New Project Wizard e fatu ai se poloketi fou a Quartus Prime, poʻo File ➤ Tatala Poloketi e tatala ai se poloketi Quartus Prime. E fa'atonu oe e le wizard e fa'ailoa se masini. I le Intel Quartus Prime Standard Edition software, i le IP Catalog (Tools IP Catalog), filifili le Arria 10 fa'atatau i le aiga masini.
2. I le IP Catalog, suʻe ma filifili 50G Ethernet. Ua aliali mai le fa'amalama New IP Variation.
3. Fa'ailoa se igoa pito i luga mo lau fesuiaiga IP ma kiliki le OK. E fa'aopoopo e le fa'atonu fa'amaufa'ailoga le .qsys pito i luga (i le Intel Quartus Prime Standard Edition) po'o le .ip (i le Intel Quartus Prime Pro Edition) file i le galuega o lo'o i ai nei otometi. Afai e fa'amalosia oe e fa'aopoopo ma le lima le .qsys po'o le .ip file i le poloketi, kiliki Project ➤ Add/Remove Files i Poloketi e fa'aopoopo le file.
4. I le polokalama Intel Quartus Prime Standard Edition, e tatau ona e filifilia se masini faapitoa Arria 10 i le fanua Device, pe taofi le masini le lelei o loʻo faʻatulagaina e le Quartus Prime software.
   Fa'aaliga: Le mamanu meafaigaluega example overwrites le filifiliga ma le masini i luga o le laupapa sini. E te faʻamaoti le laupapa faʻamoemoe mai le lisi o mamanu example filifiliga i le Example Design tab (Laasaga 8).
5. Kiliki OK. E aliali mai le fa'atonu fa'amaufa'ailoga.
6. I luga o le IP tab, faʻamaonia le faʻasologa mo lau fesuiaiga autu IP.
7. I le Example Design tab, mo Example Lisiina Files, filifili le filifiliga Fa'ata'ita'iga e fa'atupu ai le su'ega, ma filifili le filifiliga Fa'aopoopo e fa'atupuina ai le fa'asologa o meafaigaluegaample. Na'o Verilog HDL files ua gaosia.
   Fa'aaliga: E le'o maua se VHDL IP core. Fa'ailoa na'o Verilog HDL, mo lau fa'asologa autu o le IPample.
8. Mo le Komiti Fa'atonu, filifili le Arria 10 GX Transceiver Signal Integrity Development Kit.
   Fa'aaliga: Fa'afeso'ota'i lou sui Intel FPGA mo fa'amatalaga e uiga i se fa'avae e talafeagai e fa'agaioi ai lenei meafaigaluega fa'atasiample.
9. Kiliki le Generate Example fa'amau Fa'ailoga. Le Filifili Example fa'amalama o le Design Directory e aliali mai.
10. Afai e te mana'o e sui le mamanu example ala fa'atonu po'o le igoa mai fa'aletonu ua fa'aalia (alt_e50_0_example_design), suʻesuʻe i le ala fou ma faʻaoga le mamanu fou example igoa fa'atonu (ample_dir>).
11. Kiliki OK.
12. Va'ai ile KDB Tali E fa'afefea ona ou taui atu mo le fa'alili ole PLL fa'asolo po'o le ala ole uati fa'apitoa mo Arria 10 PLL fa'asino uati? mo se fofo e tatau ona e talosaga i le hardware_test_design directory i le .sdc file.

Fa'aaliga: E tatau ona e fa'afeso'ota'i lenei Tali KDB ona o le ala RX i le 50GbE IP autu e aofia ai PLL fa'asolo. O le mea lea, o le IP autu uati e mafai ona oʻo i isi faʻalavelave i Arria 10 masini. O lenei KDB Tali o loʻo faʻamalamalamaina ai faʻasalalauga polokalama e manaʻomia ai le fofo.

Fa'amatalaga Fa'atatau
KDB Tali: E fa'afefea ona ou totogia le fa'aoso o le PLL cascading po'o le ala fa'apitoa mo le uati fa'asino Arria 10 PLL?

Fa'ata'ita'iina o le 50GbE Design Example Testbench

Ata 7. Taualumaga

Mulimuli i laasaga nei e faʻatusa ai le suʻega suʻega

1. Suia i le su'ega fa'ata'ita'iga fa'atonugaample_dir>/ example_testbench.
2. Fa'asolo le fa'asologa fa'ata'ita'iga mo le simulator lagolago o lau filifiliga. O le tusitusiga e tuufaatasia ma faʻatautaia le suʻega suʻega i le simulator. Va'ai i le laulau "Laasaga e fa'ata'ita'i ai le Testbench".
3. Iloilo i'uga. O le suʻega suʻesuʻe manuia e auina atu le sefulu pepa, mauaina le sefulu pepa, ma faʻaalia le "Testbench maeʻa."

Laulau 3. Laasaga e Fa'ata'ita'i ai le Testbench

Simulator	Faatonuga
ModelSim	I le laina o le poloaiga, fa'aoga vsim -do run_vsim.do Afai e te manaʻo e faʻataʻitaʻi e aunoa ma le aumaia o le ModelSim GUI, faʻaoga vsim -c -do run_vsim.do Fa'aaliga: Ole ModelSim* - Intel FPGA Edition simulator e leai se malosi e faʻataʻitaʻiina ai lenei IP autu. E tatau ona e faʻaogaina se isi faʻataʻitaʻiga ModelSim lagolago pei ole ModelSim SE.
NCSim	I le laina faʻatonu, faʻaoga sh run_ncsim.sh
VCS	I le laina faʻatonu, faʻaoga sh run_vcs.sh
Xcelium	I le laina faʻatonu, faʻaoga sh run_xcelium.sh

O le su'ega manuia o lo'o fa'aalia le gaioiga e fa'amaonia ai amioga nei

1. Fa'atali mo le uati RX e fa'amautu
2. Lolomiina tulaga PHY
3. Tuuina atu 10 pepa
4. Mauaina 10 pepa
5. Fa'aali atu le “Testbench complete.”

O sample fa'aaliga fa'aalia se su'ega fa'atusa manuia

• #Ref uati e tamo'e ile 625 MHz ina ia mafai ona fa'aoga numera atoa mo taimi uma uati.
• # Fa'atele fa'asalalau fa'asalalau i le 33/32 e maua ai fa'asolo tonu o le uati.
• #Faatalitali mo le RX alignment
• #RX kesi loka loka
• #RX laina laina loka loka
• #TX ua mafai
• #**Auina atu le Paketi 1…
• #**Auina atu le Paketi 2…
• #**Auina atu le Paketi 3…
• #**Auina atu le Paketi 4…
• #**Auina atu le Paketi 5…
• #**Auina atu le Paketi 6…
• #**Auina atu le Paketi 7…
• #**Maua le Pepa 1…
• #**Auina atu le Paketi 8…
• #**Maua le Pepa 2…
• #**Auina atu le Paketi 9…
• #**Maua le Pepa 3…
• #**Auina atu le Paketi 10…
• #**Maua le Pepa 4…
• #**Maua le Pepa 5…
• #**Maua le Pepa 6…
• #**Maua le Pepa 7…
• #**Maua le Pepa 8…
• #**Maua le Pepa 9…
• #**Maua le Pepa 10…
• #**
• #** Ua mae'a le laulau su'esu'e.
• #**
• #****************************************

Tu'ufa'atasia ma Fa'atulaga le Fa'ata'ita'iga Example i Meafaigaluega

Ina ia tuufaatasia le mamanu meafaigaluega exampma faʻapipiʻi i luga o lau masini Arria 10 GT, mulimuli i laasaga nei

1. Fa'amautinoa le fa'atulagaina o meafaigaluega e iaiampua maea le tupulaga.
2. I le polokalama Intel Quartus Prime, tatala le poloketi Intel Quartus Primeample_dir>/hardware_test_design/eth_ex_50g.qpf.
3. A'o le'i tu'ufa'atasia, fa'amautinoa ua e fa'atinoina le fa'aogaina mai le KDB Tali E fa'apefea ona ou totogia le fa'alavelave o le PLL cascading po'o le le tu'uina atu o le ala uati mo Arria 10 PLL fa'asino uati? pe a talafeagai mo lau fa'amatu'u polokalame.
4. I luga o le Processing menu, kiliki Amata Compilation.
5. A uma ona e fatuina se mea SRAM file .sof, mulimuli i laasaga nei e faʻapolokalame le mamanu meafaigaluega exampi luga ole Arria 10 masini:

• I luga o le Meafaigaluega lisi, kiliki Programmer.
• I le Polokalama, kiliki Hardware Setup.
• Filifili se masini polokalame.
• Filifili ma faʻaopopo le Arria 10 GT laupapa ma le 25G retimer i lau Intel Quartus Prime sauniga.
• Ia mautinoa ua setiina le Faiga i le JTAG.
• Filifili le Arria 10 masini ma kiliki Add Device. E fa'aalia e le Polokalama se poloka poloka o feso'ota'iga i le va o masini i luga o lau laupapa.
• I le laina ma lau .sof, siaki le pusa mo le .sof.
• Siaki le pusa i le koluma Polokalama/Configure.
• Kiliki Amata

Fa'aaliga: O lenei mamanu example taula'i le Arria 10 GT masini. Fa'amolemole fa'afeso'ota'i lou sui o le Intel FPGA e su'esu'e e uiga i se fa'avae e talafeagai e fa'agaioi ai lenei meafaigaluega fa'amuaample

Fa'amatalaga Fa'atatau

• Tali KDB: E fa'afefea ona ou totogia le fa'alavelave o le PLL cascading po'o le ala uati le fa'apitoa mo Arria 10 PLL fa'asino uati?
• Tu'ufa'atasiga Fa'aopoopo mo Fuafuaga Fa'atonu ma Fa'avae Au
• Polokalama Intel FPGA Devices

Su'ega ole 50GbE Hardware Design Example

A uma ona e tuufaatasia le 50GbE IP core design exampma fa'apipi'i i lau masini Arria 10 GT, e mafai ona e fa'aogaina le System Console e fa'apolokalame ai le IP core ma ana fa'amaufa'ailoga a le Native PHY IP. Ia ki le System Console ma fa'ata'ita'i le mamanu o meafaigaluega fa'aample, mulimuli i laasaga nei:

1. Ina ua uma le mamanu meafaigaluega exampua fa'atulagaina i le Arria 10 masini, i le Intel Quartus Prime software, i luga o le Meafaigaluega lisi, kiliki System Debugging Tools ➤ System Console.
2. I le Tcl Console pane, lolomi le cd hwtest e sui ai le lisi iample_dir>/hardware_test_design/hwtest.
3. Tu'i puna main.tcl e tatala ai se feso'ota'iga i le JTAG matai.

E mafai ona e fa'apolokalameina le IP i le fa'ata'ita'iga leaample poloaiga

• chkphy_status: Fa'aali alaleo o le uati ma le tulaga loka PHY.
• start_pkt_gen: Faʻamataina le faʻapipiʻi pusa.
• stop_pkt_gen: Taofi le gaosiga o pusa.
• loop_on: Fa'aola i totonu fa'asologa fa'asologa loopback
• loop_off: Tape le laina i totonu loopback.
• reg_read : Fa'afo'i le tau o le resitala autu o le IP i .
• reg_tusi : Tusia i le resitala autu IP ile tuatusi .

Fa'amatalaga Fa'atatau

• 50GbE Design Example Resitala i le itulau 13 Resitala faafanua mo meafaigaluega mamanu example.
• Iloiloga ma Debugging Designs ma System Console

Design Example Faʻamatalaga

Le mamanu example faʻaalia galuega a le 50GbE faʻatasi ma le faʻaogaina o fesoʻotaʻiga e ogatasi ma le IEEE 802.3ba faʻataʻitaʻiga CAUI-4. E mafai ona e fatuina le mamanu mai le Example Design tab i le 50GbE fa'atonu fa'atonu. Le fa'atupuina o le mamanu exampO lea, e tatau ona e setiina le tau fa'atatau mo le suiga autu o le IP e te mana'o e fa'atupu i lau oloa fa'ai'uga. Fausia le mamanu example faia o se kopi o le IP autu; le su'esu'ega ma meafaigaluega fa'ata'ita'igaampfa'aaoga lenei suiga e pei o le DUT. Afai e te le setiina le fa'asologa o tau mo le DUT e fetaui ma le tau fa'amau i lau oloa fa'ai'uga, o le mamanu exampLe e fa'atupuina e le fa'aaogaina le suiga autu IP e te mana'o ai.

Fa'aaliga: O loʻo faʻaalia e le testbench se suʻega faʻavae o le IP autu. E le o fa'amoemoe e suitulaga i se siosiomaga fa'amaonia atoatoa. E tatau ona e faia ni fa'amaoniga sili atu o lau lava mamanu 50GbE ile fa'ata'ita'iga ma meafaigaluega.

Fa'amatalaga Fa'atatau
Intel Arria® 10 50Gbps Ethernet IP Autu Tagata Taiala

Design Example Amio
O le testbench e tuʻuina atu fefaʻatauaiga e ala i le IP core, faʻaogaina le itu faʻasalalau ma maua le itu o le IP core. I le mamanu meafaigaluega example, e mafai ona e fa'apolokalameina le IP autu i totonu o le fa'asologa fa'asolosolo fa'asolo i totonu ma fa'atupuina feoaiga i luga o le itu fa'asalalau lea e fa'asolo i tua i le itu e maua.

Design Example Fa'ailoga Fa'amatalaga
O le 50GbE testbench e na'o ia lava ma e le mana'omia oe e ave so'o se fa'ailoga fa'aoga.

Fuafuaga 4. 50GbE Hardware Design Example Fa'ailoga Fa'amatalaga

Fa'ailoga	Fa'atonuga	Fa'amatalaga
clk50	Ulufale	Aveta i le 50 MHz. O le fa'amoemoe o le ave lea o lenei mea mai le 50 Mhz oscillator i luga o le laupapa.
clk_ref	Ulufale	Ave taavale ile 644.53125 MHz.
cpu_resetn	Ulufale	Toe setiina le IP autu. Malosi maualalo. Fa'aola le csr_reset_n toe fa'aola le lalolagi i le IP autu.
faaauau…

Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie fa'aalia i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel e maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua. *O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.

Fa'ailoga	Fa'atonuga	Fa'amatalaga
tx_serial[1:0]	Tuuina atu	Transceiver PHY fa'amaumauga fa'asologa.
rx_serial[1:0]	Ulufale	Transceiver PHY fa'aofi fa'amaumauga fa'asologa.
ta'ita'i_tagata[7:0]	Tuuina atu	Faailoga tulaga. Le mamanu meafaigaluega example faʻafesoʻotaʻi nei fasi e faʻaulu ai LED i luga o le laupapa sini. Fa'ailoga ta'ito'atasi e atagia ai fa'ailoga fa'ailoga ma le amio uati: • [0]: Faailoga autu toe setiina ile IP autu • [1]: Vaevae vaega o clk_ref • [2]: Vaevae vaega o le clk50 • [3]: Vaevae vaega o le 100 MHz tulaga uati • [4]: ​​tx_lanes_stable • [5]: rx_block_lock • [6]: rx_am_lock • [7]: rx_pcs_ready

Fa'amatalaga Fa'atatau
Feso'ota'iga ma Fa'amatalaga Fa'ailoga Tuuina atu fa'amatalaga au'ili'ili ole 50GbE IP fa'ailoga autu ma feso'ota'iga o lo'o iai.

50GbE Design Example Resitala

Fuafuaga 5. 50GbE Hardware Design Example Resitala Faafanua
Lisi le lisi lisi fa'afanua fa'amaufa'ailoga mo le fa'ata'ita'iga o meafaigaluega e iaiample. E te mauaina nei tusi resitala i galuega reg_read ma reg_write i le System Console.

Upu Offset	Resitala Vaega
0x300–0x5FF	50GbE IP autu resitala.
0x4000–0x4C00	Arria 10 dynamic reconfiguration registers. O le tuatusi autu o le resitala o le 0x4000 mo le Lane 0 ma le 0x4400 mo le Lane 1.

Fa'amatalaga Fa'atatau

• Su'ega ole 50GbE Hardware Design Exampi le itulau 11 System Console e fa'atonuina le avanoa i le IP core ma le Native PHY registers.
• 50GbE Pulea ma Tulaga Tusi Resitala Fa'amatalaga Fa'amatala le 50GbE IP autu resitala.

Talafaasolopito Toe Iloiloga o Pepa

Laulau 6. 50G Ethernet Design Example User Guide Toe Iloilo Talafaasolopito

Aso	Fa'asa'oloto	Suiga
2019.04.03	17.0	Faʻaopoopo le faʻatonuga e faʻatautaia ai faʻataʻitaʻiga Xcelium.
2017.11.08	17.0	Fa'aopoopo le feso'ota'iga i le KDB Tali e maua ai le fofo mo le fa'alavelave fa'afuase'i i masini Intel Arria® 10 ona o le fa'auluina o ATX PLLs i le IP core. Fa'asino i Fausiaina o le Design Example i le itulau 7 ma Tuufaatasia ma Fa'atulagaina o le Design Example i Meafaigaluega i le itulau 10. O lenei mamanu exampe le'i fa'afouina le ta'iala fa'aoga e atagia ai Fa'aaliga: suiga laiti i le fausiaina o mamanu i le Intel Quartus Prime fa'amalolo mulimuli ane nai lo le Intel Quartus Prime fa'amatu'u polokalama v17.0.
2017.05.08	17.0	Fa'asalalauga muamua.

Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua. *O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.

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intel 50G Ethernet Design Example [pdf] Taiala mo Tagata Fa'aoga 50G Ethernet Design Example, 50G, Ethernet Design Example, Design Example

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