Intel 50G Ethernet Design Example
Tataiso ea ho Qala ka 50GbE
The 50GbE IP core e fana ka teko ea ho etsisa le mohlala oa moralo oa hardwareample e tšehetsang ho bokella le ho hlahloba hardware. Ha o hlahisa moqapi example, mohlophisi oa parameter o iketsetsa faele ea files bohlokoa ho etsisa, ho bokella, le ho leka moralo ho hardware. U ka khoasolla moralo o hlophisitsoeng oa lisebelisoa ho sesebelisoa sa Arria 10 GT.
Hlokomela: Moqapi ona exampe shebile sesebelisoa sa Arria 10 GT mme e hloka 25G retimer. Ka kopo ikopanye le moemeli oa hau oa Intel FPGA ho botsa ka sethala se loketseng ho tsamaisa thepa ena ea example. Maemong a mang, kalimo ea thepa e loketseng e ka ba teng. Ho feta moo, Intel e fana ka ex compilation-feelaample projeke eo u ka e sebelisang ho hakanya kapele sebaka sa mantlha sa IP le nako.
Setšoantšo sa 1. Moqapi Example Tšebeliso
Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.
Moqapi Example Sebopeho sa Directory
Setšoantšo sa 2. 50GbE Design Example Sebopeho sa Directory
Sebopeho sa hardware le teko files (moralo oa hardware example) li fumaneha hoample_dir>/hardware_test_design. Ketsiso files (testbench bakeng sa ketsiso feela) li tengample_dir>/ example_testbench.Moetso oa ho bokella feela example e tengample_dir>/compilation_test_design.
Moqapi oa Ketsiso Example Likarolo
Setšoantšo sa 3. 50GbE Simulation Design Example Block Diagram
Ketsiso example moralo oa teko ea boemo bo holimo file is basic_avl_tb_top.sv Sena file e tiisa le ho hokela ATX PLL. E kenyelletsa mosebetsi, send_packets_50g_avl, ho romella le ho amohela lipakete tse 10.
Letlapa la 1. 50GbE IP Core Testbench File Litlhaloso
| File Lebitso | Tlhaloso |
| Testbench le Simulation Files | |
| basic_avl_tb_top.sv | Testbench ea boemo bo holimo file. Testbench e tiisa DUT mme e tsamaisa mesebetsi ea Verilog HDL ho hlahisa le ho amohela lipakete. |
| Litemana tsa Testbench | |
| run_vsim.do | Sengoloa sa ModelSim ho tsamaisa testbench. |
| run_vcs.sh | Mongolo oa Synopsys VCS ho tsamaisa testbench. |
| run_ncsim.sh | Sengoloa sa Cadence NCSim ho tsamaisa testbench. |
| run_xcelium.sh | Sengoloa sa Cadence Xcelium* ho tsamaisa testbench. |
rdware Design Example Likarolo
Setšoantšo sa 4. 50GbE Hardware Design Example High Level Block Diagram
Moralo oa lisebelisoa tsa 50GbE example kenyeletsa likarolo tse latelang
- 50GbE IP ea mantlha.
- Monahano oa bareki o hokahanyang mananeo a mantlha a IP le tlhahiso ea lipakete.
- ATX PLL ho khanna likanale tsa transceiver tsa sesebelisoa.
- IOPLL ho hlahisa oache ea 100 MHz ho tloha ho 50 MHz ho ea ho sebopeho sa lisebelisoa tsa khale.ample.
- JTAG molaoli ea buisanang le System Console. U buisana le logic ea bareki ka System Console.
Letlapa la 2. 50GbE IP Core Hardware Design Example File Litlhaloso
| File Mabitso | Tlhaloso |
| eth_ex_50g.qpf | Morero oa mantlha oa Quartus file |
| eth_ex_50g.qsf | Litlhophiso tsa projeke ea Quartus file |
| eth_ex_50g.sdc | Litšitiso tsa Moqapi oa Synopsys file. U ka kopitsa le ho fetola sena file bakeng sa moralo oa hau oa 50GbE. |
| e tsoela pele… | |
Tataiso ea ho Qala ka 50GbE
| File Mabitso | Tlhaloso |
| eth_ex_50g.v | Moralo oa maemo a holimo oa Verilog HDL example file |
| tloaelehileng/ | Moetso oa li-hardware example tšehetso files |
| hwtest/main.tcl | Ka sehloohong file bakeng sa ho fihlella System Console |
Ho Hlahisa Moqapi Example
Setšoantšo sa 5. Mokhoa
Setšoantšo sa 6. Example Design Tab ho 50GbE Parameter Editor
Latela mehato ena ho hlahisa sebopeho sa hardware example le testbench
- Ho ipapisitse le hore na u sebelisa software ea Intel Quartus® Prime Pro Edition kapa software ea Intel Quartus Prime Standard Edition, etsa e 'ngoe ea liketso tse latelang: Khatisong ea Intel Quartus Prime Pro, tobetsa. File ➤ Project Wizard e Ncha ho theha projeke e ncha ea Quartus Prime, kapa File ➤ Open Project ho bula morero o teng oa Quartus Prime. Wizate e o kopa hore o hlalose sesebediswa. Ho software ea Intel Quartus Prime Standard Edition, ho IP Catalog (Tools IP Catalog), khetha lelapa la sesebelisoa sa Arria 10.
- Ho IP Catalog, fumana 'me u khethe 50G Ethernet. Ho hlaha fensetere e ncha ea IP Variation.
- Hlalosa lebitso la boemo bo holimo bakeng sa phapano ea hau ea IP ebe o tobetsa OK. Mohlophisi oa paramethara o eketsa boemo bo holimo .qsys (ho Intel Quartus Prime Standard Edition) kapa .ip (ho Intel Quartus Prime Pro Edition) file ho morero oa hajoale ka bo eona. Haeba o kopuwa ho kenya .qsys kapa .ip ka bowena file ho morero, tobetsa Morero ➤ Eketsa/Tlosa Files ho Morero ho eketsa file.
- Ho software ea Intel Quartus Prime Standard Edition, o tlameha ho khetha sesebelisoa se itseng sa Arria 10 tšimong ea Sesebelisoa, kapa u boloke sesebelisoa sa kamehla se hlahisoang ke Quartus Prime.
Hlokomela: Moetso oa hardware example overwrites kgetho le sesebediswa ka shebiloeng boto. U hlakisa boto e shebiloeng ho tsoa ho menu ea moralo oa example dikgetho ho Example Design tab (Mohato oa 8). - Tobetsa OK. Mohlophisi oa parameter oa hlaha.
- Ho tab ea IP, hlakisa li-parameter tsa IP ea hau ea mantlha.
- Ho Example Design tab, bakeng sa Example Design Files, khetha Simulation kgetho ho hlahisa testbench, 'me khetha Synthesis kgetho ho hlahisa hardware moralo ex.ample. Ke Verilog HDL feela files li hlahisoa.
Hlokomela: Sesebelisoa se sebetsang sa VHDL IP ha se fumanehe. Hlalosa Verilog HDL feela, bakeng sa moralo oa hau oa mantlha oa IPample. - Bakeng sa Hardware Board khetha Arria 10 GX Transceiver Signal Integrity Development Kit.
Hlokomela: Ikopanye le moemeli oa hau oa Intel FPGA bakeng sa tlhahisoleseling mabapi le sethala se loketseng ho tsamaisa thepa ena ea khaleample. - Tobetsa Hlahisa Example konopo ea Design. Khetha Exampho hlaha fensetere ea Design Directory.
- Haeba u lakatsa ho fetola moralo examptsela ea directory kapa lebitso ho tsoa ho li-defaults tse bontšitsoeng (alt_e50_0_example_design), sheba tsela e ncha ebe u thaepa sebopeho se secha sa examplebitso la directory (ample_dir>).
- Tobetsa OK.
- Sheba Karabo ea KDB Nka buseletsa joang jitter ea PLL cascading kapa tsela e sa inehelang ea oache ea Arria 10 PLL? bakeng sa ho sebetsa u lokela ho etsa kopo bukeng ea hardware_test_design ho .sdc file.
Hlokomela: U tlameha ho sheba Karabo ena ea KDB hobane tsela ea RX e ho 50GbE IP mantlha e kenyelletsa li-PLL tse senyehileng. Ka hona, lioache tsa mantlha tsa IP li ka ba le jitter e eketsehileng lisebelisoa tsa Arria 10. Karabo ena ea KDB e hlakisa lits'ebetso tsa software tseo ho tsona mosebetsi o hlokahalang.
Lintlha Tse Amanang
Karabo ea KDB: Ke buseletsa joang bakeng sa jitter ea PLL cascading kapa tsela e sa inehelang ea oache bakeng sa oache ea boits'oaro ea Arria 10 PLL?
Ho etsisa 50GbE Design Example Testbench
Setšoantšo sa 7. Mokhoa
Latela mehato ena ho etsisa testbench
- Fetolela bukeng ea simulation ea testbenchample_dir>/ example_testbench.
- Matha sengoloa sa ketsiso bakeng sa simulator e tšehelitsoeng eo u e khethileng. Script e bokella le ho tsamaisa testbench ho simulator. Sheba tafoleng "Mehato ea ho etsisa Testbench".
- Sekaseka liphello. Testbench e atlehileng e romella lipakete tse leshome, e amohela lipakete tse leshome, 'me e bonts'a "Testbench e felile."
Letlapa la 3. Mehato ea ho etsisa Testbench
| Moetsisi | Litaelo |
| ModelSim | Moleng oa taelo, thaepa vsim -do run_vsim.do
Haeba u khetha ho etsisa ntle le ho hlahisa ModelSim GUI, thaepa vsim -c -do run_vsim.do Hlokomela: ModelSim * - Intel FPGA Edition simulator ha e na bokhoni ba ho etsisa mantlha ena ea IP. U tlameha ho sebelisa simulator e 'ngoe e tšehelitsoeng ea ModelSim joalo ka ModelSim SE. |
| NCSim | Moleng oa taelo, thaepa sh run_ncsim.sh |
| VCS | Moleng oa taelo, thaepa sh run_vcs.sh |
| Xcelium | Moleng oa taelo, thaepa sh run_xcelium.sh |
Tlhahlobo e atlehileng ea teko e bonts'a tlhahiso e tiisang boitšoaro bo latelang
- E emetse hore oache ea RX e lule
- Ho hatisa boemo ba PHY
- Ho romela lipakete tse 10
- Ho amohela lipakete tse 10
- E hlahisa "Testbench e felile."
Tse latelang sample sephetho se bonts'a tlhahlobo e atlehileng ea ketsiso
- Oache ea #Ref e tsamaisoa ho 625 MHz kahoo linomoro tse felletseng li ka sebelisoa linakong tsohle tsa oache.
- #Multiply e tlalehile maqhubu ka 33/32 ho fumana maqhubu a oache a nnete.
- #E emetse ho lokisoa ha RX
- #RX deskew e notletsoe
- #RX lane lane e notletsoe
- #TX e lumelletsoe
- #**Ho romella Pakete ea 1…
- #**Ho romella Pakete ea 2…
- #**Ho romella Pakete ea 3…
- #**Ho romella Pakete ea 4…
- #**Ho romella Pakete ea 5…
- #**Ho romella Pakete ea 6…
- #**Ho romella Pakete ea 7…
- #**E amohetse Pakete ea 1…
- #**Ho romella Pakete ea 8…
- #**E amohetse Pakete ea 2…
- #**Ho romella Pakete ea 9…
- #**E amohetse Pakete ea 3…
- #**Ho romella Pakete ea 10…
- #**E amohetse Pakete ea 4…
- #**E amohetse Pakete ea 5…
- #**E amohetse Pakete ea 6…
- #**E amohetse Pakete ea 7…
- #**E amohetse Pakete ea 8…
- #**E amohetse Pakete ea 9…
- #**E amohetse Pakete ea 10…
- #**
- #** Testbench e phethiloe.
- #**
- ****************************************
Ho Kopanya le ho Hlophisa Moralo Example ho Hardware
Ho bokella moralo oa hardware example 'me u e hlophise sesebelisoa sa hau sa Arria 10 GT, latela mehato ena
- Netefatsa moralo oa hardware example moloko o felile.
- Ho software ea Intel Quartus Prime, bula morero oa Intel Quartus Primeample_dir>/hardware_test_design/eth_ex_50g.qpf.
- Pele o hlophisa, etsa bonnete ba hore o kentse tšebetsong mokhoa oa ho sebetsa ho tsoa ho Karabo ea KDB Nka buseletsa joang jitter ea PLL cascading kapa tsela e sa inehelang ea oache bakeng sa oache ea referense ea Arria 10 PLL? haeba e bohlokoa bakeng sa tokollo ea software ea hau.
- Ho menu ea Processing, tobetsa Start Compilation.
- Ka mor'a hore u hlahise ntho ea SRAM file .sof, latela mehato ena ho hlophisa moralo oa hardware example sesebelisoa sa Arria 10:
- Ho Tools menu, tobetsa Programmer.
- Ho "Programmer", tobetsa "Hardware Setup".
- Khetha sesebelisoa sa ho etsa mananeo.
- Khetha 'me u kenye boto ea Arria 10 GT e nang le 25G retimer ho Intel Quartus Prime session.
- Netefatsa hore Mode e setetsoe ho JTAG.
- Khetha sesebelisoa sa Arria 10 ebe o tobetsa Add sesebelisoa. Lenaneo le bonts'a setšoantšo sa li-block tsa likhokahano lipakeng tsa lisebelisoa tse botong ea hau.
- Moleng le .sof ea hau, hlahloba lebokose la .sof.
- Tshwaya lebokoso mo kholomong ya Lenaneo/Configure.
- Tobetsa Qala
Hlokomela: Moqapi ona exampe shebile sesebelisoa sa Arria 10 GT. Ka kopo ikopanye le moemeli oa hau oa Intel FPGA ho botsa ka sethala se loketseng ho tsamaisa thepa ena ea example
Lintlha Tse Amanang
- Karabo ea KDB: Ke buseletsa joang bakeng sa jitter ea PLL cascading kapa tsela e sa tsitsang ea oache bakeng sa oache ea boits'oaro ea Arria 10 PLL?
- Kopano e Eketsehileng bakeng sa Moralo oa Hierarchical le oa Sehlopha
- Lisebelisoa tsa lisebelisoa tsa Intel FPGA
Ho leka 50GbE Hardware Design Example
Kamora ho bokella 50GbE IP core design exampLe 'me u e hlophise sesebelisoa sa hau sa Arria 10 GT, u ka sebelisa System Console ho hlophisa motheo oa IP le lirejistara tsa eona tsa mantlha tsa Native PHY IP. Ho bulela System Console le ho leka moralo oa hardware example, latela mehato ena:
- Ka mor'a moralo oa hardware example e hlophisitsoe ho sesebelisoa sa Arria 10, ho software ea Intel Quartus Prime, ho Tools menu, tobetsa Lisebelisoa tsa Tsamaiso ea Ts'ebetso ➤ System Console.
- Fensetereng ea Tcl Console, thaepa cd hwtest ho fetolela directory hoample_dir>/hardware_test_design/hwtest.
- Tlanya source main.tcl ho bula khokahanyo ho JTAG monghadi.
U ka etsa lenaneo la mantlha la IP ka mohlala o latelang oa moraloample ditaelo
- chkphy_status: E bonts'a maqhubu a oache le boemo ba senotlolo sa PHY.
- start_pkt_gen: E qala jenereithara ea pakete.
- stop_pkt_gen: E emisa jenereithara ea pakete.
- loop_on: E bulela serial loopback e ka hare
- loop_off: E tima loopback ea ka hare ea serial.
- reg_bala : E khutlisa boleng ba rejisete ea mantlha ea IP ho .
- reg_ngola : oa ngola ho aterese ea mantlha ea IP atereseng .
Lintlha Tse Amanang
- 50GbE Design Example Registers leqepheng la 13 Ngoliso ea 'mapa bakeng sa moralo oa hardware example.
- Ho sekaseka le ho lokisa meralo ka System Console
Moqapi Example Tlhaloso
Moqapi example e bonts'a mesebetsi ea mantlha ea 50GbE e nang le sebopeho sa transceiver se lumellanang le IEEE 802.3ba e tloaelehileng ea CAUI-4. O ka hlahisa moralo ho tsoa ho Example Design tab ho mohlophisi oa parameter ea 50GbE. Ho hlahisa moralo exampLeha ho le joalo, u tlameha ho qala ka ho beha litekanyetso tsa paramethara bakeng sa phapano ea mantlha ea IP eo u ikemiselitseng ho e hlahisa sehlahisoa sa hau sa ho qetela. Ho hlahisa mohlala oa moraloampe etsa kopi ea mantlha ea IP; testbench le hardware design exampke sebelisa phapano ena joalo ka DUT. Haeba o sa behe boleng ba paramethara bakeng sa DUT ho tsamaisana le boleng ba paramethara sehlahiswang sa hao sa ho qetela, moralo wa ex.ampSeo u se hlahisang ha se sebelise phapang ea mantlha ea IP eo u e rerileng.
Hlokomela: Testbench e bonts'a teko ea motheo ea IP core. Ha e reretsoe ho nka sebaka sa tikoloho e felletseng ea netefatso. U tlameha ho etsa netefatso e batsi ea moralo oa hau oa 50GbE ka papiso le lisebelisoa tsa thepa.
Lintlha Tse Amanang
Intel Arria® 10 50Gbps Ethernet IP Core User Guide
Moqapi Example Boitšoaro
Testbench e romela sephethephethe ka IP core, ho sebelisa lehlakore la phetisetso le ho amohela lehlakore la IP core. Moqapi oa lisebelisoa tsa thepa example, o ka hlophisa mantlha ea IP ka har'a mokhoa oa ka hare oa serial loopback mme o hlahise sephethephethe lehlakoreng la phetisetso le khutlelang ka lehlakoreng le amohelang.
Moqapi Example Lipontšo tsa Interface
Testbench ea 50GbE e ikemetse 'me ha e hloke hore u khanne matšoao leha e le afe a ho kenya.
Letlapa la 4. 50GbE Hardware Design Example Lipontšo tsa Interface
| Letshwao | Tataiso | Maikutlo |
|
clk50 |
Kenyeletso |
Khanna ka lebelo la 50 MHz. Sepheo ke ho khanna sena ho tloha ho oscillator ea 50 Mhz ka boto. |
| clk_ref | Kenyeletso | Khanna ho 644.53125 MHz. |
|
cpu_resetn |
Kenyeletso |
E tsosolosa motheo oa IP. E sebetsa tlase. E tsamaisa csr_reset_n ea lefats'e ka bophara ho ea ho IP core. |
| e tsoela pele… | ||
Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba beha litaelo tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.
| Letshwao | Tataiso | Maikutlo |
| tx_serial[1:0] | Sephetho | Lintlha tsa seriale tsa Transceiver PHY. |
| rx_serial[1:0] | Kenyeletso | Transceiver PHY e kenya data ea seriale. |
|
mosebelisi [7:0] |
Sephetho |
Matšoao a boemo. Moetso oa hardware example e hokahanya likotoana tsena ho khanna li-LED holim'a boto e shebiloeng. Li-bits ka bomong li bonts'a boleng ba matšoao a latelang le boitšoaro ba oache:
• [0]: Letšoao la ho qala bocha ho IP core • [1]: Mofuta o arohaneng oa clk_ref • [2]: Mofuta o arohaneng oa clk50 • [3]: Mofuta o arohaneng oa 100 MHz boemo oache • [4]: tx_lanes_stable • [5]: rx_block_lock • [6]: rx_am_lock • [7]: rx_pcs_ready |
Lintlha Tse Amanang
Li-interfaces le Litlhaloso tsa Lipontšo E fana ka litlhaloso tse qaqileng tsa matšoao a mantlha a 50GbE IP le li-interfaces tseo e leng tsa tsona.
50GbE Design Example Registers
Letlapa la 5. 50GbE Hardware Design Example Register Map
E thathamisa mekhahlelo ea rejisetara ea memori bakeng sa moralo oa hardware example. U fihlella lirekoto tsena ka mesebetsi ea reg_read le reg_write ho System Console.
| Lentsoe Offset | Sehlopha sa Ngolisa |
| 0x300–0x5FF | 50GbE IP ea mantlha lirejistara. |
| 0x4000–0x4C00 | Arria 10 lirekoto tse matla tsa ntlafatso. Ngoliso ea aterese ke 0x4000 bakeng sa Lane 0 le 0x4400 bakeng sa Lane 1. |
Lintlha Tse Amanang
- Ho leka 50GbE Hardware Design Example leqepheng la 11 System Console e laela ho fihlella li-IP core le lirejistara tsa Native PHY.
- 50GbE Control and Status Register Litlhaloso E hlalosa 50GbE IP core registers.
Nalane ea Phetoho ea Litokomane
Letlapa la 6. 50G Ethernet Design Example Nalane ea Phetoho ea Bukana ea Basebelisi
| Letsatsi | Lokolla | Liphetoho |
| 2019.04.03 | 17.0 | E kentse taelo ea ho tsamaisa lipapiso tsa Xcelium. |
|
2017.11.08 |
17.0 |
Sehokelo se kenyellelitsoeng ho Karabo ea KDB e fanang ka workaround bakeng sa jitter e ka bang teng ho lisebelisoa tsa Intel Arria® 10 ka lebaka la ho phatloha ha ATX PLL ho IP core.
Sheba Ho Hlahisa Moqapi Example leqepheng la 7 le Ho bokella le Ho lokisa Moralo Example ho Hardware leqepheng la 10. Moqapi ona examptataiso ea mosebelisi ha e so ntlafatsoe ho bonahatsa Hlokomela: liphetoho tse nyane tlhahisong ea moralo ho Intel Quartus Prime e lokolloa hamorao ho feta tokollo ea software ea Intel Quartus Prime v17.0. |
| 2017.05.08 | 17.0 | Phatlalatso ea pele ea sechaba. |
Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.
Litokomane / Lisebelisoa
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Intel 50G Ethernet Design Example [pdf] Bukana ea Mosebelisi 50G Ethernet Design Example, 50G, Ethernet Design Example, Moqapi Example |
