F-Tile DisplayPort FPGA IP Design Eksample
Itọsọna olumulo

F-Tile DisplayPort FPGA IP Design Eksample

Imudojuiwọn fun Intel® Quartus® Prime Design Suite: 22.2 IP Ẹya: 21.0.1

DisplayPort Intel FPGA IP Design Example Quick Bẹrẹ Itọsọna

Awọn ohun elo DisplayPort Intel® F-tile ṣe ẹya simulating testbench ati apẹrẹ ohun elo kan ti o ṣe atilẹyin iṣakojọpọ ati idanwo ohun elo FPGA IP apẹrẹ apẹẹrẹ.amples fun Intel Agilex™
DisplayPort Intel FPGA IP nfunni ni apẹrẹ atẹleample:

• DisplayPort SST parallel loopback lai a Pixel Aago Ìgbàpadà (PCR) module
• DisplayPort SST parallel loopback pẹlu AXIS Video Interface

Nigba ti o ba se ina kan oniru example, paramita olootu laifọwọyi ṣẹda awọn files pataki lati ṣe simulate, ṣajọ, ati idanwo apẹrẹ ni hardware.
Nọmba 1. Idagbasoke StagesAlaye ti o jọmọ

• DisplayPort Intel FPGA IP Itọsọna olumulo
• Iṣilọ si Intel Quartus Prime Pro Edition

Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn aami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ṣiṣe ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ.
* Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.
ISO 9001: 2015 forukọsilẹ
1.1. Ilana Ilana
olusin 2. Directory Be

Table 1. Design Example irinše

Awọn folda	Files
rtl/mojuto	dp_core.ip
	dp_rx. ip
	dp_tx. ip
rtl/rx_phy	dp_gxb_rx/ ((DP PMA UX ile idina)
	dp_rx_data_fifo. ip
	rx_oke_phy. sv
rtl/tx_phy	dp_gxb_rx/ ((DP PMA UX ile idina)
	dp_tx_data_fifo.ip
	dp_tx_data_fifo.ip

1.2. Hardware ati Software Awọn ibeere
Intel nlo awọn wọnyi hardware ati software lati se idanwo awọn oniru example:
Hardware

• Intel Agilex I-Series Development Kit
• DisplayPort Orisun GPU
• DisplayPort rì (Abojuto)
• Biec DisplayPort FMC ọmọbinrin kaadi Àtúnyẹwò 8C
• Awọn kebulu DisplayPort

Software

• Intel Quartus® NOMBA
• Synopsys * VCS Simulator

1.3. Ti o npese awọn Design
Lo olootu paramita IP DisplayPort Intel FPGA ni sọfitiwia Intel Quartus Prime lati ṣe ipilẹṣẹ apẹrẹ tẹlẹample.
olusin 3. Ti o npese awọn Design sisan

1.  Yan Awọn irinṣẹ ➤ IP Catalog, ki o si yan Intel Agilex F-tile bi idile ẹrọ afojusun.
   Akiyesi: Apẹrẹ example nikan atilẹyin Intel Agilex F-tile awọn ẹrọ.
2. Ninu Katalogi IP, wa ati tẹ-lẹẹmeji DisplayPort Intel FPGA IP. Ferese Iyipada IP Tuntun yoo han.
3. Pato orukọ ipele-oke fun iyatọ IP aṣa rẹ. Olootu paramita n fipamọ awọn eto iyatọ IP ni a file ti a npè ni .ip.
4. Yan ohun elo Intel Agilex F-tile kan ni aaye Ẹrọ, tabi tọju yiyan ẹrọ sọfitiwia Intel Quartus Prime aiyipada.
5. Tẹ O DARA. Olootu paramita yoo han.
6. Tunto awọn paramita ti o fẹ fun mejeeji TX ati RX.
7. Labẹ apẹrẹ Examptaabu, yan DisplayPort SST Parallel Loopback Laisi PCR.
8. Yan Simulation lati se ina testbench, ki o si yan Synthesis lati se ina awọn hardware oniru example. O gbọdọ yan o kere ju ọkan ninu awọn aṣayan wọnyi lati ṣe ipilẹṣẹ apẹrẹ tẹlẹample files. Ti o ba yan awọn mejeeji, akoko iran yoo gun.
9. Fun Apo Idagbasoke Àkọlé, yan Intel Agilex I-Series SOC Development Kit. Eleyi fa awọn afojusun ẹrọ ti a ti yan ni igbese 4 lati yi lati baramu awọn ẹrọ lori awọn idagbasoke kit. Fun Intel Agilex I-Series SOC Development Kit, ẹrọ aifọwọyi jẹ AGIB027R31B1E2VR0.
10. Tẹ ina Example Design.

1.4. Simulating awọn Design
DisplayPort Intel FPGA IP apẹrẹ example testbench ṣe apẹẹrẹ apẹrẹ loopback ni tẹlentẹle lati apẹẹrẹ TX si apẹẹrẹ RX kan. Module olupilẹṣẹ apẹẹrẹ fidio ti inu wakọ apẹẹrẹ DisplayPort TX ati iṣelọpọ fidio apẹẹrẹ RX sopọ si awọn oluyẹwo CRC ni testbench.
olusin 4. Ṣiṣan Simulation Design

1. Lọ si folda Simulator Synopsys ko si yan VCS.
2. Ṣiṣe akosile kikopa.
   Orisun vcs_sim.sh
3. Iwe afọwọkọ naa n ṣe Quartus TLG, ṣe akopọ ati ṣiṣe testbench ni simulator.
4. Ṣe itupalẹ abajade.
   Simulation aṣeyọri pari pẹlu Orisun ati afiwe SRC Sink.

1.5. Iṣakojọpọ ati Idanwo Oniru naa
Ṣe nọmba 5. Ṣiṣepọ ati Simulating ApẹrẹLati ṣajọ ati ṣiṣe idanwo ifihan lori hardware exampFun apẹrẹ, tẹle awọn igbesẹ wọnyi:

1. Rii daju hardware example oniru iran jẹ pari.
2. Lọlẹ Intel Quartus Prime Pro Edition sọfitiwia ati ṣii / kuotisi/agi_dp_demo.qpf.
3. Tẹ Ṣiṣeto ➤ Bẹrẹ Iṣakojọpọ.
4. Lẹhin ikojọpọ aṣeyọri, sọfitiwia Intel Quartus Prime Pro ṣe ipilẹṣẹ .sof kan file ninu rẹ pàtó kan liana.
5. So asopọ DisplayPort RX lori kaadi ọmọbinrin Bitec si orisun DisplayPort ita, gẹgẹbi awọn kaadi eya aworan lori PC kan.
6. So asopọ DisplayPort TX lori kaadi ọmọbinrin Bitec si ẹrọ ifọwọ DisplayPort, gẹgẹbi oluyẹwo fidio tabi atẹle PC kan.
7.  Rii daju pe gbogbo awọn iyipada lori igbimọ idagbasoke wa ni ipo aiyipada.
8. Tunto ẹrọ Intel Agilex F-Tile ti a yan lori igbimọ idagbasoke nipa lilo .sof ti ipilẹṣẹ file (Awọn irinṣẹ ➤ Oluṣeto).
9. Ẹrọ ifọwọ DisplayPort ṣe afihan fidio ti o ti ipilẹṣẹ lati orisun fidio.

Alaye ti o jọmọ
Intel Agilex I-Series FPGA Itọsọna olumulo Apo Idagbasoke/
1.5.1. ELF atunṣe File
Nipa aiyipada, ELF file ti ipilẹṣẹ nigba ti o ba se ina awọn ìmúdàgba oniru Mofiample.
Sibẹsibẹ, ni awọn igba miiran, o nilo lati tun ELF pada file ti o ba yipada software file tabi tun dp_core.qsys file. Atunse dp_core.qsys file imudojuiwọn .sopcinfo file, eyi ti o nilo ki o tun ṣe atunṣe ELF file.

1. Lọ si /software ati satunkọ koodu ti o ba jẹ dandan.
2. Lọ si / akosile ki o si ṣiṣẹ awọn wọnyi Kọ akosile: orisun build_sw.sh
   • Lori Windows, wa ati ṣii Nios II Command Shell. Ni Nios II Command Shell, lọ si / akosile ati ṣiṣẹ orisun build_sw.sh.
   Akiyesi: Lati ṣiṣẹ iwe afọwọkọ kikọ lori Windows 10, eto rẹ nilo Awọn ọna ṣiṣe Windows fun Lainos (WSL). Fun alaye diẹ ẹ sii nipa awọn igbesẹ fifi sori WSL, tọka si Nios II Iwe-itumọ Agbese Software.
   • Lori Lainos, ṣe ifilọlẹ Apẹrẹ Platform, ati ṣii Awọn irinṣẹ ➤ Nios II Command Shell. Ni Nios II Command Shell, lọ si / akosile ati ṣiṣẹ orisun build_sw.sh.
3. Rii daju ohun .elf file ti ipilẹṣẹ ni /software/ dp_demo.
4. Ṣe igbasilẹ ti ipilẹṣẹ .elf file sinu FPGA lai recompiling .sof file nipa ṣiṣe awọn wọnyi akosile: nios2-download /software/dp_demo/*.elf
5. Titari bọtini atunto lori igbimọ FPGA fun sọfitiwia tuntun lati ni ipa.

1.6. DisplayPort Intel FPGA IP Design Example Parameters
Table 2. DisplayPort Intel FPGA IP Design Eksample QSF ihamọ fun Intel Agilex Ftile Device

Idiwọn QSF	Apejuwe
set_global_assignment -orukọ VERILOG_MACRO "__DISPLAYPORT_support__=1"	Lati Quartus 22.2 siwaju, idiwọ QSF yii ni a nilo lati jẹ ki iṣàn DisplayPort aṣa SRC (Aṣatunṣe Atunṣe Asọ) ṣiṣẹ

Table 3. DisplayPort Intel FPGA IP Design Eksample Parameters fun Intel Agilex F-tile Device

Paramita	Iye	Apejuwe
Apẹrẹ ti o wa Example
Yan Oniru	• Ko si •DisplayPort SST Parallel Loopback lai PCR •DisplayPort SST Parallel Loopback pẹlu AXIS Video Interface	Yan apẹrẹ example lati wa ni ipilẹṣẹ. • Ko si: Ko si oniru example wa fun yiyan paramita lọwọlọwọ. •DisplayPort SST Parallel Loopback lai PCR: Yi oniru Mofiample ṣe afihan loopback ti o jọra lati ifọwọ DisplayPort si orisun DisplayPort laisi module Aago Pixel Ìgbàpadà (PCR) nigbati o ba tan-an Jeki paramita Port Aworan Input Fidio ṣiṣẹ. •DisplayPort SST Parallel Loopback pẹlu AXIS Video Interface: Yi oniru example ṣe afihan loopback ti o jọra lati IfihanPort sink si orisun DisplayPort pẹlu wiwo Fidio AXIS nigbati Mu Awọn Ilana data Fidio ti nṣiṣe lọwọ ti ṣeto si AXIS-VVP Kikun.
Apẹrẹ Example Files
Afọwọṣe	Tan, paa	Tan aṣayan yii lati ṣe ina pataki files fun testbench kikopa.
Akopọ	Tan, paa	Tan aṣayan yii lati ṣe ina pataki files fun Intel Quartus Prime akopo ati hardware design.
Ti ipilẹṣẹ HDL kika
Ṣẹda File Ọna kika	Verilog, VHDL	Yan ọna kika HDL ti o fẹ fun apẹrẹ ti ipilẹṣẹ example fileṣeto. Akiyesi: Aṣayan yii nikan pinnu ọna kika fun ipilẹṣẹ IP ipele oke files. Gbogbo miiran files (fun apẹẹrẹample testbenches ati oke ipele files fun ifihan ohun elo) wa ni ọna kika Verilog HDL.
Àkọlé Development Kit
Yan Board	• Ko si Apo Idagbasoke • Intel Agilex I-Series Idagbasoke Apo	Yan igbimọ fun apẹrẹ ìfọkànsí example.

Paramita	Iye	Apejuwe
		Ko si Apo Idagbasoke: Aṣayan yii ko ni gbogbo awọn aaye ohun elo fun apẹrẹ tẹlẹample. P mojuto ṣeto gbogbo awọn iyansilẹ pin si awọn pinni foju. • Intel Agilex I-Series FPGA Apo Idagbasoke: Aṣayan yii laifọwọyi yan ẹrọ ibi-afẹde ti iṣẹ akanṣe lati baamu ẹrọ naa lori ohun elo idagbasoke yii. O le yi ẹrọ ibi-afẹde pada nipa lilo paramita Ẹrọ Àkọlé Yipada ti atunyẹwo igbimọ rẹ ba ni iyatọ ẹrọ ti o yatọ. Ipilẹ IP ṣeto gbogbo awọn iṣẹ iyansilẹ pin ni ibamu si ohun elo idagbasoke. Akiyesi: Apẹrẹ Alakoko Example ko ni iṣeduro iṣẹ ṣiṣe lori ohun elo ni idasilẹ Quartus yii. • Aṣa Development Apo: Eleyi aṣayan faye gba awọn oniru example ṣe idanwo lori ohun elo idagbasoke ẹni-kẹta pẹlu Intel FPGA kan. O le nilo lati ṣeto awọn iṣẹ iyansilẹ pin lori tirẹ.
Àkọlé Device
Yi Àkọlé Device	Tan, paa	Tan aṣayan yii ki o yan iyatọ ẹrọ ti o fẹ fun ohun elo idagbasoke.

Apẹrẹ Loopback Ti o jọra Eksamples

DisplayPort Intel FPGA IP apẹrẹ examples ṣe afihan loopback ti o jọra lati apẹẹrẹ DisplayPort RX si apẹẹrẹ DisplayPort TX laisi module Imularada Aago Pixel (PCR).
Table 4. DisplayPort Intel FPGA IP Design Eksample fun Intel Agilex F-tile Device

Apẹrẹ Example	Orúkọ	Data Oṣuwọn	Ipo Ikanni	Loopback Iru
DisplayPort SST ni afiwe loopback lai PCR	DisplayPort SST	RBR, HRB, HRB2, HBR3	Simplex	Ni afiwe laisi PCR
DisplayPort SST parallel loopback pẹlu AXIS Video Interface	DisplayPort SST	RBR, HRB, HRB2, HBR3	Simplex	Ni afiwe pẹlu AXIS Video Interface

2.1. Intel Agilex F-tile DisplayPort SST Parallel Loopback Design Awọn ẹya ara ẹrọ
The SST ni afiwe loopback oniru examples ṣe afihan gbigbe ti ṣiṣan fidio kan lati ifọwọ DisplayPort si orisun DisplayPort.
Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn ami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ. * Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.
ISO 9001: 2015 forukọsilẹ
olusin 6. Intel Agilex F-tile DisplayPort SST Parallel Loopback lai PCR

• Ninu iyatọ yii, paramita orisun DisplayPort, TX_SUPPORT_IM_ENABLE, wa ni titan ati wiwo aworan fidio ti lo.
• Awọn ifọwọ DisplayPort gba fidio ati tabi ṣiṣan ohun lati orisun fidio ita gẹgẹbi GPU ati ṣe ipinnu rẹ sinu wiwo fidio ti o jọra.
• Ijade fidio ti DisplayPort rii taara taara ni wiwo fidio orisun DisplayPort ati awọn koodu si ọna asopọ akọkọ DisplayPort ṣaaju gbigbe si atẹle naa.
• IOPLL n ṣe awakọ mejeeji ifọwọ DisplayPort ati awọn aago fidio orisun ni igbohunsafẹfẹ ti o wa titi.
• Ti DisplayPort rii ati paramita MAX_LINK_RATE orisun ti wa ni tunto si HBR3 ati PIXELS_PER_CLOCK ti wa ni tunto si Quad, aago fidio nṣiṣẹ ni 300 MHz lati se atileyin 8Kp30 pixel oṣuwọn (1188/4 = 297 MHz).

Nọmba 7. Intel Agilex F-tile DisplayPort SST Parallel Loopback pẹlu AXIS Fidio Ni wiwo

• Ninu iyatọ yii, orisun DisplayPort ati paramita rii, yan AXIS-VVP FULL ni MU Awọn Ilana DATA FIDIO IṢẸ lati mu Aṣisi Fidio Data Interface ṣiṣẹ.
• Awọn ifọwọ DisplayPort gba fidio ati tabi ṣiṣan ohun lati orisun fidio ita gẹgẹbi GPU ati ṣe ipinnu rẹ sinu wiwo fidio ti o jọra.
• DisplayPort Sink ṣe iyipada ṣiṣan data fidio sinu data fidio axis ati ṣe awakọ ni wiwo data fidio orisun orisun DisplayPort nipasẹ Ifipamọ Fidio Fidio VVP. Orisun DisplayPort ṣe iyipada data fidio axis sinu ọna asopọ akọkọ DisplayPort ṣaaju gbigbe si atẹle naa.
• Ninu iyatọ apẹrẹ yii, awọn aago fidio akọkọ mẹta wa, eyun rx/tx_axi4s_clk, rx_vid_clk, ati tx_vid_clk. axi4s_clk nṣiṣẹ ni 300 MHz fun awọn modulu AXIS mejeeji ni Orisun ati Sink. rx_vid_clk runsDP Sink Fidio opo gigun ti epo ni 300 MHz (lati ṣe atilẹyin ipinnu eyikeyi to 8Kp30 4PIPs), lakoko ti tx_vid_clk n ṣiṣẹ opo gigun ti Fidio Orisun DP ni igbohunsafẹfẹ Pixel Aago gangan (pin nipasẹ awọn PIPs).
• Iyatọ apẹrẹ yii ṣe atunto igbohunsafẹfẹ tx_vid_clk nipasẹ siseto I2C si ọkọ SI5391B OSC nigbati apẹrẹ ṣe iwari iyipada ninu ipinnu naa.
• Iyatọ apẹrẹ yii ṣe afihan nọmba ti o wa titi ti awọn ipinnu bi a ti sọ tẹlẹ ninu sọfitiwia DisplayPort, eyun:
  - 720p60, RGB
  - 1080p60, RGB
  - 4K30, RGB
  - 4K60, RGB

2.2. Eto aago
Eto clocking ṣe apejuwe awọn ibugbe aago ni DisplayPort Intel FPGA IP apẹrẹ example.
olusin 8. Intel Agilex F-tile DisplayPort Transceiver clocking eniTable 5. clocking Ero awọn ifihan agbara

Aago ni aworan atọka	Apejuwe
SysPLL atunṣe	Aago itọkasi F-tile System PLL eyiti o le jẹ igbohunsafẹfẹ aago eyikeyi ti o jẹ pinpin nipasẹ Eto PLL fun igbohunsafẹfẹ iṣelọpọ yẹn. Ninu apẹrẹ yii example, system_pll_clk_link ati rx/tx refclk_link pin kanna 150 MHz SysPLL refclk.

Aago ni aworan atọka	Apejuwe
	O gbọdọ jẹ aago ṣiṣiṣẹ ọfẹ eyiti o sopọ lati pin aago itọkasi transceiver igbẹhin si ibudo aago titẹ sii ti Itọkasi ati Eto PLL Clocks IP, ṣaaju ki o to so ebute iṣelọpọ ti o baamu si DisplayPort Phy Top. Akiyesi: Fun apẹrẹ yii example, tunto Aago Adarí GUI Si5391A OUT6 to 150 MHz.
ọna asopọ pll clk	Igbohunsafẹfẹ eto PLL ti o kere ju lati ṣe atilẹyin gbogbo oṣuwọn DisplayPort jẹ 320 MHz. Apẹrẹ yii example nlo igbohunsafẹfẹ 900 MHz (ti o ga julọ) ki SysPLL refclk le pin pẹlu rx/tx refclk_link ti o jẹ 150 MHz.
rx_cdr_refclk_link / tx_pll_refclk_link	Rx CDR ati Tx PLL Link refclk eyiti o wa titi si 150 MHz lati ṣe atilẹyin gbogbo oṣuwọn data DisplayPort.
rx_ls_clkout / tx_ls_clkout	Aago Iyara Ọna asopọ DisplayPort si aago DisplayPort IP mojuto. Igbohunsafẹfẹ deede si Ipin Data Oṣuwọn nipasẹ iwọn data ti o jọra. Example: Igbohunsafẹfẹ = oṣuwọn data / iwọn data = 8.1G (HBR3) / 40 die-die = 202.5 ​​MHz

2.3. Testbench kikopa
Testbench kikopa simulates DisplayPort TX ni tẹlentẹle loopback to RX.
olusin 9. DisplayPort Intel FPGA IP Simplex Mode Simulation Testbench Block aworan atọkaTable 6. Testbench irinše

Ẹya ara ẹrọ	Apejuwe
Video Àpẹẹrẹ monomono	Olupilẹṣẹ yii ṣe agbejade awọn ilana igi awọ ti o le tunto. O le parameterize awọn akoko kika fidio.
Testbench Iṣakoso	Bulọọki yii n ṣakoso ọna idanwo ti kikopa ati ṣe ipilẹṣẹ awọn ifihan agbara ayun pataki si ipilẹ TX. Bulọọki iṣakoso testbench tun ka iye CRC lati orisun mejeeji ati rii lati ṣe awọn afiwera.
Oluyẹwo Igbohunsafẹfẹ Aago Iyara RX Ọna asopọ	Oluṣayẹwo yii jẹri boya transceiver RX ti o gba igbohunsafẹfẹ aago ibaamu oṣuwọn data ti o fẹ.
TX Link Speed ​​Aago Igbohunsafẹfẹ Checker	Oluyẹwo yii jẹri boya transceiver TX ti o gba igbohunsafẹfẹ aago ibaamu oṣuwọn data ti o fẹ.

Ijẹẹri simulation ṣe awọn iṣeduro wọnyi:
Tabili 7. Awọn iṣeduro Testbench

Igbeyewo àwárí mu	Ijerisi
• Ikẹkọ Ọna asopọ ni Oṣuwọn Data HBR3 Ka awọn iforukọsilẹ DPCD lati ṣayẹwo boya Ipo DP ṣeto ati wiwọn mejeeji TX ati igbohunsafẹfẹ Iyara Ọna asopọ RX.	Ṣepọ Oluyẹwo Igbohunsafẹfẹ lati wiwọn Iyara Ọna asopọ Aago ká igbohunsafẹfẹ o wu lati TX ati RX transceiver.
Ṣiṣe apẹẹrẹ fidio lati TX si RX. Ṣayẹwo CRC fun orisun mejeeji ati rii lati ṣayẹwo boya wọn baamu	• Sopọ olupilẹṣẹ apẹẹrẹ fidio si Orisun DisplayPort lati ṣe agbekalẹ ilana fidio. • Iṣakoso Testbench nigbamii ti ka mejeeji Orisun ati Sink CRC lati DPTX ati awọn iforukọsilẹ DPRX ati ṣe afiwe lati rii daju pe awọn iye CRC mejeeji jẹ aami kanna. Akiyesi: Lati rii daju pe a ṣe iṣiro CRC, o gbọdọ mu paramita adaṣe adaṣe atilẹyin CTS ṣiṣẹ.

Itan Atunyẹwo Iwe-ipamọ fun F-Tile DisplayPort Intel FPGA IP Design Example User Itọsọna

Ẹya Iwe aṣẹ	Intel Quartus NOMBA Version	Ẹya IP	Awọn iyipada
2022.09.02	22.	20.0.1	Yi akọle iwe pada lati DisplayPort Intel Agilex F-Tile FPGA IP Design Example User Itọsọna to F-Tile DisplayPort Intel FPGA IP Design Eksample User Itọsọna. • Ṣiṣẹ AXIS Fidio Apẹrẹ Example iyatọ. • Yiyọ Aimi Rate oniru ati ki o rọpo o pẹlu Olona Rate Design Example. • Yọ akọsilẹ kuro ni DisplayPort Intel FPGA IP Design Example Quick Bẹrẹ Itọsọna ti o sọ Intel kuotisi NOMBA 21.4 software version nikan atilẹyin Alakoko Design Eksamples. Rọpo eeya Ilana Itọsọna pẹlu nọmba to pe. Fikun apakan kan ti n ṣe atunṣe ELF File labẹ Iṣakojọpọ ati Idanwo Oniru. Ti ṣe imudojuiwọn apakan Awọn ibeere Hardware ati Software lati ni afikun ohun elo awọn ibeere.
2021.12.13	21.	20.0.0	Itusilẹ akọkọ.

Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn aami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ṣiṣe ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ.
* Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.
ISO 9001: 2015 forukọsilẹ

Idajọ Ayelujara
Fi esi ranṣẹ
UG-20347
ID: 709308
Ẹya: 2022.09.02

Awọn iwe aṣẹ / Awọn orisun

intel F-Tile DisplayPort FPGA IP Design Eksample [pdf] Itọsọna olumulo F-Tile DisplayPort FPGA IP Design Eksample, F-Tile DisplayPort, DisplayPort, FPGA IP Design Eksample, IP Design Example, UG-20347, 709308

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