Microchip Technology Core JTAG Tataiso ea Basebelisi ba Li-Debug
Microchip Technology CoreJTAGLi-processor tsa Debug

Selelekela

Core JTAG Debug v4.0 e thusa khokahanyo ea Joint Test Action Group (JTAG) li-processor tse bonolo tse sebetsang ho JTAG TAP kapa General Purpose Input/Output (GPIO) lithakhisa bakeng sa ho lokisa liphoso. Setsi sena sa IP se thusa ho lokisoa ha li-processor tse bonolo tsa 16 ka har'a sesebelisoa se le seng, hape se fana ka ts'ehetso bakeng sa ho lokisa li-processor ho lisebelisoa tse 'ne tse arohaneng holim'a GPIO.

Likaroloana

CoreJTAGDebug e na le likarolo tse latelang tsa bohlokoa:

  • E fana ka phihlello ea masela ho JTAG interface ka JTAG TLAPA.
  • E fana ka phihlello ea masela ho JTAG sehokelo ka lithakhisa tsa GPIO.
  • E hlophisa tšehetso ea Khoutu ea IR bakeng sa JTAG kotopo.
  • E ts'ehetsa khokahano ea lisebelisoa tse ngata ka JTAG TLAPA.
  • E ts'ehetsa debugging ea li-processor tse ngata.
  • E khothaletsa lioache tse arohaneng le ho seta mats'oao bocha ho lisebelisoa tse tlase tsa skew routing.
  • E ts'ehetsa ho seta bocha ha sepheo se sebetsang-tlase le se sebetsang holimo.
  • E tšehetsa JTAG Tshireletso Monitor Interface (UJTAG_SEC) bakeng sa lisebelisoa tsa PolarFire.

Core Version
Tokomane ena e sebetsa ho CoreJTAGDebug v4.0

Malapa a Tšehetsoeng

  • PolarFire®
  • RTG4™
  • IGLOO® 2
  • SmartFusion® 2
  • SmartFusion
  • ProASIC3/3E/3L
  • IGLOO
  • IGLOOe/+

Tšebeliso le Ts'ebetso ea Sesebelisoa

Lintlha tsa tšebeliso le ts'ebetso li thathamisitsoe tafoleng e latelang bakeng sa malapa a lisebelisoa tse tšehetsoeng. Lintlha tse thathamisitsoeng tafoleng ena ke sesupo feela. Kakaretso ea ts'ebeliso ea sesebelisoa le ts'ebetso ea mantlha e itšetlehile ka sistimi.
Letlapa la 1. Tšebeliso le Ts'ebetso ea Sesebelisoa

Lelapa Lithaele tse Sequential Ho kopanya Kakaretso Tšebeliso Sesebelisoa Kakaretso % Tshebetso (MHz)
PolarFire 17 116 299554 MPF300TS 0.04 111.111
RTG4 19 121 151824 RT4G150 0.09 50
SmartFusion2 17 120 56340 M2S050 0.24 69.47
IGLOO2 17 120 56340 M2GL050 0.24 68.76
SmartFusion 17 151 4608 A2F200M3F 3.65 63.53
IGLOO 17 172 3072 AFL125V5 6.15 69.34
ProASIC3 17 157 13824 EA3P600 1.26 50

Hlokomela: Lintlha tse tafoleng ena li ile tsa finyelloa ho sebelisoa Verilog RTL ka mokhoa o tloaelehileng oa ho kopanya le litlhophiso tsa sebopeho likarolong tsa -1. Litekanyetso tsa boemo bo holimo kapa li-generic li siiloe maemong a kamehla.

Tlhaloso ea Ts'ebetso

CoreJTAGDebug e sebelisa UJTAG macro e thata ho fana ka phihlello ho JTAG sehokelo ho tsoa lesela la FPGA. UJTAG hard macro thusa ho hokela ho tlhahiso ea MSS kapa ASIC TAP molaoli ho tloha lesela. Ke mohlala o le mong feela oa UJTAG macro e lumelloa lesela.
Setšoantšo sa 1-1. CoreJTAGSetšoantšo sa Debug Block
Setšoantšo se Thibeloang

CoreJTAGDebug e na le tlhahiso ea uj_jtag taolo ea kotopo, e sebelisang mokhoa oa JTAG molaoli oa kotopo ho thusa JTAG ho tsamaisana pakeng tsa sebatli sa FlashPro le processor ea softcore e shebiloeng. Sesebelisoa sa softcore se hokahane ka FPGA e inehetseng ea JTAG li-interface pins. Litlhahlobo tsa IR ho tsoa ho JTAG interface ha e fumanehe lesela la FPGA. Kahoo, protocol ea kotopo ea hlokahala ho thusa ho hlahloba IR le DR ho fihlela sepheo sa debug, se tšehetsang maemo a indasteri J.TAG segokahanyi. Selaoli sa kotopo se khetholla pakete ea kotopo e fetisitsoeng e le sekena sa DR ebe se hlahisa sephetho sa IR kapa DR scan, se ipapisitse le likahare tsa pakete ea kotopo le litaba tsa rejisetara ea IR e fanoeng ka UIREG. Molaoli oa kotopo o boetse o khetholla pakete ea kotopo, ha likahare tsa ngoliso ea IR li ts'oana le khoutu ea eona ea IR.

Setšoantšo sa 1-2. Tunnel Packet Protocol
Tunnel Packet Protocol

Paramethara ea tlhophiso e fana ka tlhophiso ea khoutu ea IR e sebelisoang ke molaoli oa kotopo. Ho thusa ho lokisoa ha li-processor tse ngata tse bonolo ka har'a moralo o le mong, palo ea balaoli ba kotopo e kentsoeng e ka lokisoa ho tloha ho 1-16, ho fana ka J.TAG sehokelo se lumellanang ho processor e 'ngoe le e' ngoe e reriloeng. Li-processor tsena tse shebiloeng li ka rarolloa ka mokhoa o ikhethileng oa IR khoutu e behiloeng ka nako ea ts'ebetso.

CLKINT kapa BFR buffer e kentsoe mothalong oa TGT_TCK oa sebopeho se seng le se seng sa processor ea sepheo.

Mohala oa URSTB ho tloha UJTAG macro (TRSTB) e khothaletsoa ho ba mohloli oa lefats'e ka har'a CoreJTAGTlosa bothata. Sefetoheli sa boikhethelo se behiloe mothapong oa TGT_TRST ka har'a CoreJTAGDebug bakeng sa ho hokahanya le sepheo sa debug, eo ka nako eo ho lebelletsoeng hore e hoketsoe mohloling o sebetsang oa ho seta bocha. E hlophisitsoe ha ho nahanoa hore lets'oao le kenang la TRSTB le tsoang ho JTAG TAP e sebetsa tlase. Haeba tlhophiso ena e hloka sepheo se le seng kapa tse ngata tsa ho rarolla bothata, ho tla sebelisoa mohloli o mong oa litsela tsa lefatše.

Mohala oa URSTB ho tloha UJTAG macro (TRSTB) e khothaletsoa ho ba mohloli oa lefats'e ka har'a CoreJTAGTlosa bothata. Sefetoheli sa boikhethelo se behiloe mothapong oa TGT_TRST ka har'a CoreJTAGDebug bakeng sa ho hokahanya le sepheo sa debug, eo ka nako eo ho lebelletsoeng hore e hoketsoe mohloling o sebetsang oa ho seta bocha. E hlophisitsoe ha ho nahanoa hore lets'oao le kenang la TRSTB le tsoang ho JTAG TAP e sebetsa tlase. TGT_TRSTN ke sehlahisoa sa kamehla se sebetsang se tlase bakeng sa sepheo sa ho lokisa bothata. Haeba tlhophiso ena e hloka sepheo se le seng kapa tse ngata tsa ho rarolla bothata, ho tla sebelisoa mohloli o mong oa litsela tsa lefatše.

Setšoantšo sa 1-3. CoreJTAGDebug Serial Data le Clock
Lintlha tsa serial le ho koala

Sesebelisoa sa Chaining

Sheba ho FPGA Programming User Guides bakeng sa boto e khethehileng ea nts'etsopele kapa lelapa. Boto e 'ngoe le e' ngoe ea ntlafatso e ka sebetsa ka matla a fapanengtages, 'me u ka khetha ho netefatsa hore na ho khonahala ka sethala sa bona sa nts'etsopele. Hape, haeba u sebelisa liboto tse ngata tsa nts'etsopele, etsa bonnete ba hore li arolelana sebaka se tšoanang.

Ka FlashPro Header
Ho ts'ehetsa ketane ea lisebelisoa tse ngata lesela ho sebelisa hlooho ea FlashPro, makhetlo a mangata a uj_jtag lia hlokahala. Mofuta ona oa mantlha o fana ka phihlello ea li-cores tse 16 ntle le tlhoko ea ho kenya letsoho uj_jtag. Koko e 'ngoe le e' ngoe e na le Khoutu ea IR e ikhethang (ho tloha 0x55 ho isa 0x64) e tla fana ka phihlello ea mantlha e ts'oanang le khoutu ea ID.

Setšoantšo sa 1-4. Li-processor tse ngata ka har'a sesebelisoa se le seng
Sesebelisoa se le Mong

Ho sebelisa CoreJTAGHlakola lisebelisoa tse ngata, e 'ngoe ea lisebelisoa e hloka ho ba master. Sesebelisoa sena se na le CoreJTAGDebug core. Joale processor e 'ngoe le e' ngoe e hokahane ka tsela e latelang:
Setšoantšo sa 1-5. Li-processor tse ngata ka har'a lisebelisoa tse peli
Ka har'a Lisebelisoa tse peli

Ho lokisa mantlha botong e 'ngoe, JTAG matšoao a tsoang CoreJTAGDebug e phahamisetsoa ho li-pin tsa boemo bo holimo ho SmartDesign. Joale tsena li hokahane le JTAG matšoao ka kotloloho ho processor.
Hlokomela: A CoreJTAGDebug, moralong oa bobeli oa boto, ke boikhethelo Hlokomela hore UJ_JTAG macro le hlooho ea FlashPro ha e sebelisoe moralong oa bobeli oa boto.

Ho khetha processor bakeng sa debugging ho SoftConsole, tobetsa tlhophiso ea debug, ebe o tobetsa konopo ea Debugger.

Taelo, e bontšitsoeng setšoantšong se latelang, e ea phethisoa.

Setšoantšo sa 1-6. Debugger Configuration UJ_JTAG_IRCODE
Debugger Configuration

UJ_JTAG_IRCODE e ka fetoloa ho latela hore na o lokisa processor efe. Bakeng sa mohlalaample: ho lokisa processor ho Sesebelisoa sa 0, UJ_JTAG_IRCODE e ka hlophiswa ho 0x55 kapa 0x56.

Ka GPIO
Ho lokisa bothata holim'a GPIO, paramethara UJTAG _BYPASS e khethiloe. Li-cores tse 'nè le tse' nè li ka lokisoa holim'a lihlooho kapa lithapo tsa GPIO. Ho tsamaisa seboka sa debug u sebelisa GPIOs ho tloha SoftConsole v5.3 kapa holimo, Debug Configuration e tlameha ho hlongoa ka tsela e latelang:
Setšoantšo sa 1-7. Debugger Configuration GPIO
Debugger Configuration

Hlokomela: Haeba u lokisa bothata ka GPIO, u ke ke ua khona ho lokisa processor ka nako e le 'ngoe ka FlashPro Header kapa Embedded FlashPro5, libotong tsa nts'etsopele. Bakeng sa mohlalaample: FlashPro Header kapa Embedded FlashPro5 lia fumaneha ho thusa ho rarolla bothata ka Identify kapa SmartDebug.
Setšoantšo sa 1-8. Ho lokisa liphoso holim'a GPIO Pins
Ho lokisa liphoso holim'a GPIO Pins

Ho tsamaisa lisebelisoa ka GPIO Pins
Ho tšehetsa ketane ea lisebelisoa tse ngata ka GPIO, UJTAG_BYPASS parameter e hloka ho khethoa. Ebe mats'oao a TCK, TMS, le TRSTb a ka phahamisetsoa boema-kepeng ba maemo a holimo. Li-processor tsohle tse shebiloeng li na le TCK, TMS, le TRSTb. Tsena ha lia bontšoa ka tlase.
Setšoantšo sa 1-9. Ketane ea lisebelisoa ka GPIO Pins
Sesebelisoa sa Chaining

Ka thuto ea motheo ea JTAG chain, TDO ea processor e hokahana le TDI ea processor e 'ngoe,' me e tsoela pele ho fihlela li-processor tsohle li tlanngoe ka liketane, ka mokhoa ona. TDI ea processor ea pele le TDO ea processor ea ho qetela e hokela ho JTAG Lenaneo le kopanya li-processor tsohle. Leano la JTAG matšoao a tsoang ho li-processor a fetisetsoa ho CoreJTAGDebug, moo ba ka tlangoa ka liketane. Haeba ketane ho lisebelisoa tse ngata e phethiloe, sesebelisoa se nang le CoreJTAGDebug e fetoha sesebelisoa se ka sehloohong.

Boemong ba ho lokisa bothata ba GPIO, moo Khoutu ea IR e sa abeloang processor e 'ngoe le e' ngoe, sengoloa se fetotsoeng sa OpenOCD se sebelisetsoa ho khetha, sesebelisoa se ntseng se lokisoa. Script ea OpenOCD e fetotsoe hore e khethoe, e leng sesebelisoa se lokisitsoeng. Bakeng sa moralo oa Mi-V, the file e fumaneha sebakeng sa ho kenya SoftConsole, tlas'a openocd/scripts/board/microsemi-riscv.cfg. Bakeng sa li-processor tse ling, li files li fumaneha sebakeng se le seng sa openocd.
Hlokomela:  Likhetho tsa Debug Configuration le tsona li hloka ho ntlafatsoa, ​​haeba li file e rehoa bocha

Setšoantšo sa 1-10. Debug Configuration
Debug Configuration

Bula username-riscv-gpio-chain.cfg, e latelang ke examplintho tse lokelang ho bonoa:

Setšoantšo sa 1-11. MIV Configuration File
MIV Configuration File

Litlhophiso tse latelang li sebetsa bakeng sa sesebelisoa se le seng se lokisang GPIO. Bakeng sa ho lokisa ketane, litaelo tse ling li hloka ho eketsoa, ​​​​e le hore lisebelisoa tse sa lokisoang li kenngoe ka mokhoa oa bypass.
MIV Configuration File

Bakeng sa li-processor tse peli ka ketane, tse latelang samptaelo ea le e phethiloe:
MIV Configuration File

Sena se lumella ho lokisoa ha Target softcore Processor 1 ka ho beha Target softcore processor 0 mokhoeng oa bypass. Ho lokisa Target softcore Processor 0, ho sebelisoa taelo e latelang:
MIV Configuration File

Hlokomela:  Phapang e le 'ngoe feela lipakeng tsa litlhophiso tsena tse peli ke hore mohloli, o bitsang tlhophiso ea Microsemi RISCV. file (microsemi-riscv.cfg) e ka tla pele, ha e lokisa Target softcore Processor 0, kapa ea bobeli, ha e lokisa Target Softcore Processor 1. Bakeng sa lisebelisoa tse fetang tse peli ka ketane, j e eketsehilengtag li-newtaps li eketsoa. Bakeng sa mohlalaample, haeba ho na le li-processor tse tharo ka ketane, joale ho sebelisoa taelo e latelang:
MIV Configuration File

Setšoantšo sa 1-12. Example Sisteme ea Debug
Example Sisteme ea Debug

Sehokedi

Likarolo tse latelang li tšohla lintlha tse amanang le li-interface.

Li-Parameters tsa Tlhophiso

Likhetho tsa tlhophiso tsa CoreJTAGDebug e hlalositsoe tafoleng e latelang. Haeba ho hlokahala hore ho be le tlhophiso e 'ngoe ntle le ea kamehla, sebelisa lebokose la puisano la Configuration ho SmartDesign ho khetha litekanyetso tse loketseng bakeng sa likhetho tse ka lokisoang.
Lethathamo la 2-1. CoreJTAGDebug Configuration Options

Lebitso Range e nepahetseng Ea kamehla Tlhaloso
NUM_DEBUG_TGTS 1-16 1 Palo ea lipehelo tse fumanehang tsa ho lokisa bothata ka FlashPro (UJTAG_DEBUG = 0) ke 1-16. Palo ea lipehelo tse teng tsa ho lokisa bothata ka GPIO (UJTAG_DEBUG = 1) ke 1-4.
IR_CODE_TGT_x 0X55-0X64 0x55 JTAG Khoutu ea IR, sepheo se le seng sa debug. Theko e boletsoeng e tlameha ho ikamahanya le sepheo sena sa tharollo. Taolo ea kotopo e amanang le sebopeho sena sa sepheo sa debug se khanna TDO feela 'me se tsamaisa sehokelo sa ho lokisa bothata, ha litaba tsa rejisetara ea IR li lumellana le khoutu ena ea IR.
TGT_ACTIVE_HIGH_RESET_x 0-1 0 0: TGT_TRSTN_x tlhahiso e hokahane le mofuta oa lefats'e oa tlhahiso ea URSTB e sebetsang e tlase ea UJTAG macro.1: TGT_TRST e hlahisoang e hokahane ka hare ho sebopeho se sothehileng sa lefats'e sa URSTB e sebetsang e tlase ea UJ.TAG makhro. Mohloli o mong oa litsela oa lefats'e oa sebelisoa haeba paramethara ena e behiloe ho 1 bakeng sa sepheo leha e le sefe sa tharollo.
UJTAG_BYPASE 0-1 0 0: GPIO Debug e holofetse, Debug e fumaneha ka FlashPro Header kapa Embedded FlashPro5.1: GPIO Debug e nolofalitsoe, Debug e fumaneha ka li-pins tsa GPIO tse khethiloeng ka boto.Hlokomela:  Ha Debugging e etsoa ka GPIO, taelo e latelang ea debug e etsoa likhethong tsa SoftConsole debug: "- command "set FPGA_TAP N"".
UJTAG_SEC_EN 0-1 0 0: UJTAG macro e khethoa haeba UJTAG_BYPASS = 0. 1: UJTAG_SEC macro e khethiloe haeba UJTAG_BYPASS= 0.Hlokomela:  Paramethara ena e sebetsa feela ho PolarFire. Ke hore, LELAPA = 26.

Litlhaloso tsa Lipontšo
Tafole e latelang e thathamisa litlhaloso tsa matšoao bakeng sa CoreJTAGHlakola.
Lethathamo la 2-2. CoreJTAGDebug I/O Lipontšo

Lebitso Range e nepahetseng Ea kamehla Tlhaloso
NUM_DEBUG_TGTS 1-16 1 Palo ea lipehelo tse fumanehang tsa ho lokisa bothata ka FlashPro (UJTAG_DEBUG = 0) ke 1-16. Palo ea lipehelo tse teng tsa ho lokisa bothata ka GPIO (UJTAG_DEBUG = 1) ke 1-4.
IR_CODE_TGT_x 0X55-0X64 0x55 JTAG Khoutu ea IR, sepheo se le seng sa debug. Theko e boletsoeng e tlameha ho ikamahanya le sepheo sena sa tharollo. Taolo ea kotopo e amanang le sebopeho sena sa sepheo sa debug se khanna TDO feela 'me se tsamaisa sehokelo sa ho lokisa bothata, ha litaba tsa rejisetara ea IR li lumellana le khoutu ena ea IR.
TGT_ACTIVE_HIGH_RESET_x 0-1 0 0: TGT_TRSTN_x tlhahiso e hokahane le mofuta oa lefats'e oa tlhahiso ea URSTB e sebetsang e tlase ea UJTAG macro.1: TGT_TRST e hlahisoang e hokahane ka hare ho sebopeho se sothehileng sa lefats'e sa URSTB e sebetsang e tlase ea UJ.TAG makhro. Mohloli o mong oa litsela oa lefats'e oa sebelisoa haeba paramethara ena e behiloe ho 1 bakeng sa sepheo leha e le sefe sa tharollo.
UJTAG_BYPASE 0-1 0 0: GPIO Debug e holofetse, Debug e fumaneha ka FlashPro Header kapa Embedded FlashPro5.1: GPIO Debug e nolofalitsoe, Debug e fumaneha ka li-pins tsa GPIO tse khethiloeng ka boto.Hlokomela:  Ha Debugging e etsoa ka GPIO, taelo e latelang ea debug e etsoa likhethong tsa SoftConsole debug: "- command "set FPGA_TAP N"".
UJTAG_SEC_EN 0-1 0 0: UJTAG macro e khethoa haeba UJTAG_BYPASS = 0. 1: UJTAG_SEC macro e khethiloe haeba UJTAG_BYPASS= 0.Hlokomela:  Paramethara ena e sebetsa feela ho PolarFire. Ke hore, LELAPA = 26.

Lintlha:

  • Lipontšo tsohle ho JTAG Lethathamo la likou tsa TAP le kaholimo le tlameha ho phahamisetsoa ho li-port tsa boemo bo holimo ho SmartDesign.
  • SEC Ports e fumaneha feela ha UJTAG_SEC_EN e lumelletsoe ke CoreJTAGGUI ea tlhophiso ea Debug.
  • Ela hloko haholo ha o hokela EN_SEC. Haeba EN_SEC e phahamiselitsoe ho ba boema-fofane ba boemo bo holimo (pin input pin), u tlameha ho kena ho Configure I/O States Nakong ea J.TAG Karolo ea Mananeo ea Moralo oa Lenaneo ho phallo ea Libero le ho netefatsa hore I/0 State (Output Only) bakeng sa boema-kepe ba EN_SEC e behiloe ho 1.

Ngolisa 'mapa le Litlhaloso

Ha ho na lirekoto tsa CoreJTAGHlakola.

Phallo ea Sesebelisoa

Likarolo tse latelang li tšohla lintlha tse amanang le phallo ea lisebelisoa.

Laesense

Laesense ha e hlokehe ho sebelisa IP Core ena le Libero SoC.

RTL
Khoutu e felletseng ea RTL e fanoe bakeng sa mantlha le li-testbenche, e lumellang mantlha hore e hlahisoe ka SmartDesign. Simulation, Synthesis, le Layout li ka etsoa ka har'a Libero SoC.

SmartDesign
Mohlankanaample instantiated view ea CoreJTAGDebug e bontšoa setšoantšong se latelang. Bakeng sa tlhaiso-leseling e batsi mabapi le ho sebelisa SmartDesign ho tiisa le ho hlahisa li-cores, sheba ho Sebelisa DirectCore ho Libero® SoC User Guide.
Setšoantšo sa 4-1. SmartDesign CoreJTAGBoemo ba Debug View sebelisa JTAG Hlooho
SmartDesign

Setšoantšo sa 4-2. SmartDesign CoreJTAGMokhoa oa ho lokisa phoso o sebelisa GPIO Pins
SmartDesign

E lokisa CoreJTAGTlosa bothata ho SmartDesign

Konokono e hlophisitsoe ho sebelisoa GUI ea tlhophiso ho SmartDesign. Example ea GUI e bontšitsoe setšoantšong se latelang.
Setšoantšo sa 4-3. E lokisa CoreJTAGTlosa bothata ho SmartDesign
SmartDesign

Bakeng sa PolarFire, UJTAG_SEC e khetha UJTAG_SEC macro sebakeng sa UJTAG macro ha UJTAG_BYPASS e koetsoe. E hlokomolohuoa bakeng sa malapa a mang kaofela.
Palo ea Lipehelo tsa Debug e ka hlophisoa ho fihla ho lipehelo tse 16 tsa ho lokisa bothata, ka UJ.TAG_BYPASS e koetsoe, 'me lipehelo tse fihlang ho tse 4 tsa ho lokisa bothata, ka UJTAG_BYPASS e lumelletsoe.
UJTAG_BYPASS e khetha ho lokisa liphoso ka UJTAG le hlooho ea FlashPro, le ho lokisa liphoso ka lithapo tsa GPIO.
Sepheo sa # IR Code ke JTAG Khoutu ea IR e fuoe sepheo sa ho rarolla bothata. Ena e tlameha ho ba boleng bo ikhethileng ka har'a mefuta e boletsoeng Lethathamo la 2-1.

Ketsiso e Phallang

Testbench ea mosebelisi e fanoa ka CoreJTAGHlakola. Ho etsa lipapiso:

  1. Khetha phallo ea testbench ea mosebelisi ka har'a SmartDesign.
  2. Tobetsa Boloka le Hlahisa ka fenstereng ea Hlahisa. Khetha testbench ea mosebelisi ho tsoa ho Core Configuration GUI.

Ha SmartDesign e hlahisa morero oa Libero, e kenya testbench ea mosebedisi files. Ho tsamaisa testbench ea mosebelisi:

  1. Beha motso oa moralo ho CoreJTAGKemiso ea ho lokisa bothata ho fenstere ea maemo a maemo a meralo ea Libero.
  2. Tobetsa Netefatsa Moralo oa Pele o Synthesized> Etsisa ka fensetere ea Phallo ea Libero Design. Sena se qala ModelSim mme se tsamaisa papiso ka bo eona.
Synthesis ho Libero

Ho tsamaisa Synthesis:

  1. Tobetsa letšoao la Synthesize fensetereng ea Libero SoC Design Flow ho kopanya mantlha. Ntle le moo, tobetsa ka ho le letona khetho ea Synthesize fensetereng ea Moralo oa Phallo, ebe u khetha Open Interactively. Fesetere ea Synthesis e bonts'a projeke ea Synplify®.
  2. Tobetsa aekhone ea Matha.
    Hlokomela: Bakeng sa RTG4, ho na le temoso e fokolitsoeng ea ketsahalo ea nakoana (SET), e ka hlokomolohuoang kaha IP ena e sebelisetsoa merero ea ntlafatso feela 'me e ke ke ea sebelisoa tikolohong ea mahlaseli.
Sebaka-le-Route ho Libero

Hang ha Synthesis e phethiloe, tobetsa letšoao la Sebaka le Tsela ho Libero SoC ho qala ts'ebetso ea ho beha.

Sesebelisoa sa Lenaneo

Haeba karolo ea UJAG_SEC e sebelisoa 'me EN_SEC e phahamiselitsoe boemong ba boemo bo holimo (pin input pin), u tlameha ho kena ho Configure I/O States Nakong ea J.TAG Karolo ea Mananeo ea Moralo oa Lenaneo ho phallo ea Libero le ho netefatsa hore I/0 State (Output Only) bakeng sa boema-kepe ba EN_SEC e behiloe ho 1.

Tlhophiso ena ea hlokahala ho boloka phihlello ea JTAG boema-kepe bakeng sa ho hlophisa bocha sesebelisoa, hobane boleng bo hlalositsoeng ba Boundary Scan Register (BSR) bo feta boemo bofe kapa bofe ba kelello ho EN_SEC nakong ea ho hlophisa bocha.

Ho kopanya tsamaiso

Likarolo tse latelang li tšohla lintlha tse amanang le ho kopanya tsamaiso.

Moralo oa Boemo ba Sistimi bakeng sa IGLOO2/RTG4

Setšoantšo se latelang se bontša litlhoko tsa moralo ho etsa JTAG debugging ea processor ea softcore, e ka har'a lesela ho tloha SoftConsole ho ea ho JTAG sehokelo bakeng sa lisebelisoa tsa IGLOO2 le RTG4.
Setšoantšo sa 5-1. RTG4/IGLOO2 JTAG Moralo oa Debug
Moralo oa Boemo ba Tsamaiso

Moralo oa Boemo ba Sistimi bakeng sa SmartFusion2

Setšoantšo se latelang se bontša litlhoko tsa moralo ho etsa JTAG debugging ea processor ea softcore, e ka har'a lesela ho tloha SoftConsole ho ea ho JTAG interface bakeng sa lisebelisoa tsa SmartFusion2.
Setšoantšo sa 5-2. SmartFusion2 JTAG Moralo oa Debug
Moralo oa Boemo ba Tsamaiso

UJTAG_SEC

Bakeng sa lelapa la lisebelisoa tsa PolarFire, tokollo ena e lumella mosebelisi ho khetha pakeng tsa UJTAG le UJTAG_SEC, UJTAG_SEC_EN parameter ho GUI e tla sebelisoa ho khetha hore na e batloa ke efe.

Setšoantšo se latelang se bontša setšoantšo se bonolo se emelang likhokahano tsa 'mele tsa UJTAG/UJTAG_SEC ho PolarFire.

Setšoantšo sa 5-3. PolarFire UJTAG_SEC Macro
Moralo oa Boemo ba Tsamaiso

Litšitiso tsa Moqapi

Liqapi tse nang le CoreJTAGDebug e hloka hore sesebelisoa se latele litšitiso, phallong ea moralo, bakeng sa ho lumella tlhahlobo ea nako ho sebelisoa sebakeng sa oache sa TCK.

Ho eketsa lithibelo:

  1. Haeba phallo e ntlafalitsoeng ea Constraint ho Libero v11.7 kapa ho feta e sebelisoa, tobetsa habeli Constraints > Laola Litšitiso fensetereng ea DesignFlow ebe o tobetsa konopo ea Nako.
  2. Ho Thebo ea Nako ea fensetere ea Constraint Manager, tobetsa Ncha ho theha SDC e ncha file, le ho reha lebitso la file. Litšitiso tsa Moralo li kenyelletsa lithibelo tsa mohloli oa oache tse ka kengoang ho SDC ena e se nang letho file.
  3. Haeba Classic Constraint e phalla ho Libero v11.7 kapa ho feta e sebelisoa, tobetsa ka ho le letona ho Etsa Litšitiso> Thibelo ea Nako, fensetereng ea Design Flow, ebe o tobetsa Theha New Constraint. E theha SDC e ncha file. Litšitiso tsa moralo li kenyelletsa lithibelo tsa mohloli oa oache, tse kentsoeng ho SDC ena e se nang letho file.
  4. Bala nako ea TCK le halofo ea nako. TCK e behiloe ho 6 MHz ha debugging e etsoa ka FlashPro, 'me e behiloe ho maqhubu a mangata a 30 MHz ha debugging e tšehetsoa ke FlashPro5. Ka mor'a hore u qete mohato ona, kenya litšitiso tse latelang ho SDC file:
    create_clock -name {TCK} \
    • nako TCK_PERIOD \
    • waveform { 0 TCK_HALF_PERIOD } \ [ get_ports { TCK } ] For example, litšitiso tse latelang li sebelisoa bakeng sa moralo o sebelisang maqhubu a TCK a 6 MHz.
      create_clock -name {TCK} \
    • nako 166.67 \
    • waveform { 0 83.33 } \ [ get_ports { TCK } ]
  5. Kopanya lithibelo tsohle files le Synthesis, Place-and-Route, le Netefatso ea Nakotages ho Motsamaisi oa Constrain > Thebo ya nako. Sena se phetheloa ka ho khetha mabokose a amanang le a SDC files eo ho neng ho kenoa litšitiso ho eona

Nalane ea Phetoho

Lebitso la Port Bophara Tataiso Tlhaloso
JTAG TAP Boema-kepe
TDI 1 Kenyeletso Test Data In. Kenyelletso ea data ho tsoa ho TAP.
TCK 1 Kenyeletso Teko Clock. Mohloli oa oache ho likarolo tsohle tse latellanang ka har'a CoreJTAGHlakola.
TMS 1 Kenyeletso Test Mode Khetha.
TDO 1 Sephetho Test Data out. Sephetho sa data ho TAP.
TRSTB 1 Kenyeletso Hlakola Botjha. Kenyo e sebetsang ea ho seta bocha ho tsoa ho TAP.
JTAG Sepheo sa X Ports
TGT_TDO_x 1 Kenyeletso Lekola lintlha ho tloha ho debug target x ho ea ho TAP. Hokela ho boema-kepe ba TDO bo shebiloeng.
TGT_TCK_x 1 Sephetho Lekola tlhahiso ea Clock ho lokisa phoso x. TCK e khothaletsoa ho ba letlooa la lefats'e, le tlase la skew ka hare ho CoreJTAGHlakola.
TGT_TRST_x 1 Sephetho Seta Botjha teko e sebetsang-Phahameng. E sebelisoa feela ha TGT_ACTIVE_HIGH_RESET_x =1
TGT_TRSTN_x 1 Sephetho Seta Botjha teko e sebetsang-tlase. E sebelisoa feela ha TGT_ACTIVE_HIGH_RESET_x =0
TGT_TMS_x 1 Sephetho Mokhoa oa Teko Khetha tlhahiso ho lokisa sepheo sa x.
TGT_TDI_x 1 Sephetho Test Data In. Lintlha tse kenyelelitsoeng ho tsoa ho "debug target" x.
UJTAG_BYPASS_TCK_x 1 Kenyeletso Lekola Clock ho lokisa target x ho tsoa ho GPIO pin.
UJTAG_BYPASS_TMS_x 1 Kenyeletso Mokhoa oa Teko Khetha ho lokisa sepheo sa x ho tsoa ho GPIO pin.
UJTAG_BYPASS_TDI_x 1 Kenyeletso Lintlha tsa Teko ka hare, data ea serial ho lokisa target x ho tsoa ho GPIO pin.
UJTAG_BYPASS_TRSTB_x 1 Kenyeletso Hlakola Botjha. Seta bocha ho debug target x ho tsoa ho GPIO pin.
UJTAG_BYPASS_TDO_x 1 Sephetho Lekola Lintlha, Lintlha tse tsoang ho debug target x ho tsoa ho GPIO pin.
Libaka tsa SEC
EN_SEC 1 Kenyeletso E nolofalletsa Tšireletso. E nolofalletsa moralo oa mosebelisi ho hlakola tlhahiso ea kantle ea TDI le TRSTB ho TAP.Tlhokomeliso: Ela hloko ka ho khetheha ha u hokela boema-kepe bona. Sheba molaetsa o ka tlase le Lenaneo la Sesebelisoa bakeng sa lintlha tse ling.
TDI_SEC 1 Kenyeletso TDI Security e phahametse. E fetisa tlhahiso ea kantle ea TDI ho TAP ha EN_SEC e le HIGH.
TRSTB_SEC 1 Kenyeletso TRSTB Security override. E hlakola tlhahiso ea kantle ea TRSTB ho TAP ha SEC_EN e le HIGH.
UTRSTB 1 Sephetho Teko Reset Monitor
UTMS 1 Sephetho Mokgwa wa Teko Kgetha Mohlodi

Microchip Websebaka

Microchip e fana ka tšehetso ea inthaneteng ka rona website at www.microchip.com/. Sena websebaka se sebedisoang ho etsa files le tlhahisoleseding e fumaneha habonolo ho bareki. Tse ling tsa litaba tse fumanehang li kenyelletsa:

  • Tšehetso ea Sehlahisoa - Lipampiri tsa data le liphoso, lintlha tsa ts'ebeliso le lintlhaample mananeo, lisebelisoa tsa moralo, litataiso tsa basebelisi le litokomane tsa tšehetso ea hardware, lintlafatso tsa morao-rao tsa software le li-archived software
  • Tšehetso e Akaretsang ea Theknoloji - Lipotso tse atisang ho botsoa (FAQs), likopo tsa tšehetso ea tekheniki, lihlopha tsa lipuisano tsa inthaneteng, lethathamo la litho tsa lenaneo la balekane ba Microchip
  • Khoebo ea Microchip - Litataiso tsa ho khetha le ho odara, lingoliloeng tsa morao-rao tsa Microchip, lethathamo la lithupelo le liketsahalo, lethathamo la liofisi tsa thekiso ea Microchip, barekisi le baemeli ba feme.

Ts'ebeletso ea Tsebiso ea Phetoho ea Sehlahisoa

Ts'ebeletso ea tsebiso ea phetoho ea sehlahisoa sa Microchip e thusa ho boloka bareki ba le teng ka lihlahisoa tsa Microchip. Ba ngolisitseng ba tla fumana tsebiso ea lengolo-tsoibila neng kapa neng ha ho na le liphetoho, lintlafatso, lintlafatso kapa liphoso tse amanang le sehlahisoa se itseng sa lelapa kapa sesebelisoa sa ntlafatso sa thahasello.

Ho ngodisa, eya ho www.microchip.com/pcn 'me u latele litaelo tsa ho ngolisa Tšehetso ea Bareki  Basebelisi ba lihlahisoa tsa Microchip ba ka fumana thuso ka likanale tse 'maloa:

  • Morekisi kapa Moemedi
  • Ofisi ea Thekiso ea Lehae
  • Embedded Solutions Engineer (ESE)Technical Support Engineer ba lokela ho ikopanya le mofani oa bona, moemeli kapa ESE bakeng sa tšehetso. Liofisi tsa thekiso ea lehae le tsona li teng ho thusa bareki. Lethathamo la liofisi tsa thekiso le libaka li kenyelelitsoe tokomaneng ena.

Tšehetso ea tekheniki e fumaneha ka ho websebaka ho: www.microchip.com/support

Karolo ea Tšireletso ea Khoutu ea Lisebelisoa tsa Microchip

Hlokomela lintlha tse latelang tsa ts'ireletso ea khoutu ho lisebelisoa tsa Microchip:

  • Lihlahisoa tsa Microchip li kopana le litlhaloso tse fumanehang ho Microchip Data Sheet ea bona.
  • Microchip e lumela hore lelapa la eona la lihlahisoa le bolokehile ha li sebelisoa ka mokhoa o reriloeng le tlas'a maemo a tloaelehileng.
  • Ho na le mekhoa e sa tšepahaleng le mohlomong e seng molaong e sebelisoang ho leka ho tlola likarolo tsa ts'ireletso ea khoutu ea lisebelisoa tsa Microchip. Re lumela hore mekhoa ena e hloka ho sebelisa lihlahisoa tsa Microchip ka tsela e kantle ho lipehelo tsa ts'ebetso tse fumanehang ho Microchip's Data Sheets. Boiteko ba ho tlola likarolo tsena tsa ts'ireletso ea khoutu, mohlomong, bo ke ke ba finyelloa ntle le ho hatakela litokelo tsa thepa ea bohlale ea Microchip.
  • Microchip e ikemiselitse ho sebetsa le moreki leha e le ofe ea amehileng ka botšepehi ba khoutu ea eona.
  • Ha ho Microchip kapa moetsi ofe kapa ofe oa semiconductor ea ka netefatsang ts'ireletso ea khoutu ea eona. Tšireletso ea khoutu ha e bolele hore re tiisa hore sehlahisoa "se ke ke sa robeha." Tšireletso ea khoutu e lula e fetoha. Rona ba Microchip re ikemiselitse ho tsoela pele ho ntlafatsa likarolo tsa ts'ireletso ea khoutu ea lihlahisoa tsa rona. Boiteko ba ho senya ts'ireletso ea khoutu ea Microchip e kanna ea ba tlolo ea Molao oa Millennium Copyright Act. Haeba liketso tse joalo li lumella phihlello e sa lumelloeng ho software ea hau kapa mosebetsi o mong o nang le litokelo tsa molao, u ka ba le tokelo ea ho qosa bakeng sa phomolo tlasa Molao oo.

Tsebiso ea Molao

Tlhahisoleseding e hlahang khatisong ena e fanoe ka sepheo se le seng feela sa ho rala le ho sebelisa lihlahisoa tsa Microchip. Lintlha mabapi le lits'ebetso tsa lisebelisoa le tse ling tse joalo li fanoe molemong oa hau feela 'me li ka nkeloa sebaka ke liapdeite. Ke boikarabello ba hau ho netefatsa hore kopo ea hau e kopana le litlhaloso tsa hau.
TSEBISO ENA E FUMANA KE MICROCHIP "JOALOKAHA E LE". MICROCHIP HA E SEBELE
KAPA TIISETSO TSA MOFUTA OFE KA FEELA E KA BA E BUILENG KAPA E BONAHALA, E NGOLOA KAPA MOLOMO, KA MOLAO.
KAPA HOSE JOALE, E Amanang LE TSEBISO E KENYELETSA EMPA E SA LEKELETSO HO EFE KA FEELA.
TIISETSO TSA HO SA TLOKELETSO, BOKHOPO BA MHOEBI, LE HO LOKELA BAKENG SA MORERO O KHETHEHILENG KAPA TIISETSO TSE AMANG LE MAEMO, BOLEMO KAPA MOSEBETSI OA OO. HA HO LE TSATSAHALO, MICROCHIP E TLA BA MOTHO OA MOLATO BAKENG SA TAHLEHELO E MANG KAPA EFE, E KHETHEHILENG, EA KOTSI, TSA TLOAELO KAPA LITLHAKISO, TŠENYEHO, LITŠEnyehelo KAPA LITJEHO TSA MEFUTA EFE E Amanang LE LITSEBISO KAPA TŠEBELETSO EA LONA, LE HOJA E ENTSOE HO ETSA HORE NA. KGOTSA DITOSEKO TSA TSONA TSE BONE. HO FIHLELA KA HO FETISISA HO DUMELLA KE MOLAO, BOIKARABELO KAOFELA BA MICROCHIP HO LIKELETSO KAOFELA KA TSELA EFE KAPA E MABAPI LE BOITSEBISO KAPA TŠEBELETSO EA YONA E KE KE EA FEELA BOLIMO BA LITEFO, HA E LE TENG, TSEO O LI LEFILENG KA THOHO HO SEBELISA MICROCHIP. Tšebeliso ea lisebelisoa tsa Microchip ts'ehetso ea bophelo le/kapa lits'ebetso tsa ts'ireletso e kotsing ea moreki ka botlalo, 'me moreki o lumela ho sireletsa, ho qosa le ho boloka Microchip e se nang kotsi ho tsoa lits'enyehelo tsohle, likopo, lisutu, kapa litšenyehelo tse bakoang ke ts'ebeliso e joalo. Ha ho lilaesense tse fetisoang, ka mokhoa o hlakileng kapa ka tsela e 'ngoe, tlasa litokelo life kapa life tsa thepa ea mahlale a Microchip ntle le ha ho boletsoe ka tsela e ngoe.

LIMAKASE ASIA/PACIFIC ASIA/PACIFIC ULAYA
Ofisi ea Khoebo2355 West Chandler Blvd. Chandler, AZ 85224-6199Tel: 480-792-7200Fax: 480-792-7277Technical Support: www.microchip.com/support Web Aterese: www.microchip.com AtlantaDuluth, GATEl: 678-957-9614Fax: 678-957-1455Austin, TXMohala: 512-257-3370Boston Westborough, MA Mohala: 774-760-0087Fax: 774-760-0088ChicagoItasca, ILTel: 630-285-0071Fax: 630-285-0075DallasAddison, TXTel: 972-818-7423Fax: 972-818-2924DetroitNovi, MITel: 248-848-4000Houston, TXMohala: 281-894-5983Indianapolis Noblesville, IN Tel: 317-773-8323Fax: 317-773-5453Tel: 317-536-2380Los Angeles Mission Viejo, CA Mohala: 949-462-9523Fax: 949-462-9608Tel: 951-273-7800Raleigh, NCMohala: 919-844-7510New York, NYMohala: 631-435-6000San Jose, CAMohala: 408-735-9110Mohala: 408-436-4270Canada - TorontoMohala: 905-695-1980Fax: 905-695-2078 Australia - SydneyMohala: 61-2-9868-6733China - BeijingMohala: 86-10-8569-7000China - ChengduMohala: 86-28-8665-5511China - ChongqingMohala: 86-23-8980-9588China - DongguanMohala: 86-769-8702-9880China - GuangzhouMohala: 86-20-8755-8029China - HangzhouMohala: 86-571-8792-8115China - Hong Kong SARMohala: 852-2943-5100China - NanjingMohala: 86-25-8473-2460China - QingdaoMohala: 86-532-8502-7355China - ShanghaiMohala: 86-21-3326-8000China - ShenyangMohala: 86-24-2334-2829China - ShenzhenMohala: 86-755-8864-2200China - SuzhouMohala: 86-186-6233-1526China - WuhanMohala: 86-27-5980-5300China - XianMohala: 86-29-8833-7252China - XiamenMohala: 86-592-2388138China - ZhuhaiMohala: 86-756-3210040 India - BangaloreMohala: 91-80-3090-4444India - New DelhiMohala: 91-11-4160-8631India - PuneMohala: 91-20-4121-0141Japane - OsakaMohala: 81-6-6152-7160Japane - TokyoMohala: 81-3-6880-3770Korea - DaeguMohala: 82-53-744-4301Korea - SeoulMohala: 82-2-554-7200Malaysia - Kuala LumpurMohala: 60-3-7651-7906Malaysia - PenangMohala: 60-4-227-8870Philippines - ManilaMohala: 63-2-634-9065SingaporeMohala: 65-6334-8870Taiwan - Hsin ChuMohala: 886-3-577-8366Taiwan - KaohsiungMohala: 886-7-213-7830Taiwan – TaipeiMohala: 886-2-2508-8600Thailand - BangkokMohala: 66-2-694-1351Vietnam - Ho Chi MinhMohala: 84-28-5448-2100 Austria - WelsTel: 43-7242-2244-39Fax: 43-7242-2244-393Denmark - CopenhagenTel: 45-4485-5910Fax: 45-4485-2829Finland - EspooMohala: 358-9-4520-820Fora - ParisTel: 33-1-69-53-63-20Fax: 33-1-69-30-90-79Jeremane - Ho khabisaMohala: 49-8931-9700Jeremane - HaanMohala: 49-2129-3766400Jeremane - HeilbronnMohala: 49-7131-72400Jeremane - KarlsruheMohala: 49-721-625370Jeremane - MunichTel: 49-89-627-144-0Fax: 49-89-627-144-44Jeremane - RosenheimMohala: 49-8031-354-560Iseraele - Ra'ananaMohala: 972-9-744-7705Italy - MilanTel: 39-0331-742611Fax: 39-0331-466781Italy - PadovaMohala: 39-049-7625286Netherlands - DrunenTel: 31-416-690399Fax: 31-416-690340Norway - TrondheimMohala: 47-72884388Poland - WarsawMohala: 48-22-3325737Romania - BucharestTel: 40-21-407-87-50Spain - MadridTel: 34-91-708-08-90Fax: 34-91-708-08-91Sweden - GothenbergTel: 46-31-704-60-40Sweden - StockholmMohala: 46-8-5090-4654UK - WokinghamTel: 44-118-921-5800Fax: 44-118-921-5820

Letšoao la Microchip

Litokomane / Lisebelisoa

Microchip Technology CoreJTAGLi-processor tsa Debug [pdf] Bukana ea Mosebelisi
CoreJTAGLi-Debug processors, CoreJTAGDebug, processors

Litšupiso

Tlohela maikutlo

Aterese ea hau ea lengolo-tsoibila e ke ke ea phatlalatsoa. Libaka tse hlokahalang li tšoailoe *