Microchip Technology Core JTAG Debug Processors User Guide
Taw qhia
Core JTAG Debug v4.0 pab txhawb kev sib txuas ntawm Pawg Sib Koom Tes Ua Haujlwm (JTAG) tau tshaj soft core processors rau JTAG TAP lossis General Purpose Input/Output (GPIO) pins rau kev debugging. Cov tub ntxhais IP no pab txhawb qhov kev debugging ntawm qhov siab tshaj plaws ntawm 16 cov tub ntxhais mos cov txheej txheem hauv ib lub cuab yeej, thiab tseem muab kev txhawb nqa rau kev debugging ntawm cov txheej txheem ntawm plaub qhov sib txawv ntawm GPIO.
Nta
CoreJTAGDebug muaj cov yam ntxwv tseem ceeb hauv qab no:
- Muab cov ntaub nkag mus rau JTAG interface los ntawm JTAG THOV.
- Muab cov ntaub nkag mus rau JTAG interface los ntawm GPIO pins.
- Configures IR Code kev txhawb nqa rau JTAG kev tunneling.
- Txhawb kev sib txuas ntawm ntau yam khoom siv los ntawm JTAG THOV.
- Txhawb ntau tus processor debugging.
- Txhawb lub moos cais thiab rov pib dua cov cim rau cov khoom siv qis-skew routing.
- Txhawb nqa ob qho tib si nquag-qis thiab nquag-siab lub hom phiaj rov pib dua.
- Txhawb nqa JTAG Security Monitor Interface (UJTAG_SEC) rau cov khoom siv PolarFire.
Core Version
Cov ntaub ntawv no siv rau CoreJTAGDebug v4.0
Cov Tsev Neeg txhawb nqa
- PolarFire®
- RTG 4™
- IGLO® 2
- SmartFusion® 2
- SmartFusion
- ProASIC3/3E/3L
- IGLO
- IGLOOe/+
Cov cuab yeej siv thiab kev ua tau zoo
Cov ntaub ntawv siv thiab kev ua haujlwm tau teev nyob rau hauv cov lus hauv qab no rau cov tsev neeg cov cuab yeej txhawb nqa. Cov ntaub ntawv teev nyob rau hauv cov lus no tsuas yog qhia. Tag nrho cov cuab yeej siv thiab kev ua tau zoo ntawm cov tub ntxhais yog nyob ntawm qhov system.
Table 1. Kev siv thiab kev ua tau zoo
| Tsev neeg | Vuas Sequential | Neej Neeg Sib | Tag nrho | Kev siv Ntaus ntawv | Tag nrho % | Kev ua tau zoo (MHz) |
| PolarFire | 17 | 116 | 299554 | MPF300 TS | 0.04 | 111.111 |
| TIAB SA 4 | 19 | 121 | 151824 | RT4G 150 | 0.09 | 50 |
| SmartFusion 2 | 17 | 120 | 56340 | M2S050 | 0.24 | 69.47 |
| IGLOO 2 | 17 | 120 | 56340 | M2GL050 | 0.24 | 68.76 |
| SmartFusion | 17 | 151 | 4608 | A2F200M3F | 3.65 | 63.53 |
| IGLO | 17 | 172 | 3072 | AFL125V5 | 6.15 | 69.34 |
| ProASIC 3 | 17 | 157 | 13824 | A3P600 | 1.26 | 50 |
Nco tseg: Cov ntaub ntawv hauv cov lus no tau ua tiav los ntawm kev siv Verilog RTL nrog kev sib txuas thiab kev teeb tsa ntawm -1 ntu. Sab saum toj-theem parameters lossis generics raug tso tseg ntawm qhov chaw pib.
Functional Description
CoreJTAGDebug siv UJTAG nyuaj macro los muab kev nkag mus rau JTAG interface los ntawm FPGA ntaub. The UJTAG nyuaj macro pab txhawb kev sib txuas rau cov zis ntawm MSS lossis ASIC TAP tswj los ntawm cov ntaub. Tsuas yog ib qho piv txwv ntawm UJTAG macro tso cai rau hauv cov ntaub.
Daim duab 1-1. CoreJTAGDebug Block Diagram
CoreJTAGDebug muaj qhov instantiation ntawm uj_jtag tunnel controller, uas siv lub JTAG tunnel controller los pab JTAG tunneling ntawm FlashPro programmer thiab lub hom phiaj softcore processor. Lub softcore processor txuas nrog los ntawm FPGA's JTAG interface pins. IR scans los ntawm JTAG interface yog nkag tsis tau rau hauv FPGA ntaub. Li no, qhov kev cai lij choj yuav tsum tau pab txhawb IR thiab DR scans rau lub hom phiaj debug, uas txhawb nqa kev lag luam tus qauv JTAG interface. Tus tswj lub qhov taub txiav txim siab cov pob ntawv qhov xa mus raws li DR scan thiab tsim cov txiaj ntsig IR lossis DR scan, raws li cov ntsiab lus ntawm cov pob ntawv qhov thiab cov ntsiab lus ntawm IR sau npe muab los ntawm UIREG. Tus tswj lub qhov dej kuj tseem txiav txim siab lub pob ntawv qhov, thaum cov ntsiab lus ntawm IR sau npe sib tw nws IR code.
Daim duab 1-2. Tunnel Packet raws tu qauv
Ib tug configuration parameter muab configuration ntawm IR code siv los ntawm qhov tunnel maub los. Txhawm rau pab txhawb qhov kev debugging ntawm ntau lub software software hauv ib qho kev tsim, tus naj npawb ntawm cov tswj qhov hauv qhov instantiated yog configurable los ntawm 1-16, muab ib tug JTAG raws li interface rau txhua lub hom phiaj processor. Cov phiaj xwm txheej txheem no yog txhua qhov chaw nyob los ntawm qhov tshwj xeeb IR code teem rau lub sijhawm instantiation.
CLKINT lossis BFR tsis yog tam sim no nyob rau ntawm TGT_TCK kab ntawm txhua lub hom phiaj processor debug interface.
URSTB kab los ntawm UJTAG macro (TRSTB) tau nce mus rau thoob ntiaj teb cov peev txheej hauv CoreJTAGDebug. Ib qho kev xaiv inverter yog muab tso rau ntawm TGT_TRST kab hauv CoreJTAGDebug rau kev sib txuas rau lub hom phiaj debug, uas yog tom qab ntawd yuav tsum tau txuas nrog rau qhov chaw ua haujlwm-siab rov pib dua. Nws yog configured thaum nws yog assumed tias cov khoom TRSTB teeb liab los ntawm JTAG TAP active qis. Yog tias qhov kev teeb tsa no xav tau ib lossis ntau lub hom phiaj debug, ib qho kev pabcuam thoob ntiaj teb ntxiv yuav raug siv.
URSTB kab los ntawm UJTAG macro (TRSTB) tau nce mus rau thoob ntiaj teb cov peev txheej hauv CoreJTAGDebug. Ib qho kev xaiv inverter yog muab tso rau ntawm TGT_TRST kab hauv CoreJTAGDebug rau kev sib txuas rau lub hom phiaj debug, uas yog tom qab ntawd yuav tsum tau txuas nrog rau qhov chaw ua haujlwm-siab rov pib dua. Nws yog configured thaum nws yog assumed tias cov khoom TRSTB teeb liab los ntawm JTAG TAP active qis. TGT_TRSTN yog lub neej ua haujlwm qis qis rau lub hom phiaj debug. Yog tias qhov kev teeb tsa no xav tau ib lossis ntau lub hom phiaj debug, ib qho kev pabcuam thoob ntiaj teb ntxiv yuav raug siv.
Daim duab 1-3. CoreJTAGDebug Serial Data thiab Clocking
Ntaus Ntaus
Xa mus rau FPGA Programming User Guides rau pawg thawj coj loj loj lossis tsev neeg. Txhua pawg thawj coj loj hlob tuaj yeem ua haujlwm ntawm qhov sib txawvtages, thiab koj tuaj yeem xaiv los txheeb xyuas seb puas muaj peev xwm nrog lawv cov kev txhim kho platforms. Tsis tas li ntawd, yog tias koj siv ntau lub rooj tsav xwm txhim kho, xyuas kom meej tias, lawv sib koom ua ke.
Los ntawm FlashPro Header
Txhawm rau txhawb kev sib txuas ntawm ntau yam khoom siv hauv cov ntaub siv FlashPro header, ntau zaus ntawm uj_jtag yuav tsum tau. Qhov no version ntawm cov tub ntxhais muab kev nkag mus rau qhov siab tshaj plaws ntawm 16 cores yam tsis tas yuav tsum tau manually instantiating uj_jtag. Txhua tus tub ntxhais muaj qhov tshwj xeeb IR Code (los ntawm 0x55 txog 0x64) uas yuav muab kev nkag mus rau cov tub ntxhais tshwj xeeb sib piv rau ID code.
Daim duab 1-4. Ntau Cov Txheej Txheem hauv Ib Lub Tshuab Ib Leeg Ib Leeg
Txhawm rau siv CoreJTAGDebug hla ntau yam khoom siv, ib qho ntawm cov cuab yeej xav tau los ua tus tswv. Cov cuab yeej no muaj CoreJTAGDebug core. Txhua tus processor yog txuas nrog raws li hauv qab no:
Daim duab 1-5. Ntau tus processors hla ob lub cuab yeej
Txhawm rau debug ib qho tseem ceeb ntawm lwm lub rooj tsavxwm, JTAG signals los ntawm CoreJTAGDebug tau nce mus rau qib siab pins hauv SmartDesign. Cov no ces txuas nrog JTAG teeb liab ncaj qha rau ntawm lub processor.
Nco tseg: Ib CoreJTAGDebug, nyob rau hauv lub thib ob board tsim, yog xaiv tau Nco ntsoov tias UJ_JTAG macro thiab FlashPro header yog tsis siv nyob rau hauv lub thib ob board tsim.
Txhawm rau xaiv tus processor rau kev debugging hauv SoftConsole, nyem qhov debug configurations, thiab tom qab ntawd nyem rau ntawm Debugger tab.
Cov lus txib, qhia hauv daim duab hauv qab no, raug tua.
Daim duab 1-6. Debugger Configuration UJ_JTAG_IRCODE
The UJ_JTAG_IRCODE tuaj yeem hloov pauv raws li tus txheej txheem twg koj tab tom debugging. Rau example: mus debug lub processor hauv Device 0, UJ_JTAG_IRCODE tuaj yeem teeb tsa rau 0x55 lossis 0x56.
Los ntawm GPIO
Txhawm rau debug dhau GPIO, parameter UJTAG _BYPASS raug xaiv. Ib thiab plaub cores tuaj yeem raug debugged hla GPIO headers lossis pins. Txhawm rau khiav qhov kev sib tham debug siv GPIOs los ntawm SoftConsole v5.3 lossis siab dua, Debug Configuration yuav tsum tau teeb tsa raws li hauv qab no:
Daim duab 1-7. Debugger Configuration GPIO
Nco tseg: Yog tias koj tab tom debugging dhau GPIO, koj tsis tuaj yeem ua tib zoo debug lub processor los ntawm FlashPro Header lossis Embedded FlashPro5, ntawm cov laug cam. Rau example: FlashPro Header lossis Embedded FlashPro5 muaj los pab daws teeb meem siv Identify lossis SmartDebug.
Daim duab 1-8. Debugging dhau GPIO Pins
Ntaus chaining ntawm GPIO Pins
Txhawm rau txhawb kev sib txuas ntawm ntau yam khoom siv los ntawm GPIO, UJTAG_BYPASS parameter yuav tsum tau xaiv. Tom qab ntawd lub TCK, TMS, thiab TRSTb cov teeb liab tuaj yeem nce mus rau cov chaw nres nkoj sab saum toj. Txhua lub hom phiaj processors muaj TCK, TMS, thiab TRSTb. Cov no tsis qhia hauv qab no.
Daim duab 1-9. Ntaus chaining Los ntawm GPIO Pins
Hauv paus JTAG saw, TDO ntawm ib tug processor txuas mus rau TDI ntawm lwm tus processor, thiab nws tseem mus txog rau thaum tag nrho cov processors raug chained, raws li qhov no. TDI ntawm thawj processor thiab TDO ntawm lub processor kawg txuas mus rau JTAG programmer chaining tag nrho cov processors. Cov JTAG Cov teeb liab los ntawm cov processors raug xa mus rau CoreJTAGDebug, qhov twg lawv tuaj yeem raug chained. Yog tias txoj hlua khi hla ntau lub cuab yeej ua tiav, lub cuab yeej nrog CoreJTAGDebug dhau los ua tus tswv cuab yeej.
Hauv GPIO debug scenario, qhov twg IR Code tsis muab faib rau txhua tus processor, hloov kho OpenOCD tsab ntawv siv los xaiv, lub cuab yeej twg raug kho. Ib tsab ntawv OpenOCD tau hloov kho los xaiv, lub cuab yeej twg raug kho. Rau kev tsim Mi-V, lub file muaj nyob rau hauv SoftConsole nruab qhov chaw, nyob rau hauv lub openocd/scripts/board/ microsemi-riscv.cfg. Rau lwm cov processors, lub files muaj nyob rau hauv tib qhov chaw openocd.
Nco tseg: Cov kev xaiv Debug Configuration kuj yuav tsum tau hloov kho, yog tias tus file yog renamed
Daim duab 1-10. Debug Configuration
Qhib username-riscv-gpio-chain.cfg, hauv qab no yog ib qho example ntawm qhov yuav tsum tau pom:
Daim duab 1-11. MIV Configuration File
Cov chaw hauv qab no ua haujlwm rau ib qho khoom siv debugging tshaj GPIO. Rau kev debugging ib lub saw, cov lus txib ntxiv yuav tsum tau ntxiv, kom cov khoom siv uas tsis debugged tau muab tso rau hauv hom bypass.
Rau ob processors nyob rau hauv ib tug saw, cov nram qab no sample command yog executed:
Qhov no tso cai rau kev debugging ntawm Target softcore Processor 1 los ntawm kev tso Target softcore Processor 0 rau hauv hom bypass. Txhawm rau debug Lub Hom Phiaj softcore Processor 0, cov lus txib hauv qab no yog siv:
Nco tseg: Qhov sib txawv ntawm ob qhov kev teeb tsa no tsuas yog qhov chaw, uas yog hu rau Microsemi RISCV configuration file (microsemi-riscv.cfg) ob leeg los ua ntej, thaum debugging Target softcore Processor 0, los yog thib ob, thaum debugging Target Softcore Processor 1. Rau ntau tshaj ob pab kiag li lawm nyob rau hauv cov saw, ntxiv jtag newtaps yog ntxiv. Rau example, yog hais tias muaj peb processors nyob rau hauv ib tug saw, ces cov lus txib nram qab no yog siv:
Daim duab 1-12. Examplos ntawm Debug System
Interface
Cov ntu hauv qab no tham txog cov ntaub ntawv cuam tshuam txog kev sib txuas.
Configuration Parameters
Cov kev xaiv configuration rau CoreJTAGDebug tau piav qhia hauv cov lus hauv qab no. Yog tias qhov kev teeb tsa uas tsis yog lub neej ntawd xav tau, siv Configuration dialog box hauv SmartDesign los xaiv cov nqi tsim nyog rau cov kev xaiv configurable.
Table 2-1. CoreJTAGDebug Configuration Options
| Lub npe | Siv tau ntau yam | Default | Kev piav qhia |
| NUM_DEBUG_TGTS | 1-16 : kuv | 1 | Tus naj npawb ntawm cov phiaj xwm debug muaj los ntawm FlashPro (UJTAG_DEBUG = 0) is 1-16. Tus naj npawb ntawm cov phiaj xwm debug muaj los ntawm GPIO (UJTAG_DEBUG = 1) is 1-4. |
| IR_CODE_TGT_x | 0 x55-0x64 | 0x55 XNUMX | JTAG IR Code, ib lub hom phiaj debug. Tus nqi teev yuav tsum yog tshwj xeeb rau lub hom phiaj debug no. Tus tswj lub qhov cuam tshuam nrog qhov debug lub hom phiaj interface tsuas yog tsav TDO thiab tsav lub hom phiaj debug interface, thaum cov ntsiab lus ntawm IR sau npe sib tw IR code no. |
| TGT_ACTIVE_HIGH_RESET_x | 0-1 : kuv | 0 | 0: TGT_TRSTN_x tso zis yog txuas nrog rau lub ntiaj teb no daim ntawv ntawm lub active-low URSTB tso zis ntawm UJTAG macro.1: TGT_TRST tso zis yog nyob rau hauv kev cob cog rua rau lub ntiaj teb no inverted daim ntawv ntawm lub active-low URSTB tso zis ntawm UJTAG macro. Ib qho ntxiv thoob ntiaj teb routing peev txheej yog siv yog tias qhov ntsuas no tau teeb tsa rau 1 rau txhua lub hom phiaj debug. |
| UJTAG_PAB | 0-1 : kuv | 0 | 0: GPIO Debug yog neeg xiam oob qhab, Debug muaj nyob ntawm FlashPro Header lossis Embedded FlashPro5.1: GPIO Debug tau qhib, Debug muaj los ntawm tus neeg siv xaiv GPIO pins ntawm lub rooj tsavxwm.Nco tseg: Thaum Debugging ua tiav los ntawm GPIO, cov lus txib hauv qab no tau ua tiav hauv SoftConsole debug xaiv: "-hais kom "teeb FPGA_TAP N"". |
| UJTAG_SEC_EN | 0-1 : kuv | 0 | 0 :uaTAG macro xaiv yog UJTAG_BYPASS = 0. 1: UJTAG_SEC macro raug xaiv yog UJTAG_PASS = 0.Nco tseg: Qhov kev ntsuas no tsuas yog siv rau PolarFire. Ntawd yog, FAMILY = 26. |
Cov lus piav qhia
Cov lus hauv qab no teev cov teeb liab piav qhia rau CoreJTAGDebug.
Table 2-2. CoreJTAGDebug I/O Signals
| Lub npe | Siv tau ntau yam | Default | Kev piav qhia |
| NUM_DEBUG_TGTS | 1-16 : kuv | 1 | Tus naj npawb ntawm cov phiaj xwm debug muaj los ntawm FlashPro (UJTAG_DEBUG = 0) is 1-16. Tus naj npawb ntawm cov phiaj xwm debug muaj los ntawm GPIO (UJTAG_DEBUG = 1) is 1-4. |
| IR_CODE_TGT_x | 0 x55-0x64 | 0x55 XNUMX | JTAG IR Code, ib lub hom phiaj debug. Tus nqi teev yuav tsum yog tshwj xeeb rau lub hom phiaj debug no. Tus tswj lub qhov cuam tshuam nrog qhov debug lub hom phiaj interface tsuas yog tsav TDO thiab tsav lub hom phiaj debug interface, thaum cov ntsiab lus ntawm IR sau npe sib tw IR code no. |
| TGT_ACTIVE_HIGH_RESET_x | 0-1 : kuv | 0 | 0: TGT_TRSTN_x tso zis yog txuas nrog rau lub ntiaj teb no daim ntawv ntawm lub active-low URSTB tso zis ntawm UJTAG macro.1: TGT_TRST tso zis yog nyob rau hauv kev cob cog rua rau lub ntiaj teb no inverted daim ntawv ntawm lub active-low URSTB tso zis ntawm UJTAG macro. Ib qho ntxiv thoob ntiaj teb routing peev txheej yog siv yog tias qhov ntsuas no tau teeb tsa rau 1 rau txhua lub hom phiaj debug. |
| UJTAG_PAB | 0-1 : kuv | 0 | 0: GPIO Debug yog neeg xiam oob qhab, Debug muaj nyob ntawm FlashPro Header lossis Embedded FlashPro5.1: GPIO Debug tau qhib, Debug muaj los ntawm tus neeg siv xaiv GPIO pins ntawm lub rooj tsavxwm.Nco tseg: Thaum Debugging ua tiav los ntawm GPIO, cov lus txib hauv qab no tau ua tiav hauv SoftConsole debug xaiv: "-hais kom "teeb FPGA_TAP N"". |
| UJTAG_SEC_EN | 0-1 : kuv | 0 | 0 :uaTAG macro xaiv yog UJTAG_BYPASS = 0. 1: UJTAG_SEC macro raug xaiv yog UJTAG_PASS = 0.Nco tseg: Qhov kev ntsuas no tsuas yog siv rau PolarFire. Ntawd yog, FAMILY = 26. |
Nco tseg:
- Tag nrho cov cim hauv JTAG TAP cov chaw nres nkoj sau saum toj no yuav tsum tau nce mus rau theem siab tshaj plaws hauv cov chaw nres nkoj hauv SmartDesign.
- SEC Ports tsuas yog muaj thaum UJTAG_SEC_EN tau qhib los ntawm CoreJTAGDebug's configuration GUI.
- Ua tib zoo saib xyuas thaum txuas EN_SEC cov tswv yim. Yog tias EN_SEC tau nce mus rau qhov chaw nres nkoj saum toj kawg nkaus (cov khoom siv tus pin), koj yuav tsum nkag mus rau Configure I/O States Thaum JTAG Kev ua haujlwm ntu ntawm Kev Tsim Kho hauv Libero ntws thiab xyuas kom meej tias I / 0 Lub Xeev (Tshaj Tawm Tsuas) rau EN_SEC chaw nres nkoj tau teeb tsa rau 1.
Sau npe daim ntawv qhia thiab piav qhia
Tsis muaj npe rau CoreJTAGDebug.
Tool Flow
Cov ntu hauv qab no tham txog cov cuab yeej ntws ntsig txog cov ntaub ntawv.
Daim ntawv tso cai
Daim ntawv tso cai tsis tas yuav siv tus IP Core no nrog Libero SoC.
RTL
Ua kom tiav RTL code yog muab rau cov tub ntxhais kawm ntawv thiab cov ntawv xeem, tso cai rau cov tub ntxhais ua kom nrawm nrog SmartDesign. Simulation, Synthesis, thiab Layout tuaj yeem ua hauv Libero SoC.
SmartDesign
Ib example instantiated view ntawm CoreJTAGDebug tau qhia hauv daim duab hauv qab no. Yog xav paub ntxiv txog kev siv SmartDesign kom instantiate thiab tsim cov cores, xa mus rau Siv DirectCore hauv Libero® SoC Tus Neeg Siv Qhia.
Daim duab 4-1. SmartDesign CoreJTAGDebug Piv txwv View siv JTAG Lub taub hau
Daim duab 4-2. SmartDesign CoreJTAGDebug Instance siv GPIO Pins
Configuring CoreJTAGDebug hauv SmartDesign
Cov tub ntxhais tau teeb tsa siv GUI teeb tsa hauv SmartDesign. Ib example ntawm GUI tau qhia hauv daim duab hauv qab no.
Daim duab 4-3. Configuring CoreJTAGDebug hauv SmartDesign
PolarFire, UJTAG_SEC xaiv UJTAG_SEC macro hloov UJTAG macro thaum UJTAG_BYPASS yog neeg xiam. Nws tsis quav ntsej rau tag nrho lwm tsev neeg.
Tus naj npawb ntawm Debug Lub Hom Phiaj tau teeb tsa txog 16 lub hom phiaj debug, nrog UJTAG_BYPASS xiam thiab mus txog 4 lub hom phiaj debug, nrog UJTAG_BYPASS qhib.
UJTAG_BYPASS xaiv debugging los ntawm UJTAG thiab FlashPro header, thiab debugging los ntawm GPIO pins.
Lub Hom Phiaj # IR Code yog JTAG IR Code muab rau lub hom phiaj debug. Qhov no yuav tsum yog tus nqi tshwj xeeb hauv thaj tsam uas tau teev tseg hauv Table 2-1.
Simulation Flows
Tus neeg siv testbench yog muab nrog CoreJTAGDebug. Yuav ua li cas khiav simulations:
- Xaiv tus neeg siv testbench ntws hauv SmartDesign.
- Nyem Txuag thiab Tsim nyob rau hauv Tsim pane. Xaiv tus neeg siv testbench los ntawm Core Configuration GUI.
Thaum SmartDesign tsim Libero qhov project, nws teeb tsa tus neeg siv testbench files. Txhawm rau khiav tus neeg siv testbench:
- Teem lub hauv paus tsim rau CoreJTAGDebug instantiation hauv Libero tsim hierarchy pane.
- Nyem Txheeb Xyuas Pre-Synthesized Design> Simulate hauv Libero Design Flow window. Qhov no pib ModelSim thiab cia li khiav lub simulation.
Synthesis hauv Libero
Txhawm rau khiav Synthesis:
- Nyem lub Synthesize icon nyob rau hauv Libero SoC Design Flow qhov rais los ua ke cov tub ntxhais. Xwb, right-click the Synthesize option in the Design Flow window, and select Open Interactively. Lub qhov rais Synthesis qhia txog Synplify® qhov project.
- Nyem rau Khiav icon.
Nco tseg: Rau RTG4, muaj qhov xwm txheej hloov pauv (SET) mitigated ceeb toom, uas tuaj yeem tsis quav ntsej vim tias tus IP no tsuas yog siv rau kev tsim kho thiab yuav tsis siv rau hauv ib puag ncig hluav taws xob.
Qhov chaw-thiab-Route hauv Libero
Thaum Synthesis tiav lawm, nyem qhov Chaw thiab Route icon hauv Libero SoC los pib qhov kev tso kawm.
Device Programming
Yog tias UJAG_SEC feature tau siv thiab EN_SEC tau nce mus rau qhov chaw nres nkoj saum toj kawg nkaus (duab input tus pin), koj yuav tsum nkag mus rau Configure I/O States Thaum JTAG Kev ua haujlwm ntu ntawm Kev Tsim Kho hauv Libero ntws thiab xyuas kom meej tias I / 0 Lub Xeev (Tshaj Tawm Tsuas) rau EN_SEC chaw nres nkoj tau teeb tsa rau 1.
Qhov kev teeb tsa no yog qhov tsim nyog los tswj kev nkag mus rau JTAG chaw nres nkoj rau cov cuab yeej reprogramming, vim hais tias qhov kev txiav txim siab Boundary Scan Register (BSR) tus nqi overrides cov txheej txheem sab nraud ntawm EN_SEC thaum lub sijhawm reprogramming.
Kev sib koom ua ke
Cov tshooj hauv qab no tham txog cov ntaub ntawv hais txog kev sib koom ua ke.
System Level Design rau IGLOO2/RTG4
Cov duab hauv qab no qhia txog kev tsim qauv tsim los ua JTAG debugging ntawm softcore processor, nyob rau hauv cov ntaub ntawm SoftConsole mus rau JTAG interface rau IGLOO2 thiab RTG4 li.
Daim duab 5-1. RTG4/IGLOO2 JTAG Debug Design
System Level Design rau SmartFusion2
Cov duab hauv qab no qhia txog kev tsim qauv tsim los ua JTAG debugging ntawm softcore processor, nyob rau hauv ntaub los ntawm SoftConsole mus rau JTAG interface rau SmartFusion2 li.
Daim duab 5-2. SmartFusion 2 JTAG Debug Design
UJTAG_SEC
Rau PolarFire tsev neeg ntawm cov khoom siv, qhov kev tso tawm no tso cai rau tus neeg siv xaiv ntawm UJTAG and UJTAG_SEC, UASTAG_SEC_EN parameter hauv GUI yuav raug siv los xaiv qhov twg yog qhov xav tau.
Cov duab hauv qab no qhia txog daim duab yooj yim uas sawv cev rau lub cev sib cuam tshuam ntawm UJTAG/UJTAG_SEC hauv PolarFire.
Daim duab 5-3. PolarFire UJTAG_SEC Macro
Tsim Kev txwv
Cov qauv tsim nrog CoreJTAGDebug xav kom daim ntawv thov ua raws li cov kev txwv, nyob rau hauv tus tsim txaus, tso cai rau lub sij hawm tsom xam siv nyob rau hauv lub TCK moos sau.
Ntxiv cov kev txwv:
- Yog tias Kev Txhim Kho Kev Txwv Tsis Txaus Ntsig hauv Libero v11.7 lossis siab dua yog siv, nyem ob npaug rau kev txwv> Tswj Kev txwv hauv DesignFlow qhov rai thiab nyem lub sijhawm tab.
- Hauv Lub Sijhawm tab ntawm Constraint Manager window, nyem Tshiab los tsim SDC tshiab file, thiab npe file. Cov kev txwv tsim muaj xws li lub moos qhov kev txwv uas tuaj yeem nkag mus rau hauv SDC qhov khoob no file.
- Yog tias Classic Constraint ntws hauv Libero v11.7 los yog siab dua yog siv, right-click Create Constraints> Timing Constraint, nyob rau hauv lub Design Flow window, thiab tom qab ntawd nyem Tsim Tshiab Constraint. Nws tsim SDC tshiab file. Cov kev txwv tsim suav nrog cov kev txwv lub moos, uas tau nkag mus rau hauv SDC qhov khoob no file.
- Xam lub sijhawm TCK thiab ib nrab lub sijhawm. TCK yog teem rau 6 MHz thaum debugging ua tiav nrog FlashPro, thiab yog teem rau lub siab tshaj plaws zaus ntawm 30 MHz thaum debugging yog txaus siab los ntawm FlashPro5. Tom qab koj ua tiav cov kauj ruam no, nkag mus rau cov kev txwv hauv qab no hauv SDC file:
create_clock -name { TCK } \- lub sijhawm TCK_PERIOD \
- waveform { 0 TCK_HALF_PERIOD } \ [ get_ports { TCK } ] For example, cov kev txwv hauv qab no yog siv rau kev tsim uas siv TCK zaus ntawm 6 MHz.
create_clock -name { TCK } \ - lub sij hawm 166.67 \
- waveform { 0 83.33 } \ [ get_ports { TCK } ]
- Ua ke tag nrho cov kev txwv files nrog Synthesis, Place-and-Route, thiab Timing Verification stages hauv Constraint Manager > Timing tab. Qhov no ua tiav los ntawm kev xaiv cov thawv ntawv txheeb rau SDC files uas cov kev txwv tau nkag rau hauv
Kev kho keeb kwm
| Chaw nres nkoj npe | Dav | Kev taw qhia | Kev piav qhia |
| JTAG TAP Ports | |||
| TDI | 1 | Tswv yim | Test Cov ntaub ntawv hauv. Serial data input los ntawm TAP. |
| TCK | 1 | Tswv yim | Xeem moos. Lub moos qhov chaw rau tag nrho cov khoom sib txuas hauv CoreJTAGDebug. |
| TMS | 1 | Tswv yim | Test Hom Xaiv. |
| TDO | 1 | Tso zis | Test Data tawm. Serial cov ntaub ntawv tso zis rau TAP. |
| TRSTB | 1 | Tswv yim | Kuaj Pib dua. Active low reset input los ntawm TAP. |
| JTAG Lub Hom Phiaj X Ports | |||
| TGT_TDO_x | 1 | Tswv yim | Kuaj cov ntaub ntawv tawm ntawm debug phiaj x mus rau TAP. Txuas mus rau lub hom phiaj TDO chaw nres nkoj. |
| TGT_TTK_x | 1 | Tso zis | Test Clock tso zis rau debug lub hom phiaj x. TCK tau nce mus rau lub ntiaj teb, tsis tshua muaj skew net sab hauv hauv CoreJTAGDebug. |
| TGT_TRST_x | 1 | Tso zis | Active-High Test Reset. Tsuas yog siv thaum TGT_ACTIVE_HIGH_RESET_x = 1 |
| TGT_TRSTN_x | 1 | Tso zis | Active-Low Test Reset. Tsuas yog siv thaum TGT_ACTIVE_HIGH_RESET_x = 0 |
| TGT_TMS_x | 1 | Tso zis | Test hom Xaiv cov zis rau debug lub hom phiaj x. |
| TGT_TDI_x | 1 | Tso zis | Test Cov ntaub ntawv hauv. Serial cov ntaub ntawv tawm tswv yim los ntawm debug phiaj x. |
| UJTAG_BYPASS_TTK_x | 1 | Tswv yim | Kuaj Clock input rau debug phiaj x los ntawm GPIO tus pin. |
| UJTAG_BYPASS_TMS_x | 1 | Tswv yim | Test Hom Xaiv kom debug lub hom phiaj x los ntawm GPIO tus pin. |
| UJTAG_BYPASS_TDI_x | 1 | Tswv yim | Kuaj Cov Ntaub Ntawv Hauv, Cov ntaub ntawv Serial rau debug lub hom phiaj x los ntawm GPIO tus pin. |
| UJTAG_BYPASS_TRSTB_x | 1 | Tswv yim | Kuaj Pib dua. Pib dua cov tswv yim rau debug phiaj x los ntawm GPIO tus pin. |
| UJTAG_BYPASS_TDO_x | 1 | Tso zis | Test Data Out, Serial cov ntaub ntawv los ntawm debug phiaj x los ntawm GPIO tus pin. |
| SEC Chaw nres nkoj | |||
| EN_SEC | 1 | Tswv yim | Enables Kev Ruaj Ntseg. Ua kom tus neeg siv tsim los hla dhau TDI sab nraud thiab TRSTB cov tswv yim rau TAP.Ceev faj: Ua tib zoo saib xyuas thaum txuas qhov chaw nres nkoj no. Saib daim ntawv hauv qab no thiab ntaus ntawv Programming kom paub meej ntxiv. |
| TDI_SEC | 1 | Tswv yim | TDI Security override. Overrides lub sab nraud TDI cov tswv yim rau TAP thaum EN_SEC yog HIGH. |
| TRSTB_SEC | 1 | Tswv yim | TRSTB Security override. Overrides tus sab nraud TRSTB cov tswv yim rau TAP thaum SEC_EN yog HIGH. |
| UTRSTB | 1 | Tso zis | Kuaj Reset Monitor |
| UTMS | 1 | Tso zis | Test Hom Xaiv Saib |
Lub Microchip Webqhov chaw
Microchip muab kev txhawb nqa online ntawm peb website ntawm www.microchip.com/. Qhov no website yog siv los ua files thiab cov ntaub ntawv yooj yim muaj rau cov neeg siv khoom. Qee cov ntsiab lus muaj xws li:
- Khoom txhawb - Cov ntaub ntawv thiab cov ntaub ntawv tsis raug, daim ntawv thov thiab sample cov kev pab cuam, tsim cov peev txheej, cov neeg siv cov lus qhia thiab cov ntaub ntawv txhawb nqa kho vajtse, cov software tshiab tshaj tawm thiab cov software archived
- General Technical Support - Cov Lus Nug Nquag (FAQs), kev thov kev txhawb nqa, pab pawg sib tham hauv online, Microchip tsim tus khub koom nrog kev sau npe
- Kev lag luam ntawm Microchip - Cov khoom xaiv thiab cov lus qhia kev txiav txim, kev tshaj tawm xov xwm Microchip tshiab, cov npe ntawm cov rooj sib tham thiab cov xwm txheej, cov npe ntawm Microchip chaw muag khoom, cov neeg muag khoom thiab cov neeg sawv cev ntawm lub Hoobkas
Product Change Notification Service
Microchip cov khoom hloov kev ceeb toom kev pabcuam pab kom cov neeg siv khoom tam sim no ntawm Microchip cov khoom. Cov neeg sau npe yuav tau txais email ceeb toom thaum twg muaj kev hloov pauv, hloov tshiab, hloov kho lossis qhov tsis raug cuam tshuam nrog rau tsev neeg cov khoom lag luam lossis cov cuab yeej tsim kev txaus siab.
Mus rau npe, mus rau www.microchip.com/pcn thiab ua raws li cov lus qhia sau npe Cov Neeg Siv Khoom Cov neeg siv khoom ntawm Microchip tuaj yeem tau txais kev pab los ntawm ntau txoj hauv kev:
- Distributor lossis Tus Neeg Sawv Cev
- Lub Chaw Muag Khoom Hauv Zos
- Embedded Solutions Engineer (ESE)Technical Support Cov neeg siv khoom yuav tsum hu rau lawv tus neeg xa khoom, tus neeg sawv cev lossis ESE rau kev txhawb nqa. Cov chaw muag khoom hauv zos kuj muaj los pab cov neeg siv khoom. Cov npe ntawm cov chaw muag khoom thiab chaw nyob muaj nyob rau hauv daim ntawv no.
Kev pab txhawb nqa muaj nyob rau ntawm webqhov chaw ntawm: www.microchip.com/support
Microchip Devices Code Protection Feature
Nco ntsoov cov ntsiab lus hauv qab no ntawm tus lej tiv thaiv ntawm Microchip li:
- Cov khoom siv microchip ua tau raws li cov lus qhia tshwj xeeb uas muaj nyob rau hauv lawv cov ntaub ntawv Microchip tshwj xeeb.
- Microchip ntseeg hais tias nws tsev neeg ntawm cov khoom muaj kev ruaj ntseg thaum siv nyob rau hauv lub hom phiaj thiab nyob rau hauv ib txwm tej yam kev mob.
- Muaj cov kev tsis ncaj ncees thiab tej zaum yuav raug siv tsis raug cai hauv kev sim ua txhaum cai tiv thaiv cov yam ntxwv ntawm Microchip li. Peb ntseeg tias cov txheej txheem no yuav tsum tau siv cov khoom siv Microchip nyob rau hauv ib qho kev ua haujlwm sab nraud cov kev qhia tshwj xeeb uas muaj nyob hauv Microchip Cov Ntaub Ntawv Cov Ntawv. Kev sim ua txhaum cov cai tiv thaiv cov yam ntxwv, feem ntau yuav ua tsis tau tiav yam tsis ua txhaum Microchip txoj cai kev txawj ntse.
- Microchip txaus siab ua haujlwm nrog txhua tus neeg siv khoom uas txhawj xeeb txog kev ncaj ncees ntawm nws cov cai.
- Tsis yog Microchip lossis lwm lub chaw tsim khoom semiconductor tuaj yeem lav qhov kev ruaj ntseg ntawm nws cov cai. Kev tiv thaiv Code tsis txhais hais tias peb tau lees tias cov khoom yog "tsis tawg." Kev tiv thaiv code yog hloov zuj zus mus tas li. Peb ntawm Microchip tau cog lus tias yuav txhim kho txoj cai tiv thaiv cov yam ntxwv ntawm peb cov khoom tsis tu ncua. Kev sim ua txhaum Microchip's code tiv thaiv feature tej zaum yuav ua txhaum ntawm Digital Millennium Copyright Act. Yog tias qhov kev ua no tso cai rau koj nkag mus rau koj cov software lossis lwm yam haujlwm tsis raug cai, koj tuaj yeem muaj cai foob rau kev pab raws li Txoj Cai ntawd.
Daim Ntawv Ceeb Toom
Cov ntaub ntawv muaj nyob hauv daim ntawv tshaj tawm no yog muab rau tib lub hom phiaj ntawm kev tsim thiab siv cov khoom siv Microchip. Cov ntaub ntawv hais txog cov ntawv thov ntaus ntawv thiab cov zoo li tsuas yog muab rau koj yooj yim thiab yuav raug hloov pauv los ntawm kev hloov tshiab. Nws yog koj lub luag haujlwm los xyuas kom meej tias koj daim ntawv thov ua tau raws li koj cov lus qhia tshwj xeeb.
Cov ntaub ntawv no yog muab los ntawm microchip "raws li yog". MICROCHIP ua rau tsis muaj kev sawv cev
LUB TSEV KAWM NTAWV YUAV TSUM TAU TXAIS LUB SIJ HAWM NTAWM LUB SIJ HAWM NTAWM LUB SIJ HAWM NTAWM LUB SIJ HAWM NTAWM LUB TSEV
LUB SIJ HAWM NTAWM LUB SIJ HAWM NTAWM LUB SIJ HAWM NTAWM LUB TSEV KAWM NTAWV
WARRANTIES NTAWM NO INFRINGEMENT, MECHANT muaj peev xwm, thiab FITNESS rau ib tug tshwj xeeb lub hom phiaj los yog daim ntawv pov thawj muaj feem xyuam rau nws tej yam kev mob, zoo, los yog kev ua tau zoo. TSIS MUAJ IB TUG MICROCHIP yuav raug lav rau ib qho kev tsis ncaj ncees, tshwj xeeb, raug nplua, xwm txheej lossis cuam tshuam rau kev poob, kev puas tsuaj, raug nqi lossis kev siv nyiaj ntawm txhua yam uas cuam tshuam rau cov ntaub ntawv INVEREUS, LOSSIS YOG TAU TXAIS NTAWM LUB \ POSSIBILITY LUB SIJ HAWM YUAV TSUM PAUB TIAS. YUAV TSUM TAU TXAIS NTAWM TXOJ CAI, MICROCHIP'S TAG NRHO LIAB LIAB RAU TAG NRHO COV NTAUB NTAWV HAUV HAUV HAUV HAUV HAUV HAUV HAUV HAUV HAUV HAUV HAUV HAUV HAUV HAUV HAUJ LWM RAWS LI cov ntaub ntawv los yog nws siv yuav tsis tshaj cov nqi ntawm cov nqi, yog tias muaj, NTAWM KOJ YUAV TSUM PAUB. Kev siv cov khoom siv Microchip hauv kev txhawb nqa lub neej thiab / lossis daim ntawv thov kev nyab xeeb yog tag nrho ntawm tus neeg yuav khoom qhov kev pheej hmoo, thiab tus neeg yuav khoom pom zoo tiv thaiv, them nyiaj thiab tuav Microchip tsis raug mob los ntawm ib qho thiab tag nrho cov kev puas tsuaj, kev thov, foob, lossis cov nuj nqis uas tshwm sim los ntawm kev siv. Tsis muaj ntawv tso cai raug xa tawm, tsis hais los yog lwm yam, raws li cov cai ntawm Microchip cov cuab yeej cuab tam tshwj tsis yog hais tias lwm yam.
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Cov ntaub ntawv / Cov ntaub ntawv
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Microchip Technology CoreJTAGDebug Processors [ua pdf] Cov neeg siv phau ntawv qhia CoreJTAGDebug Processors, CoreJTAGDebug, processors |
