Microsemi SmartFusion2 MSS DDR Controller Configuration User Guide

SmartFusion 2 MSS
DDR Controller Configuration
Libero SoC v11.6 thiab tom qab ntawd

Cov ntsiab lus zais

1 Taw qhia

2 MDDR Configurator

3 MDDR Controller Configuration

4 Chaw nres nkoj piav qhia

5 Khoom txhawb

6 Cov ntaub ntawv / Cov ntaub ntawv

6.1 Cov ntaub ntawv

7 Related Posts

Taw qhia

Lub SmartFusion2 MSS muaj ib qho embedded DDR maub los. Qhov no DDR maub los yog npaj los tswj lub off-chip DDR nco. MDDR maub los tuaj yeem nkag tau los ntawm MSS thiab los ntawm FPGA ntaub. Tsis tas li ntawd, tus tswj hwm DDR kuj tseem tuaj yeem hla dhau, muab kev sib txuas ntxiv rau FPGA ntaub (Soft Controller Mode (SMC)).
Txhawm rau txhim kho MSS DDR maub los, koj yuav tsum:

Xaiv cov datapath siv MDDR Configurator.

Teem tus nqi sau npe rau DDR tswj cov npe.
Xaiv lub DDR nco moos zaus thiab FPGA ntaub rau MDDR moos piv (yog xav tau) siv MSS CCC Configurator.

Txuas tus maub los's APB configuration interface raws li tau hais los ntawm Peripheral Initialization tov. Rau MDDR Initialization circuitry tsim los ntawm System Builder, xa mus rau "MSS DDR Configuration Path" nyob rau nplooj 13 thiab daim duab 2-7.
Koj tuaj yeem tsim koj tus kheej kev pib circuitry siv standalone (tsis yog los ntawm System Builder) Peripheral Initialization. Xa mus rau SmartFusion2 Standalone Peripheral Initialization User Guide.

MDDR Configurator

MDDR Configurator yog siv los teeb tsa tag nrho datapath thiab sab nraud DDR Memory Parameters rau MSS DDR maub los.

General tab teeb tsa koj lub cim xeeb thiab Fabric Interface chaw (Daim duab 1-1).
Memory Settings
Nkag mus rau DDR Memory Settling Time. Nov yog lub sijhawm DDR lub cim xeeb yuav tsum tau pib. Tus nqi pib yog 200 peb. Xa mus rau koj daim DDR Memory Data Sheet rau tus nqi raug nkag.
Siv Memory Settings los teeb tsa koj cov kev xaiv nco hauv MDDR.

Hom Nco - LPDDR, DDR2, lossis DDR3
Cov ntaub ntawv dav - 32-ntsis, 16-ntsis lossis 8-ntsis

SECDED Enabled ECC - ON lossis OFF
Kev Txiav Txim Siab - Hom-0, Hom-1, Hom-2, Hom-3

Qhov tseem ceeb tshaj plaws ID - Qhov tseem ceeb siv tau yog los ntawm 0 txog 15
Chaw Nyob Dav (ntsis) - Xa mus rau koj daim ntawv DDR Memory Data Sheet rau cov naj npawb ntawm kab, lub txhab nyiaj, thiab kab nyob hauv kab rau LPDDR / DDR2 / DDR3 nco koj siv. xaiv cov ntawv qhia rub-down los xaiv tus nqi raug rau kab / tsev txhab nyiaj / kab raws li cov ntaub ntawv ntawm LPDDR / DDR2 / DDR3 nco.

Nco tseg: Tus lej hauv daim ntawv rub-down yog hais txog tus lej ntawm Chaw Nyob, tsis yog tus lej ntawm kab / txhab nyiaj / kab. Rau example, yog tias koj lub cim xeeb DDR muaj 4 lub tsev txhab nyiaj, xaiv 2 (2 ² = 4) rau cov tsev txhab nyiaj. Yog tias koj lub cim xeeb DDR muaj 8 lub tsev txhab nyiaj, xaiv 3 (2³ = 8) rau cov tsev txhab nyiaj.

Fabric Interface Settings
Los ntawm lub neej ntawd, lub zog Cortex-M3 processor tau teeb tsa kom nkag mus rau DDR Controller. Koj tseem tuaj yeem tso cai rau Fabric Master nkag mus rau DDR Controller los ntawm kev tso cai rau Fabric Interface Setting checkbox. Hauv qhov no, koj tuaj yeem xaiv ib qho ntawm cov kev xaiv hauv qab no:

Siv AXI Interface - Cov ntaub Master nkag mus rau DDR Controller los ntawm 64-ntsis AXI interface.
Siv Ib Leeg AHBLite Interface - Cov ntaub Master nkag mus rau DDR Controller los ntawm ib qho 32-ntsis AHB interface.

Siv ob AHBLite Interfaces - Ob daim ntaub Masters nkag mus rau DDR Controller siv ob 32-ntsis AHB interfaces.
Lub configuration view (Daim duab 1-1) hloov tshiab raws li koj qhov kev xaiv Fabric Interface.

I/O Tsav Zog (DDR2 thiab DDR3 nkaus xwb)
Xaiv ib qho ntawm cov hauv qab no lub zog tsav rau koj DDR I/Os:

Ib nrab Tsav Zog
Tag Nrho Tsav Zog

Libero SoC teeb tsa DDR I/O Standard rau koj MDDR system raws li koj hom DDR Memory thiab I/O Drive Strength (raws li qhia hauv Tab le 1-1).
Table 1-1 • I/O Drive Strength thiab DDR Memory Type

DDR Nco Hom	Ib nrab Lub Zog Tsav	Full Strength Drive
DDR 3	SSTL15I	TIAB SA 15 II
DDR 2	SSTL18I	TIAB SA 18 II
LPDDR	LPDRI	LPDRII

IO Standard (LPDDR nkaus xwb)
Xaiv ib qho ntawm cov kev xaiv hauv qab no:

LVCMOS18 (Lowest Power) rau LVCMOS 1.8V IO tus qauv. Siv rau hauv cov ntawv thov LPDDR1.
LPDDRI Nco tseg: Ua ntej koj xaiv tus qauv no, xyuas kom koj lub rooj tsavxwm txhawb nqa tus qauv no. Koj yuav tsum siv qhov kev xaiv no thaum tsom rau M2S-EVAL-KIT lossis SF2-STARTER-KIT boards. LPDDRI IO cov qauv xav kom muaj IMP_CALIB resistor raug ntsia rau ntawm lub rooj tsavxwm.

IO Calibration (LPDDR nkaus xwb)
Xaiv ib qho ntawm cov kev xaiv hauv qab no thaum siv LVCMOS18 IO tus qauv:

Off (Tswj)

Calibration ON thiab OFF optionally tswj kev siv ntawm IO calibration block uas calibrates IO tsav mus rau ib tug sab nraud resistor. Thaum OFF, lub cuab yeej siv preset IO tsav tsheb hloov.
Thaum ON, qhov no yuav tsum muaj 150-ohm IMP_CALIB resistor los nruab rau ntawm PCB.
Qhov no yog siv los ntsuas IO rau cov yam ntxwv ntawm PCB. Txawm li cas los xij, thaum teem rau ON, tus resistor yuav tsum tau nruab los yog lub cim xeeb tswj yuav tsis pib.
Yog xav paub ntxiv, xa mus rau AC393-SmartFusion2 thiab IGLOO2 Board Design Guidelines Application
Nco tseg thiab SmartFusion2 SoC FPGA High Speed DDR Interfaces User Guide.

MDDR Controller Configuration

Thaum koj siv MSS DDR Controller kom nkag mus rau sab nraud DDR Nco, DDR Controller yuav tsum tau teeb tsa thaum lub sijhawm ua haujlwm. Qhov no yog ua los ntawm kev sau cov ntaub ntawv teeb tsa rau DDR kev tswj hwm kev teeb tsa kev sau npe. Cov ntaub ntawv teeb tsa no yog nyob ntawm tus yam ntxwv ntawm lub cim xeeb sab nraud DDR thiab koj daim ntawv thov. Tshooj lus no piav qhia txog yuav ua li cas nkag mus rau cov kev teeb tsa no hauv MSS DDR controller configurator thiab yuav ua li cas cov ntaub ntawv teeb tsa raug tswj raws li ib feem ntawm tag nrho Peripheral Initialization daws.

MSS DDR Control Registers
MSS DDR Controller muaj cov txheej txheem sau npe uas yuav tsum tau teeb tsa thaum lub sijhawm ua haujlwm. Cov nqi tsim nyog rau cov ntawv sau npe no sawv cev rau qhov sib txawv, xws li DDR hom, PHY dav, hom tawg, thiab ECC. Yog xav paub meej txog DDR controller configuration registers, xa mus rau SmartFusion2 SoC FPGA High Speed DDR Interfaces User's Guide.
MDDR Registers Configuration
Siv lub cim xeeb Initialization (Daim duab 2-1, Daim duab 2-2, thiab daim duab 2-3) thiab Lub Sijhawm Nco (Daim duab 2-4) tabs txhawm rau nkag mus rau qhov tsis sib xws rau koj lub cim xeeb DDR thiab daim ntawv thov. Cov txiaj ntsig koj nkag rau hauv cov tab no tau muab txhais ua qhov tsim nyog rau npe. Thaum koj nyem ib qho kev txwv tshwj xeeb, nws cov ntawv sau npe sib raug tau piav qhia nyob rau hauv Daim Ntawv Sau Npe Pane (qis dua hauv daim duab 1-1 ntawm nplooj ntawv 4).
Nco Initialization
Lub Memory Initialization tab tso cai rau koj los teeb tsa txoj hauv kev uas koj xav kom koj lub LPDDR / DDR2 / DDR3 nco pib. Cov ntawv qhia zaub mov thiab cov kev xaiv muaj nyob rau hauv Memory Initialization tab txawv nrog hom DDR nco (LPDDR/DDR2/DDR3) koj siv. Xa mus rau koj daim DDR Memory Data Sheet thaum koj teeb tsa cov kev xaiv. Thaum koj hloov lossis nkag mus rau tus nqi, Daim Ntawv Sau Npe Qhia pane muab koj lub npe sau npe thiab sau npe tus nqi uas hloov kho. Cov nqi tsis raug raug chij ua lus ceeb toom. Daim duab 2-1, Daim duab 2-2, thiab Daim duab 2-3 qhia qhov Initialization tab rau LPDDR, DDR2 thiab DDR3, feem.

Sijhawm hom - Xaiv 1T lossis 2T Sijhawm hom. Hauv 1T (tus qauv ua ntej), tus tswj hwm DDR tuaj yeem tshaj tawm cov lus txib tshiab ntawm txhua lub voj voog moos. Hauv 2T lub sij hawm hom, DDR maub los tuav qhov chaw nyob thiab hais kom lub tsheb npav siv tau rau ob lub moos. Qhov no txo cov kev ua haujlwm ntawm lub tsheb npav mus rau ib qho kev hais kom ua rau ob lub moos, tab sis nws ua rau ob npaug ntawm kev teeb tsa thiab tuav lub sijhawm.
Ib nrab-Array Self Refresh (LPDDR nkaus xwb). Cov yam ntxwv no yog rau kev txuag hluav taws xob rau LPDDR.
Xaiv ib qho ntawm cov hauv qab no rau tus maub los kom rov ua kom lub cim xeeb rov qab thaum lub sijhawm rov ua tus kheej:
- Tag nrho cov array: Ntug dej 0, 1,2, thiab 3
- Ib nrab array: Lub txhab nyiaj 0 thiab 1
- Lub quarter array: Bank 0
- Ib-yim array: Bank 0 nrog kab chaw nyob MSB = 0
- Ib-kaum kaum rau: Lub txhab nyiaj 0 nrog kab chaw nyob MSB thiab MSB-1 ob qho tib si sib npaug rau 0.
Rau tag nrho lwm cov kev xaiv, xa mus rau koj daim ntawv DDR Memory Data Sheet thaum koj teeb tsa cov kev xaiv.

Lub Sijhawm Nco
Cov tab no tso cai rau koj los teeb tsa Lub Sijhawm Memory tsis txwv. Xa mus rau Daim Ntawv Teev Npe ntawm koj lub cim xeeb LPDDR / DDR2 / DDR3 thaum teeb tsa Lub Sijhawm Memory.
Thaum koj hloov lossis nkag mus rau tus nqi, Daim Ntawv Sau Npe Qhia pane muab koj lub npe sau npe thiab sau npe tus nqi uas hloov kho. Cov nqi tsis raug raug chij ua lus ceeb toom.

Importing DDR Configuration Files
Ntxiv rau kev nkag mus rau DDR Memory tsis siv lub cim xeeb pib thiab Lub Sijhawm tab, koj tuaj yeem import DDR cov nqi sau npe los ntawm ib qho file. Txhawm rau ua li ntawd, nyem qhov Ntshuam Configuration khawm thiab mus rau cov ntawv nyeem file muaj DDR sau npe thiab cov nqi. Daim duab 2-5 qhia tau hais tias ntshuam configuration syntax.

Nco tseg: Yog tias koj xaiv import tus nqi sau npe ntau dua li nkag mus rau lawv siv GUI, koj yuav tsum qhia tag nrho cov nqi sau npe tsim nyog. Xa mus rau SmartFusion2 SoC FPGA High Speed DDR Interfaces Tus Neeg Siv Phau Ntawv Qhia kom paub meej.

Exporting DDR Configuration Files
Koj tseem tuaj yeem xa cov ntaub ntawv sau npe tam sim no rau hauv cov ntawv nyeem file. Qhov no file yuav muaj cov nqi sau npe uas koj tau xa tuaj (yog tias muaj) nrog rau cov uas tau suav los ntawm GUI tsis tau koj nkag rau hauv qhov kev sib tham no.
Yog tias koj xav thim rov qab cov kev hloov pauv uas koj tau ua rau DDR rau npe teeb tsa, koj tuaj yeem ua li ntawd nrog Restore Default. Nco ntsoov tias qhov no tshem tawm tag nrho cov ntaub ntawv teev npe teeb tsa thiab koj yuav tsum rov ua dua lossis rov sau cov ntaub ntawv no. Cov ntaub ntawv rov pib dua rau qhov kho vajtse rov pib dua qhov tseem ceeb.
Cov ntaub ntawv tsim tawm
Nyem OK los tsim cov kev teeb tsa. Raws li koj cov tswv yim hauv General, Memory Timing thiab Memory Initialization tabs, MDDR Configurator suav cov txiaj ntsig rau tag nrho DDR teeb tsa kev sau npe thiab xa tawm cov txiaj ntsig no rau hauv koj qhov project firmware thiab simulation. files. Cov exported file syntax muaj nyob rau hauv daim duab 2-6.

Firmware

Thaum koj tsim SmartDesign, cov hauv qab no files yog generated nyob rau hauv lub /firmware/ drivers_config/sys_config directory. Cov no files yog xav tau rau CMSIS firmware core kom muab tso ua ke kom raug thiab muaj cov ntaub ntawv hais txog koj qhov kev tsim tam sim no suav nrog cov ntaub ntawv teeb tsa peripheral thiab cov ntaub ntawv teev teev rau MSS. Tsis txhob hloov cov no files manually raws li lawv tau rov tsim dua txhua zaus koj lub hauv paus tsim rov tsim dua.

sys_config.c
sys_config.h

sys_config_mddr_define.h – MDDR configuration data.
Sys_config_fddr_define.h – FDDR configuration data.
sys_config_mss_clocks.h – MSS moos configuration

Kev simulation
Thaum koj tsim SmartDesign cuam tshuam nrog koj MSS, simulation hauv qab no files yog generated nyob rau hauv lub / simulation directory:

test.bfm – Qib BFM file uas yog thawj zaug "tua" thaum lub sijhawm simulation uas ua haujlwm ntawm SmartFusion2 MSS 'Cortex-M3 processor. Nws ua haujlwm peripheral_init.bfm thiab user.bfm, hauv qhov kev txiav txim ntawd.
peripheral_init.bfm – Muaj cov txheej txheem BFM uas emulates CMSIS::SystemInit() muaj nuj nqi khiav ntawm Cortex-M3 ua ntej koj nkag mus rau lub ntsiab() txheej txheem. Nws yog qhov tseem ceeb luam cov ntaub ntawv teeb tsa rau ib qho khoom siv peripheral siv hauv kev tsim kom raug peripheral configuration registers thiab ces tos rau tag nrho cov peripheral npaj ua ntej hais tias tus neeg siv yuav siv tau cov peripherals.

MDDR_init.bfm - Muaj BFM sau cov lus txib uas simulate sau ntawm MSS DDR teeb tsa kev sau npe cov ntaub ntawv uas koj tau nkag mus (siv cov Edit Registers dialog saum toj no) rau hauv DDR Controller sau npe.
user.bfm - Npaj rau cov neeg siv cov lus txib. Koj tuaj yeem simulate datapath los ntawm kev ntxiv koj tus kheej BFM cov lus txib hauv qhov no file. Cov lus txib hauv qhov no file yuav raug "ua tiav" tom qab peripheral_init.bfm ua tiav.

Siv cov files saum toj no, txoj kev configuration yog simulated txiav. Koj tsuas yog yuav tsum hloov kho user.bfm file los simulate datapath. Tsis txhob hloov qhov test.bfm, peripheral_init.bfm, lossis MDDR_init.bfm files as cov files yog rov tsim dua txhua zaus koj lub hauv paus tsim rov tsim dua.

MSS DDR Configuration Path
Txoj kev daws teeb meem Peripheral Initialization xav kom, ntxiv rau qhov qhia meej txog MSS DDR teeb tsa kev sau npe qhov tseem ceeb, koj teeb tsa APB teeb tsa cov ntaub ntawv kab hauv MSS (FIC_2). Qhov SystemInit() muaj nuj nqi sau cov ntaub ntawv rau MDDR teeb tsa kev sau npe ntawm FIC_2 APB interface.
Nco tseg: Yog tias koj siv System Builder txoj kev teeb tsa tau teeb tsa thiab txuas nrog txiav.

Txhawm rau teeb tsa FIC_2 interface:

Qhib FIC_2 configurator dialog (Daim duab 2-7) los ntawm MSS configurator.
Xaiv qhov Initialize peripherals siv Cortex-M3 kev xaiv.
Nco ntsoov tias MSS DDR raug kuaj xyuas, zoo li Fabric DDR / SERDES thaiv yog tias koj siv lawv.

Nyem OK kom txuag koj qhov chaw. Qhov no yuav nthuav tawm FIC_2 configuration ports (Clock, Reset, thiab APB bus interfaces), raws li qhia hauv daim duab 2-8.
Tsim MSS. Lub FIC_2 cov chaw nres nkoj (FIC_2_APB_MASTER, FIC_2_APB_M_PCLK thiab FIC_2_APB_M_RESET_N) tam sim no nthuav tawm ntawm MSS interface thiab tuaj yeem txuas nrog CoreConfigP thiab CoreResetP raws li Peripheral Initialization tov specification.

Txhawm rau ua kom tiav cov ntsiab lus ntawm kev teeb tsa thiab txuas CoreConfigP thiab CoreResetP cores, xa mus rau Peripheral Initialization User Guide.

Chaw nres nkoj piav qhia

DDR PHY Interface
Table 3-1 • DDR PHY Interface

Chaw nres nkoj npe	Kev taw qhia	Kev piav qhia
MDDR_CAS_N	Tawm	DRAM CASN
MDDR_CKE	Tawm	DRAM CKE
MDDR_CLK	Tawm	moos, P sab
MDDR_CLK_N	Tawm	moos, N sab
MDDR_CS_N	Tawm	DRAM CSN
MDDR_ODT	Tawm	DRAM ODT
MDDR_RAS_N	Tawm	DRAM RASN
MDDR_RESET_N	Tawm	DRAM Reset rau DDR3. Tsis quav ntsej cov teeb liab no rau LPDDR thiab DDR2 Interfaces. Kos nws tsis siv rau LPDDR thiab DDR2 Interfaces.
MDDR_WE_N	Tawm	DRAM WEN
MDDR_ADDR[15:0]	Tawm	Dram Address bits
MDDR_BA[2:0]	Tawm	Dram Bank Chaw Nyob
MDDR_DM_RDQS ([3:0]/[1:0]/[0])	NCO	Dram Data Mask
MDDR_DQS ([3:0]/[1:0]/[0])	NCO	Dram Data Strobe Input/Output – P Sab
MDDR_DQS_N ([3:0]/[1:0]/[0])	NCO	Dram Data Strobe Input/Output – N Sab
MDDR_DQ ([31:0]/[15:0]/[7:0])	NCO	DRAM Cov ntaub ntawv nkag / tawm
MDDR_DQS_TMATCH_0_IN	IN	FIFO hauv teeb liab
MDDR_DQS_TMATCH_0_OUT	Tawm	FIFO tawm signal
MDDR_DQS_TMATCH_1_IN	IN	FIFO hauv teeb liab (32-ntsis nkaus xwb)
MDDR_DQS_TMATCH_1_OUT	Tawm	FIFO tawm teeb liab (32-ntsis nkaus xwb)
MDDR_DM_RDQS_ECC	NCO	Dram ECC Data Mask
MDDR_DQS_ECC	NCO	Dram ECC Data Strobe Input/Output – P Sab
MDDR_DQS_ECC_N	NCO	Dram ECC Data Strobe Input/Output – N Sab
MDDR_DQ_ECC ([3:0]/[1:0]/[0])	NCO	DRAM ECC Cov ntaub ntawv nkag / tawm
MDDR_DQS_TMATCH_ECC_IN	IN	ECC FIFO hauv teeb liab
MDDR_DQS_TMATCH_ECC_OUT	Tawm	ECC FIFO tawm teeb liab (32-ntsis nkaus xwb)

Nco tseg: Qhov dav ntawm qhov chaw nres nkoj rau qee qhov chaw nres nkoj hloov raws li kev xaiv ntawm PHY dav. Cov cim "[a:0]/ [b:0]/[c:0]" yog siv los qhia cov chaw nres nkoj, qhov twg "[a:0]" yog hais txog qhov chaw nres nkoj dav thaum xaiv 32-ntsis PHY dav. , "[b:0]" sib raug rau 16-ntsis PHY dav, thiab "[c:0]" sib raug rau 8-ntsis PHY dav.

Fabric Master AXI Bus Interface
Table 3-2 • Fabric Master AXI Bus Interface

Chaw nres nkoj npe	Kev taw qhia	Kev piav qhia
DDR_AXI_S_AWREADY	Tawm	Sau chaw nyob npaj txhij
DDR_AXI_S_WREADY	Tawm	Sau chaw nyob npaj txhij
DDR_AXI_S_BID[3:0]	Tawm	Teb ID
DDR_AXI_S_BRESP[1:0]	Tawm	Sau cov lus teb
DDR_AXI_S_BVALID	Tawm	Sau cov lus teb siv tau
DDR_AXI_S_ARREADY	Tawm	Nyeem qhov chaw nyob npaj
DDR_AXI_S_RID[3:0]	Tawm	Nyeem ID Tag
DDR_AXI_S_RRESP[1:0]	Tawm	Nyeem Teb
DDR_AXI_S_RDATA[63:0]	Tawm	Nyeem cov ntaub ntawv
DDR_AXI_S_RLAST	Tawm	Nyeem Kawg Qhov teeb liab no qhia txog kev hloov pauv zaum kawg hauv kev nyeem ntawv tawg
DDR_AXI_S_RVALID	Tawm	Nyeem qhov chaw nyob siv tau
DDR_AXI_S_AWID[3:0]	IN	Sau ID Chaw Nyob
DDR_AXI_S_AWADDR[31:0]	IN	Sau chaw nyob
DDR_AXI_S_AWLEN[3:0]	IN	tawg ntev
DDR_AXI_S_AWSIZE[1:0]	IN	tawg loj
DDR_AXI_S_AWBURST[1:0]	IN	Hom tawg
DDR_AXI_S_AWLOCK[1:0]	IN	Xauv hom Lub teeb liab no muab cov ntaub ntawv ntxiv txog cov yam ntxwv atomic ntawm kev hloov pauv
DDR_AXI_S_AWVALID	IN	Sau qhov chaw nyob siv tau
DDR_AXI_S_WID[3:0]	IN	Sau cov ntaub ntawv ID tag
DDR_AXI_S_WDATA[63:0]	IN	Sau cov ntaub ntawv
DDR_AXI_S_WSTRB[7:0]	IN	Sau strobes
DDR_AXI_S_WLAST	IN	Sau ntawv kawg
DDR_AXI_S_WVALID	IN	Sau siv tau
DDR_AXI_S_BREADY	IN	Sau ntawv npaj txhij
DDR_AXI_S_ARID[3:0]	IN	Nyeem Qhov Chaw Nyob ID
DDR_AXI_S_ARADDR[31:0]	IN	Nyeem qhov chaw nyob
DDR_AXI_S_ARLEN[3:0]	IN	tawg ntev
DDR_AXI_S_ARSIZE[1:0]	IN	tawg loj
DDR_AXI_S_ARBUST[1:0]	IN	Hom tawg
DDR_AXI_S_ARLOCK[1:0]	IN	Hom xauv
DDR_AXI_S_ARVALID	IN	Nyeem qhov chaw nyob siv tau
DDR_AXI_S_RREADY	IN	Nyeem qhov chaw nyob npaj

Table 3-2 • Fabric Master AXI Bus Interface (txuas ntxiv)

Chaw nres nkoj npe	Kev taw qhia	Kev piav qhia
DDR_AXI_S_CORE_RESET_N	IN	MDDR Ntiaj teb no Reset
DDR_AXI_S_RMW	IN	Qhia seb tag nrho cov bytes ntawm 64 me ntsis txoj kab siv tau rau txhua qhov kev sib tw ntawm AXI hloov chaw. 0: Qhia tias tag nrho cov bytes nyob rau hauv tag nrho cov neeg ntaus yeej siv tau nyob rau hauv lub tawg thiab tus maub los yuav tsum tau default los sau commands 1: Qhia tias qee cov bytes tsis raug thiab tus maub los yuav tsum ua raws li RMW cov lus txib Qhov no yog classed raws li AXI sau chaw nyob channel sideband teeb liab thiab siv tau nrog AWVALID teeb liab. Tsuas yog siv thaum ECC qhib.

Fabric Master AHB0 Bus Interface
Table 3-3 • Fabric Master AHB0 Bus Interface

Chaw nres nkoj npe	Kev taw qhia	Kev piav qhia
DDR_AHB0_SHREADYOUT	Tawm	AHBL qhev npaj - Thaum siab rau kev sau ntawv qhia tias MDDR tau npaj los lees txais cov ntaub ntawv thiab thaum siab nyeem ntawv qhia tias cov ntaub ntawv siv tau
DDR_AHB0_SHRESP	Tawm	AHBL cov xwm txheej teb - Thaum tsav siab thaum kawg ntawm kev sib pauv qhia tias kev hloov pauv tau ua tiav nrog qhov yuam kev. Thaum tsav qis thaum kawg ntawm kev sib pauv qhia tias qhov kev sib pauv tau ua tiav tiav.
DDR_AHB0_SHRDATA[31:0]	Tawm	AHBL nyeem cov ntaub ntawv - Nyeem cov ntaub ntawv los ntawm MDDR qhev rau tus tswv ntaub
DDR_AHB0_SHSEL	IN	AHBL qhev xaiv - Thaum lees paub, MDDR yog tam sim no xaiv AHBL qhev ntawm daim ntaub AHB tsheb npav
DDR_AHB0_SHADDR[31:0]	IN	AHBL chaw nyob - byte chaw nyob ntawm AHBL interface
DDR_AHB0_SHBURST[2:0]	IN	AHBL tawg Length
DDR_AHB0_SHSIZE[1:0]	IN	AHBL hloov pauv loj - Qhia qhov loj ntawm kev hloov pauv tam sim no (8/16/32 byte kev lag luam nkaus xwb)
DDR_AHB0_SHTRANS[1:0]	IN	AHBL hloov hom - Qhia txog hom kev hloov pauv ntawm kev hloov pauv tam sim no
DDR_AHB0_SHMASTLOCK	IN	AHBL xauv - Thaum lees paub qhov kev hloov pauv tam sim no yog ib feem ntawm kev lag luam xauv
DDR_AHB0_SHWRITE	IN	AHBL sau - Thaum siab qhia tias kev hloov pauv tam sim no yog sau. Thaum qis qhia tias qhov kev hloov pauv tam sim no yog nyeem
DDR_AHB0_S_HREADY	IN	AHBL npaj txhij - Thaum siab, qhia tias MDDR tau npaj los lees txais kev hloov pauv tshiab
DDR_AHB0_S_HWDATA[31:0]	IN	AHBL sau cov ntaub ntawv - Sau cov ntaub ntawv los ntawm tus tswv ntaub rau MDDR

Fabric Master AHB1 Bus Interface
Table 3-4 • Fabric Master AHB1 Bus Interface

Chaw nres nkoj npe	Kev taw qhia	Kev piav qhia
DDR_AHB1_SHREADYOUT	Tawm	AHBL qhev npaj - Thaum siab rau kev sau ntawv qhia tias MDDR tau npaj los lees txais cov ntaub ntawv thiab thaum siab nyeem ntawv qhia tias cov ntaub ntawv siv tau
DDR_AHB1_SHRESP	Tawm	AHBL cov xwm txheej teb - Thaum tsav siab thaum kawg ntawm kev sib pauv qhia tias kev hloov pauv tau ua tiav nrog qhov yuam kev. Thaum tsav qis thaum kawg ntawm kev sib pauv qhia tias qhov kev sib pauv tau ua tiav tiav.
DDR_AHB1_SHRDATA[31:0]	Tawm	AHBL nyeem cov ntaub ntawv - Nyeem cov ntaub ntawv los ntawm MDDR qhev rau tus tswv ntaub
DDR_AHB1_SHSEL	IN	AHBL qhev xaiv - Thaum lees paub, MDDR yog tam sim no xaiv AHBL qhev ntawm daim ntaub AHB tsheb npav
DDR_AHB1_SHADDR[31:0]	IN	AHBL chaw nyob - byte chaw nyob ntawm AHBL interface
DDR_AHB1_SHBURST[2:0]	IN	AHBL tawg Length
DDR_AHB1_SHSIZE[1:0]	IN	AHBL hloov pauv loj - Qhia qhov loj ntawm kev hloov pauv tam sim no (8/16/32 byte kev lag luam nkaus xwb)
DDR_AHB1_SHTRANS[1:0]	IN	AHBL hloov hom - Qhia txog hom kev hloov pauv ntawm kev hloov pauv tam sim no
DDR_AHB1_SHMASTLOCK	IN	AHBL xauv - Thaum lees paub qhov kev hloov pauv tam sim no yog ib feem ntawm kev lag luam xauv
DDR_AHB1_SHWRITE	IN	AHBL sau - Thaum siab qhia tias kev hloov pauv tam sim no yog sau. Thaum qis qhia tias qhov kev hloov pauv tam sim no yog nyeem.
DDR_AHB1_SHREADY	IN	AHBL npaj txhij - Thaum siab, qhia tias MDDR tau npaj los lees txais kev hloov pauv tshiab
DDR_AHB1_SHWDATA[31:0]	IN	AHBL sau cov ntaub ntawv - Sau cov ntaub ntawv los ntawm tus tswv ntaub rau MDDR

Soft Memory Controller Hom AXI Bus Interface
Table 3-5 • Mos Memory Controller Hom AXI Bus Interface

Chaw nres nkoj npe	Kev taw qhia	Kev piav qhia
SMC_AXI_M_WLAST	Tawm	Sau ntawv kawg
SMC_AXI_M_WVALID	Tawm	Sau siv tau
SMC_AXI_M_AWLEN[3:0]	Tawm	tawg ntev
SMC_AXI_M_AWBURST[1:0]	Tawm	Hom tawg
SMC_AXI_M_BREADY	Tawm	Teb npaj txhij
SMC_AXI_M_AWVALID	Tawm	Sau Chaw Nyob Muaj Cai
SMC_AXI_M_AWID[3:0]	Tawm	Sau ID Chaw Nyob
SMC_AXI_M_WDATA[63:0]	Tawm	Sau cov ntaub ntawv
SMC_AXI_M_ARVALID	Tawm	Nyeem qhov chaw nyob siv tau
SMC_AXI_M_WID[3:0]	Tawm	Sau cov ntaub ntawv ID tag
SMC_AXI_M_WSTRB[7:0]	Tawm	Sau strobes
SMC_AXI_M_ARID[3:0]	Tawm	Nyeem Qhov Chaw Nyob ID
SMC_AXI_M_ARADDR[31:0]	Tawm	Nyeem qhov chaw nyob
SMC_AXI_M_ARLEN[3:0]	Tawm	tawg ntev
SMC_AXI_M_ARSIZE[1:0]	Tawm	tawg loj
SMC_AXI_M_ARBURST[1:0]	Tawm	Hom tawg
SMC_AXI_M_AWADDR[31:0]	Tawm	Sau Chaw Nyob
SMC_AXI_M_RREADY	Tawm	Nyeem qhov chaw nyob npaj
SMC_AXI_M_AWSIZE[1:0]	Tawm	tawg loj
SMC_AXI_M_AWLOCK[1:0]	Tawm	Xauv hom Lub teeb liab no muab cov ntaub ntawv ntxiv txog cov yam ntxwv atomic ntawm kev hloov pauv
SMC_AXI_M_ARLOCK[1:0]	Tawm	Hom xauv
SMC_AXI_M_BID[3:0]	IN	Teb ID
SMC_AXI_M_RID[3:0]	IN	Nyeem ID Tag
SMC_AXI_M_RRESP[1:0]	IN	Nyeem Teb
SMC_AXI_M_BRESP[1:0]	IN	Sau cov lus teb
SMC_AXI_M_AWREADY	IN	Sau chaw nyob npaj txhij
SMC_AXI_M_RDATA[63:0]	IN	Nyeem cov ntaub ntawv
SMC_AXI_M_WREADY	IN	Sau ntawv npaj txhij
SMC_AXI_M_BVALID	IN	Sau cov lus teb siv tau
SMC_AXI_M_ARREADY	IN	Nyeem qhov chaw nyob npaj
SMC_AXI_M_RLAST	IN	Nyeem Kawg Qhov teeb liab no qhia txog kev hloov pauv zaum kawg hauv kev nyeem ntawv tawg
SMC_AXI_M_RVALID	IN	Nyeem siv tau

Mos Memory Controller Hom AHB0 Bus Interface
Table 3-6 • Mos Memory Controller Hom AHB0 Bus Interface

Chaw nres nkoj npe	Kev taw qhia	Kev piav qhia
SMC_AHB_M_HBURST[1:0]	Tawm	AHBL tawg Length
SMC_AHB_M_HTRANS[1:0]	Tawm	AHBL hloov hom - Qhia txog hom kev hloov pauv ntawm kev hloov pauv tam sim no.
SMC_AHB_M_HMASTLOCK	Tawm	AHBL xauv - Thaum lees paub qhov kev hloov pauv tam sim no yog ib feem ntawm kev lag luam xauv
SMC_AHB_M_HWRITE	Tawm	AHBL sau - Thaum siab qhia tias kev hloov pauv tam sim no yog sau. Thaum qis qhia tias qhov kev hloov pauv tam sim no yog nyeem
SMC_AHB_M_HSIZE[1:0]	Tawm	AHBL hloov pauv loj - Qhia qhov loj ntawm kev hloov pauv tam sim no (8/16/32 byte kev lag luam nkaus xwb)
SMC_AHB_M_HWDATA[31:0]	Tawm	AHBL sau cov ntaub ntawv - Sau cov ntaub ntawv los ntawm MSS tus tswv rau cov ntaub mos Memory Controller
SMC_AHB_M_HADDR[31:0]	Tawm	AHBL chaw nyob - byte chaw nyob ntawm AHBL interface
SMC_AHB_M_HRESP	IN	AHBL cov xwm txheej teb - Thaum tsav siab thaum kawg ntawm kev sib pauv qhia tias kev hloov pauv tau ua tiav nrog qhov yuam kev. Thaum tsav qis thaum kawg ntawm kev sib pauv qhia tias qhov kev sib pauv tau ua tiav tiav
SMC_AHB_M_HRDATA[31:0]	IN	AHBL nyeem cov ntaub ntawv - Nyeem cov ntaub ntawv los ntawm cov ntaub mos Memory Controller rau MSS tus tswv
SMC_AHB_M_HREADY	IN	AHBL npaj txhij - Siab qhia tias lub tsheb npav AHBL npaj tau txais kev hloov pauv tshiab

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