Microsemi IGLOO2 HPMS DDR Controller Configuration
Taw qhia
Lub IGLOO2 HPMS muaj ib tug embedded DDR maub los (HPMS DDR). Qhov no DDR maub los yog npaj los tswj lub off-chip DDR nco. Lub HPMS DDR maub los tuaj yeem nkag tau los ntawm HPMS (siv HPDMA) thiab los ntawm FPGA ntaub.
Thaum koj siv System Builder los tsim lub kaw lus uas suav nrog HPMS DDR, System Builder teeb tsa HPMS DDR maub los rau koj raws li koj qhov kev nkag thiab xaiv.
Tsis muaj kev sib cais HPMS DDR teeb tsa los ntawm tus neeg siv yuav tsum tau ua. Yog xav paub ntxiv, thov mus saib IGLOO2 System Builder User's Guide.
Qhov System Builder
Qhov System Builder
Hauv em Builder los teeb tsa HPMS DDR tau txais.
- Hauv Cov Ntaus Ntaus tab ntawm System Builder, kos HPMS Sab Nraud DDR Nco (HPMS DDR).
- Hauv Memories tab, xaiv DDR Memory Type:
- DDR 2
- DDR 3
- LPDDR
- Xaiv qhov dav ntawm DDR Nco: 8, 16 lossis 32
- Xyuas ECC yog tias koj xav kom muaj ECC rau DDR.
- Nkag mus rau DDR lub sijhawm teeb tsa lub cim xeeb. Nov yog lub sijhawm DDR lub cim xeeb yuav tsum tau pib.
- Nyem Ntshuam Register Configuration kom import tus nqi sau npe rau FDDR los ntawm cov ntawv uas twb muaj lawm file muaj cov nqi sau npe. Saib Table 1 rau kev sau npe configuration file syntax.
Libero cia li khaws cov ntaub ntawv teeb tsa no hauv eNVM. Thaum FPGA rov pib dua, cov ntaub ntawv teeb tsa no yuav cia li muab theej rau hauv HPMS DDR.
Daim duab 1 • System Builder thiab HPMS DDR
Table 1 • Sau npe Configuration File Syntax
- ddrc_dyn_soft_reset_CR 0x00 ;
- ddrc_dyn_refresh_1_CR 0x27DE ;
- ddrc_dyn_refresh_2_CR 0x30F ;
- ddrc_dyn_powerdown_CR 0x02 ;
- ddrc_dyn_debug_CR 0x00 ;
- ddrc_ecc_data_mask_CR 0x0000 ;
- ddrc_addr_map_col_1_CR 0x3333 ;
HPMS DDR Controller Configuration
Thaum koj siv HPMS DDR Controller kom nkag mus rau sab nraud DDR Nco, DDR Controller yuav tsum tau pib thaum lub sijhawm ua haujlwm. Qhov no yog ua los ntawm kev sau cov ntaub ntawv teeb tsa rau DDR kev tswj hwm kev teeb tsa kev sau npe. Hauv IGLOO2, eNVM khaws cov ntaub ntawv teev npe teeb tsa thiab tom qab FPGA rov pib dua, cov ntaub ntawv teeb tsa tau theej los ntawm eNVM mus rau HPMS DDR cov ntawv tshwj xeeb rau kev pib.
HPMS DDR Control Registers
HPMS DDR Controller muaj cov txheej txheem sau npe uas yuav tsum tau teeb tsa thaum lub sijhawm ua haujlwm. Cov nqi tsim nyog rau cov ntawv sau npe no sawv cev rau qhov sib txawv, xws li DDR hom, PHY dav, hom tawg, thiab ECC. Yog xav paub meej txog DDR tswj kev teeb tsa kev sau npe thov xa mus rau Microsemi IGLOO2 Tus Neeg Siv Khoom Qhia
HPMS MDDR Registers Configuration
Txhawm rau qhia qhov DDR Register tus nqi:
- Siv cov ntawv nyeem sab nraud ntawm Libero SoC, npaj cov ntawv nyeem file muaj cov npe sau npe thiab cov nqi, xws li hauv daim duab 1-1.
- Los ntawm System Builder's Memory tab, nyem Ntshuam Register Configuration.
- Nkag mus rau qhov chaw ntawm Cov Ntawv Sau Npe Configuration file koj tau npaj hauv Kauj Ruam 1 thiab xaiv cov file mus import.
Daim duab 1-1 • Sau npe Configuration Data – Text Format
HPMS DDR Initialization
Cov ntaub ntawv Register Configuration koj import rau HPMS DDR yog loaded rau hauv eNVM thiab theej rau HPMS DDR configuration registers thaum FPGA reset. Tsis muaj tus neeg siv yuav tsum tau ua kom pib HPMS DDR ntawm lub sijhawm ua haujlwm. Qhov no automated pib kuj tseem ua qauv hauv simulation.
Chaw nres nkoj piav qhia
DDR PHY Interface
Cov chaw nres nkoj no tau nthuav tawm nyob rau theem sab saum toj ntawm System Builder generated block. Yog xav paub ntxiv, sab laj IGLOO2 System Builder User Guide. Txuas cov chaw nres nkoj no rau koj lub cim xeeb DDR.
Table 2-1 • DDR PHY Interface
| Chaw nres nkoj npe | Kev taw qhia | Kev piav qhia |
| MDDR_CAS_N | Tawm | DRAM CASN |
| MDDR_CKE | Tawm | DRAM CKE |
| MDDR_CLK | Tawm | moos, P sab |
| MDDR_CLK_N | Tawm | moos, N sab |
| MDDR_CS_N | Tawm | DRAM CSN |
| MDDR_ODT | Tawm | DRAM ODT |
| MDDR_RAS_N | Tawm | DRAM RASN |
| MDDR_RESET_N | Tawm | DRAM Reset rau DDR3 |
| MDDR_WE_N | Tawm | DRAM WEN |
| MDDR_ADDR[15:0] | Tawm | Dram Address bits |
| MDDR_BA[2:0] | Tawm | Dram Bank Chaw Nyob |
| MDDR_DM_RDQS ([3:0]/[1:0]/[0]) | NCO | Dram Data Mask |
| MDDR_DQS ([3:0]/[1:0]/[0]) | NCO | Dram Data Strobe Input/Output – P Sab |
| MDDR_DQS_N ([3:0]/[1:0]/[0]) | NCO | Dram Data Strobe Input/Output – N Sab |
| MDDR_DQ ([31:0]/[15:0]/[7:0]) | NCO | DRAM Cov ntaub ntawv nkag / tawm |
| MDDR_DQS_TMATCH_0_IN | IN | FIFO hauv teeb liab |
| MDDR_DQS_TMATCH_0_OUT | Tawm | FIFO tawm signal |
| MDDR_DQS_TMATCH_1_IN | IN | FIFO hauv teeb liab (32-ntsis nkaus xwb) |
| MDDR_DQS_TMATCH_1_OUT | Tawm | FIFO tawm teeb liab (32-ntsis nkaus xwb) |
| MDDR_DM_RDQS_ECC | NCO | Dram ECC Data Mask |
| MDDR_DQS_ECC | NCO | Dram ECC Data Strobe Input/Output – P Sab |
| MDDR_DQS_ECC_N | NCO | Dram ECC Data Strobe Input/Output – N Sab |
| MDDR_DQ_ECC ([3:0]/[1:0]/[0]) | NCO | DRAM ECC Cov ntaub ntawv nkag / tawm |
| MDDR_DQS_TMATCH_ECC_IN | IN | ECC FIFO hauv teeb liab |
| MDDR_DQS_TMATCH_ECC_OUT | Tawm | ECC FIFO tawm teeb liab (32-ntsis nkaus xwb) |
Qhov dav ntawm qhov chaw nres nkoj rau qee qhov chaw nres nkoj hloov raws li kev xaiv ntawm PHY dav. Cov ntawv sau "[a:0]/[b:0]/[c:0]" yog siv los qhia cov chaw nres nkoj, qhov twg "[a:0]" yog hais txog qhov chaw nres nkoj dav thaum xaiv 32-ntsis PHY dav. , "[b:0]" sib raug rau 16-ntsis PHY dav, thiab "[c:0]" sib raug rau 8-ntsis PHY dav.
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