Microsemi IGLOO2 HPMS DDR Controller Configuration
Nhanganyaya
Iyo IGLOO2 HPMS ine yakamisikidzwa DDR controller (HPMS DDR). Iyi DDR controller inoitirwa kudzora off-chip DDR memory. Iyo HPMS DDR controller inogona kuwanikwa kubva kuHPMS (uchishandisa HPDMA) uye kubva kuFPGA jira.
Paunoshandisa System Builder kuvaka system block iyo inosanganisira HPMS DDR, System Builder inogadzirisa iyo HPMS DDR controller yako zvichienderana nezvaunopinda uye sarudzo.
Hapana yakaparadzana HPMS DDR kumisikidzwa nemushandisi inodiwa. Kuti uwane ruzivo, ndapota tarisa kune IGLOO2 System Builder Mushandisi's Guide.
System Builder
System Builder
In em Builder kugadzirisa iyo HPMS DDR otomatiki.
- MuChidimbu Zvimiro tebhu yeSisitimu Builder, tarisa HPMS Yekunze DDR Memory (HPMS DDR).
- MuMemories tab, sarudza iyo DDR Memory Type:
- DDR2
- DDR3
- LPDDR
- Sarudza Upamhi hweDDR Memory: 8, 16 kana 32
- Tarisa ECC kana iwe uchida kuve neECC yeDDR.
- Pinda iyo DDR memory yekuseta nguva. Ino ndiyo nguva iyo DDR ndangariro inoda kutanga.
- Dzvanya Import Register Configuration kuti utore maRejista kukosha kweiyo FDDR kubva pane iripo zvinyorwa file ine zvinyorwa zverejista. Ona Tafura 1 yegadziriro yerejista file syntax.
Libero inongochengeta iyi data yekumisikidza muNVM. Pamusoro peFPGA reset, iyi data yekumisikidza inozokopwa otomatiki muHPMS DDR.
Mufananidzo 1 • System Builder uye HPMS DDR
Tafura 1 • Register Configuration File Syntax
- ddrc_dyn_soft_reset_CR 0x00 ;
- ddrc_dyn_refresh_1_CR 0x27DE ;
- ddrc_dyn_refresh_2_CR 0x30F ;
- ddrc_dyn_powerdown_CR 0x02 ;
- ddrc_dyn_debug_CR 0x00 ;
- ddrc_ecc_data_mask_CR 0x0000 ;
- ddrc_addr_map_col_1_CR 0x3333 ;
HPMS DDR Controller Configuration
Paunoshandisa iyo HPMS DDR Controller kuwana yekunze DDR Memory, iyo DDR Controller inofanirwa kutangwa panguva yekumhanya. Izvi zvinoitwa nekunyora dhizaini yekumisikidza kune yakatsaurwa DDR controller kumisikidzwa marejista. MuIGLOO2, iyo eNVM inochengeta register yekumisikidza data uye mushure meFPGA kusetwa patsva, data rekumisikidza rinokopwa kubva kuNVM kuenda kuHPMS DDR's yakatsaurirwa marejista kuti itange.
HPMS DDR Kudzora Marejista
Iyo HPMS DDR Controller ine seti yemarejista inoda kugadzirwa panguva yekumhanya. Mamiriro ekugadzirisa emarejista aya anomiririra akasiyana ma paramita, akadai seDDR modhi, PHY upamhi, burst mode, uye ECC. Kuti uwane ruzivo rwakakwana nezve DDR controller kumisikidza marejista ndapota tarisa kune Microsemi IGLOO2 Mushandisi's Guide.
HPMS MDDR Rejista Kugadzirisa
Kutsanangura kukosha kweDDR Register:
- Shandisa chinyorwa chinyorwa kunze kweLibero SoC, gadzirira chinyorwa file ine Rejista mazita uye kukosha, sepaMufananidzo 1-1.
- Kubva kuSystem Builder's Memory tab, tinya Import Register Configuration.
- Enda kunzvimbo yeRegistration Configuration text file iwe wakagadzirira muNhanho 1 uye sarudza iyo file kupinza.
Mufananidzo 1-1 • Nyoresa Kugadzirisa Data - Text Format
HPMS DDR Kutanga
Iyo Register Configuration data yaunopinza yeHPMS DDR inoiswa muNVM uye inokopwa kuHPMS DDR kumisikidzwa marejista paFPGA reset. Hapana chiito chemushandisi chinodiwa kuti utange iyo HPMS DDR panguva yekumhanya. Iyi otomatiki yekutanga inoteedzerwawo mukuenzanisa.
Port Description
DDR PHY Interface
Aya madoko anoburitswa padanho repamusoro reSystem Builder yakagadzirwa block. Kuti uwane ruzivo, bvunza IGLOO2 System Builder Mushandisi Guide. Batanidza aya madoko kune yako DDR memory.
Tafura 2-1 • DDR PHY Interface
| Port Name | Direction | Tsanangudzo |
| MDDR_CAS_N | OUT | DRAM CASN |
| MDDR_CKE | OUT | DRAM CKE |
| MDDR_CLK | OUT | Clock, P side |
| MDDR_CLK_N | OUT | Clock, N side |
| MDDR_CS_N | OUT | DRAM CSN |
| MDDR_ODT | OUT | DRAM ODT |
| MDDR_RAS_N | OUT | DRAM RASN |
| MDDR_RESET_N | OUT | DRAM Reset yeDDR3 |
| MDDR_WE_N | OUT | DRAM WEN |
| MDDR_ADDR[15:0] | OUT | Dram Kero bits |
| MDDR_BA[2:0] | OUT | Dram Bank Kero |
| MDDR_DM_RDQS ([3:0]/[1:0]/[0]) | INOUT | Dram Data Mask |
| MDDR_DQS ([3:0]/[1:0]/[0]) | INOUT | Dram Data Strobe Input/Output – P Side |
| MDDR_DQS_N ([3:0]/[1:0]/[0]) | INOUT | Dram Data Strobe Input/Output – N Side |
| MDDR_DQ ([31:0]/[15:0]/[7:0]) | INOUT | DRAM Data Input/Output |
| MDDR_DQS_TMATCH_0_IN | IN | FIFO muchiratidzo |
| MDDR_DQS_TMATCH_0_OUT | OUT | FIFO kunze chiratidzo |
| MDDR_DQS_TMATCH_1_IN | IN | FIFO muchiratidzo (32-bit chete) |
| MDDR_DQS_TMATCH_1_OUT | OUT | FIFO kunze chiratidzo (32-bit chete) |
| MDDR_DM_RDQS_ECC | INOUT | Dram ECC Data Mask |
| MDDR_DQS_ECC | INOUT | Dram ECC Data Strobe Input/Output – P Side |
| MDDR_DQS_ECC_N | INOUT | Dram ECC Data Strobe Input/Output – N Side |
| MDDR_DQ_ECC ([3:0]/[1:0]/[0]) | INOUT | DRAM ECC Data Input/Output |
| MDDR_DQS_TMATCH_ECC_IN | IN | ECC FIFO muchiratidzo |
| MDDR_DQS_TMATCH_ECC_OUT | OUT | ECC FIFO kunze chiratidzo (32-bit chete) |
Port wides kune mamwe madoko anoshanduka zvichienderana nekusarudzwa kwehupamhi hwePHY. Chiratidzo "[a:0]/[b:0]/[c:0]" chinoshandiswa kuratidza zviteshi zvakadaro, apo “[a:0]” zvichireva hupamhi hwechiteshi panosarudzwa hupamhi hwe32-bit PHY. , “[b:0]” inofambirana nehupamhi hwe16-bit PHY, uye “[c:0]” inofambirana nehupamhi hwe8-bit PHY.
Product Support
Microsemi SoC Zvigadzirwa Boka inodzosera zvigadzirwa zvayo neakasiyana masevhisi ekutsigira, anosanganisira Mutengi Sevhisi, Mutengi Unyanzvi Tsigiro Center, a websaiti, tsamba dzemagetsi, uye mahofisi ekutengesa pasi rese. Apendikisi iyi ine ruzivo rwekubata Microsemi SoC Zvigadzirwa Boka uye kushandisa aya masevhisi ekutsigira.
Mabatiro evatengi
Bata Mutengi Sevhisi kune isiri-tekinoroji yechigadzirwa rutsigiro, semitengo yechigadzirwa, kukwidziridzwa kwechigadzirwa, ruzivo rwekuvandudza, mamiriro eodha, uye mvumo.
Kubva kuNorth America, fonera 800.262.1060
Kubva kune dzimwe nyika, fonera 650.318.4460 Fax, chero kupi zvako munyika, 408.643.6913
Mutengi Technical Support Center
Microsemi SoC Zvigadzirwa Boka tsvimbo yayo Mutengi Unyanzvi Tsigiro Center ine mainjiniya ane hunyanzvi anogona kubatsira kupindura Hardware yako, software, uye dhizaini mibvunzo nezve Microsemi SoC Zvigadzirwa. Mutengi Unyanzvi Wetsigiro Center inopedza nguva yakawanda ichigadzira zvinyorwa zvekushandisa, mhinduro kumibvunzo yakajairwa dhizaini kutenderera, zvinyorwa zvenyaya dzinozivikanwa, uye akasiyana maFAQ. Saka, usati watibata, ndapota shanyira yedu online zviwanikwa. Zvingangodaro kuti isu takatopindura mibvunzo yako.
Technical Support
Shanyira Rutsigiro rweMutengi websaiti (www.microsemi.com/soc/support/search/default.aspx) kuti uwane rumwe ruzivo nerutsigiro. Mhinduro dzakawanda dziripo pane zvinotsvakwa web resource inosanganisira dhayagiramu, mifananidzo, uye zvinongedzo kune zvimwe zviwanikwa pa website.
Website
Unogona kutarisa akasiyana siyana ehunyanzvi uye asiri-tekinoroji ruzivo pane iyo SoC peji repamba, pa www.microsemi.com/soc.
Kubata neCustomer Technical Support Center
Mainjiniya vane hunyanzvi vanoshanda muTechnical Support Center. Iyo Technical Support Center inogona kufonerwa neemail kana kuburikidza neMicrosemi SoC Zvigadzirwa Boka website.
Email
Unogona kutaurira mibvunzo yako yehunyanzvi kukero yedu yeemail uye wogashira mhinduro neemail, fax, kana foni. Zvakare, kana uine matambudziko ekugadzira, unogona kutumira email dhizaini yako files kuwana rubatsiro. Isu tinogara tichitarisa iyo email account zuva rese. Paunenge uchitumira chikumbiro chako kwatiri, ndapota iva nechokwadi chekuisa zita rako rakazara, zita rekambani, uye ruzivo rwako rwekufonera kuti unyatso kugadzirisa chikumbiro chako.
Iyo tekinoroji yekutsigira email kero ndeye soc_tech@microsemi.com.
Nyaya dzangu
Microsemi SoC Zvigadzirwa Boka vatengi vanogona kuendesa uye kuteedzera matekiniki makesi online nekuenda kuMakesi Angu.
Kunze kweUS
Vatengi vanoda rubatsiro kunze kwenzvimbo dzenguva dzeUS vanogona kubata rubatsiro rwehunyanzvi kuburikidza neemail (soc_tech@microsemi.com) kana kubata hofisi yekutengesa yemuno. Sales office zvinyorwa zvinogona kuwanikwa pa
www.microsemi.com/soc/company/contact/default.aspx.
ITAR Technical Support
Kuti uwane rutsigiro rwehunyanzvi paRH uye RT FPGAs dzinodzorwa neInternational Traffic muArms Regulations (ITAR), taura nesu kuburikidza soc_tech_itar@microsemi.com. Neimwe nzira, mukati meNyaya Dzangu, sarudza Hongu mune ITAR yekudonha-pasi runyorwa. Kuti uwane runyorwa rwakakwana rweITAR-yakadzorwa Microsemi FPGAs, shanyira ITAR web peji.
Microsemi Corporation (NASDAQ: MSCC) inopa ruzivo rwakakwana rwezvigadziriso zve semiconductor zve: aerospace, kudzivirira uye kuchengeteka; bhizinesi uye kutaurirana; uye maindasitiri uye mamwe magetsi misika. Zvigadzirwa zvinosanganisira kuita kwepamusoro-soro, kuvimbika kwepamusoro analog uye RF zvishandiso, siginecha yakasanganiswa uye RF yakasanganiswa maseketi, customizable SoCs, FPGAs, uye yakakwana subsystems. Microsemi inotungamirwa muAliso Viejo, Calif. Dzidza zvakawanda pa www.microsemi.com.
Microsemi Corporate Headquarters One Enterprise, Aliso Viejo CA 92656 USA Mukati meUSA: +1 949-380-6100 Kutengeswa: +1 949-380-6136
Fax: +1 949-215-4996
© 2013 Microsemi Corporation. Kodzero dzese dzakachengetwa. Microsemi uye iyo Microsemi logo zviratidzo zveMicrosemi Corporation. Mamwe matrademark ese uye masevhisi mamaki zvinhu zvevaridzi vazvo.
Zvinyorwa / Zvishandiso
 |
Microsemi IGLOO2 HPMS DDR Controller Configuration [pdf] Bhuku reMushandisi IGLOO2 HPMS DDR Controller Configuration, IGLOO2, HPMS DDR Controller Configuration, DDR Controller Configuration, Configuration |
