F-Tile DisplayPort FPGA IP Design Example
Jagorar Mai Amfani

F-Tile DisplayPort FPGA IP Design Example

An sabunta don Intel® Quartus® Prime Design Suite: 22.2 Sigar IP: 21.0.1

DisplayPort Intel FPGA IP Design ExampJagorar Farawa Mai sauri

Na'urori na DisplayPort Intel® F-tile sun ƙunshi simulating testbench da ƙirar kayan masarufi wanda ke goyan bayan haɗawa da gwajin kayan aikin FPGA IP ƙirar ƙira.ampdon Intel Agilex™
DisplayPort Intel FPGA IP yana ba da ƙira mai zuwaampda:

• DisplayPort SST layi daya madauki ba tare da tsarin farfadowa na agogo na Pixel (PCR).
• DisplayPort SST daidaitaccen madauki tare da AXIS Video Interface

Lokacin da kuka samar da zane exampHar ila yau, editan siga yana ƙirƙirar ta atomatik fileya zama dole don kwaikwaya, tarawa, da gwada ƙira a cikin kayan masarufi.
Hoto 1. Ci gaban StagesBayanai masu alaƙa

• DisplayPort Intel FPGA IP Jagorar Mai amfani
• Hijira zuwa Intel Quartus Prime Pro Edition

Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka.
*Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.
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1.1. Tsarin Jagora
Hoto 2. Tsarin Jagora

Tebur 1. Zane ExampAbubuwan da aka gyara

Jakunkuna	Files
rtl/core	dp_core.ip
	dp_rx. ip
	dp_tx. ip
rtl/rx_phy	dp_gxb_rx/ ((DP PMA UX block)
	dp_rx_data_fifo . ip
	rx_top_phy . sv
rtl/tx_phy	dp_gxb_rx/ ((DP PMA UX block)
	dp_tx_data_fifo.ip
	dp_tx_data_fifo.ip

1.2. Bukatun Hardware da Software
Intel yana amfani da kayan masarufi da software masu zuwa don gwada ƙirar ƙiraampda:
Hardware

• Intel Agilex I-Series Development Kit
• GPU SourcePort
• DisplayPort Sink (Duba)
• Biec DisplayPort FMC katin 'yar Revision 8C
• Kebul na DisplayPort

Software

• Intel Quartus® Prime
• Synopsys* VCS Simulator

1.3. Samar da Zane
Yi amfani da editan madaidaicin IP na DisplayPort Intel FPGA a cikin software na Intel Quartus Prime don samar da ƙirar ƙiraample.
Hoto 3. Samar da Tsarin Zane

1.  Zaɓi Kayan aiki ➤ IP Catalog, kuma zaɓi Intel Agilex F-tile azaman dangin na'urar da aka yi niyya.
   Lura: Zane exampLe kawai yana goyan bayan na'urorin F-tile na Intel Agilex.
2. A cikin Catalog na IP, gano wuri kuma danna DisplayPort Intel FPGA IP sau biyu. Sabuwar taga Bambancin IP yana bayyana.
3. Ƙayyade sunan babban matakin don bambancin IP na al'ada. Editan siga yana adana saitunan bambancin IP a cikin a file mai suna .ip.
4. Zaɓi na'urar tayal F-tile na Intel Agilex a cikin filin Na'ura, ko kiyaye tsoffin zaɓin na'urar software ta Intel Quartus Prime.
5. Danna Ok. Editan siga ya bayyana.
6. Sanya sigogin da ake so don duka TX da RX.
7. Karkashin Zane ExampDaga shafin, zaɓi DisplayPort SST Daidaitacce Loopback Ba tare da PCR ba.
8. Zaɓi Simulation don samar da benci na gwaji, kuma zaɓi Synthesis don samar da ƙirar kayan masarufiample. Dole ne ku zaɓi aƙalla ɗaya daga cikin waɗannan zaɓuɓɓukan don samar da ƙirar tsohuwarample files. Idan kun zaɓi duka biyun, lokacin tsara zai zama tsayi.
9. Don Kit ɗin Ci gaban Target, zaɓi Intel Agilex I-Series SOC Development Kit. Wannan yana sa na'urar da aka zaɓa a mataki na 4 ta canza don dacewa da na'urar akan kayan haɓakawa. Don Intel Agilex I-Series SOC Development Kit, tsohuwar na'urar ita ce AGIB027R31B1E2VR0.
10. Danna Ƙirƙirar Exampda Design.

1.4. Simulating da Zane
DisplayPort Intel FPGA IP ƙira example testbench yana kwaikwayi ƙirar madauki na serial daga misalin TX zuwa misalin RX. Modulin janareta na bidiyo na ciki yana fitar da misalin DisplayPort TX kuma fitowar bidiyo ta RX ta haɗa zuwa masu duba CRC a cikin testbench.
Hoto 4. Zane Simulators

1. Jeka babban fayil ɗin Synopsys na'urar kwaikwayo kuma zaɓi VCS.
2. Gudanar da rubutun kwaikwayo.
   Tushen vcs_sim.sh
3. Rubutun yana yin Quartus TLG, yana tattarawa kuma yana gudanar da gwajin benci a cikin na'urar kwaikwayo.
4. Yi nazarin sakamakon.
   Nasarar kwaikwayo ta ƙare tare da kwatanta Source da Sink SRC.

1.5. Haɗawa da Gwajin Zane
Hoto 5. Haɗawa da Kwaikwaya ZaneDon haɗawa da gudanar da gwajin gwaji akan hardware exampdon tsarawa, bi waɗannan matakan:

1. Tabbatar da hardware example zane tsara ya cika.
2. Kaddamar da Intel Quartus Prime Pro Edition software kuma buɗe / quartus/agi_dp_demo.qpf.
3. Danna Processing ➤ Fara Tari.
4. Bayan nasarar haɗawa, Intel Quartus Prime Pro software software yana haifar da .sof file a cikin ƙayyadadden kundin adireshi.
5. Haɗa mai haɗin DisplayPort RX akan katin 'yar Bitec zuwa tushen DisplayPort na waje, kamar katin zane akan PC.
6. Haɗa mai haɗin DisplayPort TX akan katin 'yar Bitec zuwa na'urar nutsewar DisplayPort, kamar na'urar tantance bidiyo ko mai duba PC.
7.  Tabbatar cewa duk masu sauyawa akan allon haɓaka suna cikin tsoho matsayi.
8. Sanya na'urar Intel Agilex F-Tile da aka zaɓa akan allon haɓaka ta amfani da .sof da aka samar file (Kayan aiki ➤ Mai shirye-shirye).
9. Na'urar nutsewar DisplayPort tana nuna bidiyon da aka ƙirƙira daga tushen bidiyo.

Bayanai masu alaƙa
Intel Agilex I-Series FPGA Jagorar Mai amfani Kit
1.5.1. Sabunta ELF File
Ta hanyar tsoho, ELF file ana haifar dashi lokacin da kuka samar da zane mai tsauri example.
Koyaya, a wasu lokuta, kuna buƙatar sake haɓaka ELF file idan kun canza software file ko sabunta dp_core.qsys file. Sake sabunta dp_core.qsys file sabunta .sopcinfo file, wanda ke buƙatar ku sake haɓaka ELF file.

1. Je zuwa /software kuma gyara lambar idan ya cancanta.
2. Je zuwa /rubutu kuma aiwatar da rubutun ginawa mai zuwa: tushen build_sw.sh
   • A kan Windows, bincika kuma buɗe Nios II Command Shell. A cikin Nios II Command Shell, je zuwa /rubutu kuma aiwatar da tushen build_sw.sh.
   Lura: Don aiwatar da rubutun gini akan Windows 10, tsarin ku yana buƙatar Tsarin Windows don Linux (WSL). Don ƙarin bayani game da matakan shigarwa na WSL, koma zuwa Nios II Littafin Jagorar Haɓaka Software.
   • A Linux, ƙaddamar da Platform Designer, kuma buɗe Kayan aiki ➤ Nios II Command Shell. A cikin Nios II Command Shell, je zuwa /rubutu kuma aiwatar da tushen build_sw.sh.
3. Tabbatar da .kai file aka haifar a /software/dp_demo.
4. Zazzage .elf da aka samar file cikin FPGA ba tare da sake tattara .sof ba file ta hanyar gudanar da rubutun mai zuwa: nios2-zazzagewa /software/dp_demo/*.elf
5. Danna maɓallin sake saiti akan allon FPGA don sabuwar software ta fara aiki.

1.6. DisplayPort Intel FPGA IP Design Exampda Parameters
Tebur 2. DisplayPort Intel FPGA IP Design ExampLe QSF ƙuntatawa don Intel Agilex Ftile Device

QSF takura	Bayani
saitin_assignment_global_name VERILOG_MACRO "__DISPLAYPORT_support__=1"	Daga Quartus 22.2 zuwa gaba, ana buƙatar wannan ƙuntatawar QSF don kunna al'adar DisplayPort SRC (Mai Sake saitin Mai Rarraba)

Tebur 3. DisplayPort Intel FPGA IP Design ExampLe Parameters don Intel Agilex F-tile Device

Siga	Daraja	Bayani
Akwai Zane Example
Zaɓi Zane	•Babu •DisplayPort SST Parallel Loopback ba tare da PCR ba •DisplayPort SST Parallel Loopback tare da AXIS Video Interface	Zaɓi zane exampda za a haifar. •Babu: Babu zane example yana samuwa don zaɓin siga na yanzu. •DisplayPort SST Parallel Loopback ba tare da PCR ba: Wannan ƙirar misaliample yana nuna madaidaicin madaidaici daga nutsewar DisplayPort zuwa tushen DisplayPort ba tare da ƙirar Pixel Clock farfadowa da na'ura ba (PCR) lokacin da kuka kunna siginar tashar Hoton shigar da Bidiyo. •DisplayPort SST Parallel Loopback tare da AXIS Video Interface: Wannan zane example yana nuna madaidaicin madaidaici daga nutsewar DisplayPort zuwa tushen DisplayPort tare da AXIS Bidiyo lokacin da aka saita Ka'idojin Bayanan Bidiyo masu Aiki zuwa AXIS-VVP Full.
Zane Example Files
kwaikwayo	Kunnawa, Kashe	Kunna wannan zaɓi don samar da abin da ake bukata files don simulation testbench.
Magana	Kunnawa, Kashe	Kunna wannan zaɓi don samar da abin da ake bukata files don Haɗin Intel Quartus Prime da ƙirar kayan masarufi.
Samar da Tsarin HDL
Ƙirƙira File Tsarin	Verilog, VHDL	Zaɓi tsarin HDL da kuka fi so don ƙirar ƙiraample filesaita. Lura: Wannan zaɓin yana ƙayyadaddun tsari ne kawai don babban matakin IP da aka samar files. Duk sauran files (misaliample testbenches da babban matakin files don zanga-zangar hardware) suna cikin tsarin Verilog HDL.
Kit ɗin Ci gaban Target
Zaɓi Board	•Babu Kayan Ci Gaba •Intel Agilex I-Series Kit ɗin Ci gaba	Zaɓi allon don ƙirar da aka yi niyya example.

Siga	Daraja	Bayani
		•Babu Kayan Haɓakawa: Wannan zaɓin ya keɓance duk abubuwan kayan masarufi don ƙirar ƙiraample. P core yana saita duk ayyukan fil zuwa fil masu kama-da-wane. •Intel Agilex I-Series FPGA Development Kit: Wannan zaɓi yana zaɓar na'urar da aka yi niyya ta atomatik don dacewa da na'urar akan wannan kayan haɓakawa. Kuna iya canza na'urar da aka yi niyya ta amfani da ma'aunin Canja Na'urar Target idan bita na allo yana da bambancin na'urar daban. Tushen IP yana saita duk ayyukan fil bisa ga kayan haɓakawa. Lura: Zane na Farko Example ba a tabbatar da aikin ba akan kayan masarufi a cikin wannan sakin Quartus. • Kit ɗin Haɓakawa na Musamman: Wannan zaɓi yana ba da damar ƙira exampza a gwada shi akan kayan haɓaka na ɓangare na uku tare da Intel FPGA. Kuna iya buƙatar saita ayyukan fil da kanku.
Na'urar Target
Canja Na'urar Target	Kunnawa, Kashe	Kunna wannan zaɓi kuma zaɓi bambance-bambancen na'urar da aka fi so don kayan haɓakawa.

Daidaici Loopback Design Examples

DisplayPort Intel FPGA IP ƙira exampmu nuna madaidaicin madogara daga DisplayPort RX misali zuwa DisplayPort TX misali ba tare da tsarin Farko na Clock na Pixel (PCR).
Tebur 4. DisplayPort Intel FPGA IP Design Exampdon Intel Agilex F-tile Device

Zane Example	Nadi	Adadin Bayanai	Yanayin Channel	Nau'in Loopback
DisplayPort SST layi daya madauki ba tare da PCR ba	DisplayPort SST	RBR, HRB, HRB2, HBR3	Simplex	Daidaitacce ba tare da PCR ba
DisplayPort SST daidaitaccen madauki tare da AXIS Video Interface	DisplayPort SST	RBR, HRB, HRB2, HBR3	Simplex	Daidaitacce tare da Interface Bidiyo na AXIS

2.1. Intel Agilex F-tile DisplayPort SST Daidaitaccen Tsarin Loopback Siffofin
The SST layi daya loopback zane exampdon nuna watsa rafin bidiyo guda ɗaya daga nutsewar DisplayPort zuwa tushen DisplayPort.
Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka. *Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.
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Hoto 6. Intel Agilex F-tile DisplayPort SST Parallel Loopback ba tare da PCR ba

• A cikin wannan bambance-bambancen, ana kunna ma'aunin tushen DisplayPort, TX_SUPPORT_IM_ENABLE, kuma ana amfani da mu'amalar hoton bidiyo.
• The DisplayPort nutse yana karɓar bidiyo da ko sauti mai gudana daga tushen bidiyo na waje kamar GPU kuma yana yanke shi zuwa yanayin mu'amalar bidiyo iri ɗaya.
• Fitowar bidiyo ta nutsewa ta DisplayPort kai tsaye tana tafiyar da ƙirar bidiyo ta tushen DisplayPort kuma tana ɓoyewa zuwa babban hanyar haɗin gwiwar DisplayPort kafin aikawa zuwa mai saka idanu.
• IOPLL tana tafiyar da ma'aunin nuninPort da agogon bidiyo mai tushe a mitoci masu tsayi.
• Idan DisplayPort nutse da ma'aunin MAX_LINK_RATE na tushe an saita su zuwa HBR3 kuma an saita PIXELS_PER_CLOCK zuwa Quad, agogon bidiyo yana gudana a 300 MHz don tallafawa ƙimar pixel 8Kp30 (1188/4 = 297 MHz).

Hoto 7. Intel Agilex F-tile DisplayPort SST Parallel Loopback tare da AXIS Bidiyo Interface

• A cikin wannan bambance-bambancen, tushen DisplayPort da ma'aunin nutsewa, zaɓi AXIS-VVP FULL a cikin KYAUTA KYAUTA KYAUTA VIDEO DATA PROTOCOLS don ba da damar Interface Bayanan Bidiyo na Axis.
• The DisplayPort nutse yana karɓar bidiyo da ko sauti mai gudana daga tushen bidiyo na waje kamar GPU kuma yana yanke shi zuwa yanayin mu'amalar bidiyo iri ɗaya.
• DisplayPort Sink yana jujjuya rafin bayanan bidiyo zuwa bayanan bidiyo na axis kuma yana sarrafa bayanan bayanan bidiyo na tushen DisplayPort ta hanyar VVP Video Frame Buffer. SourcePort yana canza bayanan bidiyo na axis zuwa babban hanyar haɗin kai na DisplayPort kafin aikawa zuwa mai saka idanu.
• A cikin wannan bambance-bambancen ƙira, akwai manyan agogon bidiyo guda uku, wato rx/tx_axi4s_clk, rx_vid_clk, da tx_vid_clk. axi4s_clk yana gudana a 300 MHz don duka nau'ikan AXIS a cikin Source da Sink. rx_vid_clk yana gudanar da bututun Bidiyo na DP Sink a 300 MHz (don tallafawa kowane ƙuduri har zuwa 8Kp30 4PIPs), yayin da tx_vid_clk ke gudanar da bututun Bidiyo na DP Source a ainihin mitar agogon Pixel (wanda PIPs ya raba).
• Wannan bambance-bambancen ƙira na atomatik yana daidaita mitar tx_vid_clk ta hanyar shirye-shiryen I2C zuwa kan-jirgin SI5391B OSC lokacin da ƙira ta gano canji a cikin ƙuduri.
• Wannan bambance-bambancen ƙira kawai yana nuna ƙayyadaddun adadin shawarwari kamar yadda aka riga aka ayyana a cikin software na DisplayPort, wato:
  - 720p60, RGB
  - 1080p60, RGB
  - 4K30, RGB
  - 4K60, RGB

2.2. Tsarin agogo
Tsarin agogo yana kwatanta wuraren agogo a cikin DisplayPort Intel FPGA IP ƙiraample.
Hoto 8. Intel Agilex F-tile DisplayPort Transceiver clocking makirciTebur 5. Siginonin Tsare-tsaren agogo

Agogo a cikin zane	Bayani
Rahoton da aka ƙayyade na SysPLL	F-tile System Agogon tunani na PLL wanda zai iya zama kowane mitar agogo wanda System PLL ke raba don wannan mitar fitarwa. A cikin wannan zane example, system_pll_clk_link da rx/tx refclk_link suna raba 150 MHz SysPLL refclk iri ɗaya.

Agogo a cikin zane	Bayani
	Dole ne ya zama agogon gudu na kyauta wanda aka haɗa daga keɓaɓɓen madaidaicin agogon nuni zuwa tashar agogon shigarwa na Reference da System PLL Clocks IP, kafin haɗa tashar fitarwa mai dacewa zuwa DisplayPort Phy Top. Lura: Don wannan ƙira example, saita Clock Controller GUI Si5391A OUT6 zuwa 150 MHz.
tsarin pll clk mahada	Matsakaicin mitar fitarwa na System PLL don tallafawa duk ƙimar DisplayPort shine 320 MHz. Wannan zane example yana amfani da mitar fitarwa na 900 MHz (mafi girma) don a iya raba SysPLL refclk tare da rx/tx refclk_link wanda shine 150 MHz.
rx_cdr_refclk_link / tx_pll_refclk_link	Rx CDR da Tx PLL Link refclk wanda aka gyara zuwa 150 MHz don tallafawa duk ƙimar bayanan DisplayPort.
rx_ls_clkout / tx_ls_clkout	Agogo saurin Haɗin Haɗin kai zuwa agogo DisplayPort IP core. Mitar daidai yake da Raba ƙimar Bayanai ta hanyar faɗin bayanan layi ɗaya. Exampda: Frequency = ƙimar bayanai / faɗin bayanai = 8.1G (HBR3) / 40 ragowa = 202.5 MHz

2.3. Simulators Testbench
Gwajin simintin simintin yana simintin siginar DisplayPort TX zuwa RX.
Hoto 9. DisplayPort Intel FPGA IP Simplex Mode Simulation Testbench Block zaneTebur 6. Abubuwan Gwajin Testbench

Bangaren	Bayani
Bidiyo Tsarin Generator	Wannan janareta yana samar da alamun mashaya launi waɗanda zaku iya saita su. Za ka iya parameterize da video format lokaci.
Gudanarwar Testbench	Wannan toshe yana sarrafa jerin gwajin simulation kuma yana haifar da sigina masu mahimmanci ga ainihin TX. Katangar sarrafa gwajin gwaji kuma tana karanta ƙimar CRC daga tushe da nutse don yin kwatance.
RX Link Speed ​​​​Clock Checker	Wannan mai duba yana tabbatar da idan mai karɓar RX ya dawo da mitar agogo yayi daidai da ƙimar bayanan da ake so.
TX Link Speed ​​​​Clock Checker	Wannan mai duba yana tabbatar da idan mai karɓar TX da aka dawo da mitar agogo yayi daidai da ƙimar bayanan da ake so.

The simulation testbench yana yin waɗannan tabbaci masu zuwa:
Tebur 7. Tabbatar da Testbench

Ma'aunin Gwaji	Tabbatarwa
• Koyarwar haɗin kai a ƙimar bayanai HBR3 • Karanta rajistar DPCD don bincika idan Matsayin DP ya saita kuma yana auna mitar saurin haɗin TX da RX.	Yana Haɗa Mai duba Mitar don auna Gudun Haɗin Fitowar mitar agogo daga TX da RX transceiver.
• Gudanar da tsarin bidiyo daga TX zuwa RX. • Tabbatar da CRC don duka tushe da nutsewa don bincika idan sun dace	• Haɗa janareta ƙirar bidiyo zuwa Tushen DisplayPort don samar da tsarin bidiyo. • Ikon Testbench na gaba yana karanta duka Source da Sink CRC daga rajistar DPTX da DPRX kuma suna kwatanta don tabbatar da ƙimar CRC duka iri ɗaya ne. Lura: Don tabbatar da an ƙididdige CRC, dole ne ku kunna madaidaicin gwajin CTS na goyan baya.

Tarihin Bita na Takardu don F-Tile DisplayPort Intel FPGA IP Design ExampJagorar Mai Amfani

Sigar Takardu	Intel Quartus Prime Version	Sigar IP	Canje-canje
2022.09.02	22.	20.0.1	• Canza taken daftarin aiki daga DisplayPort Intel Agilex F-Tile FPGA IP Design ExampJagorar Mai Amfani zuwa F-Tile DisplayPort Intel FPGA IP Design ExampJagorar Mai Amfani. •An kunna AXIS Video Design Exampda bambancin. • An Cire Tsararren Ƙimar ƙira kuma a maye gurbinsa da Multi Rate Design Example. •An cire bayanin kula a cikin DisplayPort Intel FPGA IP Design ExampJagoran Farawa Mai sauri wanda ya ce sigar software ta Intel Quartus Prime 21.4 kawai tana goyan bayan Zane na Farko Examples. •Maye gurbin Hoton Tsarin Gida da adadi daidai. •An ƙara wani sashe Yana Sake Haɓaka ELF File karkashin Hardawa da Gwajin Zane. •An sabunta sashin Buƙatun Hardware da Software don haɗa ƙarin kayan aiki bukatun.
2021.12.13	21.	20.0.0	Sakin farko.

Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka.
*Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.
ISO 9001: 2015 Rajista

Online Version
Aika da martani
Saukewa: UG-20347
Saukewa: 709308
Shafin: 2022.09.02

Takardu / Albarkatu

intel F-Tile DisplayPort FPGA IP Design Example [pdf] Jagorar mai amfani F-Tile DisplayPort FPGA IP Design Example, F-Tile DisplayPort, DisplayPort, FPGA IP Design Example, IP Design Example, UG-20347, 709308

Magana

• Manual mai amfani