intel F-Tile CPRI PHY FPGA IP Design Example
Taiala vave amata
O le F-Tile CPRI PHY Intel® FPGA IP autu e maua ai se faʻataʻitaʻiga suʻega suʻega ma meafaigaluega faʻataʻitaʻigaampe lagolagoina le tu'ufa'atasiga ma su'ega meafaigaluega. A e gaosia le mamanu example, e otometi lava ona fatuina e le faatonu parameter le files e manaʻomia e faʻataʻitaʻi, faʻapipiʻi, ma suʻe le mamanu i meafaigaluega.
E tu'uina atu fo'i e Intel se tu'ufa'atasi-na'o example poloketi e mafai ona e faʻaogaina e faʻatatau vave ai le vaega autu o le IP ma le taimi.
O le F-Tile CPRI PHY Intel FPGA IP autu e maua ai le agava'a o le fa'atupuina o fa'ata'ita'igaamples mo tu'ufa'atasiga lagolago uma o le numera o laina CPRI ma fua fa'atatau o laina CPRI. Le su'ega ma le mamanu exampE lagolagoina le tele o tu'ufa'atasiga o le F-Tile CPRI PHY Intel FPGA IP core.
Ata 1. Laasaga Atina'e mo le Fuafuaga Example
Fa'amatalaga Fa'atatau
- F-Tile CPRI PHY Intel FPGA IP Taiala mo Tagata Fa'aoga
- Mo fa'amatalaga auiliili ile F-tile CPRI PHY IP.
- F-Tile CPRI PHY Intel FPGA IP Fa'amatalaga Fa'amatalaga
- O le IP Release Notes lisi suiga IP i se faʻasalalauga faʻapitoa.
Meafaigaluega ma Polokalama Manaoga
Ina ia tofotofoina le example mamanu, faʻaaoga meafaigaluega ma polokalama nei:
- Polokalama Intel Quartus® Prime Pro Edition
- Fa'amafanafanaga faiga
- Simulators Lagolago:
- Synopsy* VCS*
- Synopsys VCS MX
- Siemens* EDA ModelSim* SE poʻo Questa*— Questa-Intel FPGA Edition
Fausiaina o le Fuafuaga
Ata 2. Taualumaga
Ata 3. Esample Design Tab i le IP Parameter Editor
Ina ia faia se poloketi Intel Quartus Prime Pro Edition:
- I le Intel Quartus Prime Pro Edition, kiliki File ➤ New Project Wizard e fatu ai se poloketi fou a Quartus Prime, poʻo File ➤ Tatala Poloketi e tatala ai se poloketi Intel Quartus Prime. E fa'atonu oe e le wizard e fa'ailoa se masini.
- Fa'ailoa le masini aiga Agilex (I-series) ma filifili se masini e fa'amalieina uma nei mana'oga:
- Transceiver tile ole F-tile
- Ole togi ole saoasaoa ole Transceiver ole -1 pe -2
- Ole vasega ole saoasaoa ole -1 po'o le -2 po'o le -3
- Kiliki Fa'auma.
Mulimuli i laasaga nei e fa'atupu ai le F-Tile CPRI PHY Intel FPGA IP hardware design example ma le testbench:
- I le IP Catalog, su'e ma filifili F-Tile CPRI PHY Intel FPGA IP. Ua aliali mai le fa'amalama New IP Variation.
- Fa'ailoa se igoa pito i luga mo lau suiga masani IP. E fa'asaoina e le fa'atonu fa'amaufa'ailoga le fa'atulagaina o suiga o le IP ile a file igoa .ip.
- Kiliki OK. E aliali mai le fa'atonu fa'amaufa'ailoga.
- I luga o le IP tab, faʻamaonia le faʻasologa mo lau fesuiaiga autu IP.
- I le Example Design tab, i lalo o Example Lisiina Files, filifili le filifiliga Simulation e faʻatupu ai le suʻega suʻega ma le faʻapipiʻi-naʻo le poloketi. Filifili le filifiliga Synthesis e fa'atupu ai le fa'asologa o meafaigaluega fa'aample. E tatau ona e filifilia le itiiti ifo ma le tasi o le Simulation and Synthesis options e fa'atupu ai le mamanu example.
- I le Example Design tab, i lalo o le Generated HDL Format, filifili Verilog HDL poʻo le VHDL. Afai e te filifilia le VHDL, e tatau ona e faʻataʻitaʻiina le suʻega faʻatasi ma se simulator faʻafefiloi-gagana. Le masini o loʻo faʻataʻitaʻiina i le ex_ directory o se faʻataʻitaʻiga VHDL, ae o le suʻega autu file o se System Verilog file.
- Kiliki le Generate Example fa'amau Fa'ailoga. Le Filifili Example fa'amalama o le Design Directory e aliali mai.
- Afai e te manaʻo e sui le mamanu example ala o le lisi poʻo le igoa mai faʻaletonu o loʻo faʻaalia (cpriphy_ftile_0_example_design), suʻesuʻe i le ala fou ma faʻaoga le mamanu fou example igoa fa'atonu (ample_dir>).
Fa'atonuga Fa'atonu
Le F-Tile CPRI PHY Intel FPGA IP mamanu autu example file fa'atonuga o lo'o i ai mea nei na gaosia files mo le mamanu example.
Ata 4. Fa'atonuga Fa'atonu o le Fa'atupuina Example Lisiina
Laulau 1. Su'ega Su'ega File Fa'amatalaga
| File Igoa | Fa'amatalaga |
| Ki Testbench ma Fa'ata'ita'iga Files | |
| <design_example_dir>/ example_testbench/basic_avl_tb_top.sv | Tulaga maualuga su'ega file. O le su'ega su'esu'e e vave fa'apipi'i le afifi DUT ma fa'atino galuega a le Verilog HDL e fa'atupu ma talia fa'aputu. |
| <design_example_dir>/ example_testbench/ cpriphy_ftile_wrapper.sv | DUT afifi e vave faʻapipiʻi le DUT ma isi vaega suʻega. |
| Tusi Su'ega (1) | |
| <design_example_dir>/ example_testbench/run_vsim.do | O le Siemens EDA ModelSim SE poʻo le Questa poʻo le Questa-Intel FPGA Edition tusitusiga e faʻatautaia le suʻega suʻega. |
| <design_example_dir>/ example_testbench/run_vcs.sh | Le Synopsys VCS script e faʻatautaia le suʻega suʻega. |
| <design_example_dir>/ example_testbench/run_vcsmx.sh | Le Synopsys VCS MX script (tu'ufa'atasia Verilog HDL ma SystemVerilog ma VHDL) e fa'atino ai le su'ega. |
Le amanaʻia soʻo se isi faʻamatalaga simulator i leample_dir>/example_testbench/ faila.
Laulau 2. Fuafuaga Meafaigaluega Example File Fa'amatalaga
| File Igoa | Fa'amatalaga |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.qpf | Poloketi Intel Quartus Prime file. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.qsf | Fa'atulagaina o galuega faatino a le Intel Quartus Prime file. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.sdc | Synopsys Design Constraints files. E mafai ona e kopiina ma suia nei mea filemo lau lava Intel Agilex ™ mamanu. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.v | Tulaga maualuga Verilog HDL mamanu example file. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_wrapper.sv | DUT afifi e vave faʻapipiʻi le DUT ma isi vaega suʻega. |
| <design_example_dir>/hardware_test_design/ hwtest_sl/main_script.tcl | Autu file mo le mauaina o le System Console. |
Fa'ata'ita'iina o le Fa'ata'ita'iga Example Testbench
Ata 5. Taualumaga
Mulimuli i laasaga nei e faʻataʻitaʻi ai le suʻega:
- I le faʻatonuga vave, sui i le suʻega faʻataʻitaʻiga directoryample_dir>/example_testbench. cd /example_testbench
- Fa'asolo le quartus_tlg i luga ole galuega fa'atino file: quartus_tlg cpriphy_ftile_hw
- Fai ip-setup-simulation: ip-setup-simulation –output-directory=./sim_script –use-relative-paths –quartus project=cpriphy_ftile_hw.qpf
- Fa'asolo le fa'asologa fa'ata'ita'iga mo le simulator lagolago o lau filifiliga. O le tusitusiga e tuufaatasia ma faʻatautaia le suʻega suʻega i le simulator. Va'ai i le laulau Laasaga e Fa'ata'ita'i ai le Testbench.
- Iloilo i'uga. O le suʻega suʻesuʻe manuia na maua ni hyperframes e lima, ma faʻaalia le "PASSED".
Laulau 3. Laasaga e fa'ata'ita'i ai le Testbench i le Synopsys VCS* Simulator
| Simulator | Faatonuga | |
| VCS | I le laina faʻatonu, faʻaoga: | |
| sh run_vcs.sh | ||
| faaauau… | ||
| Simulator | Faatonuga | |
| VCS MX | I le laina faʻatonu, faʻaoga: | |
| sh run_vcsmx.sh | ||
| ModelSim SE poʻo Questa poʻo Questa-Intel FPGA Edition | I le laina faʻatonu, faʻaoga: | |
| vsim -do run_vsim.do | ||
| Afai e te manaʻo e faʻataʻitaʻi e aunoa ma le aumaia o le GUI, faʻaoga: | ||
| vsim -c -do run_vsim.do | ||
O sampLe fa'atinoga o lo'o fa'aalia ai le manuia o le su'ega fa'ata'ita'iga mo le 24.33024 Gbps fa'atasi ai ma le 4 CPRI auala:
Tu'ufa'atasia o le Poloketi Fa'atasi-Na'o
Ia tuufaatasia le tuufaatasiga-na'o example poloketi, mulimuli i laasaga nei:
- Ia mautinoa le tuufaatasia o le mamanu exampua maea le tupulaga.
- I le polokalama Intel Quartus Prime Pro Edition, tatala le poloketi Intel Quartus Prime Pro Editionample_dir>/compilation_test_design/cpriphy_ftile.qpf.
- I luga o le Processing menu, kiliki Amata Compilation.
- A mae'a fa'aputuga manuia, o lo'o maua lipoti mo le taimi ma le fa'aogaina o puna'oa i lau vasega Intel Quartus Prime Pro Edition.
Fa'amatalaga Fa'atatau
Fuafuaga Fa'avae Poloka
Tu'ufa'atasia ma Fa'atulaga le Fa'ata'ita'iga Example i Meafaigaluega
Ina ia tuufaatasia le mamanu meafaigaluega exampma faʻapipiʻi i luga o lau masini Intel Agilex, mulimuli i laasaga nei:
- Fa'amautinoa le fa'atulagaina o meafaigaluega e iaiampua maea le tupulaga.
- I le polokalama Intel Quartus Prime Pro Edition, tatala le poloketi Intel Quartus Primeample_dir>/hardware_test_design/ cpriphy_ftile_hw.qpf.
- Fa'asa'o le .qsf file e tofia pine e fa'atatau i au meafaigaluega.
- I luga o le Processing menu, kiliki Amata Compilation.
- A mae'a le fa'aputuga manuia, a .sof file e maua i totonuample_dir>/hardware_test_design/output_files directory.
Mulimuli i la'asaga nei e fa'apolokalame ai le fa'atulagaina o meafaigaluega fa'apeaampi luga ole masini Intel Agilex:
- Faʻafesoʻotaʻi le Intel Agilex I-series Transceiver Signal Integrity Development Kit i le komepiuta talimalo.
Fa'aaliga: O le pusa atina'e ua mua'i fa'apolokalameina i alaleo sa'o o le uati ona o le faaletonu. E te le manaʻomia le faʻaogaina o le Clock Control application e seti ai laina. - I luga o le Meafaigaluega lisi, kiliki Programmer.
- I le Polokalama, kiliki Hardware Setup.
- Filifili se masini polokalame.
- Ia mautinoa ua setiina le Faiga i le JTAG.
- Filifili le masini Intel Agilex ma kiliki le Add Device. E fa'aalia e le Polokalama se poloka poloka o feso'ota'iga i le va o masini i luga o lau laupapa.
- I le laina ma lau .sof, siaki le pusa mo le .sof.
- Siaki le pusa i le koluma Polokalama/Configure.
- Kiliki Amata.
Fa'amatalaga Fa'atatau
- Fuafuaga Fa'avae Poloka
- Polokalama Intel FPGA Devices
- Iloiloga ma Debugging Designs ma System Console
Su'esu'e le Mea Fa'a Meafaigaluega Example
A uma ona e tuufaatasia le F-Tile CPRI PHY Intel FPGA IP mamanu autu exampma fa'apipi'i i lau masini Intel Agilex, e mafai ona e fa'aogaina le System Console e fa'apolokalame ai le IP core ma ana PHY IP core registers.
Ia ki le System Console ma fa'ata'ita'i le mamanu o meafaigaluega fa'aample, mulimuli i laasaga nei:
- Ina ua uma le mamanu meafaigaluega exampua fa'atulagaina i luga o le masini Intel Agilex, i le Intel Quartus Prime Pro Edition software, i luga o le Meafaigaluega lisi, kiliki System Debugging Tools ➤ System Console.
- I le Tcl Console pane, lolomi le cd hwtest e sui ai le lisi iample_dir>/hardware_test_design/hwtest_sl.
- Fa'aigoa source main_script.tcl e tatala ai se feso'ota'iga i le JTAG matai ma amata le suega.
Design Example Faʻamatalaga
Le mamanu example fa'aalia le fa'atinoga autu o le F-Tile CPRI PHY Intel FPGA IP core. E mafai ona e fatuina le mamanu mai le Example Design tab i le F-Tile CPRI PHY Intel FPGA IP fa'atonu fa'atonu.
Le fa'atupuina o le mamanu exampO lea, e tatau ona e setiina le tau fa'atatau mo le suiga autu o le IP e te mana'o e fa'atupu i lau oloa fa'ai'uga. E mafai ona e filifili e gaosia le mamanu example fa'atasi pe leai fo'i le fa'ailoga RS-FEC. Ole vaega RS-FEC o lo'o avanoa ile 10.1376, 12.1651 ma le 24.33024 Gbps CPRI laina laina.
Laulau 4. F-Tile CPRI PHY Intel FPGA IP Core Feature Matrix
| CPRI Line Bitrate (Gbps) | RS-FEC Lagolago | Fa'asinoala Uati (MHz) | Lagolago Deterministic Latency |
| 1.2288 | Leai | 153.6 | Ioe |
| 2.4576 | Leai | 153.6 | Ioe |
| 3.072 | Leai | 153.6 | Ioe |
| 4.9152 | Leai | 153.6 | Ioe |
| 6.144 | Leai | 153.6 | Ioe |
| 9.8304 | Leai | 153.6 | Ioe |
| 10.1376 | Faatasi ai ma le Aunoa | 184.32 | Ioe |
| 12.1651 | Faatasi ai ma le Aunoa | 184.32 | Ioe |
| 24.33024 | Faatasi ai ma le Aunoa | 184.32 | Ioe |
Vaega
- Fausia le mamanu example fa'atasi ai ma le fa'aaliga RS-FEC
- Fa'atonuga ole su'eina o pepa e aofia ai ma le faitau toe fo'i o le tuai
Fuafuaga Fa'ata'ita'iga Example
Le F-Tile CPRI PHY Intel FPGA IP design example fa'atupuina se su'ega fa'ata'ita'iga ma fa'ata'ita'iga files e instantiates le F-Tile CPRI PHY Intel FPGA IP autu pe a e filifilia le filifiliga Simulation.
Ata 6. Fa'ailoga poloka mo 10.1316, 12.1651, ma le 24.33024 Gbps (fa'atasi ma leai RS-FEC) Fua Fa'atatau
Ata 7. Fa'afanua poloka mo 1.228, 2.4576, 3.072, 4.9152, 6.144, ma le 9.8304 Gbps Line Rate
I lenei mamanu example, o le simulation testbench e maua ai galuega faʻavae e pei o le amataga ma faʻatali mo loka, faʻasalalau ma maua pepa.
O le su'ega manuia o lo'o fa'aalia ai galuega e fa'amaonia ai amioga nei:
- O le manatu o tagata o tausia e toe setiina le IP core.
- O lo'o fa'atali le manatu o le kalani mo le fa'aogaina o alafa'amatalaga RX.
- O le manatu o le tagata o tausia e fa'asalalauina fa'alavalava i luga o le TX MII ma fa'atali mo fa'ata'ita'iga e lima e maua ile RX MII. Hyperframes e tuʻuina atu ma maua i luga ole MII faʻaoga e tusa ai ma faʻamatalaga CPRI v7.0.
Fa'aaliga: O fuafuaga a le CPRI e faʻatatau i le 1.2, 2.4, 3, 4.9, 6.1, ma le 9.8 Gbps laina laina faʻaogaina le 8b / 10b interface ma mamanu e faʻatatau i le 10.1, 12.1 ma le 24.3 Gbps (faʻatasi ma le leai o le RS-FEC) faʻaoga MII interface. O lenei mamanu exampe aofia ai se fa'ailoga ta'amilosaga e faitau ai le ta'amilosaga mai le TX i le RX. - E faitau e le tagata o tausia le tau o malaga taamilo ma siaki le mea o iai ma le sa'o o fa'amatalaga hyperframes i le itu o le RX MII pe a mae'a e le fata le faitauga o le toe fo'i.
Fa'amatalaga Fa'atatau
- CPRI Fa'amatalaga
Fuafuaga Meafaigaluega Example
Ata 8. Fuafuaga Meafaigaluega Example Ata poloka
Manatua
- O mamanu CPRI ma 2.4 / 4.9 / 9.8 Gbps CPRI laina laina faʻaoga 8b / 10b atinaʻe ma isi uma CPRI laina fua faʻatatau e faʻaogaina le MII interface.
- O fuafuaga a le CPRI i le 2.4/4.9/9.8 Gbps CPRI laina laina e mana'omia le 153.6 MHz transceiver reference clock ma isi laina CPRI uma e mana'omia le 184.32 MHz.
O le F-Tile CPRI PHY Intel FPGA IP fa'asologa o meafaigaluega fa'apitoaample aofia ai vaega nei:
- F-Tile CPRI PHY Intel FPGA IP autu.
- Packet client logic block lea e fa'atupu ma maua ai feoaiga.
- Fa'ailoga malaga taamilo.
- IOPLL e fa'atupu sampling le uati mo le fa'atonuga fa'aletonu i totonu o le IP, ma le ta'amilosaga ta'amilosaga vaega i le su'ega.
- System PLL e fa'atupu ai uati faiga mo le IP.
- Avalon®-MM address decoder e fa'asolo ai le toe fetuutuunaiga o avanoa tuatusi mo CPRI, Transceiver, ma Ethernet modules i le taimi e toe fa'aogaina ai avanoa.
- Punaoa ma su'esu'ega mo le fa'amautuina o le toe setiina ma le mata'ituina o uati ma nai vaega o tulaga.
- JTAG pule e feso'ota'i ma le System Console. E te fa'afeso'ota'i ma le tagata o tausia e ala ile System Console.
Fa'ailoga Fa'afeso'ota'i
Laulau 5. Fuafuaga Example Fa'ailoga Fa'amatalaga
| Fa'ailoga | Fa'atonuga | Fa'amatalaga |
| ref_clk100MHz | Ulufale | Fa'aofi le uati mo le avanoa CSR i feso'ota'iga toe fetu'una'iga uma. Aveta i le 100 MHz. |
| i_clk_ref[0] | Ulufale | Uati fa'asino mo le System PLL. Aveta i le 156.25 MHz. |
| i_clk_ref[1] | Ulufale | Transceiver faasinoupu uati. Ave taavale i
• 153.6 MHz mo laina laina CPRI 1.2, 2.4, 3, 4.9, 6.1, ma le 9.8 Gbps. • 184.32 MHz mo laina laina CPRI 10.1,12.1, ma le 24.3 Gbps fa'atasi ma le leai o se RS-FEC. |
| i_rx_serial[n] | Ulufale | Transceiver PHY fa'aofi fa'amaumauga fa'asologa. |
| o_tx_serial[n] | Tuuina atu | Transceiver PHY fa'amaumauga fa'asologa. |
Design Example Resitala
Laulau 6. Fuafuaga Example Resitala
| Numera alalaupapa | Tuatusi Autu (Byte Address) | Ituaiga Resitala |
|
0 |
0x00000000 | CPRI PHY Toe fa'atulagaina resitala mo Alaleo 0 |
| 0x00100000 | Ethernet Toefa'atonu resitala mo le Alalaupapa 0 | |
| 0x00200000 | Lesitala Reconfiguration Transceiver mo Alavai 0 | |
|
1(2) |
0x01000000 | CPRI PHY Toe fa'atulagaina resitala mo Alaleo 1 |
| 0x01100000 | Ethernet Toefa'atonu resitala mo le Alalaupapa 1 | |
| 0x01200000 | Lesitala Reconfiguration Transceiver mo Alavai 1 | |
|
2(2) |
0x02000000 | CPRI PHY Toe fa'atulagaina resitala mo Alaleo 2 |
| 0x02100000 | Ethernet Toefa'atonu resitala mo le Alalaupapa 2 | |
| 0x02200000 | Lesitala Reconfiguration Transceiver mo Alavai 2 | |
| faaauau… | ||
| Numera alalaupapa | Tuatusi Autu (Byte Address) | Ituaiga Resitala |
|
3(2) |
0x03000000 | CPRI PHY Toe fa'atulagaina resitala mo Alaleo 3 |
| 0x03100000 | Ethernet Toefa'atonu resitala mo le Alalaupapa 3 | |
| 0x03200000 | Lesitala Reconfiguration Transceiver mo Alavai 3 |
O nei resitala e fa'aagaga pe a le fa'aogaina le alalaupapa.
F-Tile CPRI PHY Intel FPGA IP Design Example User Guide Archives
Afai e le o lisiina se fa'asologa autu o le IP, e fa'aoga le ta'iala mo le fa'asologa muamua o le IP.
| Intel Quartus Prime Version | IP Core Version | Fa'aoga Taiala |
| 21.2 | 2.0.0 | F-Tile CPRI PHY Intel FPGA IP Design Example User Guide |
Fa'amatalaga Toe Iloiloga mo F-Tile CPRI PHY Intel FPGA IP Design Example User Guide
| Fa'amatalaga Fa'amaumauga | Intel Quartus Prime Version | IP Version | Suiga |
| 2021.10.04 | 21.3 | 3.0.0 |
|
| 2021.06.21 | 21.2 | 2.0.0 | Fa'asalalauga muamua. |
Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua.
*O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.
Pepa / Punaoa
 |
intel F-Tile CPRI PHY FPGA IP Design Example [pdf] Taiala mo Tagata Fa'aoga F-Tile CPRI PHY FPGA IP Design Example, PHY FPGA IP Design Example, F-Tile CPRI IP Design Example, IP Design Example, IP Design |
