intel F-Tile CPRI PHY FPGA IP Design Example

Quick Start Guide

F-Tile CPRI PHY Intel® FPGA IP core imapereka testbench yoyeserera komanso kapangidwe kazinthu kakale.ample yomwe imathandizira kusonkhanitsa ndi kuyesa kwa hardware. Mukapanga zojambula zakaleampndi, mkonzi wa parameter amangopanga files zofunika kuyerekezera, kusonkhanitsa, ndi kuyesa mapangidwe mu hardware.
Intel imaperekanso zophatikiza zokhazokhaample pulojekiti yomwe mungagwiritse ntchito kuyerekeza mwachangu malo oyambira a IP ndi nthawi yake.
F-Tile CPRI PHY Intel FPGA IP pachimake imapereka kuthekera kopanga kapangidwe kakaleampLes pazophatikizika zonse zothandizidwa za kuchuluka kwa njira za CPRI ndi mitengo yamitengo ya CPRI. Testbench ndi kapangidwe exampndikuthandizira kuphatikizika kwamitundu yambiri ya F-Tile CPRI PHY Intel FPGA IP pachimake.

Chithunzi 1. Njira Zachitukuko za Design Example

Zambiri Zogwirizana

• F-Tile CPRI PHY Intel FPGA IP User Guide
  • Kuti mudziwe zambiri pa F-tile CPRI PHY IP.
• F-Tile CPRI PHY Zolemba Zotulutsidwa za Intel FPGA IP
  • Ma IP Release Notes amalemba zosintha za IP pakutulutsa kwina.

Zofunikira pa Hardware ndi Mapulogalamu

Kuyesa example design, gwiritsani ntchito zida ndi mapulogalamu awa:

• Pulogalamu ya Intel Quartus® Prime Pro Edition
• System console
• Ma Simulators Othandizira:
  • Synopsy* VCS*
  • Zithunzi za VCS MX
  • Siemens* EDA ModelSim* SE kapena Questa*— Kope la Questa-Intel FPGA

Kupanga Mapangidwe

Chithunzi 2. Ndondomeko

Chithunzi 3. Exampndi Design Tab mu IP Parameter Editor

Kupanga pulojekiti ya Intel Quartus Prime Pro Edition:

1. Mu Intel Quartus Prime Pro Edition, dinani File ➤ Project Wizard Watsopano kuti apange polojekiti yatsopano ya Quartus Prime, kapena File ➤ Open Project kuti mutsegule pulojekiti yomwe ilipo ya Intel Quartus Prime. Wizard imakulimbikitsani kuti mutchule chipangizo.
2. Tchulani chipangizo cha banja la Agilex (I-series) ndikusankha chipangizo chomwe chikukwaniritsa zofunikira zonsezi:
   • Tile ya Transceiver ndi F-tile
   • Transceiver liwiro kalasi ndi -1 kapena -2
   • Kore liwiro kalasi ndi -1 kapena -2 kapena -3
3. Dinani Malizani.

Tsatirani izi kuti mupange F-Tile CPRI PHY Intel FPGA IP hardware design example ndi testbench:

1. Mu IP Catalog, pezani ndikusankha F-Tile CPRI PHY Intel FPGA IP. Zenera la New IP Variation likuwonekera.
2. Tchulani dzina lapamwamba pakusintha kwanu kwa IP. Mkonzi wa parameter amasunga zosintha za IP mu a file dzina .ip.
3. Dinani Chabwino. The parameter editor ikuwonekera.
4. Pa tabu ya IP, tchulani magawo akusintha kwanu kwa IP.
5. Pa Eksample Design tabu, pansi pa Eksampndi Design Files, sankhani njira yoyeserera kuti mupange testbench ndi polojekiti yokhayo. Sankhani njira ya Synthesis kuti mupange mawonekedwe a Hardware example. Muyenera kusankha chimodzi mwazosankha za Simulation ndi kaphatikizidwe kuti mupange zojambula zakaleample.
6. Pa Eksample Design tabu, pansi pa Generated HDL Format, sankhani Verilog HDL kapena VHDL. Mukasankha VHDL, muyenera kutsanzira testbench ndi choyimira chinenero chosakanikirana. Chipangizocho chikuyesedwa mu ex_ chikwatu ndi mtundu wa VHDL, koma testbench yayikulu file ndi System Verilog file.
7. Dinani Pangani Exampndi Design batani. Sankhani Exampzenera la Design Directory likuwonekera.
8. Ngati mukufuna kusintha kapangidwe example chikwatu njira kapena dzina kuchokera zosasintha zomwe zikuwonetsedwa (cpriphy_ftile_0_example_design), sakatulani njira yatsopano ndikulemba mawonekedwe atsopanoample directory name (ample_dir>).

Kapangidwe ka Kalozera

F-Tile CPRI PHY Intel FPGA IP core design example file akalozera ali ndi zotsatirazi zopangidwa files kwa kapangidwe example.

Chithunzi 4. Kapangidwe ka Kalozera wa Zopangidwa Exampndi Design

Table 1. Testbench File Kufotokozera

File Mayina	Kufotokozera
Key Testbench ndi Kuyerekeza Files
<design_example_dir>/example_testbench/basic_avl_tb_top.sv	Testbench yapamwamba kwambiri file. Testbench imayambitsa chopukutira cha DUT ndikuyendetsa ntchito za Verilog HDL kuti apange ndi kuvomereza mapaketi.
<design_example_dir>/example_testbench/ cpriphy_ftile_wrapper.sv	DUT wrapper yomwe imayambitsa DUT ndi zigawo zina za testbench.
Zolemba za Testbench(1)
<design_example_dir>/example_testbench/run_vsim.do	The Siemens EDA ModelSim SE kapena Questa kapena Questa-Intel FPGA Edition script kuyendetsa testbench.
<design_example_dir>/example_testbench/run_vcs.sh	Synopsys VCS script yoyendetsa testbench.
<design_example_dir>/example_testbench/run_vcsmx.sh	Synopsys VCS MX script (yophatikiza Verilog HDL ndi SystemVerilog yokhala ndi VHDL) kuyendetsa testbench.

Musanyalanyaze script ina iliyonse ya simulator muample_dir>/example_testbench/ chikwatu.

Table 2. Mapangidwe a Hardware Example File Kufotokozera

File Mayina	Kufotokozera
<design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.qpf	Intel Quartus Prime Project file.
<design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.qsf	Intel Quartus Prime projekiti yokhazikika file.
<design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.sdc	Zolepheretsa Zopanga za Synopsys files. Mutha kukopera ndi kusintha izi files pamapangidwe anu a Intel Agilex™.
<design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.v	Mapangidwe apamwamba a Verilog HDL example file.
<design_example_dir>/hardware_test_design/ cpriphy_ftile_wrapper.sv	DUT wrapper yomwe imayambitsa DUT ndi zigawo zina za testbench.
<design_example_dir>/hardware_test_design/ hwtest_sl/main_script.tcl	Chachikulu file kuti mupeze System Console.

Kutsanzira Design Exampndi Testbench

Chithunzi 5. Ndondomeko

Tsatirani izi kuti muyesere testbench:

1. Pakulamula, sinthani ku bukhu la testbench simulationample_dir>/example_testbench. cd /example_testbench
2. Thamangani quartus_tlg pa polojekiti yopangidwa file: quartus_tlg cpriphy_ftile_hw
3. Thamangani ip-setup-simulation: ip-setup-simulation -output-directory=./sim_script -use-relative-paths -quartus project=cpriphy_ftile_hw.qpf
4. Yendetsani script yoyeserera ya simulator yothandizidwa yomwe mungasankhe. Zolembazo zimaphatikiza ndikuyendetsa testbench mu simulator. Onani pa tebulo Masitepe Kuti Mutsanzire Testbench.
5. Unikani zotsatira. Testbench yopambana idalandira ma hyperframes asanu, ndikuwonetsa "PASSED".

Table 3. Njira Zotsanzira Testbench mu Synopsy VCS* Simulator

Woyeserera	Malangizo
Zithunzi za VCS	Mu mzere wolamula, lembani:
	sh run_vcs.sh
anapitiriza…

Woyeserera	Malangizo
Chithunzi cha VCS MX	Mu mzere wolamula, lembani:
	sh run_vcsmx.sh
ModelSim SE kapena Questa kapena Questa-Intel FPGA Edition	Mu mzere wolamula, lembani:
	vsim -do run_vsim.do
	Ngati mukufuna kuyerekezera popanda kubweretsa GUI, lembani:
	vsim -c -do run_vsim.do

Zotsatirazi sample output ikuwonetsa kuyesa koyeserera kopambana kwa 24.33024 Gbps ndi 4 CPRI njira:

Kupanga Ntchito Yophatikizira Yokha

Kupanga chophatikiza-chokha exampndi polojekiti, tsatirani izi:

1. Onetsetsani kapangidwe kakuphatikiza example generation yatha.
2. Mu pulogalamu ya Intel Quartus Prime Pro Edition, tsegulani pulojekiti ya Intel Quartus Prime Pro Editionample_dir>/compilation_test_design/cpriphy_ftile.qpf.
3. Pa Processing menyu, dinani Start Compilation.
4. Pambuyo pakuphatikiza bwino, malipoti a nthawi komanso kugwiritsa ntchito zida akupezeka mu gawo lanu la Intel Quartus Prime Pro Edition.

Zambiri Zogwirizana
Mapangidwe Otengera Mapangidwe Amayenda

Kupanga ndi Kukonza Design Exampndi mu Hardware

Kupanga kapangidwe ka hardware example ndikuikonza pa chipangizo chanu cha Intel Agilex, tsatirani izi:

1. Onetsetsani kuti hardware kapangidwe example generation yatha.
2. Mu pulogalamu ya Intel Quartus Prime Pro Edition, tsegulani pulojekiti ya Intel Quartus Primeample_dir>/hardware_test_design/ cpriphy_ftile_hw.qpf.
3. Sinthani .qsf file kuti mugawire zikhomo potengera zida zanu.
4. Pa Processing menyu, dinani Start Compilation.
5. Pambuyo pophatikiza bwino, a .sof file ikupezeka muample_dir>/hardware_test_design/output_files chikwatu.

Tsatirani izi kuti mukonze zojambula za Hardware example pa chipangizo cha Intel Agilex:

• Lumikizani Intel Agilex I-series Transceiver Signal Integrity Development Kit ku kompyuta yomwe ili nayo.
  Zindikirani: Zida zachitukuko zimakonzedweratu ndi ma frequency olondola a wotchi mwachisawawa. Simufunikanso kugwiritsa ntchito Clock Control application kukhazikitsa ma frequency.
• Pa Zida menyu, dinani Programmer.
• Mu Programmer, dinani Hardware Setup.
• Sankhani chipangizo chokonzera.
• Onetsetsani kuti Mode yakhazikitsidwa ku JTAG.
• Sankhani chipangizo cha Intel Agilex ndikudina Add Chipangizo. The Programmer akuwonetsa chithunzi cholumikizira cha kulumikizana pakati pa zida pa bolodi lanu.
• Mu mzere ndi .sof yanu, fufuzani bokosi la .sof.
• Chongani bokosi mu gawo la Pulogalamu/Sinthani.
• Dinani Yambani.

Zambiri Zogwirizana

• Mapangidwe Otengera Mapangidwe Amayenda
• Mapulogalamu a Intel FPGA Devices
• Kusanthula ndi Kuthetsa Mapangidwe ndi System Console

Kuyesa Hardware Design Example

Mukapanga F-Tile CPRI PHY Intel FPGA IP core design example ndikuikonza pa chipangizo chanu cha Intel Agilex, mutha kugwiritsa ntchito System Console kukonza maziko a IP ndi zolembera zake za PHY IP.
Kuti muyatse System Console ndikuyesa kapangidwe ka Hardware example, tsatirani izi:

1. Pambuyo pa mapangidwe a hardware example imakonzedwa pa chipangizo cha Intel Agilex, mu pulogalamu ya Intel Quartus Prime Pro Edition, pa Zida menyu, dinani Zida Zowonongeka pa System ➤ System Console.
2. Pagawo la Tcl Console, lembani cd hwtest kuti musinthe chikwatuample_dir>/hardware_test_design/hwtest_sl.
3. Lembani source main_script.tcl kuti mutsegule kulumikizana ndi JTAG mbuye ndikuyamba mayeso.

Design Example Kufotokozera

Mapangidwe example akuwonetsa magwiridwe antchito a F-Tile CPRI PHY Intel FPGA IP pachimake. Mutha kupanga mapangidwe kuchokera ku Example Design tabu mu F-Tile CPRI PHY Intel FPGA IP parameter editor.
Kupanga kapangidwe exampLero, muyenera kukhazikitsa kaye magawo amitundu yosiyanasiyana ya IP yomwe mukufuna kupanga pomaliza. Mutha kusankha kupanga ex designample ndi kapena popanda mawonekedwe a RS-FEC. Mbali ya RS-FEC ikupezeka ndi 10.1376, 12.1651 ndi 24.33024 Gbps CPRI mzere wa bit rates.
Table 4. F-Tile CPRI PHY Intel FPGA IP Core Feature Matrix

CPRI Line Bit Rate (Gbps)	Thandizo la RS-FEC	Clock (MHz)	Thandizo la Deterministic Latency
1.2288	Ayi	153.6	Inde
2.4576	Ayi	153.6	Inde
3.072	Ayi	153.6	Inde
4.9152	Ayi	153.6	Inde
6.144	Ayi	153.6	Inde
9.8304	Ayi	153.6	Inde
10.1376	Ndi ndi popanda	184.32	Inde
12.1651	Ndi ndi popanda	184.32	Inde
24.33024	Ndi ndi popanda	184.32	Inde

Mawonekedwe

• Pangani ex designample ndi mawonekedwe a RS-FEC
• Kuthekera koyambira kwa paketi kuphatikiza kuwerengera kwa latency yaulendo wobwerera

Simulation Design Example

Mapangidwe a F-Tile CPRI PHY Intel FPGA IP example amapanga testbench yoyeserera ndi kuyerekezera files yomwe imayambitsa F-Tile CPRI PHY Intel FPGA IP pachimake mukasankha njira ya Simulation.

Chithunzi 6. Chojambula cha Block cha 10.1316, 12.1651, ndi 24.33024 Gbps (ndi popanda RS-FEC) Mizere Yamzere

Chithunzi 7. Chojambula cha Block cha 1.228, 2.4576, 3.072, 4.9152, 6.144, ndi 9.8304 Gbps Line Rate

M'mapangidwe awa exampndi, kayeseleledwe testbench amapereka ntchito zofunika monga poyambira ndi kudikira loko, kufalitsa ndi kulandira mapaketi.
Kuthamanga kochita bwino kumawonetsa zotsatira zotsimikizira izi:

1. Malingaliro a kasitomala amakhazikitsanso IP core.
2. Malingaliro a kasitomala amadikirira kulumikizana kwa datapath ya RX.
3. Malingaliro a kasitomala amatumiza ma hyperframe pa mawonekedwe a TX MII ndikudikirira kuti ma hyperframe asanu alandiridwe pa mawonekedwe a RX MII. Ma Hyperframe amatumizidwa ndikulandiridwa pa mawonekedwe a MII malinga ndi CPRI v7.0.
   Zindikirani: Mapangidwe a CPRI omwe amayang'ana 1.2, 2.4, 3, 4.9, 6.1, ndi 9.8 Gbps mlingo amagwiritsa ntchito mawonekedwe a 8b / 10b ndi mapangidwe omwe amayang'ana 10.1, 12.1 ndi 24.3 Gbps (ndi popanda RS-FEC) amagwiritsa ntchito mawonekedwe a MII. Mapangidwe awa example imaphatikizapo kauntala yaulendo wobwerera kuwerengera ulendo wobwerera kuchokera ku TX kupita ku RX.
4. Malingaliro a kasitomala amawerenga mtengo wozungulira wa latency ndikuyang'ana zomwe zili ndi kulondola kwa data ya hyperframes kumbali ya RX MII pomwe kauntala ikamaliza kuwerengera kwanthawi yobwerera.

Zambiri Zogwirizana

• Zofunikira za CPRI

Mapangidwe a Hardware Example

Chithunzi 8. Mapangidwe a Hardware Exampndi Block Diagram

 

Zindikirani

1. CPRI imapanga ndi 2.4 / 4.9 / 9.8 Gbps CPRI mizere ya mzere imagwiritsa ntchito mawonekedwe a 8b / 10b ndi zina zonse za CPRI zopangira mizere zimagwiritsa ntchito mawonekedwe a MII.
2. Mapangidwe a CPRI okhala ndi 2.4 / 4.9 / 9.8 Gbps CPRI mizere ya mzere amafunikira 153.6 MHz transceiver reference clock ndi zina zonse za CPRI mizere imafunikira 184.32 MHz.

F-Tile CPRI PHY Intel FPGA IP core hardware design example ili ndi zigawo zotsatirazi:

• F-Tile CPRI PHY Intel FPGA IP core.
• Packet kasitomala logic block yomwe imapanga ndikulandila traffic.
• Kauntala yozungulira.
• IOPLL kupanga sampwotchi ya deterministic latency logic mkati mwa IP, ndi gawo la counter trip pa testbench.
• System PLL kuti apange mawotchi amtundu wa IP.
• Avalon®-MM adilesi ya decoder kuti afotokozerenso malo adilesi a CPRI, Transceiver, ndi Ethernet ma module panthawi yokonzanso.
• Magwero ndi ma probe otsimikizira kukhazikitsidwanso ndi kuyang'anira mawotchi ndi ma bits angapo.
• JTAG woyang'anira yemwe amalumikizana ndi System Console. Mumalumikizana ndi malingaliro a kasitomala kudzera pa System Console.

Zizindikiro za Interface

Table 5. Design Exampndi Interface Signals

Chizindikiro	Mayendedwe	Kufotokozera
ref_clk100MHz	Zolowetsa	Lowetsani wotchi yofikira CSR pamawonekedwe onse okonzanso. Kuthamanga pa 100 MHz.
i_clk_ref[0]	Zolowetsa	Wotchi yolozera ya System PLL. Yendetsani pa 156.25 MHz.
i_clk_ref[1]	Zolowetsa	Wotchi yowonetsera transceiver. Yendetsani pa • 153.6 MHz pa mlingo wa CPRI mzere 1.2, 2.4, 3, 4.9, 6.1, ndi 9.8 Gbps. • 184.32 MHz kwa CPRI mzere mitengo 10.1,12.1, ndi 24.3 Gbps ndi popanda RS-FEC.
i_rx_serial[n]	Zolowetsa	Transceiver PHY yolowetsa data.
o_tx_serial[n]	Zotulutsa	Transceiver PHY linanena bungwe deta siriyo.

Design Exampndi Registers

Table 6. Design Exampndi Registers

Nambala ya Channel	Adilesi Yoyambira (Byte Address)	Register Type
0	0x00000000 pa	CPRI PHY Reconfiguration registry for Channel 0
	0x00100000 pa	Ethernet Reconfiguration registry ya Channel 0
	0x00200000 pa	Transceiver Reconfiguration registry ya Channel 0
1(2)	0x01000000 pa	CPRI PHY Reconfiguration registry for Channel 1
	0x01100000 pa	Ethernet Reconfiguration registry ya Channel 1
	0x01200000 pa	Transceiver Reconfiguration registry ya Channel 1
2(2)	0x02000000 pa	CPRI PHY Reconfiguration registry for Channel 2
	0x02100000 pa	Ethernet Reconfiguration registry ya Channel 2
	0x02200000 pa	Transceiver Reconfiguration registry ya Channel 2
anapitiriza…

Nambala ya Channel	Adilesi Yoyambira (Byte Address)	Register Type
3(2)	0x03000000 pa	CPRI PHY Reconfiguration registry for Channel 3
	0x03100000 pa	Ethernet Reconfiguration registry ya Channel 3
	0x03200000 pa	Transceiver Reconfiguration registry ya Channel 3

Zolemberazi zimasungidwa ngati tchanelo sichikugwiritsidwa ntchito.

F-Tile CPRI PHY Intel FPGA IP Design Exampndi User Guide Archives

Ngati mtundu wa IP core sunatchulidwe, chiwongolero cha ogwiritsa ntchito pamtundu wakale wa IP akugwira ntchito.

Intel Quartus Prime Version	IP Core Version	Wogwiritsa Ntchito
21.2	2.0.0	F-Tile CPRI PHY Intel FPGA IP Design Exampndi User Guide

Mbiri Yokonzanso Zolemba za F-Tile CPRI PHY Intel FPGA IP Design Exampndi User Guide

Document Version	Intel Quartus Prime Version	Mtundu wa IP	Zosintha
2021.10.04	21.3	3.0.0	Thandizo lowonjezera la oyeserera atsopano mugawo: Zofunikira pa Hardware ndi Mapulogalamu. Masitepe osinthidwa mugawo: Kutsanzira Design Exampndi Testbench. Sinthani magawo otsatirawa ndi chidziwitso chatsopano cha mizere: Design Example Kufotokozera Simulation Design Example Zizindikiro za Interface Adasinthidwa adilesi mugawo: Design Exampndi Registers.
2021.06.21	21.2	2.0.0	Kutulutsidwa koyamba.

Malingaliro a kampani Intel Corporation Maumwini onse ndi otetezedwa. Intel, logo ya Intel, ndi zizindikiro zina za Intel ndi zizindikiro za Intel Corporation kapena mabungwe ake. Intel imatsimikizira kugwira ntchito kwa FPGA yake ndi zida za semiconductor malinga ndi zomwe zili pano malinga ndi chitsimikizo cha Intel, koma ili ndi ufulu wosintha zinthu ndi ntchito zilizonse nthawi iliyonse popanda kuzindikira. Intel sakhala ndi udindo kapena udindo chifukwa chakugwiritsa ntchito kapena kugwiritsa ntchito zidziwitso zilizonse, malonda, kapena ntchito zomwe zafotokozedwa pano kupatula monga momwe Intel adavomerezera momveka bwino. Makasitomala a Intel amalangizidwa kuti apeze mtundu waposachedwa kwambiri wamakina a chipangizocho asanadalire zidziwitso zilizonse zosindikizidwa komanso asanayike maoda azinthu kapena ntchito.
*Mayina ena ndi mtundu zitha kunenedwa kuti ndi za ena.

Zolemba / Zothandizira

intel F-Tile CPRI PHY FPGA IP Design Example [pdf] Buku Logwiritsa Ntchito F-Tile CPRI PHY FPGA IP Design Example, PHY FPGA IP Design Example, F-Tile CPRI IP Design Exampndi, IP Design Exampndi, IP Design

Maumboni

• Buku Logwiritsa Ntchito