intel F-Tile CPRI PHY FPGA IP Design Example
Tataiso ea ho Qala ka Potlako
F-Tile CPRI PHY Intel® FPGA IP core e fana ka mohlala oa tlhahlobo ea liteko le moralo oa hardware ex.ample e tšehetsang ho bokella le ho hlahloba hardware. Ha o hlahisa moqapi example, mohlophisi oa parameter o iketsetsa faele ea files bohlokoa ho etsisa, ho bokella, le ho leka moralo ho hardware.
Intel e boetse e fana ka mohlala oa ho kopanya feelaample projeke eo u ka e sebelisang ho hakanya kapele sebaka sa mantlha sa IP le nako.
F-Tile CPRI PHY Intel FPGA IP core e fana ka bokhoni ba ho hlahisa moralo examples bakeng sa metsoako eohle e tšehetsoeng ea palo ea likanale tsa CPRI le CPRI line bit rates. The testbench le moralo exampe ts'ehetsa mefuta e mengata ea liparamente tsa F-Tile CPRI PHY Intel FPGA IP ea mantlha.
Setšoantšo sa 1. Mehato ea Ntlafatso ea Moqapi Example
Lintlha Tse Amanang
- F-Tile CPRI PHY Intel FPGA IP User Guide
- Bakeng sa lintlha tse felletseng mabapi le F-tile CPRI PHY IP.
- F-Tile CPRI PHY Lintlha tsa Phatlalatso tsa Intel FPGA IP
- Lintlha tsa IP Release Notes li thathamisa liphetoho tsa IP tokollong e itseng.
Litlhoko tsa Hardware le Software
Ho leka example design, sebelisa hardware le software tse latelang:
- Intel Quartus® Prime Pro Edition software
- Khokahano ea sistimi
- Li-simulator tse tšehelitsoeng:
- Synopsy* VCS*
- Litlhaloso tsa VCS MX
- Siemens* EDA ModelSim* SE kapa Questa*— Khatiso ea Questa-Intel FPGA
Ho Hlahisa Moralo
Setšoantšo sa 2. Mokhoa
Setšoantšo sa 3. Example Design Tab ho IP Parameter Editor
Ho theha projeke ea Intel Quartus Prime Pro Edition:
- Ho Intel Quartus Prime Pro Edition, tobetsa File ➤ Project Wizard e Ncha ho theha projeke e ncha ea Quartus Prime, kapa File ➤ Open Project ho bula morero o teng oa Intel Quartus Prime. Wizate e o kopa hore o hlalose sesebediswa.
- Hlalosa lelapa la sesebelisoa Agilex (I-Series) 'me u khethe sesebelisoa se fihlelang litlhoko tsena kaofela:
- Tile ea Transceiver ke F-tile
- Lebelo la lebelo la transceiver ke -1 kapa -2
- Core lebelo kereiti -1 kapa -2 kapa -3
- Tobetsa Qetella.
Latela mehato ena ho hlahisa F-Tile CPRI PHY Intel FPGA IP hardware design example le testbench:
- Lethathamong la IP, fumana 'me u khethe F-Tile CPRI PHY Intel FPGA IP. Ho hlaha fensetere e ncha ea IP Variation.
- Hlalosa lebitso la boemo bo holimo bakeng sa phapang ea hau ea IP e tloaelehileng. Mohlophisi oa paramethara o boloka litlhophiso tsa phapang ea IP ho a file bitsetsoe .ip.
- Tobetsa OK. Mohlophisi oa parameter oa hlaha.
- Ho tab ea IP, hlakisa li-parameter tsa IP ea hau ea mantlha.
- Ho Example Design tab, tlas'a Example Design Files, khetha khetho ea Simulation ho hlahisa testbench le morero oa ho bokella feela. Khetha khetho ea Synthesis ho hlahisa moralo oa hardware example. U tlameha ho khetha bonyane khetho e le 'ngoe ea Simulation le Synthesis ho hlahisa moralo oa example.
- Ho Example Design tab, tlas'a Format ea HDL e hlahisitsoeng, khetha Verilog HDL kapa VHDL. Haeba u khetha VHDL, u tlameha ho etsisa testbench ka simulator ea puo e tsoakiloeng. Sesebelisoa se ntse se lekoa ho ex_ directory ke mohlala oa VHDL, empa testbench ea mantlha file ke System Verilog file.
- Tobetsa Hlahisa Example konopo ea Design. Khetha Exampho hlaha fensetere ea Design Directory.
- Haeba u batla ho fetola moralo examptsela ea directory kapa lebitso ho tsoa ho li-defaults tse bontšitsoeng (cpriphy_ftile_0_example_design), sheba tsela e ncha ebe u thaepa sebopeho se secha sa examplebitso la directory (ample_dir>).
Sebopeho sa Directory
The F-Tile CPRI PHY Intel FPGA IP core design example file li-directory li na le tse latelang tse hlahisitsoeng files bakeng sa moralo example.
Setšoantšo sa 4. Sebopeho sa Directory sa Example Design
Letlapa la 1. Testbench File Litlhaloso
| File Mabitso | Tlhaloso |
| Testbench ea bohlokoa le Simulation Files | |
| <design_example_dir>/ example_testbench/basic_avl_tb_top.sv | Testbench ea boemo bo holimo file. Testbench e tiisa sekoahelo sa DUT mme e tsamaisa mesebetsi ea Verilog HDL ho hlahisa le ho amohela lipakete. |
| <design_example_dir>/ example_testbench/ cpriphy_ftile_wrapper.sv | DUT wrapper e tiisang DUT le likarolo tse ling tsa testbench. |
| Mengolo ea Testbench(1) | |
| <design_example_dir>/ example_testbench/run_vsim.do | The Siemens EDA ModelSim SE kapa Questa kapa Questa-Intel FPGA Edition script ho tsamaisa testbench. |
| <design_example_dir>/ example_testbench/run_vcs.sh | Mongolo oa Synopsys VCS ho tsamaisa testbench. |
| <design_example_dir>/ example_testbench/run_vcsmx.sh | Sengoloa sa Synopsys VCS MX (se kopantsoeng le Verilog HDL le SystemVerilog le VHDL) ho tsamaisa benche ea liteko. |
Hlokomoloha mongolo ofe kapa ofe oa simulator hoample_dir>/example_testbench/ foldara.
Lethathamo la 2. Moqapi oa lisebelisoa tsa thepa Example File Litlhaloso
| File Mabitso | Litlhaloso |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.qpf | Morero oa mantlha oa Intel Quartus file. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.qsf | Tlhophiso ea morero oa Intel Quartus Prime file. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.sdc | Litšitiso tsa Moqapi oa Synopsys files. U ka li kopitsa le ho li fetola files bakeng sa moralo oa hau oa Intel Agilex™. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.v | Moralo oa maemo a holimo oa Verilog HDL example file. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_wrapper.sv | DUT wrapper e tiisang DUT le likarolo tse ling tsa testbench. |
| <design_example_dir>/hardware_test_design/ hwtest_sl/main_script.tcl | Ka sehloohong file bakeng sa ho fihlella System Console. |
Ho Etsisa Moralo Example Testbench
Setšoantšo sa 5. Mokhoa
Latela mehato ena ho etsisa testbench:
- Ka potlako ea taelo, fetola ho directory ea simulation ea testbenchample_dir>/example_testbench. cd /mohlample_testbench
- Matha quartus_tlg ho projeke e hlahisitsoeng file: quartus_tlg cpriphy_ftile_hw
- Matha ip-setup-simulation: ip-setup-simulation -output-directory=./sim_script -use-relative-paths -quartus project=cpriphy_ftile_hw.qpf
- Matha sengoloa sa ketsiso bakeng sa simulator e tšehelitsoeng eo u e khethileng. Script e bokella le ho tsamaisa testbench ho simulator. Sheba tafole Mehato ea ho etsisa Testbench.
- Sekaseka liphello. Testbench e atlehileng e fumane li-hyperframe tse hlano, 'me e bonts'a "PASSED".
Lethathamo la 3. Mehato ea ho Etsisa Testbench ho Synopsy VCS* Simulator
| Moetsisi | Litaelo | |
| VCS | Moleng oa taelo, thaepa: | |
| sh run_vcs.sh | ||
| e tsoela pele… | ||
| Moetsisi | Litaelo | |
| Tlhaloso: VCS MX | Moleng oa taelo, thaepa: | |
| sh run_vcsmx.sh | ||
| ModelSim SE kapa Khatiso ea Questa kapa Questa-Intel FPGA | Moleng oa taelo, thaepa: | |
| vsim -do run_vsim.do | ||
| Haeba u khetha ho etsisa ntle le ho hlahisa GUI, thaepa: | ||
| vsim -c -do run_vsim.do | ||
Tse latelang sample sephetho se bonts'a tlhahlobo e atlehileng ea tlhahlobo ea 24.33024 Gbps e nang le likanale tse 4 tsa CPRI:
Ho hlophisa Morero oa ho Kopanya Feela
Ho bokella mokhahlelo feela example morero, latela mehato ena:
- Netefatsa moetso oa moetso example moloko o felile.
- Ho software ea Intel Quartus Prime Pro Edition, bula morero oa Intel Quartus Prime Pro Editionample_dir>/compilation_test_design/cpriphy_ftile.qpf.
- Ho menu ea Processing, tobetsa Start Compilation.
- Kamora ho bokelloa ka katleho, litlaleho tsa nako le ts'ebeliso ea lisebelisoa li fumaneha lenaneong la hau la Intel Quartus Prime Pro Edition.
Lintlha Tse Amanang
Li-Block-Thehiloeng Moralo Phallang
Ho Kopanya le ho Hlophisa Moralo Example ho Hardware
Ho bokella moralo oa hardware example 'me u e hlophise sesebelisoa sa hau sa Intel Agilex, latela mehato ena:
- Netefatsa moralo oa hardware example moloko o felile.
- Ho software ea Intel Quartus Prime Pro Edition, bula morero oa Intel Quartus Primeample_dir>/hardware_test_design/ cpriphy_ftile_hw.qpf.
- Fetola .qsf file ho abela likhoele tse ipapisitseng le hardware ea hau.
- Ho menu ea Processing, tobetsa Start Compilation.
- Ka mor'a ho bokella ka katleho, a .sof file e fumaneha kaample_dir>/hardware_test_design/output_files directory.
Latela mehato ena ho hlophisa moralo oa hardware example sesebelisoa sa Intel Agilex:
- Hokela Intel Agilex I-series Transceiver Signal Integrity Development Kit khomphuteng e amohelang batho.
Tlhokomeliso: Setsi sa nts'etsopele se hlophisitsoe esale pele ka maqhubu a nepahetseng a oache ka ho sa feleng. Ha ho hlokahale hore u sebelise sesebelisoa sa Clock Control ho seta maqhubu. - Ho Tools menu, tobetsa Programmer.
- Ho "Programmer", tobetsa "Hardware Setup".
- Khetha sesebelisoa sa ho etsa mananeo.
- Netefatsa hore Mode e setetsoe ho JTAG.
- Khetha sesebelisoa sa Intel Agilex ebe o tobetsa Eketsa Sesebelisoa. Lenaneo le bonts'a setšoantšo sa li-block tsa likhokahano lipakeng tsa lisebelisoa tse botong ea hau.
- Moleng le .sof ea hau, hlahloba lebokose la .sof.
- Tshwaya lebokoso mo kholomong ya Lenaneo/Configure.
- Tobetsa Qala.
Lintlha Tse Amanang
- Li-Block-Thehiloeng Moralo Phallang
- Lisebelisoa tsa lisebelisoa tsa Intel FPGA
- Ho sekaseka le ho lokisa meralo ka System Console
Ho Lekola Moetso oa Hardware Example
Kamora hore o bokelle moralo oa mantlha oa F-Tile CPRI PHY Intel FPGA IP exampLe 'me u e hlophise sesebelisoa sa hau sa Intel Agilex, u ka sebelisa System Console ho hlophisa setsi sa IP le lirekoto tsa eona tsa mantlha tsa PHY IP.
Ho bulela System Console le ho leka moralo oa hardware example, latela mehato ena:
- Ka mor'a moralo oa hardware example e hlophisitsoe ho sesebelisoa sa Intel Agilex, ho software ea Intel Quartus Prime Pro Edition, ho Tools menu, tobetsa Tool Debugging Tools ➤ System Console.
- Fensetereng ea Tcl Console, thaepa cd hwtest ho fetolela directory hoample_dir>/hardware_test_design/hwtest_sl.
- Ngola mohloli main_script.tcl ho bula khokahanyo ho JTAG mong'a 'me u qale tlhahlobo.
Moqapi Example Tlhaloso
Moqapi example e bonts'a ts'ebetso ea mantlha ea F-Tile CPRI PHY Intel FPGA IP core. O ka hlahisa moralo ho tsoa ho Example Design tab ho F-Tile CPRI PHY Intel FPGA IP parameter mohlophisi.
Ho hlahisa moralo exampLeha ho le joalo, u tlameha ho qala ka ho beha litekanyetso tsa paramethara bakeng sa phapano ea mantlha ea IP eo u ikemiselitseng ho e hlahisa sehlahisoa sa hau sa ho qetela. U ka khetha ho hlahisa ex designample ka kapa ntle le tšobotsi ea RS-FEC. Sebopeho sa RS-FEC se fumaneha ka 10.1376, 12.1651 le 24.33024 Gbps CPRI line bit rates.
Letlapa la 4. F-Tile CPRI PHY Intel FPGA IP Core Feature Matrix
| CPRI Line Bit Rate (Gbps) | Tšehetso ea RS-FEC | Tshupanako (MHz) | Tšehetso ea Latency ea Deterministic |
| 1.2288 | Che | 153.6 | Ee |
| 2.4576 | Che | 153.6 | Ee |
| 3.072 | Che | 153.6 | Ee |
| 4.9152 | Che | 153.6 | Ee |
| 6.144 | Che | 153.6 | Ee |
| 9.8304 | Che | 153.6 | Ee |
| 10.1376 | Ka le Ntle | 184.32 | Ee |
| 12.1651 | Ka le Ntle | 184.32 | Ee |
| 24.33024 | Ka le Ntle | 184.32 | Ee |
Likaroloana
- Hlahisa sebopeho sa mohlalaample e nang le tšobotsi ea RS-FEC
- Bokhoni ba ho hlahloba liphutheloana ho kenyelletsa le palo ea latency ea maeto a ho khutla
Moqapi oa Ketsiso Example
Moetso oa F-Tile CPRI PHY Intel FPGA IP example hlahisa teko ea ketsiso le ketsiso files e tiisang motheo oa F-Tile CPRI PHY Intel FPGA IP ha u khetha khetho ea Simulation.
Setšoantšo sa 6. Block Diagram bakeng sa 10.1316, 12.1651, le 24.33024 Gbps (ka ntle le RS-FEC) Line Rates
Setšoantšo sa 7. Block Diagram bakeng sa 1.228, 2.4576, 3.072, 4.9152, 6.144, le 9.8304 Gbps Line Rate
Moqaping ona example, ketsiso testbench e fana ka tshebetso ya motheo e kang ho qala le ho emela ho notlela, fetisa le ho amohela lipakete.
Teko e atlehileng e bonts'a tlhahiso e netefatsang boitšoaro bo latelang:
- Monahano oa moreki o khutlisetsa IP core.
- Monahano oa moreki o emetse ho tsamaisana le datapath ea RX.
- Monahano oa moreki o fetisetsa li-hyperframe ho sebopeho sa TX MII ebe o emela hore li-hyperframe tse hlano li amoheloe ho interface ea RX MII. Li-hyperframes li fetisoa 'me li amoheloa ka sebopeho sa MII ho latela litlhaloso tsa CPRI v7.0.
Hlokomela: CPRI e qapa e lebisang ho 1.2, 2.4, 3, 4.9, 6.1, le 9.8 Gbps line rate e sebelisa 8b / 10b interface le meralo e lebisang ho 10.1, 12.1 le 24.3 Gbps (e nang le ntle le RS-FEC) e sebelisa sebopeho sa MII. Moqapi ona example kenyelletsa khaontara ea ho khutla ho bala nako ea ho khutla ho tloha TX ho ea RX. - Monahano oa moreki o bala boleng ba nako ea ho khutla le ho hlahloba litaba le ho nepahala ha data ea hyperframes lehlakoreng la RX MII hang ha k'hamphani e phethela palo ea nako ea ho khutla.
Lintlha Tse Amanang
- Litlhaloso tsa CPRI
Moqapi oa lisebelisoa tsa thepa Example
Setšoantšo sa 8. Sebopeho sa Hardware Example Block Diagram
Hlokomela
- CPRI e qapa ka 2.4 / 4.9 / 9.8 Gbps CPRI line rates e sebelisa 8b / 10b interface le tse ling tsohle tsa CPRI line rates meralo sebelisa MII interface.
- Liqapi tsa CPRI tse nang le 2.4 / 4.9 / 9.8 Gbps CPRI line rates li hloka 153.6 MHz transceiver reference clock le tse ling tsohle tsa CPRI line litekanyetso li hloka 184.32 MHz.
The F-Tile CPRI PHY Intel FPGA IP core hardware design example kenyeletsa likarolo tse latelang:
- F-Tile CPRI PHY Intel FPGA IP ea mantlha.
- Packet client logic block e hlahisang le ho amohela sephethephethe.
- Khaontara ea maeto a ho khutla.
- IOPLL ho hlahisa sampoache bakeng sa deterministic latency logic ka hare ho IP, le karolo ea counter trip ea ho khutla ho testbench.
- System PLL ho hlahisa lioache tsa sistimi bakeng sa IP.
- Avalon®-MM aterese ea decoder ho khetholla sebaka sa aterese sa CPRI, Transceiver, le Ethernet nakong ea phihlello ea ntlafatso.
- Mehloli le lipatlisiso tsa ho tiisa litlhophiso le ho beha leihlo lioache le maemo a seng makae.
- JTAG molaoli ea buisanang le System Console. U buisana le logic ea bareki ka System Console.
Lipontšo tsa Interface
Lethathamo la 5. Moqapi Example Lipontšo tsa Interface
| Letshwao | Tataiso | Tlhaloso |
| ref_clk100MHz | Kenyeletso | Oache e kentsoeng bakeng sa phihlello ea CSR lihokelong tsohle tsa tlhophiso. Khanna ka lebelo la 100 MHz. |
| i_clk_ref[0] | Kenyeletso | Oache ea litšupiso bakeng sa System PLL. Khanna ho 156.25 MHz. |
| i_clk_ref[1] | Kenyeletso | Oache ea litšupiso ea transceiver. Khanna ho
• 153.6 MHz bakeng sa sekhahla sa mohala oa CPRI 1.2, 2.4, 3, 4.9, 6.1, le 9.8 Gbps. • 184.32 MHz bakeng sa CPRI line rates 10.1,12.1, le 24.3 Gbps le ntle le RS-FEC. |
| i_rx_serial[n] | Kenyeletso | Transceiver PHY e kenya data ea seriale. |
| o_tx_serial[n] | Sephetho | Lintlha tsa seriale tsa Transceiver PHY. |
Moqapi Example Registers
Lethathamo la 6. Moqapi Example Registers
| Nomoro ea Channel | Aterese ea Motheo (Aterese ea Byte) | Mofuta oa Ngoliso |
|
0 |
0x00000000 | CPRI PHY Reconfiguration ngoliso bakeng sa Channel 0 |
| 0x00100000 | Ethernet Reconfiguration ngoliso bakeng sa Channel 0 | |
| 0x00200000 | Lirekoto tsa Transceiver Reconfiguration bakeng sa Channel 0 | |
|
1(2) |
0x01000000 | CPRI PHY Reconfiguration ngoliso bakeng sa Channel 1 |
| 0x01100000 | Ethernet Reconfiguration ngoliso bakeng sa Channel 1 | |
| 0x01200000 | Lirekoto tsa Transceiver Reconfiguration bakeng sa Channel 1 | |
|
2(2) |
0x02000000 | CPRI PHY Reconfiguration ngoliso bakeng sa Channel 2 |
| 0x02100000 | Ethernet Reconfiguration ngoliso bakeng sa Channel 2 | |
| 0x02200000 | Lirekoto tsa Transceiver Reconfiguration bakeng sa Channel 2 | |
| e tsoela pele… | ||
| Nomoro ea Channel | Aterese ea Motheo (Aterese ea Byte) | Mofuta oa Ngoliso |
|
3(2) |
0x03000000 | CPRI PHY Reconfiguration ngoliso bakeng sa Channel 3 |
| 0x03100000 | Ethernet Reconfiguration ngoliso bakeng sa Channel 3 | |
| 0x03200000 | Lirekoto tsa Transceiver Reconfiguration bakeng sa Channel 3 |
Lirekoto tsena li bolokiloe haeba mocha o sa sebelisoe.
F-Tile CPRI PHY Intel FPGA IP Design Example User Guide Archives
Haeba mofuta oa IP core o sa thathamisoa, ho sebetsa tataiso ea mosebelisi bakeng sa mofuta o fetileng oa IP.
| Intel Quartus Prime Version | IP Core Version | Bukana ea Mosebelisi |
| 21.2 | 2.0.0 | F-Tile CPRI PHY Intel FPGA IP Design Example Bukana ea Mosebelisi |
Nalane ea Phetoho ea Litokomane bakeng sa F-Tile CPRI PHY Intel FPGA IP Design Example Bukana ea Mosebelisi
| Tokomane Version | Intel Quartus Prime Version | IP Version | Liphetoho |
| 2021.10.04 | 21.3 | 3.0.0 |
|
| 2021.06.21 | 21.2 | 2.0.0 | Tokollo ea pele. |
Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso.
*Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.
Litokomane / Lisebelisoa
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intel F-Tile CPRI PHY FPGA IP Design Example [pdf] Bukana ea Mosebelisi F-Tile CPRI PHY FPGA IP Design Example, PHY FPGA IP Design Example, F-Tile CPRI IP Design Example, IP Design Example, IP Design |
