intel F-Tile CPRI PHY FPGA IP Tsim Example

Phau Ntawv Qhia Pib Ceev

F-Tile CPRI PHY Intel® FPGA IP core muab lub simulation testbench thiab kho vajtse tsim example uas txhawb kev muab tso ua ke thiab kev sim kho vajtse. Thaum koj tsim tus tsim example, parameter editor cia li tsim cov files yuav tsum simulate, compile, thiab sim tus tsim nyob rau hauv hardware.
Intel tseem muab kev sau ua ke nkaus xwb example qhov project uas koj tuaj yeem siv los kwv yees tus IP core cheeb tsam sai thiab sijhawm.
F-Tile CPRI PHY Intel FPGA IP core muab lub peev xwm ntawm kev tsim qauv examples rau txhua qhov kev txhawb nqa ua ke ntawm tus lej ntawm CPRI raws thiab CPRI kab me ntsis tus nqi. The testbench thiab design example txhawb ntau qhov kev sib txuas ntawm F-Tile CPRI PHY Intel FPGA IP core.

Daim duab 1. Kev Txhim Kho Cov kauj ruam rau tus tsim Example

Cov ntaub ntawv ntsig txog

• F-Tile CPRI PHY Intel FPGA IP Tus Neeg Siv Qhia
  • Yog xav paub ntxiv txog F-tile CPRI PHY IP.
• F-Tile CPRI PHY Intel FPGA IP Tso Lus Sau
  • IP Release Notes teev IP hloov pauv hauv ib qho kev tso tawm.

Hardware thiab Software Requirements

Mus kuaj tus example tsim, siv hardware thiab software hauv qab no:

• Intel Quartus® Prime Pro Edition software
• System console
• Txhawb Simulators:
  • Synopsys* VCS*
  • Synopsys VCS MX
  • Siemens* EDA ModelSim* SE or Questa* — Questa-Intel FPGA Edition

Tsim tus Tsim

Daim duab 2. Cov txheej txheem

Daim duab 3. Example Design Tab hauv IP Parameter Editor

Txhawm rau tsim qhov project Intel Quartus Prime Pro Edition:

1. Hauv Intel Quartus Prime Pro Edition, nyem File ➤ New Project Wizard los tsim ib qhov project Quartus Prime tshiab, lossis File ➤ Qhib Project qhib qhov project Intel Quartus Prime uas twb muaj lawm. Tus wizard qhia koj kom qhia meej lub cuab yeej.
2. Qhia cov cuab yeej cuab tam tsev neeg Agilex (I-series) thiab xaiv ib lub cuab yeej uas ua tau raws li tag nrho cov kev cai no:
   • Transceiver pobzeb yog F-tile
   • Transceiver ceev qib yog -1 lossis -2
   • Core ceev qib yog -1 lossis -2 lossis -3
3. Nyem Ua kom tiav.

Ua raws li cov kauj ruam no los tsim F-Tile CPRI PHY Intel FPGA IP kho vajtse tsim example and testbench:

1. Hauv IP Catalog, nrhiav thiab xaiv F-Tile CPRI PHY Intel FPGA IP. Lub qhov rais tshiab IP Variation tshwm.
2. Qhia lub npe saum toj kawg nkaus rau koj tus IP kev hloov pauv. Tus parameter editor txuag tus IP variation nqis hauv a file npe .ip ib.
3. Nyem OK. Cov parameter editor tshwm.
4. Ntawm tus IP tab, qhia qhov tsis muaj rau koj tus IP qhov hloov pauv.
5. Hauv Example Design tab, under Examptsim Files, xaiv qhov kev xaiv Simulation los tsim lub testbench thiab qhov kev tso ua ke nkaus xwb. Xaiv qhov kev xaiv Synthesis los tsim kho vajtse tsim example. Koj yuav tsum xaiv yam tsawg kawg ib qho ntawm Simulation thiab Synthesis kev xaiv los tsim cov qauv tsim example.
6. Hauv Example Design tab, nyob rau hauv Generated HDL Format, xaiv Verilog HDL lossis VHDL. Yog tias koj xaiv VHDL, koj yuav tsum simulate lub testbench nrog cov lus sib xyaw simulator. Cov cuab yeej nyob rau hauv kev sim hauv ex_ directory yog VHDL qauv, tab sis lub ntsiab testbench file yog System Verilog file.
7. Nyem qhov Generate Example Design button. Xaiv Example Design Directory window tshwm.
8. Yog tias koj xav hloov kho tus tsim example directory path los yog lub npe los ntawm lub neej ntawd tso tawm (cpriphy_ftile_0_example_design), xauj rau txoj hauv kev tshiab thiab ntaus tus qauv tshiab examplub npe directory (ample_dir>).

Directory Structure

F-Tile CPRI PHY Intel FPGA IP core tsim example file directory muaj cov nram qab no generated files rau tus tsim example.

Daim duab 4. Directory Structure ntawm Generated Examptsim

Rooj 1. Testbench File Cov lus piav qhia

File Cov npe	Kev piav qhia
Qhov tseem ceeb Testbench thiab Simulation Files
<design_example_dir>/ example_testbench/basic_avl_tb_top.sv	Sab saum toj-theem testbench file. Lub testbench instantiates DUT wrapper thiab khiav Verilog HDL cov dej num los tsim thiab txais cov pob ntawv.
<design_example_dir>/ example_testbench/cpriphy_ftile_wrapper.sv	DUT wrapper uas instantiates DUT thiab lwm yam testbench Cheebtsam.
Testbench Scripts (1)
<design_example_dir>/ example_testbench/run_vsim.do	Siemens EDA ModelSim SE los yog Questa los yog Questa-Intel FPGA Tsab ntawv sau los khiav lub testbench.
<design_example_dir>/ example_testbench/run_vcs.sh	Synopsys VCS tsab ntawv los khiav lub testbench.
<design_example_dir>/ example_testbench/run_vcsmx.sh	Cov Synopsys VCS MX tsab ntawv (ua ke Verilog HDL thiab SystemVerilog nrog VHDL) los khiav lub testbench.

Tsis quav ntsej lwm yam simulator tsab ntawv hauvample_dir>/example_testbench/ folder.

Table 2. Hardware Design Example File Cov lus piav qhia

File Cov npe	Cov lus piav qhia
<design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.qpf	Qhov project Intel Quartus Prime file.
<design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.qsf	Intel Quartus Prime qhov project teeb tsa file.
<design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.sdc	Synopsys Design Constraints files. Koj tuaj yeem luam thiab hloov cov no files rau koj tus kheej Intel Agilex™ tsim.
<design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.v	Sab saum toj-theem Verilog HDL tsim example file.
<design_example_dir>/hardware_test_design/ cpriphy_ftile_wrapper.sv	DUT wrapper uas instantiates DUT thiab lwm yam testbench Cheebtsam.
<design_example_dir>/hardware_test_design/ hwtest_sl/main_script.tcl	Main file rau kev nkag mus rau System Console.

Simulating Design Exampua Testbench

Daim duab 5. Cov txheej txheem

Ua raws li cov kauj ruam no los simulate lub testbench:

1. Ntawm qhov hais kom ua, hloov mus rau testbench simulation directoryample_dir>/example_testbench. cd /example_testbench
2. Khiav quartus_tlg ntawm qhov project generated file: quartus_tlg cpriphy_ftile_hw
3. Khiav ip-setup-simulation: ip-setup-simulation -output-directory=./sim_script -use-relative-paths -quartus project=cpriphy_ftile_hw.qpf
4. Khiav cov ntawv simulation rau qhov kev txhawb nqa simulator ntawm koj xaiv. Cov ntawv sau ua ke thiab khiav lub testbench hauv lub simulator. Xa mus rau lub rooj Cov kauj ruam los simulate Testbench.
5. Txheeb xyuas cov txiaj ntsig. Lub testbench ua tiav tau txais tsib hyperframes, thiab qhia "PASSED".

Table 3. Cov kauj ruam los simulate Testbench hauv Synopsys VCS* Simulator

Simulator	Cov lus qhia
VCS	Hauv kab hais kom ua, ntaus:
	sh run_vcs.sh
txuas ntxiv…

Simulator	Cov lus qhia
VCS MX	Hauv kab hais kom ua, ntaus:
	sh run_vcsmx.sh
ModelSim SE lossis Questa lossis Questa-Intel FPGA Edition	Hauv kab hais kom ua, ntaus:
	vsim -do run_vsim.do
	Yog tias koj xav simulate yam tsis tau nqa GUI, ntaus:
	vsim -c -do run_vsim.do

Cov nram qab no sample cov zis qhia txog qhov ua tau zoo simulation sim khiav rau 24.33024 Gbps nrog 4 CPRI raws:

Compiling the Compilation-Tsuas Project

Txhawm rau muab tso ua ke-tsuas yog example project, ua raws li cov kauj ruam no:

1. Xyuas kom muab tso ua ke tsim example tiam tag.
2. Hauv Intel Quartus Prime Pro Edition software, qhib Intel Quartus Prime Pro Edition projectample_dir>/compilation_test_design/cpriphy_ftile.qpf.
3. Nyob rau hauv cov ntawv qhia zaub mov, nyem Start Compilation.
4. Tom qab kev ua tiav tiav, cov lus ceeb toom rau lub sijhawm thiab kev siv cov peev txheej muaj nyob hauv koj qhov kev sib tham Intel Quartus Prime Pro Edition.

Cov ntaub ntawv ntsig txog
Block-Based Design Flows

Compiling thiab Configuring Design Examphauv Hardware

Txhawm rau sau cov khoom siv kho vajtse example thiab teeb tsa nws ntawm koj lub cuab yeej Intel Agilex, ua raws li cov kauj ruam no:

1. Xyuas kom hardware design example tiam tag.
2. Hauv Intel Quartus Prime Pro Edition software, qhib Intel Quartus Prime projectample_dir>/hardware_test_design/ cpriphy_ftile_hw.qpf.
3. Kho cov .qsf file los muab cov pins raws li koj qhov kho vajtse.
4. Nyob rau hauv cov ntawv qhia zaub mov, nyem Start Compilation.
5. Tom qab kev ua tiav tiav, a .sof file muaj nyob rau hauvample_dir>/hardware_test_design/output_files cov directory.

Ua raws li cov kauj ruam no los tsim kho kho vajtse example ntawm Intel Agilex ntaus ntawv:

• Txuas Intel Agilex I-series Transceiver Signal Integrity Development Kit rau lub khoos phis tawm.
  Nco tseg: Cov khoom siv txhim kho yog preprogrammed nrog lub moos kom raug raws li lub neej ntawd. Koj tsis tas yuav siv daim ntawv thov Clock Control los teeb tsa cov zaus.
• Hauv cov cuab yeej ntawv qhia zaub mov, nyem Programmer.
• Hauv Programmer, nyem Hardware Setup.
• Xaiv ib lub programming ntaus ntawv.
• Xyuas kom meej tias hom yog teem rau JTAG.
• Xaiv Intel Agilex ntaus ntawv thiab nyem Ntxiv Ntaus. Tus Programmer qhia ib daim duab thaiv ntawm kev sib txuas ntawm cov khoom siv ntawm koj lub rooj tsavxwm.
• Hauv kab nrog koj .sof, kos lub thawv rau .sof.
• Kos lub npov nyob rau hauv Program/Configure kem.
• Nyem Pib.

Cov ntaub ntawv ntsig txog

• Block-Based Design Flows
• Programming Intel FPGA Devices
• Txheeb xyuas thiab Debugging Designs nrog System Console

Testing Hardware Design Example

Tom qab koj suav nrog F-Tile CPRI PHY Intel FPGA IP core tsim example thiab teeb tsa nws ntawm koj lub cuab yeej Intel Agilex, koj tuaj yeem siv System Console los pab txhawb IP core thiab nws cov PHY IP core registers.
Txhawm rau qhib qhov System Console thiab sim kho vajtse tsim example, ua raws li cov kauj ruam no:

1. Tom qab kho vajtse tsim example yog teeb tsa ntawm Intel Agilex ntaus ntawv, hauv Intel Quartus Prime Pro Edition software, ntawm cov cuab yeej ntawv qhia zaub mov, nyem System Debugging Tools ➤ System Console.
2. Hauv Tcl Console pane, ntaus cd hwtest hloov cov npe rauample_dir>/hardware_test_design/hwtest_sl.
3. Ntaus qhov chaw main_script.tcl qhib kev sib txuas rau JTAG tswv thiab pib qhov kev xeem.

Tsim Examplus piav qhia

Design example qhia txog kev ua haujlwm yooj yim ntawm F-Tile CPRI PHY Intel FPGA IP core. Koj tuaj yeem tsim qhov tsim los ntawm Example Tsim tab hauv F-Tile CPRI PHY Intel FPGA IP parameter editor.
Tsim kom muaj tus tsim example, koj yuav tsum xub teem lub parameter qhov tseem ceeb rau tus IP core variation koj npaj siab yuav tsim nyob rau hauv koj cov khoom kawg. Koj tuaj yeem xaiv los tsim tus tsim example nrog lossis tsis muaj RS-FEC feature. RS-FEC feature muaj nrog 10.1376, 12.1651 thiab 24.33024 Gbps CPRI kab me ntsis nqi.
Table 4. F-Tile CPRI PHY Intel FPGA IP Core Feature Matrix

CPRI Kab ntsis tus nqi (Gbps)	RS-FEC Kev them nyiaj yug	Lub moos siv (MHz)	Txiav txim siab Latency Support
1.2288	Tsis muaj	153.6	Yog lawm
2.4576	Tsis muaj	153.6	Yog lawm
3.072	Tsis muaj	153.6	Yog lawm
4.9152	Tsis muaj	153.6	Yog lawm
6.144	Tsis muaj	153.6	Yog lawm
9.8304	Tsis muaj	153.6	Yog lawm
10.1376	Nrog thiab Tsis muaj	184.32	Yog lawm
12.1651	Nrog thiab Tsis muaj	184.32	Yog lawm
24.33024	Nrog thiab Tsis muaj	184.32	Yog lawm

Nta

• Tsim tus tsim example nrog RS-FEC feature
• Cov peev txheej tshawb xyuas pob ntawv suav nrog kev ncig ncig mus ncig latency suav

Simulation Design Example

F-Tile CPRI PHY Intel FPGA IP tsim example generates ib simulation testbench thiab simulation files uas instantiates F-Tile CPRI PHY Intel FPGA IP core thaum koj xaiv qhov kev xaiv Simulation.

Daim duab 6. Block Diagram rau 10.1316, 12.1651, thiab 24.33024 Gbps (nrog thiab tsis muaj RS-FEC) Kab Nqi

Daim duab 7. Block Diagram rau 1.228, 2.4576, 3.072, 4.9152, 6.144, thiab 9.8304 Gbps Kab Rate

Nyob rau hauv no tsim example, lub simulation testbench muab kev ua haujlwm yooj yim xws li pib thiab tos rau xauv, xa thiab tau txais pob ntawv.
Qhov kev sim ua tiav ua tiav tso tawm cov zis lees paub cov cwj pwm hauv qab no:

1. Cov neeg siv logic rov pib dua tus IP core.
2. Cov neeg siv khoom logic tos rau RX datapath kev sib raug zoo.
3. Cov neeg siv logic xa cov hyperframes ntawm TX MII interface thiab tos tsib hyperframes kom tau txais ntawm RX MII interface. Hyperframes raug xa mus thiab tau txais ntawm MII interface raws li CPRI v7.0 specifications.
   Nco tseg: CPRI tsim cov phiaj xwm 1.2, 2.4, 3, 4.9, 6.1, thiab 9.8 Gbps kab tus nqi siv 8b / 10b interface thiab cov qauv tsim uas lub hom phiaj 10.1, 12.1 thiab 24.3 Gbps (nrog thiab tsis muaj RS-FEC) siv MII interface. Qhov no tsim example suav nrog lub txee ncig mus ncig los suav cov kev ncig mus ncig latency ntawm TX rau RX.
4. Tus neeg siv lub logic nyeem cov nqi ncig mus ncig latency thiab kuaj xyuas cov ntsiab lus thiab qhov tseeb ntawm cov ntaub ntawv hyperframes ntawm RX MII sab thaum lub txee ua tiav qhov kev mus ncig latency suav.

Cov ntaub ntawv ntsig txog

• CPRI Specifications

Hardware Design Example

Daim duab 8. Hardware Design Exampthiab Block Diagram

 

Nco tseg

1. CPRI tsim nrog 2.4 / 4.9 / 9.8 Gbps CPRI kab nqi siv 8b / 10b interface thiab tag nrho lwm cov kab CPRI tus nqi tsim siv MII interface.
2. CPRI tsim nrog 2.4/4.9/9.8 Gbps CPRI kab tus nqi xav tau 153.6 MHz transceiver siv moos thiab tag nrho lwm cov kab CPRI tus nqi xav tau 184.32 MHz.

F-Tile CPRI PHY Intel FPGA IP core hardware tsim example suav nrog cov hauv qab no:

• F-Tile CPRI PHY Intel FPGA IP core.
• Packet client logic block uas tsim thiab tau txais kev khiav tsheb.
• Round trip counter.
• IOPLL los tsim sampling moos rau kev txiav txim siab latency logic sab hauv IP, thiab ncig ncig ncig lub txee tiv thaiv ntawm testbench.
• System PLL los tsim lub moos moos rau IP.
• Avalon®-MM chaw nyob decoder los txiav txim siab qhov chaw nyob ntawm qhov chaw nyob rau CPRI, Transceiver, thiab Ethernet modules thaum lub sij hawm nkag mus rau reconfiguration.
• Cov peev txheej thiab kev sojntsuam rau kev lees paub rov pib dua thiab saib xyuas lub moos thiab ob peb qhov xwm txheej.
• JTAG controller uas sib txuas lus nrog System Console. Koj sib txuas lus nrog tus neeg siv khoom logic los ntawm System Console.

Interface Signals

Table 5. Tsim Example Interface Signals

Teeb liab	Kev taw qhia	Kev piav qhia
ref_clk100MHz	Tswv yim	Input moos rau CSR nkag mus rau tag nrho cov kev teeb tsa interfaces. Tsav ntawm 100 MHz.
i_clk_ref[0]	Tswv yim	Kev siv moos rau System PLL. Tsav ntawm 156.25 MHz.
i_clk_ref[1]	Tswv yim	Transceiver siv moos. Tsav ntawm • 153.6 MHz rau CPRI kab tus nqi 1.2, 2.4, 3, 4.9, 6.1, thiab 9.8 Gbps. • 184.32 MHz rau CPRI kab tus nqi 10.1,12.1, thiab 24.3 Gbps nrog thiab tsis muaj RS-FEC.
i_rx_serial[n]	Tswv yim	Transceiver PHY input serial cov ntaub ntawv.
o_tx_serial[n]	Tso zis	Transceiver PHY tso zis serial cov ntaub ntawv.

Tsim Example Registers

Table 6. Tsim Example Registers

Channel Number	Base Chaw Nyob (Byte Chaw Nyob)	Sau npe hom
0	0 x 00000000	CPRI PHY Reconfiguration sau npe rau Channel 0
	0 x 00100000	Ethernet Reconfiguration sau npe rau Channel 0
	0 x 00200000	Transceiver Reconfiguration sau npe rau Channel 0
1(2)	0 x 01000000	CPRI PHY Reconfiguration sau npe rau Channel 1
	0 x 01100000	Ethernet Reconfiguration sau npe rau Channel 1
	0 x 01200000	Transceiver Reconfiguration sau npe rau Channel 1
2(2)	0 x 02000000	CPRI PHY Reconfiguration sau npe rau Channel 2
	0 x 02100000	Ethernet Reconfiguration sau npe rau Channel 2
	0 x 02200000	Transceiver Reconfiguration sau npe rau Channel 2
txuas ntxiv…

Channel Number	Base Chaw Nyob (Byte Chaw Nyob)	Sau npe hom
3(2)	0 x 03000000	CPRI PHY Reconfiguration sau npe rau Channel 3
	0 x 03100000	Ethernet Reconfiguration sau npe rau Channel 3
	0 x 03200000	Transceiver Reconfiguration sau npe rau Channel 3

Cov npe no tau tshwj tseg yog tias tsis siv channel.

F-Tile CPRI PHY Intel FPGA IP Tsim Example User Guide Archives

Yog tias tus IP core version tsis tau teev tseg, cov lus qhia siv rau tus IP core version dhau los siv.

Intel Quartus Prime Version	IP Core Version	Cov neeg siv phau ntawv qhia
21.2	2.0.0	F-Tile CPRI PHY Intel FPGA IP Tsim Example User Guide

Cov ntaub ntawv kho dua tshiab rau F-Tile CPRI PHY Intel FPGA IP Tsim Example User Guide

Cov ntaub ntawv Version	Intel Quartus Prime Version	IP Version	Hloov
2021.10.04	21.3	3.0.0	Ntxiv kev txhawb nqa rau cov simulator tshiab hauv ntu: Hardware thiab Software Requirements. Hloov kho cov kauj ruam hauv ntu: Simulating Design Exampua Testbench. Hloov kho cov ntu hauv qab no nrog cov ntaub ntawv tus nqi tshiab: Tsim Examplus piav qhia Simulation Design Example Interface Signals Hloov kho qhov chaw nyob hauv seem: Tsim Example Registers.
2021.06.21	21.2	2.0.0	Kev tso tawm thawj zaug.

Intel Corporation. Txhua txoj cai. Intel, Intel logo, thiab lwm yam Intel cov cim yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom haum. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam.
* Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.

Cov ntaub ntawv / Cov ntaub ntawv

intel F-Tile CPRI PHY FPGA IP Tsim Example [ua pdf] Cov neeg siv phau ntawv qhia F-Tile CPRI PHY FPGA IP Tsim Example, PHY FPGA IP Design Example, F-Tile CPRI IP Design Example, IP Design Example, IP Design

Cov ntaub ntawv

• Cov neeg siv phau ntawv