intel F-Tile CPRI PHY FPGA IP Design Example
Isikhokelo sokuQalisa ngokukhawuleza
I-F-Tile CPRI PHY Intel® FPGA IP core ibonelela ngebhentshi yokulinganisa kunye noyilo lwehardware ex.ample exhasa ukuhlanganiswa kunye novavanyo lwehardware. Xa uvelisa uyilo exampLe, umhleli weparameter yenza ngokuzenzekelayo i files iyimfuneko ukulinganisa, ukuqulunqa, kunye nokuvavanya uyilo kwihardware.
I-Intel ikwabonelela ngokuhlanganiswa-kuphela example projekthi onokuyisebenzisa ukuqikelela ngokukhawuleza indawo engundoqo ye-IP kunye nexesha.
I-F-Tile CPRI PHY Intel FPGA IP core ibonelela ngesakhono sokuvelisa uyilo exampi-les kuzo zonke iindibaniselwano ezixhaswayo zenani lamajelo e-CPRI kunye nemilinganiselo yebit ye-CPRI. I-testbench kunye noyilo exampLe ixhasa indibaniselwano ezininzi zeeparameter ze-F-Tile CPRI PHY Intel FPGA IP core.
Umzobo 1. Amanyathelo oPhuhliso kuYilo Example
Ulwazi olunxulumeneyo
- F-Tile CPRI PHY Intel FPGA IP User Guide
- Ngolwazi oluneenkcukacha kwi-F-tile CPRI PHY IP.
- I-F-Tile CPRI PHY Intel FPGA IP amanqaku okukhutshwa
- Amanqaku okukhutshwa kwe-IP uluhlu lweenguqu ze-IP kukhupho oluthile.
IiMfuno zeHardware kunye neSoftware
Ukuvavanya i-example uyilo, sebenzisa ihardware elandelayo kunye nesoftware:
- Intel Quartus® Prime Pro Edition software
- Inkqubo console
- Izilingisi ezixhaswayo:
- Isishwankathelo* VCS*
- Iisinopsy VCS MX
- Siemens* EDA ModelSim* SE okanye Questa*— Questa-Intel FPGA Edition
Ukuvelisa uYilo
Umzobo 2. Inkqubo
Umzobo 3. Eksample Tab yoYilo kwi-IP Parameter Editor
Ukwenza iprojekthi ye-Intel Quartus Prime Pro Edition:
- Kwi-Intel Quartus Prime Pro Edition, cofa File ➤ IWizard yeProjekthi eNtsha yokudala iprojekthi entsha yeQuartus Prime, okanye File ➤ Vula iProjekthi yokuvula iprojekthi esele ikho ye-Intel Quartus Prime. Iwizard ikwenza ukuba uchaze isixhobo.
- Cacisa isixhobo usapho Agilex (I-series) kwaye ukhethe isixhobo esihlangabezana nazo zonke ezi mfuno:
- Ithayile yeTransceiver yiF-tile
- Ibanga lesantya seTransceiver ngu-1 okanye -2
- Umgangatho wesantya esingundoqo ngu -1 okanye -2 okanye -3
- Cofa Gqiba.
Landela la manyathelo ukuvelisa i-F-Tile CPRI PHY Intel FPGA IP hardware uyilo example kunye ne-testbench:
- KwiKhathalogi ye-IP, fumana kwaye ukhethe i-F-Tile CPRI PHY Intel FPGA IP. Iwindow entsha yoKwahluka kwe-IP iyavela.
- Chaza igama lomgangatho ophezulu ukwenzela ukwahluka kwe-IP yakho. Umhleli weparameter ugcina useto loguqulo lwe IP kwi file igama .ip.
- Cofa u-Kulungile. Umhleli weparameter uyavela.
- Kwi-IP ithebhu, khankanya iiparamitha zokwahluka kondoqo we-IP yakho.
- KwiEksample thebhu yoYilo, phantsi kweEksample Design Files, khetha i Ukulinganisa ukhetho ukuvelisa testbench kunye neprojekthi yokuqokelela-kuphela. Khetha i Synthesis ukhetho ukuvelisa uyilo lwe hardware example. Kufuneka ukhethe enye yeenketho zokulinganisa kunye noHlanganiso ukwenza uyilo lwe example.
- KwiEksample Ithebhu yoYilo, phantsi kweFomathi yeHDL eveliswe, khetha iVerilog HDL okanye iVHDL. Ukuba ukhetha i-VHDL, kufuneka ulinganise i-testbench kunye ne-simulator yolwimi oluxubekileyo. Isixhobo siphantsi kovavanyo kwi-ex_ isilawuli yimodeli yeVHDL, kodwa eyona testbench file yi-Verilog yeNkqubo file.
- Cofa uVelisa Example Design iqhosha. Khetha Eksample Dizayini kavimba weefayili iwindow iyavela.
- Ukuba ufuna ukulungisa uyilo example ndlela yolawulo okanye igama ukusuka kokungagqibekanga okubonisiwe (cpriphy_ftile_0_example_design), khangela kwindlela entsha kwaye uchwetheze uyilo olutsha exampigama lolawulo (ample_dir>).
Ulwakhiwo lukavimba weefayili
I-F-Tile CPRI PHY Intel FPGA IP core uyilo example file abalawuli baqulathe oku kulandelayo kwenziwe files yoyilo example.
Umzobo 4. Ulwakhiwo lweNkomfa yeMpahla eVeliswe iExample Design
Itheyibhile 1. Testbench File Iinkcazelo
| File Amagama | Inkcazo |
| I-Testbench engundoqo kunye nokulinganisa Files | |
| <design_example_dir>/ umzample_testbench/basic_avl_tb_top.sv | Inqanaba eliphezulu testbench file. I-testbench iqinisekisa i-DUT wrapper kwaye iqhuba imisebenzi ye-Verilog HDL ukuvelisa kunye nokwamkela iipakethi. |
| <design_example_dir>/ umzample_testbench/ cpriphy_ftile_wrapper.sv | I-DUT wrapper eqinisekisa i-DUT kunye namanye amacandelo e-testbench. |
| Izikripthi zeTestbench(1) | |
| <design_example_dir>/ umzample_testbench/run_vsim.do | I-Siemens EDA ModelSim SE okanye i-Questa okanye i-Questa-Intel FPGA Edition script ukuqhuba i-testbench. |
| <design_example_dir>/ umzample_testbench/run_vcs.sh | Iskripthi se-Synopsys VCS sokusebenzisa i-testbench. |
| <design_example_dir>/ umzample_testbench/run_vcsmx.sh | Iskripthi se-Synopsys VCS MX (edibeneyo ye-Verilog HDL kunye ne-SystemVerilog ene-VHDL) ukuqhuba i-testbench. |
Ungahoyi nasiphi na esinye iskripthi sokulinganisa kwiample_dir>/example_testbench/ ifolda.
Itheyibhile 2. Uyilo lweHardware Example File Iinkcazelo
| File Amagama | Iinkcazelo |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.qpf | Iprojekthi ye-Intel Quartus Prime file. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.qsf | Intel Quartus Prime useto lweprojekthi file. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.sdc | Izithintelo zoYilo lwe-Synopsy files. Ungakopa kwaye ulungise ezi files kuyilo lwakho lwe-Intel Agilex™. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.v | Umgangatho ophezulu weVerilog HDL uyilo example file. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_wrapper.sv | I-DUT wrapper eqinisekisa i-DUT kunye namanye amacandelo e-testbench. |
| <design_example_dir>/hardware_test_design/ hwtest_sl/main_script.tcl | Engundoqo file yokufikelela kwiNkqubo yeConsole. |
Ukulinganisa i-Design Example Testbench
Umzobo 5. Inkqubo
Landela la manyathelo ukulinganisa i-testbench:
- Kwi-prompt yomyalelo, tshintshela kwi-testbench simulation directoryample_dir>/example_testbench. cd /umzample_testbench
- Qhuba iquartus_tlg kwiprojekthi eyenziweyo file: quartus_tlg cpriphy_ftile_hw
- Qhuba i-ip-setup-simulation: ip-setup-simulation -output-directory=./sim_script -use-relative-paths -quartus project=cpriphy_ftile_hw.qpf
- Sebenzisa iskripthi sokulinganisa kwi-simulator exhaswayo oyikhethileyo. Iskripthi siqulunqa kwaye siqhuba i-testbench kwi-simulator. Jonga kwitheyibhile Amanyathelo ukulinganisa i-Testbench.
- Hlalutya iziphumo. I-testbench ephumeleleyo ifumene i-hyperframes emihlanu, kwaye ibonisa "PASSED".
ITheyibhile 3. Amanyathelo okulinganisa i-Testbench kwi-Synopsys VCS* Isifanisi
| Isifanisi | Imiyalelo | |
| VCS | Kumgca womyalelo, chwetheza: | |
| sh run_vcs.sh | ||
| iqhubekile... | ||
| Isifanisi | Imiyalelo | |
| VCS MX | Kumgca womyalelo, chwetheza: | |
| sh run_vcsmx.sh | ||
| ModelSim SE okanye Questa okanye Questa-Intel FPGA Edition | Kumgca womyalelo, chwetheza: | |
| vsim -yenza run_vsim.do | ||
| Ukuba ukhetha ukulinganisa ngaphandle kokuzisa i-GUI, chwetheza: | ||
| vsim -c -yenza run_vsim.do | ||
Oku kulandelayo sample mveliso ibonisa uvavanyo lokulinganisa oluyimpumelelo lwe-24.33024 Gbps kunye neziteshi ze-4 CPRI:
Ukuqulunqa iProjekthi yokuHlanganisa Kuphela
Ukuqulunqa umdibaniso-kuphela exampkwiprojekthi, landela la manyathelo:
- Qinisekisa uyilo lokuhlanganisa exampisizukulwana sigqityiwe.
- Kwisoftware ye-Intel Quartus Prime Pro Edition, vula iprojekthi ye-Intel Quartus Prime Pro Editionample_dir>/compilation_test_design/cpriphy_ftile.qpf.
- Kwi-Processing menu, cofa Qala ukuHlanganisa.
- Emva kokuhlanganiswa ngempumelelo, iingxelo zexesha kunye nokusetyenziswa kwezixhobo ziyafumaneka kwiseshoni yakho ye-Intel Quartus Prime Pro Edition.
Ulwazi olunxulumeneyo
Ibhlokhi eSekwe kuYilo oluQuquza
Ukuqulunqa kunye nokuqwalasela i-Design Example kwi-Hardware
Ukuqokelela uyilo lwehardware example kwaye uyiqwalasele kwisixhobo sakho se-Intel Agilex, landela la manyathelo:
- Qinisekisa uyilo lwehardware exampisizukulwana sigqityiwe.
- Kwisoftware ye-Intel Quartus Prime Pro Edition, vula iprojekthi ye-Intel Quartus Primeample_dir>/hardware_test_design/ cpriphy_ftile_hw.qpf.
- Hlela i .qsf file ukwabela izikhonkwane ezisekwe kwihardware yakho.
- Kwi-Processing menu, cofa Qala ukuHlanganisa.
- Emva kokuhlanganiswa ngempumelelo, i.sof file iyafumaneka kwiample_dir>/hardware_test_design/output_files ulawulo.
Landela la manyathelo ukucwangcisa uyilo lwehardware exampkwisixhobo se-Intel Agilex:
- Qhagamshela i-Intel Agilex I-series ye-Transceiver Signal Integrity Development Kit kwi-host computer.
Qaphela: Ikhithi yophuhliso icwangciswe kwangaphambili ngamaza ewotshi achanekileyo ngokungagqibekanga. Awudingi ukusebenzisa usetyenziso lolawulo lwekloko ukuseta iifrikhwensi. - Kwimenyu yeZixhobo, cofa uMlungisi.
- KuMdwelisi weNkqubo, cofa uSeto lweHardware.
- Khetha isixhobo sokucwangcisa.
- Qinisekisa ukuba iMowudi isetelwe ku-JTAG.
- Khetha isixhobo se-Intel Agilex kwaye ucofe Yongeza isixhobo. I-Programmer ibonisa umzobo webhloko woqhagamshelwano phakathi kwezixhobo ebhodini yakho.
- Kumqolo neyakho .sof, khangela ibhokisi ye .sof.
- Khangela ibhokisi kwiNkqubo/Qwalasela ikholam.
- Cofa uQalisa.
Ulwazi olunxulumeneyo
- Ibhlokhi eSekwe kuYilo oluQuquza
- Ukucwangcisa Intel FPGA Devices
- Ukuhlalutya kunye noYilo lwe-Debugging nge-System Console
Ukuvavanya i-Hardware Design Example
Emva kokuba uqokelele i-F-Tile CPRI PHY Intel FPGA IP core design example kwaye uyiqwalasele kwisixhobo sakho se-Intel Agilex, ungasebenzisa iSistim Console ukucwangcisa undoqo we-IP kunye neerejista zayo eziphambili ze-PHY IP.
Ukuvula iNkqubo yeConsole kwaye uvavanye uyilo lwehardware exampLe, landela la manyathelo:
- Emva koyilo lwehardware example iqwalaselwe kwisixhobo se-Intel Agilex, kwisoftware ye-Intel Quartus Prime Pro Edition, kwimenyu yeZixhobo, cofa iziXhobo zokulungisa iimpazamo ➤ Ikhonsoli yeNkqubo.
- Kwipheyini ye-Tcl Console, chwetheza cd hwtest ukutshintsha ulawulo ukuyaample_dir>/hardware_test_design/hwtest_sl.
- Chwetheza umthombo main_script.tcl ukuvula umdibaniso kwi-JTAG master kwaye uqale uvavanyo.
Uyilo Eksample Inkcazo
Uyilo example ibonisa umsebenzi osisiseko we-F-Tile CPRI PHY Intel FPGA IP core. Uyakwazi ukuvelisa uyilo ukusuka Example Yila ithebhu kwi-F-Tile CPRI PHY Intel FPGA IP parameter umhleli.
Ukuvelisa i-design exampLe, kufuneka uqale usete amaxabiso eparameter yondoqo we IP oceba ukuyivelisa kwimveliso yakho yokugqibela. Unokukhetha ukuvelisa i-ex yoyiloample kunye okanye ngaphandle kwe-RS-FEC uphawu. Uphawu lwe-RS-FEC lufumaneka nge-10.1376, 12.1651 kunye ne-24.33024 Gbps CPRI umgca we-bit rates.
Itheyibhile 4. F-Tile CPRI PHY Intel FPGA IP Core Feature Matrix
| I-CPRI Line Bit Rate (Gbps) | Inkxaso ye-RS-FEC | IKloshi yoNgeniso (MHz) | Inkxaso yeLatency yokumisela |
| 1.2288 | Hayi | 153.6 | Ewe |
| 2.4576 | Hayi | 153.6 | Ewe |
| 3.072 | Hayi | 153.6 | Ewe |
| 4.9152 | Hayi | 153.6 | Ewe |
| 6.144 | Hayi | 153.6 | Ewe |
| 9.8304 | Hayi | 153.6 | Ewe |
| 10.1376 | Ngaphakathi nangaphandle | 184.32 | Ewe |
| 12.1651 | Ngaphakathi nangaphandle | 184.32 | Ewe |
| 24.33024 | Ngaphakathi nangaphandle | 184.32 | Ewe |
Iimbonakalo
- Veza uyilo example kunye RS-FEC isici
- Ipakethe esisiseko yokujonga amandla okubandakanya ukubalwa kwexesha lokubuya lokubuya
Uyilo lokulinganisa Eksample
I-F-Tile CPRI PHY Intel FPGA IP uyilo example yenza i-testbench yokulinganisa kunye nokulinganisa files eqinisekisa i-F-Tile CPRI PHY Intel FPGA IP engundoqo xa ukhetha ukhetho lokulinganisa.
Umzobo 6. Umzobo weBlock ye-10.1316, 12.1651, kunye ne-24.33024 Gbps (kunye kunye nangaphandle kwe-RS-FEC) Imilinganiselo yomgca
Umzobo 7. I-Block Diagram ye-1.228, 2.4576, 3.072, 4.9152, 6.144, kunye ne-9.8304 Gbps Line Rate
Kulo mzekelo woyiloampLe, i-testbench yokulinganisa ibonelela ngokusebenza okusisiseko njengokuqalisa kunye nokulinda ukutshixa, ukuhambisa kunye nokufumana iipakethi.
Uvavanyo oluyimpumelelo lubonisa imveliso eqinisekisa oku kulandelayo:
- Ingqiqo yomxhasi imisela kwakhona undoqo we-IP.
- Ingqiqo yomxhasi ilinda ulungelelwaniso lwedatapath ye-RX.
- Ingqiqo yomxhasi ithumela iihyperframes kujongano lweTX MII kwaye ilindele iihyperframes ezintlanu ukuba zamkelwe kujongano lweRX MII. I-Hyperframes ithunyelwa kwaye ifunyenwe kwi-interface ye-MII ngokuhambelana ne-CPRI v7.0.
Phawula: I-CPRI iqulunqa ezijolise kwi-1.2, 2.4, 3, 4.9, 6.1, kunye ne-9.8 Gbps yezinga lomgca usebenzisa i-interface ye-8b / 10b kunye noyilo olujolise kwi-10.1, 12.1 kunye ne-24.3 Gbps (kunye nangaphandle kwe-RS-FEC) sebenzisa i-MII interface. Olu luyilo example ibandakanya ikhawuntara yokuya nokubuya ukubala ukubuya nokubuya kwe-latency ukusuka kwi-TX ukuya kwi-RX. - Ingqiqo yomxhasi ifunda ixabiso le-latency yohambo olubuyayo kwaye ijonga umxholo kunye nokuchaneka kwedatha ye-hyperframes kwicala le-RX MII emva kokuba ikhawunta igqibe ukubala kokubuya nokubuya.
Ulwazi olunxulumeneyo
- Iimpawu zeCPRI
Uyilo lwezixhobo zekhompyutha Eksample
Umzobo 8. Uyilo lweHardware Example Block Diagram
Phawula
- I-CPRI iqulunqa nge-2.4 / 4.9 / 9.8 Gbps CPRI amazinga omgca asebenzisa i-interface ye-8b / 10b kunye nazo zonke ezinye iireyithi ze-CPRI zokuyila zisebenzisa i-MII interface.
- I-CPRI iqulunqa nge-2.4 / 4.9 / 9.8 Gbps imilinganiselo yomgca we-CPRI idinga i-clock ye-transceiver ye-153.6 MHz kunye nazo zonke ezinye iireyithi ze-CPRI zomgca zifuna i-184.32 MHz.
I-F-Tile CPRI PHY Intel FPGA IP core hardware design example iquka la malungu alandelayo:
- F-Tile CPRI PHY Intel FPGA IP core.
- Ibhloko ye-Packet ye-logic yeklayenti eyenza kwaye ifumane i-traffic.
- Ikhawuntara yokuya nokubuya.
- IOPLL ukwenza i-sampIkloko ye-ling ye-deterministic latency logic ngaphakathi kwe-IP, kunye necandelo lokukhawula lokuya nokubuya kwi-testbench.
- Inkqubo yePLL ukwenza iiwotshi zesixokelelwano ze IP.
- I-Avalon®-MM idilesi ye-decoder ukucacisa indawo yedilesi ye-CPRI, Transceiver, kunye ne-Ethernet ngexesha lokufikelela kwakhona.
- Imithombo kunye neeprobe zokuqinisekisa ukusetha kwakhona kunye nokubeka esweni iiwotshi kunye nemilinganiselo embalwa.
- JTAG umlawuli onxibelelana neNkqubo yeConsole. Unxibelelana nengqiqo yomxhasi ngeNkqubo yeConsole.
Iimpawu zokunxibelelana
Uluhlu 5. Uyilo Eksample Iimpawu zoNxibelelwano
| Umqondiso | Isalathiso | Inkcazo |
| ref_clk100MHz | Igalelo | Ikloko yokufaka yofikelelo lweCSR kulo lonke ujongano loqwalaselo ngokutsha. Qhuba kwi-100 MHz. |
| i_clk_ref[0] | Igalelo | Ikloko yeReferensi yeNkqubo yePLL. Qhuba kwi-156.25 MHz. |
| i_clk_ref[1] | Igalelo | Iwotshi yereferensi yeTransceiver. Qhuba kwi
• 153.6 MHz kwireyithi ye-CPRI yomgca we-1.2, 2.4, 3, 4.9, 6.1, kunye ne-9.8 Gbps. • I-184.32 MHz kumazinga omgca we-CPRI 10.1,12.1, kunye ne-24.3 Gbps kunye nangaphandle kwe-RS-FEC. |
| i_rx_serial[n] | Igalelo | Transceiver PHY igalelo idatha yothotho. |
| o_tx_serial[n] | Isiphumo | I-Transceiver PHY imveliso yedata yedata. |
Uyilo Eksample Iirejista
Uluhlu 6. Uyilo Eksample Iirejista
| Inombolo yomjelo | Idilesi esisiseko (idilesi ye-Byte) | Bhalisa Uhlobo |
|
0 |
0x00000000 | I-CPRI PHY iirejista zokuLungiselela kwakhona iChaneli 0 |
| 0x00100000 | Iirejista zokuLungiselela kwakhona i-Ethernet ye-Channel 0 | |
| 0x00200000 | Iirejista zoLungiselelo lweTransceiver zeChannel 0 | |
|
1(2) |
0x01000000 | I-CPRI PHY iirejista zokuLungiselela kwakhona iChaneli 1 |
| 0x01100000 | Iirejista zokuLungiselela kwakhona i-Ethernet ye-Channel 1 | |
| 0x01200000 | Iirejista zoLungiselelo lweTransceiver zeChannel 1 | |
|
2(2) |
0x02000000 | I-CPRI PHY iirejista zokuLungiselela kwakhona iChaneli 2 |
| 0x02100000 | Iirejista zokuLungiselela kwakhona i-Ethernet ye-Channel 2 | |
| 0x02200000 | Iirejista zoLungiselelo lweTransceiver zeChannel 2 | |
| iqhubekile... | ||
| Inombolo yomjelo | Idilesi esisiseko (idilesi ye-Byte) | Bhalisa Uhlobo |
|
3(2) |
0x03000000 | I-CPRI PHY iirejista zokuLungiselela kwakhona iChaneli 3 |
| 0x03100000 | Iirejista zokuLungiselela kwakhona i-Ethernet ye-Channel 3 | |
| 0x03200000 | Iirejista zoLungiselelo lweTransceiver zeChannel 3 |
Ezi rejista zigcinwe ukuba ijelo alisetyenziswanga.
I-F-Tile CPRI PHY Intel FPGA IP Design Example ULondolozo lweeNkcukacha eziBalulekileyo
Ukuba i-IP core version ayidweliswanga, isikhokelo somsebenzisi senguqulo yangaphambili ye-IP siyasebenza.
| Intel Quartus Prime Version | IP Core Version | Isikhokelo somsebenzisi |
| 21.2 | 2.0.0 | I-F-Tile CPRI PHY Intel FPGA IP Design Example Isikhokelo somsebenzisi |
Imbali yoHlaziyo yoXwebhu lwe-F-Tile CPRI PHY Intel FPGA IP Design Example Isikhokelo somsebenzisi
| Inguqulelo yoXwebhu | Intel Quartus Prime Version | IP Version | Iinguqu |
| 2021.10.04 | 21.3 | 3.0.0 |
|
| 2021.06.21 | 21.2 | 2.0.0 | Ukukhutshwa kokuqala. |
Intel Corporation. Onke Amalungelo Agciniwe. I-Intel, ilogo ye-Intel, kunye nezinye iimpawu ze-Intel ziimpawu zorhwebo ze-Intel Corporation okanye iinkampani eziphantsi kwayo. I-Intel iqinisekisa ukusebenza kweFPGA yayo kunye neemveliso zesemiconductor kwiinkcukacha zangoku ngokuhambelana newaranti esemgangathweni ye-Intel, kodwa inelungelo lokwenza utshintsho kuzo naziphi na iimveliso kunye neenkonzo nangaliphi na ixesha ngaphandle kwesaziso. I-Intel ayithathi xanduva okanye ityala elivela kwisicelo okanye ukusetyenziswa kwalo naluphi na ulwazi, imveliso, okanye inkonzo echazwe apha ngaphandle kokuba kuvunyelwene ngokubhaliweyo yi-Intel. Abathengi be-Intel bayacetyiswa ukuba bafumane inguqulelo yamva nje yeenkcazo zesixhobo ngaphambi kokuba baxhomekeke kulo naluphi na ulwazi olupapashiweyo naphambi kokubeka iiodolo zeemveliso okanye iinkonzo.
*Amanye amagama kunye neempawu zingabangwa njengempahla yabanye.
Amaxwebhu / Izibonelelo
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intel F-Tile CPRI PHY FPGA IP Design Example [pdf] Isikhokelo somsebenzisi F-Tile CPRI PHY FPGA IP Design Example, PHY FPGA IP Design Example, F-Tile CPRI IP Design Example, IP Design Example, IP Design |
