intel F-Tile CPRI PHY FPGA IP Design Example
Quick Bẹrẹ Itọsọna
F-Tile CPRI PHY Intel® FPGA IP mojuto n pese bench testbench kan ati apẹrẹ ohun elo tẹlẹample ti o atilẹyin akopo ati hardware igbeyewo. Nigbati o ba ṣe ina apẹrẹ example, paramita olootu laifọwọyi ṣẹda awọn files pataki lati ṣe simulate, ṣajọ, ati idanwo apẹrẹ ni hardware.
Intel tun pese akopọ-nikan example ise agbese ti o le lo lati ni kiakia siro IP mojuto agbegbe ati ìlà.
F-Tile CPRI PHY Intel FPGA IP mojuto n pese agbara ti ipilẹṣẹ apẹrẹ examples fun gbogbo awọn akojọpọ atilẹyin nọmba ti awọn ikanni CPRI ati awọn oṣuwọn bit laini CPRI. Awọn testbench ati oniru example ṣe atilẹyin ọpọlọpọ awọn akojọpọ paramita ti F-Tile CPRI PHY Intel FPGA IP mojuto.
Nọmba 1. Awọn Igbesẹ Idagbasoke fun Oniru Example
Alaye ti o jọmọ
- F-Tile CPRI PHY Intel FPGA IP Itọsọna olumulo
- Fun alaye alaye lori F-tile CPRI PHY IP.
- F-Tile CPRI PHY Intel FPGA IP Awọn akọsilẹ Tu
- Awọn akọsilẹ Itusilẹ IP ṣe atokọ awọn iyipada IP ni idasilẹ kan pato.
Hardware ati Software Awọn ibeere
Lati ṣe idanwo exampFun apẹrẹ, lo hardware ati sọfitiwia atẹle:
- Intel Quartus® NOMBA Pro Edition software
- console System
- Awọn Simulators atilẹyin:
- Afoyemọ* VCS*
- Synopsys VCS MX
- Siemens* EDA ModelSim* SE tabi Questa*— Questa-Intel FPGA Edition
Ti o npese awọn Design
olusin 2. Ilana
Aworan 3. Eksample Design Tab in IP Parameter Olootu
Lati ṣẹda iṣẹ akanṣe Intel Quartus Prime Pro Edition:
- Ni Intel Quartus Prime Pro Edition, tẹ File ➤ Oluṣeto Iṣẹ Tuntun lati ṣẹda iṣẹ akanṣe Quartus Prime tuntun, tabi File ➤ Ṣii Project lati ṣii iṣẹ Intel Quartus Prime ti o wa tẹlẹ. Oluṣeto naa ta ọ lati pato ẹrọ kan.
- Pato idile ẹrọ Agilex (I-jara) ati yan ẹrọ kan ti o pade gbogbo awọn ibeere wọnyi:
- Tile transceiver jẹ F-tile
- Iwọn iyara transceiver jẹ -1 tabi -2
- Mojuto iyara ite ni -1 tabi -2 tabi -3
- Tẹ Pari.
Tẹle awọn igbesẹ wọnyi lati ṣe ipilẹṣẹ F-Tile CPRI PHY Intel FPGA IP apẹrẹ ohun elo example ati testbench:
- Ninu Katalogi IP, wa ko si yan F-Tile CPRI PHY Intel FPGA IP. Ferese Iyipada IP Tuntun yoo han.
- Pato orukọ ipele oke kan fun aṣa IP iyatọ rẹ. Olootu paramita n fipamọ awọn eto iyatọ IP ni a file ti a npè ni .ip.
- Tẹ O DARA. Olootu paramita yoo han.
- Lori IP taabu, pato awọn paramita fun iyatọ ipilẹ IP rẹ.
- Lori Example Design taabu, labẹ Eksample Apẹrẹ Files, yan aṣayan Simulation lati ṣe ina testbench ati ise agbese akopọ-nikan. Yan aṣayan Synthesis lati ṣe ina apẹrẹ hardware example. O gbọdọ yan o kere ju ọkan ninu awọn aṣayan Simulation ati Synthesis lati ṣe ipilẹṣẹ apẹrẹ tẹlẹample.
- Lori Examptaabu Oniru, labẹ Ti ipilẹṣẹ HDL kika, yan Verilog HDL tabi VHDL. Ti o ba yan VHDL, o gbọdọ ṣe simulate testbench pẹlu simulator ede adapo. Ẹrọ ti o wa labẹ idanwo ni ex_ liana jẹ awoṣe VHDL, ṣugbọn testbench akọkọ file jẹ System Verilog file.
- Tẹ Ina Example Design bọtini. Awọn Yan Example Design Directory window han.
- Ti o ba fẹ yi awọn oniru exampọna itọsọna tabi orukọ lati awọn aṣiṣe ti o han (cpriphy_ftile_0_example_design), lọ kiri si ọna tuntun ki o tẹ apẹrẹ tuntun example orukọ liana (ample_dir>).
Ilana Ilana
F-Tile CPRI PHY Intel FPGA IP mojuto apẹrẹ example file awọn ilana ni awọn wọnyi ti ipilẹṣẹ files fun apẹrẹ example.
olusin 4. Ilana Ilana ti ipilẹṣẹ Example Apẹrẹ
Table 1. Testbench File Awọn apejuwe
| File Awọn orukọ | Apejuwe |
| Key Testbench ati Simulation Files | |
| <design_example_dir>/ example_testbench/ipilẹ_avl_tb_top.sv | Igbeyewo ipele oke file. Awọn testbench ese awọn DUT wrapper ati ki o nṣiṣẹ Verilog HDL awọn iṣẹ-ṣiṣe lati se ina ati ki o gba awọn apo-iwe. |
| <design_example_dir>/ example_testbench / cpriphy_ftile_wrapper.sv | Ohun elo DUT ti o ṣe itọsẹ DUT ati awọn paati testbench miiran. |
| Awọn iwe afọwọkọ Testbench(1) | |
| <design_example_dir>/ example_testbench/run_vsim.do | Siemens EDA ModelSim SE tabi Questa tabi Questa-Intel FPGA iwe afọwọkọ lati ṣiṣe testbench. |
| <design_example_dir>/ example_testbench/run_vcs.sh | Awọn Synopsys VCS iwe afọwọkọ lati ṣiṣe awọn testbench. |
| <design_example_dir>/ example_testbench/run_vcsmx.sh | Awọn Synopsys VCS MX iwe afọwọkọ (ni idapo Verilog HDL ati SystemVerilog pẹlu VHDL) lati ṣiṣe awọn testbench. |
Foju eyikeyi iwe afọwọṣe simulator miiran ninuample_dir>/ apẹẹrẹample_testbench/ folda.
Table 2. Hardware Design Eksample File Awọn apejuwe
| File Awọn orukọ | Awọn apejuwe |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.qpf | Intel Quartus NOMBA ise agbese file. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.qsf | Intel Quartus NOMBA eto ise agbese file. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.sdc | Synopsys Design inira files. O le daakọ ati satunkọ awọn wọnyi files fun apẹrẹ Intel Agilex™ tirẹ. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.v | Oke-ipele Verilog HDL oniru example file. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_wrapper.sv | Ohun elo DUT ti o ṣe itọsẹ DUT ati awọn paati testbench miiran. |
| <design_example_dir>/hardware_test_design/ hwtest_sl/main_script.tcl | Akọkọ file fun wiwọle System Console. |
Simulating awọn Oniru Example Testbench
olusin 5. Ilana
Tẹle awọn igbesẹ wọnyi lati ṣe adaṣe testbench:
- Ni aṣẹ aṣẹ, yipada si iwe ilana kikopa testbenchample_dir>/ apẹẹrẹample_testbench. cd / Example_testbench
- Ṣiṣe quartus_tlg lori iṣẹ akanṣe ti ipilẹṣẹ file: quartus_tlg cpriphy_ftile_hw
- Ṣiṣe ip-setup-simulation: ip-setup-simulation –output-directory=./sim_script –use-relative-paths –quartus project=cpriphy_ftile_hw.qpf
- Ṣiṣe awọn iwe afọwọkọ kikopa fun atilẹyin simulator ti o fẹ. Awọn akosile akopọ ati ki o nṣiṣẹ testbench ni labeabo. Tọkasi tabili Awọn Igbesẹ lati ṣe Simulate Testbench.
- Ṣe itupalẹ awọn abajade. Aṣeyọri testbench gba hyperframes marun, ati awọn ifihan “PASSED”.
Tabili 3. Awọn Igbesẹ lati ṣe Simulate Testbench ni Synopsys VCS * Simulator
| Simulator | Awọn ilana | |
| VCS | Ninu laini aṣẹ, tẹ: | |
| sh run_vcs.sh | ||
| tesiwaju… | ||
| Simulator | Awọn ilana | |
| VCS MX | Ninu laini aṣẹ, tẹ: | |
| sh run_vcsmx.sh | ||
| ModelSim SE tabi Questa tabi Questa-Intel FPGA Edition | Ninu laini aṣẹ, tẹ: | |
| vsim -ṣe run_vsim.do | ||
| Ti o ba fẹ lati ṣe adaṣe lai mu GUI soke, tẹ: | ||
| vsim -c -ṣe run_vsim.do | ||
Awọn atẹle sampIṣẹjade le ṣe afihan ṣiṣe idanwo kikopa aṣeyọri fun 24.33024 Gbps pẹlu awọn ikanni CPRI 4:
Iṣakojọpọ Akopọ-Nikan Project
Lati ṣajọ akojọpọ-nikan exampfun ise agbese, tẹle awọn igbesẹ wọnyi:
- Rii daju akopo oniru example iran jẹ pari.
- Ninu sọfitiwia Intel Quartus Prime Pro Edition, ṣii iṣẹ akanṣe Intel Quartus Prime Pro Editionample_dir> / akopo_test_design/cpriphy_ftile.qpf.
- Lori awọn Processing akojọ, tẹ Bẹrẹ akopo.
- Lẹhin ikojọpọ aṣeyọri, awọn ijabọ fun akoko ati fun lilo awọn orisun wa ninu igba Intel Quartus Prime Pro Edition rẹ.
Alaye ti o jọmọ
Dina-Da Design ṣiṣan
Iṣakojọpọ ati Ṣiṣeto Oniru Example ni Hardware
Lati sakojo awọn hardware oniru example ki o tunto lori ẹrọ Intel Agilex rẹ, tẹle awọn igbesẹ wọnyi:
- Rii daju hardware oniru example iran jẹ pari.
- Ninu sọfitiwia Intel Quartus Prime Pro Edition, ṣii iṣẹ akanṣe Intel Quartus Primeample_dir>/hardware_test_design/ cpriphy_ftile_hw.qpf.
- Ṣatunkọ .qsf file lati fi pinni da lori rẹ hardware.
- Lori awọn Processing akojọ, tẹ Bẹrẹ akopo.
- Lẹhin akojọpọ aṣeyọri, a .sof file wa ninuample_dir>/hardware_test_design/jade_files liana.
Tẹle awọn igbesẹ wọnyi lati ṣe eto apẹrẹ hardware example lori ẹrọ Intel Agilex:
- So Intel Agilex I-jara Iyipada Transceiver Signal Integrity Development Apo si kọnputa agbalejo.
Akiyesi: Ohun elo idagbasoke ti wa ni tito tẹlẹ pẹlu awọn iwọn aago to pe nipasẹ aiyipada. O ko nilo lati lo ohun elo Iṣakoso aago lati ṣeto awọn loorekoore. - Lori awọn Irinṣẹ akojọ, tẹ Programmer.
- Ni awọn Programmer, tẹ Hardware Setup.
- Yan ẹrọ siseto.
- Rii daju pe Ipo ti ṣeto si JTAG.
- Yan ẹrọ Intel Agilex ki o tẹ Fi ẹrọ kun. Awọn pirogirama ṣe afihan aworan atọka Àkọsílẹ ti awọn asopọ laarin awọn ẹrọ lori igbimọ rẹ.
- Ni ila pẹlu .sof rẹ, ṣayẹwo apoti fun .sof.
- Ṣayẹwo apoti ti o wa ninu iwe Eto / Tunto.
- Tẹ Bẹrẹ.
Alaye ti o jọmọ
- Dina-Da Design ṣiṣan
- Siseto Intel FPGA Devices
- Ṣiṣayẹwo ati Awọn apẹrẹ N ṣatunṣe aṣiṣe pẹlu Eto Console
Idanwo Oniru Hardware Example
Lẹhin ti o ṣe akopọ F-Tile CPRI PHY Intel FPGA IP mojuto apẹrẹ example ati tunto lori ẹrọ Intel Agilex rẹ, o le lo Console System lati ṣe eto ipilẹ IP ati awọn iforukọsilẹ mojuto IP PHY rẹ.
Lati tan-an Console System ati idanwo apẹrẹ hardware example, tẹle awọn igbesẹ wọnyi:
- Lẹhin ti hardware oniru example jẹ tunto lori ẹrọ Intel Agilex, ninu sọfitiwia Intel Quartus Prime Pro Edition, lori atokọ Awọn irinṣẹ, tẹ Awọn irinṣẹ N ṣatunṣe aṣiṣe System ➤ Console System.
- Ninu iwe Tcl Console, tẹ cd hwest lati yi ilana pada siample_dir>/hardware_test_design/hwtest_sl.
- Tẹ orisun main_script.tcl lati ṣii asopọ si JTAG oluwa ki o bẹrẹ idanwo naa.
Apẹrẹ Example Apejuwe
Apẹrẹ example ṣe afihan iṣẹ ṣiṣe ipilẹ ti F-Tile CPRI PHY Intel FPGA IP mojuto. O le ṣe ina apẹrẹ lati Examptaabu Oniru ninu F-Tile CPRI PHY Intel FPGA IP olootu paramita.
Lati ṣe ina apẹrẹ exampNitorina, o gbọdọ kọkọ ṣeto awọn iye paramita fun iyatọ ipilẹ IP ti o pinnu lati ṣe ina ni ọja ipari rẹ. O le yan lati ṣe ina apẹrẹ example pẹlu tabi laisi ẹya RS-FEC. Awọn ẹya ara ẹrọ RS-FEC wa pẹlu 10.1376, 12.1651 ati 24.33024 Gbps CPRI awọn oṣuwọn bit ila.
Table 4. F-Tile CPRI PHY Intel FPGA IP mojuto Ẹya Matrix
| Oṣuwọn Bit Laini CPRI (Gbps) | RS-FEC Atilẹyin | Aago Itọkasi (MHz) | Atilẹyin Lairi Ipinnu |
| 1.2288 | Rara | 153.6 | Bẹẹni |
| 2.4576 | Rara | 153.6 | Bẹẹni |
| 3.072 | Rara | 153.6 | Bẹẹni |
| 4.9152 | Rara | 153.6 | Bẹẹni |
| 6.144 | Rara | 153.6 | Bẹẹni |
| 9.8304 | Rara | 153.6 | Bẹẹni |
| 10.1376 | Pẹlu ati Laisi | 184.32 | Bẹẹni |
| 12.1651 | Pẹlu ati Laisi | 184.32 | Bẹẹni |
| 24.33024 | Pẹlu ati Laisi | 184.32 | Bẹẹni |
Awọn ẹya ara ẹrọ
- Ṣe ina apẹrẹ example pẹlu RS-FEC ẹya-ara
- Awọn agbara iṣayẹwo idii ipilẹ pẹlu kika lairi irin ajo yika
Simulation Design Example
F-Tile CPRI PHY Intel FPGA IP apẹrẹ example ṣe agbejade testbench kikopa ati kikopa files ti o lẹsẹkẹsẹ F-Tile CPRI PHY Intel FPGA IP mojuto nigbati o yan aṣayan Simulation.
Ṣe nọmba 6. Aworan atọka Àkọsílẹ fun 10.1316, 12.1651, ati 24.33024 Gbps (pẹlu ati laisi RS-FEC) Awọn oṣuwọn Laini
Ṣe nọmba 7. Idina aworan fun 1.228, 2.4576, 3.072, 4.9152, 6.144, ati 9.8304 Gbps Laini Oṣuwọn
Ninu apẹrẹ yii example, testbench kikopa pese iṣẹ ṣiṣe ipilẹ gẹgẹbi ibẹrẹ ati duro fun titiipa, gbigbe ati gba awọn apo-iwe.
Ṣiṣe idanwo aṣeyọri ṣe afihan iṣelọpọ ti o jẹrisi ihuwasi atẹle:
- Onibara kannaa tun IP mojuto.
- Imọye-ọrọ alabara n duro de titete ipa ọna data RX.
- Imọran alabara n ṣe atagba awọn hyperframes lori wiwo TX MII ati duro fun awọn hyperframes marun lati gba lori wiwo RX MII. Hyperframes ti wa ni gbigbe ati gba lori wiwo MII ni ibamu si awọn pato CPRI v7.0.
Akiyesi: Awọn apẹrẹ CPRI ti o fojusi 1.2, 2.4, 3, 4.9, 6.1, ati 9.8 Gbps laini oṣuwọn lo wiwo 8b / 10b ati awọn apẹrẹ ti o fojusi 10.1, 12.1 ati 24.3 Gbps (pẹlu ati laisi RS-FEC) lo wiwo MII. Apẹrẹ yii example pẹlu counter irin ajo yika lati ka airi irin ajo yika lati TX si RX. - Imọye ti alabara ka iye idaduro irin-ajo yika ati ṣayẹwo fun akoonu ati deede ti data hyperframes lori ẹgbẹ RX MII ni kete ti counter ba pari kika idaduro irin-ajo yika.
Alaye ti o jọmọ
- Awọn pato CPRI
Hardware Design Example
olusin 8. Hardware Design Example Àkọsílẹ aworan atọka
Akiyesi
- Awọn apẹrẹ CPRI pẹlu 2.4 / 4.9 / 9.8 Gbps CPRI awọn oṣuwọn laini lo 8b / 10b ni wiwo ati gbogbo awọn aṣa ila ila CPRI miiran lo wiwo MII.
- Awọn apẹrẹ CPRI pẹlu 2.4/4.9/9.8 Gbps CPRI awọn oṣuwọn laini nilo aago itọkasi transceiver 153.6 MHz ati gbogbo awọn oṣuwọn laini CPRI miiran nilo 184.32 MHz.
F-Tile CPRI PHY Intel FPGA IP mojuto apẹrẹ hardware apẹẹrẹample pẹlu awọn eroja wọnyi:
- F-Tile CPRI PHY Intel FPGA IP mojuto.
- Packet kannaa Àkọsílẹ ti ose ti o npese ati ki o gba ijabọ.
- Yika irin ajo counter.
- IOPLL lati ṣe ipilẹṣẹ sampling aago fun deterministic lairi kannaa inu awọn IP, ati yika irin ajo counter paati ni testbench.
- PLL eto lati ṣe ina awọn aago eto fun IP.
- Avalon®-MM oluyipada adiresi lati ṣatunṣe aaye adirẹsi atunto fun CPRI, Transceiver, ati Ethernet module lakoko awọn iraye si atunto atunto.
- Awọn orisun ati awọn iwadii fun idasi awọn atunto ati mimojuto awọn aago ati awọn ipo ipo diẹ.
- JTAG oludari ti o ibasọrọ pẹlu awọn System Console. O ṣe ibasọrọ pẹlu ọgbọn alabara nipasẹ System Console.
Awọn ifihan agbara wiwo
Table 5. Design Example Interface Awọn ifihan agbara
| Ifihan agbara | Itọsọna | Apejuwe |
| ref_clk100MHz | Iṣawọle | Aago titẹ sii fun wiwọle CSR lori gbogbo awọn atọkun atunto. Wakọ ni 100 MHz. |
| i_clk_ref[0] | Iṣawọle | Aago itọkasi fun System PLL. Wakọ ni 156.25 MHz. |
| i_clk_ref[1] | Iṣawọle | Aago itọkasi Transceiver. Wakọ ni
• 153.6 MHz fun oṣuwọn laini CPRI 1.2, 2.4, 3, 4.9, 6.1, ati 9.8 Gbps. • 184.32 MHz fun awọn oṣuwọn laini CPRI 10.1,12.1, ati 24.3 Gbps pẹlu ati laisi RS-FEC. |
| i_rx_serial[n] | Iṣawọle | Transceiver PHY igbewọle data ni tẹlentẹle. |
| o_tx_serial[n] | Abajade | Transceiver PHY o wu data ni tẹlentẹle. |
Apẹrẹ Example Awọn iforukọsilẹ
Table 6. Design Example Awọn iforukọsilẹ
| Nọmba ikanni | Adirẹsi ipilẹ (Adirẹsi Baiti) | Forukọsilẹ Iru |
|
0 |
0x00000000 | Awọn iforukọsilẹ atunto atunto CPRI PHY fun ikanni 0 |
| 0x00100000 | Awọn iforukọsilẹ atunto Ethernet fun ikanni 0 | |
| 0x00200000 | Awọn iforukọsilẹ atunto Transceiver fun ikanni 0 | |
|
1(2) |
0x01000000 | Awọn iforukọsilẹ atunto atunto CPRI PHY fun ikanni 1 |
| 0x01100000 | Awọn iforukọsilẹ atunto Ethernet fun ikanni 1 | |
| 0x01200000 | Awọn iforukọsilẹ atunto Transceiver fun ikanni 1 | |
|
2(2) |
0x02000000 | Awọn iforukọsilẹ atunto atunto CPRI PHY fun ikanni 2 |
| 0x02100000 | Awọn iforukọsilẹ atunto Ethernet fun ikanni 2 | |
| 0x02200000 | Awọn iforukọsilẹ atunto Transceiver fun ikanni 2 | |
| tesiwaju… | ||
| Nọmba ikanni | Adirẹsi ipilẹ (Adirẹsi Baiti) | Forukọsilẹ Iru |
|
3(2) |
0x03000000 | Awọn iforukọsilẹ atunto atunto CPRI PHY fun ikanni 3 |
| 0x03100000 | Awọn iforukọsilẹ atunto Ethernet fun ikanni 3 | |
| 0x03200000 | Awọn iforukọsilẹ atunto Transceiver fun ikanni 3 |
Awọn iforukọsilẹ wọnyi wa ni ipamọ ti ikanni ko ba lo.
F-Tile CPRI PHY Intel FPGA IP Design Example User Itọsọna Archives
Ti ẹya IP mojuto ko ba ṣe akojọ, itọsọna olumulo fun ẹya IP mojuto ti tẹlẹ kan.
| Intel Quartus NOMBA Version | IP Core Version | Itọsọna olumulo |
| 21.2 | 2.0.0 | F-Tile CPRI PHY Intel FPGA IP Design Example User Itọsọna |
Itan Atunyẹwo Iwe-ipamọ fun F-Tile CPRI PHY Intel FPGA IP Design Example User Itọsọna
| Ẹya Iwe aṣẹ | Intel Quartus NOMBA Version | Ẹya IP | Awọn iyipada |
| 2021.10.04 | 21.3 | 3.0.0 |
|
| 2021.06.21 | 21.2 | 2.0.0 | Itusilẹ akọkọ. |
Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn aami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ṣiṣe ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ.
* Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.
Awọn iwe aṣẹ / Awọn orisun
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intel F-Tile CPRI PHY FPGA IP Design Example [pdf] Itọsọna olumulo F-Tile CPRI PHY FPGA IP Design Example, PHY FPGA IP Design Example, F-Tile CPRI IP Design Example, IP Design Example, IP Design |
