SmartFusion2 MSS
Sebopeho sa DDR Controller
Libero SoC v11.6 le hamorao
Selelekela
SmartFusion2 MSS e na le molaoli oa DDR o kentsoeng. Taolo ena ea DDR e reretsoe ho laola memori ea off-chip DDR. Taolo ea MDDR e ka fumaneha ho tsoa ho MSS hammoho le lesela la FPGA. Ho phaella moo, molaoli oa DDR a ka boela a fetisoa, a fana ka sebopeho se eketsehileng ho lesela la FPGA (Soft Controller Mode (SMC)).
Ho lokisa selaoli sa MSS DDR ka botlalo, o tlameha ho:
- Khetha sebaka sa data ho sebelisa MDDR Configurator.
- Beha litekanyetso tsa rejisetara bakeng sa lirejisete tsa balaoli ba DDR.
- Khetha maqhubu a oache ea memori ea DDR le lesela la FPGA ho tekanyo ea oache ea MDDR (ha ho hlokahala) u sebelisa MSS CCC Configurator.
- Hokela sebopeho sa APB sa molaoli joalo ka ha se hlalositsoe ke Pheripheral Initialization tharollo. Bakeng sa potoloho ea MDDR Initialization e hahiloeng ke System Builder, bua ka "MSS DDR Configuration Path" leqepheng la 13 le Figure 2-7.
U ka boela ua iketsetsa potoloho ea hau ea ho qala u sebelisa li-standalone (eseng ka System Builder) Peripheral Initialization. Sheba ho SmartFusion2 Standalone Peripheral Initialization User Guide.
MDDR Configurator
MDDR Configurator e sebelisetsoa ho lokisa datapath ka kakaretso le DDR Memory Parameters ea ka ntle bakeng sa molaoli oa MSS DDR.
Thebo ea Kakaretso e seta litlhophiso tsa Memori le Lesela la Sehokelo sa Masela (Setšoantšo sa 1-1).
Litlhophiso tsa memori
Kenya Nako ea ho Lokisa Memori ea DDR. Ena ke nako eo memori ea DDR e hlokang ho qala. Theko ea kamehla ke 200 us. Sheba Leqephe la Memori ea hau ea DDR bakeng sa boleng bo nepahetseng boo u ka bo kenyang.
Sebelisa Litlhophiso tsa Memori ho hlophisa likhetho tsa memori ea hau ho MDDR.
- Mofuta oa memori - LPDDR, DDR2, kapa DDR3
- Bophara ba data - 32-bit, 16-bit kapa 8-bit
- SECDED Enabled ECC - ON kapa TIMA
- Sekema sa Arbitration – Type-0, Type -1, Type-2,Type-3
- ID ea Bohlokoa ka ho Fetisisa - Litekanyetso tse sebetsang li tsoa ho 0 ho isa ho 15
- Bophara ba Aterese (likotoana) - Sheba Leqephe la Memori ea DDR ea hau bakeng sa palo ea mela, banka, le likotoana tsa aterese bakeng sa memori ea LPDDR/DDR2/DDR3 eo u e sebelisang. khetha lethathamo la ho hula ho khetha boleng bo nepahetseng bakeng sa mela/libanka/likholomo ho latela leqephe la data la memori ea LPDDR/DDR2/DDR3.
Hlokomela: Nomoro e lethathamong la ho theola e bolela palo ea liaterese, eseng palo e felletseng ea mela/libanka/likholomo. Bakeng sa mohlalaample, haeba memori ea DDR e na le libanka tse 4, khetha tse 2 (2 ²=4) bakeng sa libanka. Haeba memori ea DDR e na le libanka tse 8, khetha 3 (2³ =8) bakeng sa libanka.
Litlhophiso tsa Sebopeho sa Lesela
Ka ho sa feleng, processor e thata ea Cortex-M3 e hlophisoa ho fihlella DDR Controller. U ka boela ua lumella Lesela la Master hore le fihle ho DDR Controller ka ho nolofalletsa lebokose la ho hlahloba la Fabric Interface Setting. Tabeng ena, o ka khetha e 'ngoe ea likhetho tse latelang:
- Sebelisa AXI Interface - The fabric Master e fihlella DDR Controller ka sebopeho sa 64-bit AXI.
- Sebelisa Sehokelo se le seng sa AHBLite - Monghali oa lesela o fihlella DDR Controller ka sebopeho se le seng sa 32-bit AHB.
- Sebelisa li-interfaces tse peli tsa AHBLite - Masters a mabeli a masela a fihlella DDR Controller a sebelisa li-interfaces tse peli tsa 32-bit AHB.
Tlhophiso view (Setšoantšo sa 1-1) lintlafatso ho latela khetho ea hau ea Sebopeho sa Lesela.
I/O Drive Strength (DDR2 le DDR3 feela)
Khetha e 'ngoe ea matla a drive a latelang bakeng sa DDR I/Os ea hau:
- Half Drive Matla
- Matla a Drive a Felletseng
Libero SoC e beha DDR I/O Standard bakeng sa sistimi ea MDDR ea hau e ipapisitse le mofuta oa Memory ea DDR le I/O Drive Strength (joalo ka ha ho bonts'itsoe ho Tab le 1-1).
Letlapa la 1-1 • I/O Drive Matla le Mofuta oa Memori ea DDR
| Mofuta oa memori ea DDR | Half Strength Drive | E Feletseng Matla Drive |
| DDR3 | SSTL15I | SSTL15II |
| DDR2 | SSTL18I | SSTL18II |
| LPDDR | LPDRI | LPDRII |
IO Standard (LPDDR feela)
Khetha e 'ngoe ea likhetho tse latelang:
- LVCMOS18 (Matla a Tlase) bakeng sa maemo a tloaelehileng a LVCMOS 1.8V IO. E sebelisoa lits'ebetsong tse tloaelehileng tsa LPDDR1.
- Tlhokomeliso ea LPDDRI: Pele u khetha maemo ana, etsa bonnete ba hore boto ea hau e tšehetsa maemo ana. U tlameha ho sebelisa khetho ena ha u shebile M2S-EVAL-KIT kapa liboto tsa SF2-STARTER-KIT. Litekanyetso tsa LPDDRI IO li hloka hore sehanyetsi sa IMP_CALIB se kenngoe botong.
IO Calibration (LPDDR feela)
Khetha e 'ngoe ea likhetho tse latelang ha u sebelisa standard LVCMOS18 IO:
- On
- Koala (Tlwaelelo)
Calibration ON le OFF e laola ka boikgethelo tshebediso ya boloko ba tekano ba IO bo lekanyang bakganni ba IO ho sehanyetsi sa kantle. Ha HO TLOHILE, sesebelisoa se sebelisa litokiso tse seng li setiloe tsa mokhanni oa IO.
Ha ON, sena se hloka 150-ohm IMP_CALIB resistor hore e kenngwe ho PCB.
Sena se sebelisetsoa ho lekanya IO ho litšobotsi tsa PCB. Leha ho le joalo, ha e setetsoe ho ON, sehanyetsi se hloka ho kenngoa kapa molaoli oa memori o ke ke oa qala.
Bakeng sa lintlha tse ling, sheba ho AC393-SmartFusion2 le IGLOO2 Board Design Guidelines Application
Hlokomela le SmartFusion2 SoC FPGA High Speed DDR Interfaces Guide Guide.
Tlhophiso ea Molaoli oa MDDR
Ha o sebelisa MSS DDR Controller ho fihlella DDR Memory e kantle, DDR Controller e tlameha ho hlophisoa ka nako ea ts'ebetso. Sena se etsoa ka ho ngola lintlha tsa tlhophiso ho lirejistara tse inehetseng tsa DDR controller. Lintlha tsena tsa tlhophiso li ipapisitse le litšobotsi tsa memori ea kantle ea DDR le ts'ebeliso ea hau. Karolo ena e hlalosa mokhoa oa ho kenya likarolo tsena tsa tlhophiso ho configurator ea molaoli oa MSS DDR le hore na data ea tlhophiso e laoloa joang e le karolo ea tharollo ea kakaretso ea Peripheral Initialization.
Lingoliloeng tsa Taolo ea MSS DDR
MSS DDR Controller e na le lethathamo la lirejisetara tse hlokang ho hlophisoa ka nako ea ts'ebetso. Maemo a tlhophiso bakeng sa lirekoto tsena a emela liparamente tse fapaneng, joalo ka DDR mode, bophara ba PHY, mokhoa oa ho phatloha, le ECC. Bakeng sa lintlha tse felletseng mabapi le lirejistara tsa tlhophiso ea taolo ea DDR, sheba ho SmartFusion2 SoC FPGA High Speed DDR Interfaces Guide's Guide.
Tlhophiso ea Lingoliloeng tsa MDDR
Sebelisa Memory Initialization (setšoantšo sa 2-1, setšoantšo sa 2-2, le setšoantšo sa 2-3) le nako ea ho hopola (setšoantšo sa 2-4) ho kenya li-parameter tse tsamaellanang le DDR Memori le ts'ebeliso ea hau. Lipalo tseo u li kenyang ho li-tab tsena li fetoleloa ka bo eona ho ea ho litekanyetso tse loketseng tsa rejisetara. Ha o tobetsa paramethara e itseng, rejisetara ea eona e tsamaellanang e hlalositsoe fenstereng ea Tlhaloso ea Ngoliso (karolo e tlase ho Setšoantšo sa 1-1 leqepheng la 4).
Ho qala ka Memori
Taba ea Memory Initialization e u lumella ho hlophisa mekhoa eo u batlang hore mehopolo ea hau ea LPDDR/DDR2/DDR3 e qalisoe. Lenane le likhetho tse fumanehang ho "Memory Initialization" tab li fapana ho latela mofuta oa memori ea DDR (LPDDR/DDR2/DDR3) eo u e sebelisang. Sheba Leqephe la Memori ea DDR ha u hlophisa likhetho. Ha o fetola kapa o kenya boleng, fenstere ea Tlhaloso ea Ngoliso e u fa lebitso la ngoliso le boleng bo ntlafalitsoeng. Lintlha tse fosahetseng li tšoauoa e le litemoso. Setšoantšo sa 2-1, Figure 2-2, le Figure 2-3 se bonts'a Taba ea ho Qala bakeng sa LPDDR, DDR2 le DDR3, ka ho latellana.
- Boemo ba Nako – Kgetha 1T kapa 2T Mokgwa wa Nako. Ka 1T (mokhoa oa kamehla), molaoli oa DDR a ka fana ka taelo e ncha potolohong e 'ngoe le e 'ngoe ea oache. Ka mokhoa oa 2T oa nako, molaoli oa DDR o tšoara aterese le bese ea taelo e sebetsang bakeng sa lipotoloho tse peli tsa oache. Sena se fokotsa ts'ebetso ea bese ho taelo e le 'ngoe ka lioache tse peli, empa e eketsa habeli palo ea ho seta le ho boloka nako.
- Partial-Array Self Refresh (LPDDR feela). Karolo ena ke ea ho boloka matla bakeng sa LPDDR.
Khetha e 'ngoe ea tse latelang hore molaoli a khatholle boholo ba mohopolo nakong ea ho itlhabolla:
- Lethathamo le felletseng: Libanka 0, 1,2 le 3
- Half array: Banks 0 le 1
- Sehlopha sa kotara: Banka 0
- Sehlopha sa borobeli: Banka 0 e nang le aterese ea mola MSB=0
- Sehlopha sa leshome le metso e ts'eletseng: Banka 0 e nang le aterese ea mola MSB le MSB-1 ka bobeli e lekana le 0.
Bakeng sa likhetho tse ling kaofela, sheba leqephe la hau la DDR Memory Data Sheet ha u hlophisa likhetho.
Nako ea ho Hopola
Taba ena e u lumella ho hlophisa liparamente tsa Nako ea Memori. Sheba Leqephe la Lintlha la memori ea hau ea LPDDR/DDR2/DDR3 ha u hlophisa liparamente tsa Nako ea Memori.
Ha o fetola kapa o kenya boleng, fenstere ea Tlhaloso ea Ngoliso e u fa lebitso la ngoliso le boleng bo ntlafalitsoeng. Lintlha tse fosahetseng li tšoauoa e le litemoso.
E kenya DDR Configuration Files
Ntle le ho kenya liparamente tsa Memori ea DDR u sebelisa li-tabo tsa Memory Initialization le Nako, o ka kenya boleng ba ngoliso ea DDR ho tsoa ho file. Ho etsa joalo, tobetsa konopo ea Import Configuration ebe u ea ho mongolo file e nang le mabitso a ngoliso ea DDR le boleng. Setšoantšo sa 2-5 se bontša syntax ea tlhophiso ea ho kenya.
Hlokomela: Haeba u khetha ho tlisa boleng ba ngoliso ho e-na le ho bo kenya u sebelisa GUI, u tlameha ho totobatsa boleng bohle bo hlokahalang ba ngoliso. Sheba Tataiso ea Basebelisi ea SmartFusion2 SoC FPGA High Speed DDR bakeng sa lintlha.
E romela DDR Configuration Files
U ka boela ua romella lintlha tsa hajoale tsa tlhophiso ea ngoliso ho mongolo file. Sena file e tla ba le litekanyetso tsa ngoliso tseo u li tlisitseng kantle ho naha (haeba li teng) hammoho le tse khomiloeng ho tsoa ho li-parameter tsa GUI tseo u li kentseng puisanong ena.
Haeba u batla ho etsolla liphetoho tseo u li entseng ho tlhophiso ea ngoliso ea DDR, u ka etsa joalo ka Restore Default. Hlokomela hore sena se hlakola lintlha tsohle tsa tlhophiso ea ngoliso mme o tlameha ho reka hape kapa ho kenya data ena hape. Lintlha li seta botjha ho boleng ba ho seta botjha ha hardware.
Lintlha tse hlahisitsoeng
Tobetsa OK ho etsa tlhophiso. Ho ipapisitsoe le seo u se kentseng ho li-tabo tsa Kakaretso, Nako ea Memori le ho Qala Memori, MDDR Configurator e kopanya boleng ba lirekoto tsohle tsa tlhophiso ea DDR ebe e romela boleng bona ho projeke ea hau ea firmware le papiso. files. E romelloang kantle ho naha file syntax e bontšoa ho Setšoantšo sa 2-6.
Firmware
Ha o hlahisa SmartDesign, tse latelang files li hlahisoa ka har'a /firmware/drivers_config/sys_config directory. Tsena files lia hlokahala hore setsi sa firmware sa CMSIS se hlophise hantle 'me se be le leseli mabapi le moralo oa hau oa hajoale ho kenyeletsoa le data ea phetisetso ea phetisetso le tlhaiso-leseling ea lioache bakeng sa MSS. Se ke oa hlophisa tsena files ka letsoho ha li ntse li bōptjoa nako le nako ha moralo oa hau oa metso o etsoa bocha.
- sys_config.c
- sys_config.h
- sys_config_mddr_define.h - MDDR dintlha tsa tlhophiso.
- Sys_config_fddr_define.h - Lintlha tsa tlhophiso ea FDDR.
- sys_config_mss_clocks.h – tlhophiso ea lioache tsa MSS
Ketsiso
Ha o hlahisa SmartDesign e amanang le MSS ea hau, ketsiso e latelang files li hlahisoa ka har'a / directory ea mohlala:
- test.bfm - BFM ea boemo bo holimo file e "phethiloeng" ka lekhetlo la pele nakong ea papiso efe kapa efe e sebelisang processor ea SmartFusion2 MSS' Cortex-M3. E etsa peripheral_init.bfm le user.bfm, ka tatellano eo.
- peripheral_init.bfm – E na le tshebetso ya BFM e etsisang tshebetso ya CMSIS::SystemInit() e sebetsang ho Cortex-M3 pele o kenya () tshebetso. Ha e le hantle e kopiletsa lintlha tsa tlhophiso bakeng sa tlhophiso efe kapa efe e sebelisitsoeng moahong ho lirejisetara tse nepahetseng tsa tlhophiso ebe e emela hore li-peripheral tsohle li be malala-a-laotsoe pele e tiisa hore mosebelisi a ka sebelisa li-peripherals tsena.
- MDDR_init.bfm - E na le litaelo tsa ho ngola tsa BFM tse etsisang mongolo oa data ea rejisetara ea tlhophiso ea MSS DDR eo u e kentseng (u sebelisa lebokose la Edit Registers ka holimo) lirejiseteng tsa DDR Controller.
- user.bfm - E reretsoe litaelo tsa basebelisi. U ka etsisa datapath ka ho eketsa litaelo tsa hau tsa BFM ho sena file. Litaelo ho sena file e tla "phethisoa" ka mor'a hore peripheral_init.bfm e phethe.
Ho sebelisa the files ka holimo, tsela ea tlhophiso e etsisoa ka bo eona. U hloka feela ho fetola user.bfm file ho etsisa datapath. Se ke oa fetola test.bfm, peripheral_init.bfm, kapa MDDR_init.bfm files joalo ka tsena files li etsoa bocha nako le nako ha moralo oa hau oa metso o etsoa bocha.
MSS DDR Configuration Path
Pheripheral Initialization tharollo e hloka hore, ntle le ho hlakisa boleng ba rejisetara ea tlhophiso ea MSS DDR, o lokise tsela ea data ea tlhophiso ea APB ho MSS (FIC_2). Sesebediswa sa SystemInit() se ngolla datha ho direjistara tsa tlhophiso tsa MDDR ka sebopeho sa FIC_2 APB.
Hlokomela: Haeba o sebelisa System Builder, tsela ea tlhophiso e tla beoa ebe e hokahanngoa ka bo eona.
Ho lokisa sebopeho sa FIC_2:
- Bula lebokose la tlhophiso la FIC_2 (setšoantšo sa 2-7) ho tsoa ho setlhophiso sa MSS.
- Khetha khetho ea Initialize peripherals u sebelisa khetho ea Cortex-M3.
- Etsa bonnete ba hore MSS DDR e khethiloe, joalo ka li-block tsa Lesela la DDR/SERDES ha u li sebelisa.
- Tobetsa OK ho boloka litlhophiso tsa hau. Sena se tla pepesa likou tsa tlhophiso tsa FIC_2 (Clock, Reset, le APB bus interfaces), joalo ka ha ho bonts'itsoe ho Setšoantšo sa 2-8.
- Hlahisa MSS. Likou tsa FIC_2 (FIC_2_APB_MASTER, FIC_2_APB_M_PCLK le FIC_2_APB_M_RESET_N) joale li pepesitsoe ho MSS interface 'me li ka hokeloa ho CoreConfigP le CoreResetP ho latela Peripheral Initialization solution.
Bakeng sa lintlha tse felletseng mabapi le ho hlophisa le ho hokahanya li-cores tsa CoreConfigP le CoreResetP, sheba ho Peripheral Initialization User Guide.
Tlhaloso ea Boema-kepe
DDR PHY Interface
Lethathamo la 3-1 • DDR PHY Interface
| Lebitso la Port | Tataiso | Tlhaloso |
| MDDR_CAS_N | TSOA | DRAM CASN |
| MDDR_CKE | TSOA | DRAM CKE |
| MDDR_CLK | TSOA | Tshupanako, lehlakore la P |
| MDDR_CLK_N | TSOA | Tshupanako, N side |
| MDDR_CS_N | TSOA | DRAM CSN |
| MDDR_ODT | TSOA | DRAM ODT |
| MDDR_RAS_N | TSOA | DRAM RASN |
| MDDR_RESET_N | TSOA | Seta bocha DRAM bakeng sa DDR3. Hlokomoloha lets'oao lena bakeng sa LPDDR le DDR2 Interfaces. E tšoaee e sa sebelisoe bakeng sa LPDDR le DDR2 Interfaces. |
| MDDR_WE_N | TSOA | TERAMA WEN |
| MDDR_ADDR[15:0] | TSOA | Likotoana tsa Aterese ea Dram |
| MDDR_BA[2:0] | TSOA | Aterese ea Banka ea Dram |
| MDDR_DM_RDQS ([3:0]/[1:0]/[0]) | LIEKETSENG | Dram Data Mask |
| MDDR_DQS ([3:0]/[1:0]/[0]) | LIEKETSENG | Dram Data Strobe Input/Output – P Side |
| MDDR_DQS_N ([3:0]/[1:0]/[0]) | LIEKETSENG | Dram Data Strobe Input/Output – N Side |
| MDDR_DQ ([31:0]/[15:0]/[7:0]) | LIEKETSENG | DRAM Data Input/Output |
| MDDR_DQS_TMATCH_0_IN | IN | FIFO ka pontšo |
| MDDR_DQS_TMATCH_0_OUT | TSOA | FIFO e tsoa letšoao |
| MDDR_DQS_TMATCH_1_IN | IN | FIFO ho lets'oao (32-bit feela) |
| MDDR_DQS_TMATCH_1_OUT | TSOA | Lets'oao la FIFO (32-bit feela) |
| MDDR_DM_RDQS_ECC | LIEKETSENG | Dram ECC Data Mask |
| MDDR_DQS_ECC | LIEKETSENG | Dram ECC Data Strobe Input/Output – P Side |
| MDDR_DQS_ECC_N | LIEKETSENG | Dram ECC Data Strobe Input/Output – N Side |
| MDDR_DQ_ECC ([3:0]/[1:0]/[0]) | LIEKETSENG | DRAM ECC Data Input/Output |
| MDDR_DQS_TMATCH_ECC_IN | IN | ECC FIFO ka pontšo |
| MDDR_DQS_TMATCH_ECC_OUT | TSOA | ECC FIFO lets'oao la kantle (32-bit feela) |
Hlokomela: Bophahamo ba likou bakeng sa likou tse ling boa fetoha ho latela khetho ea bophara ba PHY. Mantsoe “[a:0]/ [b:0]/[c:0]” a sebelisoa ho supa likou tse joalo, moo “[a:0]” e supang bophara ba kou ha ho khethoa bophara ba 32-bit PHY. , “[b:0]” e tsamaellana le bophara ba 16-bit PHY, le “[c:0]” e tsamaellana le 8-bit PHY bophara.
Lesela Master AXI Bus Interface
Letlapa la 3-2 • Lesela la Master AXI Bus Interface
| Lebitso la Port | Tataiso | Tlhaloso |
| DDR_AXI_S_A HLOKOMELA | TSOA | Ngola aterese e lokile |
| DDR_AXI_S_WREADY | TSOA | Ngola aterese e lokile |
| DDR_AXI_S_BID[3:0] | TSOA | ID ea karabo |
| DDR_AXI_S_BRSP[1:0] | TSOA | Ngola karabo |
| DDR_AXI_S_BVALID | TSOA | Ngola karabo e nepahetse |
| DDR_AXI_S_ARREADY | TSOA | Bala aterese e lokile |
| DDR_AXI_S_RID[3:0] | TSOA | Bala ID Tag |
| DDR_AXI_S_RRSP[1:0] | TSOA | Bala Karabo |
| DDR_AXI_S_RDATA[63:0] | TSOA | Bala data |
| DDR_AXI_S_RLAST | TSOA | Bala Qetellong Letšoao lena le bontša phetiso ea ho qetela ka ho phatloha ho hoholo |
| DDR_AXI_S_RVALID | TSOA | Aterese ea ho bala e nepahetse |
| DDR_AXI_S_AWID[3:0] | IN | Ngola Aterese ID |
| DDR_AXI_S_AWADDR[31:0] | IN | Ngola aterese |
| DDR_AXI_S_AWLEN[3:0] | IN | Bolelele ba ho phatloha |
| DDR_AXI_S_AWSIZE[1:0] | IN | Boholo ba ho phatloha |
| DDR_AXI_S_AWBURST[1:0] | IN | Mofuta oa ho phatloha |
| DDR_AXI_S_AWLOCK[1:0] | IN | Mofuta oa senotlolo Letšoao lena le fana ka tlhahisoleseling e eketsehileng mabapi le litšobotsi tsa athomo tsa phetiso |
| DDR_AXI_S_AWVALID | IN | Ngola aterese e nepahetse |
| DDR_AXI_S_WID[3:0] | IN | Ngola Data ID tag |
| DDR_AXI_S_WDATA[63:0] | IN | Ngola lintlha |
| DDR_AXI_S_WSTRB[7:0] | IN | Ngola strobes |
| DDR_AXI_S_WLAST | IN | Ngola qetellong |
| DDR_AXI_S_WVALID | IN | Ngola e nepahetse |
| DDR_AXI_S_BREADY | IN | Ngola o itokisitse |
| DDR_AXI_S_ARID[3:0] | IN | Bala ID ea Aterese |
| DDR_AXI_S_ARADDR[31:0] | IN | Bala aterese |
| DDR_AXI_S_ARLEN[3:0] | IN | Bolelele ba ho phatloha |
| DDR_AXI_S_ARSIZE[1:0] | IN | Boholo ba ho phatloha |
| DDR_AXI_S_ARBURST[1:0] | IN | Mofuta oa ho phatloha |
| DDR_AXI_S_ARLOCK[1:0] | IN | Mofuta oa Lock |
| DDR_AXI_S_ARVALID | IN | Aterese ea ho bala e nepahetse |
| DDR_AXI_S_RREADY | IN | Bala aterese e lokile |
Tafole 3-2 • Fabric Master AXI Bus Interface (e tsoela pele)
| Lebitso la Port | Tataiso | Tlhaloso |
| DDR_AXI_S_CORE_RESET_N | IN | MDDR Global Reset |
| DDR_AXI_S_RMW | IN | E bontša hore na li-byte tsohle tsa 64 bit lane li nepahetse bakeng sa li-beats tsohle tsa phetisetso ea AXI. 0: E bontša hore li-byte tsohle ho li-beats tsohle li nepahetse ha ho phatloha 'me molaoli o tlameha ho ngola litaelo. 1: E bontša hore li-byte tse ling ha li sebetse 'me molaoli o lokela ho latela litaelo tsa RMW Sena se khethiloe e le lets'oao la lehlakore la AXI la aterese mme le sebetsa ka lets'oao la AWVALID. E sebelisoa feela ha ECC e buletsoe. |
Lesela Master AHB0 Bus Interface
Letlapa 3-3 • Lesela Master AHB0 Bus Interface
| Lebitso la Port | Tataiso | Tlhaloso |
| DDR_AHB0_SHREADYOUT | TSOA | AHBL lekhoba le itokisitse - Ha e phahame bakeng sa ho ngola e bontša hore MDDR e se e loketse ho amohela data mme ha e phahame bakeng sa ho bala e bontša hore data e nepahetse. |
| DDR_AHB0_SHRESP | TSOA | Boemo ba karabo ea AHBL - Ha e tsamaisoa holimo qetellong ea transaction e bontša hore transaction e phethiloe ka liphoso. Ha e tsamaisoa tlase qetellong ea transaction e bontša hore transaction e phethiloe ka katleho. |
| DDR_AHB0_SHRDATA[31:0] | TSOA | AHBL e bala data - Bala lintlha tse tsoang ho lekhoba la MDDR ho ea ho mong'a masela |
| DDR_AHB0_SHSEL | IN | Khetho ea makhoba a AHBL - Ha ho boleloa, MDDR ke lekhoba le khethiloeng hajoale la AHBL ka beseng ea AHB. |
| DDR_AHB0_SHADDR[31:0] | IN | Aterese ea AHBL - aterese ea byte ho sebopeho sa AHBL |
| DDR_AHB0_SHBURST[2:0] | IN | AHBL Burst Length |
| DDR_AHB0_SHSIZE[1:0] | IN | Boholo ba phetisetso ea AHBL - E bonts'a boholo ba phetisetso ea hajoale (8/16/32 byte transactions feela) |
| DDR_AHB0_SHTRANS[1:0] | IN | Mofuta oa phetisetso ea AHBL - E bontša mofuta oa phetisetso ea transaction ea hajoale |
| DDR_AHB0_SHMASTLOCK | IN | AHBL Lock - Ha ho boleloa hore phetisetso ea hajoale ke karolo ea khoebo e notletsoeng |
| DDR_AHB0_SHWRITE | IN | AHBL ngola - Ha phahameng e bontša hore transaction ea hona joale ke ho ngola. Ha tlase e bontša hore transaction ea hajoale e baloa |
| DDR_AHB0_S_HREADY | IN | AHBL e loketse - Ha e phahame, e bontša hore MDDR e se e loketse ho amohela transaction e ncha |
| DDR_AHB0_S_HWDATA[31:0] | IN | AHBL ngola lintlha - Ngola lintlha ho tloha ho setsebi sa masela ho ea ho MDDR |
Lesela Master AHB1 Bus Interface
Letlapa 3-4 • Lesela Master AHB1 Bus Interface
| Lebitso la Port | Tataiso | Tlhaloso |
| DDR_AHB1_SHREADYOUT | TSOA | AHBL lekhoba le itokisitse - Ha e phahame bakeng sa ho ngola e bontša hore MDDR e se e loketse ho amohela data mme ha e phahame bakeng sa ho bala e bontša hore data e nepahetse. |
| DDR_AHB1_SHRESP | TSOA | Boemo ba karabo ea AHBL - Ha e tsamaisoa holimo qetellong ea transaction e bontša hore transaction e phethiloe ka liphoso. Ha e tsamaisoa tlase qetellong ea transaction e bontša hore transaction e phethiloe ka katleho. |
| DDR_AHB1_SHRDATA[31:0] | TSOA | AHBL e bala data - Bala lintlha tse tsoang ho lekhoba la MDDR ho ea ho mong'a masela |
| DDR_AHB1_SHSEL | IN | Khetho ea makhoba a AHBL - Ha ho boleloa, MDDR ke lekhoba le khethiloeng hajoale la AHBL ka beseng ea AHB. |
| DDR_AHB1_SHADDR[31:0] | IN | Aterese ea AHBL - aterese ea byte ho sebopeho sa AHBL |
| DDR_AHB1_SHBURST[2:0] | IN | AHBL Burst Length |
| DDR_AHB1_SHSIZE[1:0] | IN | Boholo ba phetisetso ea AHBL - E bonts'a boholo ba phetisetso ea hajoale (8/16/32 byte transactions feela) |
| DDR_AHB1_SHTRANS[1:0] | IN | Mofuta oa phetisetso ea AHBL - E bontša mofuta oa phetisetso ea transaction ea hajoale |
| DDR_AHB1_SHMASTLOCK | IN | AHBL Lock - Ha ho boleloa hore phetisetso ea hajoale ke karolo ea khoebo e notletsoeng |
| DDR_AHB1_SHWRITE | IN | AHBL ngola - Ha holimo ho bontša hore transaction ea hona joale ke ho ngola. Ha tlase e bontša hore transaction ea hajoale e baloa. |
| DDR_AHB1_SHREADY | IN | AHBL e loketse - Ha e phahame, e bontša hore MDDR e se e loketse ho amohela transaction e ncha |
| DDR_AHB1_SHWDATA[31:0] | IN | AHBL ngola lintlha - Ngola lintlha ho tloha ho setsebi sa masela ho ea ho MDDR |
Soft Memory Controller Mode AXI Bus Interface
Letlapa la 3-5 • Mokhoa oa Soft Memory Controller AXI Bus Interface
| Lebitso la Port | Tataiso | Tlhaloso |
| SMC_AXI_M_WLAST | TSOA | Ngola qetellong |
| SMC_AXI_M_WVALID | TSOA | Ngola e nepahetse |
| SMC_AXI_M_AWLEN[3:0] | TSOA | Bolelele ba ho phatloha |
| SMC_AXI_M_AWBURST[1:0] | TSOA | Mofuta oa ho phatloha |
| SMC_AXI_M_Bready | TSOA | Karabo e lokile |
| SMC_AXI_M_AWVALID | TSOA | Ngola Aterese e ea nepahala |
| SMC_AXI_M_AWID[3:0] | TSOA | Ngola Aterese ID |
| SMC_AXI_M_WDATA[63:0] | TSOA | Ngola Lintlha |
| SMC_AXI_M_ARVALID | TSOA | Aterese ea ho bala e nepahetse |
| SMC_AXI_M_WID[3:0] | TSOA | Ngola Data ID tag |
| SMC_AXI_M_WSTRB[7:0] | TSOA | Ngola strobes |
| SMC_AXI_M_ARID[3:0] | TSOA | Bala ID ea Aterese |
| SMC_AXI_M_ARADDR[31:0] | TSOA | Bala aterese |
| SMC_AXI_M_ARLEN[3:0] | TSOA | Bolelele ba ho phatloha |
| SMC_AXI_M_ARSIZE[1:0] | TSOA | Boholo ba ho phatloha |
| SMC_AXI_M_ARBURST[1:0] | TSOA | Mofuta oa ho phatloha |
| SMC_AXI_M_AWADDR[31:0] | TSOA | Ngola Aterese |
| SMC_AXI_M_RREATS | TSOA | Bala aterese e lokile |
| SMC_AXI_M_AWSIZE[1:0] | TSOA | Boholo ba ho phatloha |
| SMC_AXI_M_AWLOCK[1:0] | TSOA | Mofuta oa senotlolo Letšoao lena le fana ka tlhahisoleseling e eketsehileng mabapi le litšobotsi tsa athomo tsa phetiso |
| SMC_AXI_M_ARLOCK[1:0] | TSOA | Mofuta oa Lock |
| SMC_AXI_M_BID[3:0] | IN | ID ea karabo |
| SMC_AXI_M_RID[3:0] | IN | Bala ID Tag |
| SMC_AXI_M_RRSP[1:0] | IN | Bala Karabo |
| SMC_AXI_M_BRSP[1:0] | IN | Ngola karabo |
| SMC_AXI_M_E HLAHILE | IN | Ngola aterese e lokile |
| SMC_AXI_M_RDATA[63:0] | IN | Bala Lintlha |
| SMC_AXI_M_LOITSE | IN | Ngola o itokisitse |
| SMC_AXI_M_BVALID | IN | Ngola karabo e nepahetse |
| SMC_AXI_M_ARREADY | IN | Bala aterese e lokile |
| SMC_AXI_M_RLAST | IN | Bala Qetellong Letšoao lena le bontša phetiso ea ho qetela ka ho phatloha ho hoholo |
| SMC_AXI_M_RVALID | IN | E Balehile |
Mokhoa oa Soft Memory Controller AHB0 Bus Interface
Letlapa la 3-6 • Mokhoa oa Soft Memory Controller AHB0 Bus Interface
| Lebitso la Port | Tataiso | Tlhaloso |
| SMC_AHB_M_HBURST[1:0] | TSOA | AHBL Burst Length |
| SMC_AHB_M_HTRANS[1:0] | TSOA | Mofuta oa phetisetso ea AHBL - E bontša mofuta oa phetisetso ea transaction ea hajoale. |
| SMC_AHB_M_HMASTLOCK | TSOA | AHBL Lock - Ha ho boleloa hore phetisetso ea hajoale ke karolo ea khoebo e notletsoeng |
| SMC_AHB_M_HWRITE | TSOA | AHBL ngola - Ha e phahameng e bontša hore transaction ea hona joale ke ho ngola. Ha tlase e bontša hore transaction ea hajoale e baloa |
| SMC_AHB_M_HSIZE[1:0] | TSOA | Boholo ba phetisetso ea AHBL - E bonts'a boholo ba phetisetso ea hajoale (8/16/32 byte transactions feela) |
| SMC_AHB_M_HWDATA[31:0] | TSOA | AHBL ngola data - Ngola data ho tsoa ho master MSS ho ea leselang Soft Memory Controller |
| SMC_AHB_M_HADDR[31:0] | TSOA | Aterese ea AHBL - aterese ea byte ho sebopeho sa AHBL |
| SMC_AHB_M_HRSP | IN | Boemo ba karabo ea AHBL - Ha e tsamaisoa holimo qetellong ea transaction e bontša hore transaction e phethiloe ka liphoso. Ha e tsamaisoa tlase qetellong ea transaction e bontša hore transaction e phethiloe ka katleho |
| SMC_AHB_M_HRDATA[31:0] | IN | AHBL bala data – Bala data ho tswa ho lesela Soft Memory Controller ho MSS master |
| SMC_AHB_M_HREADY | IN | AHBL e itokisitse - Phahameng e bontša hore bese ea AHBL e se e loketse ho amohela transaction e ncha |
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5-02-00377-5/11.16
Litokomane / Lisebelisoa
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Sebopeho sa Microsemi SmartFusion2 MSS DDR Controller [pdf] Bukana ea Mosebelisi Tlhophiso ea SmartFusion2 MSS DDR Controller, SmartFusion2 MSS, DDR Controller Configuration, Configuration ea Molaoli. |
