SmartFusion2 MSS
DDR Pule Fa'atonu
Libero SoC v11.6 ma mulimuli ane 

Folasaga

O le SmartFusion2 MSS o loʻo i ai le faʻapipiʻiina o le DDR controller. O lenei fa'atonu DDR ua fa'amoemoe e fa'atonutonu se fa'amanatu DDR i fafo. E mafai ona maua le pule MDDR mai le MSS fa'apea fo'i ma le ie FPGA. E le gata i lea, o le DDR controller e mafai foi ona faʻafefe, tuʻuina atu se faʻaopoopoga faʻaopoopoga i le ie FPGA (Soft Controller Mode (SMC)).
Ina ia fa'atulaga atoatoa le MSS DDR controller, e tatau ona e:

1. Filifili le auala faʻamatalaga e faʻaaoga ai le MDDR Configurator.
2. Seti le tau resitala mo le DDR controller registers.
3. Filifili le DDR memory clock frequency ma le FPGA fabric i le MDDR clock ratio (pe a manaʻomia) faʻaaoga le MSS CCC Configurator.
4. Fa'afeso'ota'i le fa'atonuga o le APB fa'apipi'i e pei ona fa'amatalaina e le vaifofo o le Fa'asalalauga Fa'asao. Mo le MDDR Initialization circuitry fausia e System Builder, tagai i le “MSS DDR Configuration Path” i le itulau 13 ma le Ata 2-7.
   E mafai fo'i ona e fau sau lava ta'aloga fa'amataina e fa'aoga tu'utasi (ae le o le Faufale Fa'atonu) Fa'amataina Fa'aalaala. Va'ai ile SmartFusion2 Standalone Peripheral Initialization Guide Guide.

MDDR Configurator

O le MDDR Configurator o loʻo faʻaaogaina e faʻapipiʻi ai le faʻamaumauga atoa ma le DDR Memory Parameters i fafo mo le MSS DDR controller.

O le General tab e fa'atulaga ai lau Fa'amanatuga ma Ie Fa'afeso'ota'i (Ata 1-1).
Fa'atonuga
Ulufale i le DDR Memory Settling Time. O le taimi lea e manaʻomia e le DDR memory e amata ai. Ole tau fa'aletonu ole 200 us. Va'ai lau DDR Memory Data Pepa mo le tau sa'o e ulufale.
Fa'aoga Seti Manatu e fa'atulaga ai au filifiliga e manatua ile MDDR.

• Ituaiga Manatu - LPDDR, DDR2, poʻo DDR3
• Fa'amatalaga Lautele - 32-bit, 16-bit po'o le 8-bit
• SECDED Enabled ECC – ON pe OFF
• Fuafuaga Faʻatonu - Ituaiga-0, Ituaiga -1, Ituaiga-2, Ituaiga-3
• ID Fa'amuamua - O tau aoga e mai le 0 i le 15
• Itulau Lautele (bits) – Va'ai lau DDR Memory Data Pepa mo le numera o laina, faletupe, ma koluma tuatusi pito mo le LPDDR/DDR2/DDR3 manatua e te fa'aogaina. filifili le lisi toso i lalo e filifili ai le tau saʻo mo laina / faletupe / koluma e tusa ai ma le pepa faʻamatalaga o le LPDDR / DDR2 / DDR3 manatua.

Fa'aaliga: Ole numera ile lisi toso i lalo e faasino ile numera ole Address bits, ae le o le numera atoa o laina / faletupe / koluma. Mo example, afai o lau DDR memory e 4 faletupe, filifili le 2 (2 ²=4) mo faletupe. Afai o lau DDR memory e 8 faletupe, filifili le 3 (2³ =8) mo faletupe.

Fa'asagaga Fa'afeso'ota'i Ie
Ona o le faaletonu, ua setiina le Cortex-M3 processor e maua ai le DDR Controller. E mafai fo'i ona e fa'ataga se Matai ie e fa'aoga i le DDR Controller e ala i le fa'aagaina o le Fabric Interface Set checkbox. I lenei tulaga, e mafai ona e filifilia se tasi o filifiliga nei:

• Fa'aoga se AXI Interface - E maua e le Master ie le DDR Controller e ala ile 64-bit AXI interface.
• Fa'aoga se Feso'ota'iga AHBLite Tasi - O lo'o fa'aogaina e le Master ie i le DDR Controller e ala i se tasi 32-bit AHB interface.
• Fa'aoga lua AHBLite Interfaces - Lua ie Masters maua le DDR Controller e faʻaaoga ai fesoʻotaʻiga 32-bit AHB e lua.
  Le faatulagaga view (Ata 1-1) fa'afouga e tusa ai ma lau filifiliga Fa'aoga Ie.

Malosi o le Ta'avale I/O (Na'o DDR2 ma DDR3)
Filifili se tasi o le malosi o le taʻavale mo lau DDR I/Os:

• Malosi Avega afa
•  Malosi o le Avetaavale atoa

Libero SoC e setiina le DDR I/O Standard mo lau MDDR system e fa'atatau i lau DDR Memory type ma le I/O Drive Strength (e pei ona fa'aalia i le Tab le 1-1).
Laulau 1-1 • Malosiaga o le Ta'avale I/O ma le Ituaiga Fa'amanatu DDR

DDR Memory Ituaiga	Avega afa Malosi	Malosi atoatoa Avetaavale
DDR3	SSTL15I	SSTL15II
DDR2	SSTL18I	SSTL18II
LPDDR	LPDRI	LPDRII

IO Standard (LPDDR na'o)
Filifili se tasi o filifiliga nei:

• LVCMOS18 (Malosi Maulalo) mo LVCMOS 1.8V IO tulaga masani. Fa'aoga i fa'aoga masani LPDDR1.
• LPDDRI Fa'aaliga: Ae e te le'i filifilia lenei tulaga, ia mautinoa o lo'o lagolagoina e lau laupapa lenei tulaga. E tatau ona e fa'aogaina lenei filifiliga pe a tulimata'i le M2S-EVAL-KIT po'o le SF2-STARTER-KIT laupapa. LPDDRI IO tulaga faatonuina e manaʻomia se IMP_CALIB tetee faʻapipiʻi i luga o le laupapa.

IO Fa'avasegaina (LPDDR na'o)
Filifili se tasi o filifiliga nei pe a faʻaogaina le LVCMOS18 IO tulaga:

• On
• Pa'u (Toe masani)

Calibration ON ma OFF filifili filifiliga pulea le faaaogaina o se IO calibration poloka e calibrates le avetaavale IO i se tetee fafo. A OFF, e fa'aaoga e le masini se fa'atonuga fa'atonu aveta'avale IO.
A ON, e manaʻomia se 150-ohm IMP_CALIB tetee e faʻapipiʻi i luga o le PCB.
E faʻaaogaina lenei mea e faʻavasega ai le IO i uiga PCB. Ae peitaʻi, pe a seti i ON, e manaʻomia ona faʻapipiʻi se tetee pe o le a le amataina le faʻatonuga manatua.
Mo nisi faʻamatalaga, vaʻai ile AC393-SmartFusion2 ma IGLOO2 Board Design Guidelines Application
Manatua ma le SmartFusion2 SoC FPGA High Speed ​​DDR Interfaces User Guide.

MDDR Pule Fa'atonu

A e faʻaogaina le MSS DDR Pule e faʻaoga ai se DDR Memory i fafo, e tatau ona faʻapipiʻi le DDR Controller i le taimi e taʻavale ai. E faia lenei mea e ala i le tusiaina o faʻamaumauga o faʻamaumauga i faʻamaumauga tuʻufaʻatasia o le DDR controller. O faʻamaumauga faʻatulagaina e faʻalagolago i uiga o le DDR memory i fafo ma lau talosaga. O lenei vaega o loʻo faʻamatalaina pe faʻafefea ona faʻaogaina nei faʻamaufaʻailoga i le MSS DDR controller configurator ma pe faʻafefea ona faʻatautaia faʻamaumauga o faʻamaumauga e avea o se vaega o le aotelega o le Peripheral Initialization solution.

MSS DDR Pule Resitala
O le MSS DDR Controller o loʻo i ai se seti o tusi resitala e manaʻomia ona faʻatulagaina i le taimi e taʻavale ai. O tulaga fa'atulagaina mo nei tusi resitala o lo'o fa'atusalia ai ta'iala eseese, pei ole DDR mode, PHY lautele, burst mode, ma ECC. Mo fa'amatalaga atoatoa e uiga i le DDR controller configurations registers, tagai ile SmartFusion2 SoC FPGA High Speed ​​DDR Interfaces User's Guide.
MDDR Registers Configuration
Fa'aoga le Fa'amatalaga Fa'amatalaga (Ata 2-1, Ata 2-2, ma le Ata 2-3) ma le Taimi Fa'amanatu (Ata 2-4) e fa'aulu ai ta'iala e fetaui ma lau DDR Memory ma le fa'aoga. O tau e te fa'aulu i totonu o nei fa'ailoga e otometi lava ona fa'aliliu i fa'atauga resitala talafeagai. A e kilikiina se parakalafa patino, o lona tusi resitala e faʻamatalaina i le Resitala Faʻamatalaga pane (vaega pito i lalo ile Ata 1-1 ile itulau 4).
Fa'aliga Fa'amanatu
O le fa'ailoga o le Memory Initialization e mafai ai e oe ona fa'atulaga auala e te mana'o ai e fa'amataina au manatuaga LPDDR/DDR2/DDR3. O le lisi ma filifiliga o loʻo avanoa i le Memory Initialization tab e eseese ma le ituaiga DDR memory (LPDDR/DDR2/DDR3) e te faʻaaogaina. Va'ai i lau DDR Memory Data Pepa pe a e fa'atulagaina filifiliga. A e suia pe ulufale i se tau, o le Resitala Faʻamatalaga pane e tuʻuina atu ia te oe le igoa resitala ma le tau resitala o loʻo faʻafouina. O tau le aoga o lo'o fa'ailogaina o ni lapataiga. Ata 2-1, Ata 2-2, ma le Ata 2-3 o loʻo faʻaalia ai le faʻasologa o le Initialization mo LPDDR, DDR2 ma DDR3.

• Taimi Taimi - Filifili le 1T poʻo le 2T Taimi taimi. I le 1T (le tulaga le lelei), e mafai e le DDR controller ona tuʻuina atu se poloaiga fou i taʻamilosaga uma o le uati. I le 2T timing mode, o le DDR controller o loʻo umia le tuatusi ma le faʻatonuga o pasi aoga mo le lua taamilosaga uati. Ole mea lea e fa'aitiitia ai le lelei ole pasi ile tasi le fa'atonuga ile lua uati, ae fa'aluaina le aofa'i o le seti ma le taimi fa'amau.
• Fa'a-vaega Fa'afou Lava (LPDDR na'o). O lenei vaega e mo le fa'asaoina o le eletise mo le LPDDR.
  Filifili se tasi o mea nei mo le pule e faʻafouina le aofaʻi o manatua i le taimi o le faʻafouina o le tagata lava ia:
  - Fa'asologa atoa: Faletupe 0, 1,2, ma le 3
  - afa afa: Faletupe 0 ma le 1
  - Fa'asologa o kuata: Faletupe 0
  – Tasi-valu laina: Faletupe 0 ma le laina tuatusi MSB=0
  – Tasi-sefuluono laina: Faletupe 0 ma le laina tuatusi MSB ma MSB-1 e tutusa uma ma le 0.
  Mo isi filifiliga uma, va'ai i lau DDR Memory Data Pepa pe ae fa'atulagaina filifiliga.
  

Taimi Fa'amanatu
O lenei laupepa e mafai ai e oe ona faʻapipiʻi faʻamaufaʻailoga Taimi Faʻamanatuga. Va'ai i le Pepa Fa'amatalaga o lou LPDDR/ DDR2/DDR3 manatua pe a fa'atulaga le taimi o le Fa'amanatuga.
A e suia pe ulufale i se tau, o le Resitala Faʻamatalaga pane e tuʻuina atu ia te oe le igoa resitala ma le tau resitala o loʻo faʻafouina. O fa'atauga le aoga o lo'o fa'ailogaina o ni lapataiga.

Fa'aulufaleina o le DDR Configuration Files
I le faaopoopo atu i le ulufale i le DDR Memory parameters e faʻaaoga ai le Memory Initialization ma Taimi taimi, e mafai ona e faʻaulufaleina faʻamaufaʻailoga DDR mai se file. Ina ia faia, kiliki i le Fa'aulufalega Fa'amau fa'amau ma fa'afeiloa'i i le tusitusiga file o lo'o iai igoa resitara DDR ma tau. Ata 2-5 o lo'o fa'aalia ai le fa'asologa o fa'aulufale mai.

Fa'aaliga: Afai e te filifili e fa'aulufale mai fa'atauga resitala nai lo le fa'auluina i latou e fa'aaoga ai le GUI, e tatau ona e fa'ama'oti uma fa'atauga resitala talafeagai. Va'ai ile SmartFusion2 SoC FPGA High Speed ​​DDR Interfaces User's Guide mo fa'amatalaga.

Fa'atauina atu o le DDR Configuration Files
E mafai fo'i ona e fa'atauina atu fa'amaumauga o fa'amaumauga o le resitala o lo'o iai nei i totonu o se tusitusiga file. Lenei file o le a iai fa'atauga resitala na e fa'aulufale mai (pe a iai) fa'apea fo'i ma mea na fa'atatauina mai fa'amaufa'ailoga GUI na e ulufale i ai i lenei talanoaga.
Afai e te mana'o e fa'aleaogaina suiga na e faia i le DDR register configuration, e mafai ona e faia i le Restore Default. Manatua o lenei mea e tape uma ai faʻamaumauga o faʻamaumauga o le resitala ma e tatau ona e toe faʻaulufaleina pe toe tuʻuina atu nei faʻamatalaga. O fa'amaumauga e toe fa'afo'i i le fa'atonuga o meafaigaluega.
Fa'atupuina Fa'amaumauga
Kiliki OK e fa'atupu ai le fa'atulagaga. Faʻavae i luga o lau faʻaoga i le General, Memory Timing ma Memory Initialization tabs, o le MDDR Configurator e faʻatatauina tau mo faʻamaumauga uma o le DDR ma faʻatau atu nei tau i totonu o lau poloketi firmware ma faʻataʻitaʻiga. files. O le auina atu i fafo file syntax o lo'o fa'aalia ile Ata 2-6.

Firmware

A e fatuina le SmartDesign, o mea nei files e gaosia i totonu o le /firmware/ drivers_config/sys_config directory. O nei files e mana'omia mo le CMSIS firmware core e tu'ufa'atasia lelei ma aofia ai fa'amatalaga e uiga i lau mamanu o lo'o iai nei e aofia ai fa'amatalaga fa'asologa o le peripheral ma fa'amatalaga fa'atulagaina o le uati mo le MSS. Aua le fa'asa'o nei mea files ma le lima a'o toe faia i taimi uma e toe fa'atupuina ai lau mamanu a'a.

• sys_config.c
• sys_config.h
•  sys_config_mddr_define.h – MDDR faʻamaumauga faʻatulagaina.
• Sys_config_fddr_define.h – FDDR faʻamaumauga faʻatulagaina.
•  sys_config_mss_clocks.h – MSS uati faatulagaina

Fa'ata'oto
A e faʻatupuina le SmartDesign e fesoʻotaʻi ma lau MSS, o le faʻataʻitaʻiga lea files e gaosia i totonu o le /fa'ailoga fa'atusa:

•  test.bfm – Tulaga maualuga BFM file e muamua "fa'atinoina" i so'o se fa'ata'ita'iga o lo'o fa'aogaina le SmartFusion2 MSS 'Cortex-M3 processor. E fa'atinoina le peripheral_init.bfm ma le user.bfm, i lena fa'atonuga.
•  peripheral_init.bfm - O loʻo i ai le BFM faʻataʻitaʻiga e faʻataʻitaʻia le CMSIS :: SystemInit () galuega faʻatino i luga o le Cortex-M3 ae e te leʻi ulufale i le autu () taualumaga. E matua'i kopiina fa'amaumauga o fa'amaumauga mo so'o se peripheral fa'aogaina i le mamanu i le sa'o o le resitara o fa'atonuga fa'apitonu'u ona fa'atali lea mo so'o se peripherals e sauni a'o le'i fa'ailoa mai e mafai e le tagata fa'aoga ona fa'aoga nei peripheral.
• MDDR_init.bfm - O loʻo i ai le BFM tusitusi faʻatonuga e faʻataʻitaʻia tusitusiga o le MSS DDR configuration register data na e ulufale i ai (faʻaaogaina le Edit Registers dialog i luga) i totonu o le DDR Controller registers.
• user.bfm – Fa'amoemoe mo fa'atonuga fa'aoga. E mafai ona e faʻataʻitaʻiina le datapath e ala i le faʻaopoopoina o au lava tulafono BFM i lenei mea file. Poloaiga i lenei file o le a "fa'atinoina" pe a mae'a le peripheral_init.bfm.

Fa'aaogaina o le files luga, o le ala faatulagaga e simulated otometi. E na'o lou fa'asa'o ole user.bfm file e fa'ata'ita'i le alafa'amatalaga. Aua le fa'asa'o le test.bfm, peripheral_init.bfm, po'o le MDDR_init.bfm filee pei o nei files e toe faia i taimi uma e toe fa'atupuina ai lau mamanu a'a.

MSS DDR Configuration Ala
E mana'omia e le vaifofo Peripheral Initialization, fa'aopoopo i le fa'ama'otiina o tau o le resitala o le resitara o le MSS DDR, e te fa'atulagaina le ala o fa'amaumauga a le APB i le MSS (FIC_2). O le SystemInit () galuega e tusi ai faʻamatalaga i le MDDR configuration registers e ala i le FIC_2 APB interface.
Fa'aaliga: Afai o lo'o e fa'aogaina le System Builder e fa'apipi'i ma feso'ota'i aunoa le ala fa'aopoopo.

Ina ia fa'atulaga le FIC_2 fa'aoga:

1. Tatala le FIC_2 configurator dialog (Ata 2-7) mai le MSS configurator.
2. Filifili le Initialize peripherals e faʻaaoga Cortex-M3 filifiliga.
3. Ia mautinoa ua siaki le MSS DDR, e pei o poloka DDR/SERDES Ie pe a e fa'aaogaina.
4.  Kiliki OK e teu ai au fa'atulagaga. O lenei mea o le a fa'aalia ai le FIC_2 fetuutuunaiga ports (Uti, Toe Seti, ma APB feso'ota'iga pasi), e pei ona fa'aalia i le Ata 2-8.
5.  Fausia le MSS. O ports FIC_2 (FIC_2_APB_MASTER, FIC_2_APB_M_PCLK ma FIC_2_APB_M_RESET_N) o loʻo faʻaalia nei i le MSS interface ma e mafai ona faʻafesoʻotaʻi i le CoreConfigP ma CoreResetP e pei o le Peripheral Initialization solution specification.

Mo fa'amatalaga atoatoa i le fa'atulagaina ma le fa'afeso'ota'i o le CoreConfigP ma le CoreResetP cores, tagai ile Peripheral Initialization User Guide.

Fa'amatalaga Taulaga

DDR PHY Interface
Laulau 3-1 • DDR PHY Feso'ota'iga

Igoa o le Taulaga	Fa'atonuga	Fa'amatalaga
MDDR_CAS_N	IFO	DRAM CASN
MDDR_CKE	IFO	DRAM CKE
MDDR_CLK	IFO	Uati, itu P
MDDR_CLK_N	IFO	Uati, itu N
MDDR_CS_N	IFO	DRAM CSN
MDDR_ODT	IFO	DRAM ODT
MDDR_RAS_N	IFO	DRAM RASN
MDDR_RESET_N	IFO	Toe seti DRAM mo DDR3. Le amana'ia lenei faailo mo LPDDR ma DDR2 Interfaces. Faailoga e le faʻaaogaina mo LPDDR ma DDR2 Interfaces.
MDDR_WE_N	IFO	DRAM WEN
MDDR_ADDR[15:0]	IFO	Dram Address bits
MDDR_BA[2:0]	IFO	tuatusi Dram Bank
MDDR_DM_RDQS ([3:0]/[1:0]/[0])	INOUT	Dram Data Mask
MDDR_DQS ([3:0]/[1:0]/[0])	INOUT	Dram Data Strobe Input / Output - Itu P
MDDR_DQS_N ([3:0]/[1:0]/[0])	INOUT	Dram Data Strobe Input/Autput – N Itu
MDDR_DQ ([31:0]/[15:0]/[7:0])	INOUT	DRAM Fa'amatalaga Fa'amatalaga/Auga
MDDR_DQS_TMATCH_0_IN	IN	FIFO i le faailo
MDDR_DQS_TMATCH_0_OUT	IFO	FIFO out signal
MDDR_DQS_TMATCH_1_IN	IN	FIFO i le faailo (32-bit na'o)
MDDR_DQS_TMATCH_1_OUT	IFO	FIFO out signal (na'o le 32-bit)
MDDR_DM_RDQS_ECC	INOUT	Dram ECC Fa'amatalaga Mask
MDDR_DQS_ECC	INOUT	Dram ECC Fa'amatalaga Strobe Input/Autput – P Itu
MDDR_DQS_ECC_N	INOUT	Dram ECC Fa'amatalaga Strobe Input/Autput – N Itu
MDDR_DQ_ECC ([3:0]/[1:0]/[0])	INOUT	DRAM ECC Faʻamatalaga Faʻamatalaga / Faʻamatalaga
MDDR_DQS_TMATCH_ECC_IN	IN	ECC FIFO i le faailo
MDDR_DQS_TMATCH_ECC_OUT	IFO	ECC FIFO i fafo faailoilo (32-bit na'o)

Fa'aaliga: Ole lautele ole uafu mo nisi uafu e suia e fuafua ile filifiliga ole lautele ole PHY. O le fa'ailoga “[a:0]/ [b:0]/[c:0]” o lo'o fa'aaogaina e fa'ailoa ai ia ports, lea o le “[a:0]” e fa'asino i le lautele o le uafu pe a filifilia se 32-bit PHY lautele. , “[b:0]” e fetaui ma le 16-bit PHY lautele, ma “[c:0]” e fetaui ma le 8-bit PHY lautele.

Fabry Master AXI Bus Interface
Fuafuaga 3-2 • Faiga Fa'akomepiuta AXI Bus Interface

Igoa o le Taulaga	Fa'atonuga	Fa'amatalaga
DDR_AXI_S_AWREADY	IFO	Tusi le tuatusi ua saunia
DDR_AXI_S_WREADY	IFO	Tusi le tuatusi ua saunia
DDR_AXI_S_BID[3:0]	IFO	ID Tali
DDR_AXI_S_BRESP[1:0]	IFO	Tusi le tali
DDR_AXI_S_BVALID	IFO	Tusi tali sa'o
DDR_AXI_S_ARREADY	IFO	Faitau le tuatusi ua saunia
DDR_AXI_S_RID[3:0]	IFO	Faitau ID Tag
DDR_AXI_S_RRESP[1:0]	IFO	Faitau Tali
DDR_AXI_S_RDATA[63:0]	IFO	Faitau fa'amaumauga
DDR_AXI_S_RLAST	IFO	Faitau Mulimuli Ole fa'ailoga lea e fa'ailoa ai le fesiitaiga mulimuli ile faitau fa'amata
DDR_AXI_S_RVALID	IFO	Faitau tuatusi aoga
DDR_AXI_S_AWID[3:0]	IN	Tusi le ID ID
DDR_AXI_S_AWADDR[31:0]	IN	Tusi le tuatusi
DDR_AXI_S_AWLEN[3:0]	IN	Pa'u umi
DDR_AXI_S_AWSIZE[1:0]	IN	Tele pa'u
DDR_AXI_S_AWBURST[1:0]	IN	Ituaiga pa
DDR_AXI_S_AWLOCK[1:0]	IN	Loka ituaiga O lenei faailo e maua ai faʻamatalaga faaopoopo e uiga i uiga atomika o le fesiitaiga
DDR_AXI_S_AWVALID	IN	Tusi le tuatusi aoga
DDR_AXI_S_WID[3:0]	IN	Tusi ID ID tag
DDR_AXI_S_WDATA[63:0]	IN	Tusi fa'amaumauga
DDR_AXI_S_WSTRB[7:0]	IN	Tusi strobes
DDR_AXI_S_WLAST	IN	Tusi mulimuli
DDR_AXI_S_WVALID	IN	Tusi aoga
DDR_AXI_S_BREADY	IN	Tusi saunia
DDR_AXI_S_ARID[3:0]	IN	Faitau tuatusi ID
DDR_AXI_S_ARADDR[31:0]	IN	Faitau le tuatusi
DDR_AXI_S_ARLEN[3:0]	IN	Pa'u umi
DDR_AXI_S_ARSIZE[1:0]	IN	Tele pa'u
DDR_AXI_S_ARBURST[1:0]	IN	Ituaiga pa
DDR_AXI_S_ARLOCK[1:0]	IN	Ituaiga Loka
DDR_AXI_S_ARVALID	IN	Faitau tuatusi aoga
DDR_AXI_S_RREADY	IN	Faitau le tuatusi ua saunia

Fuafuaga 3-2 • Ie Matai AXI Bus Interface (fa'aauau)

Igoa o le Taulaga	Fa'atonuga	Fa'amatalaga
DDR_AXI_S_CORE_RESET_N	IN	MDDR Global Reset
DDR_AXI_S_RMW	IN	Fa'ailoa mai pe aoga uma paita ole laina 64 bit mo pa'o uma ole AXI. 0: Faʻailoa mai o paita uma i paʻu uma e aoga i le paʻu ma e tatau i le pule ona le mafai ona tusia ni poloaiga. 1: Fa'ailoa mai o nisi bytes e le aoga ma e tatau ona fa'aletonu le pule i tulafono a le RMW O lo'o fa'avasegaina ose fa'ailoga AXI tusitusi alalaupapa alalaupapa ma e aoga i le fa'ailoga AWVALID. Na'o le fa'aaogaina pe a mafai ECC.

Fabry Master AHB0 Bus Interface
Fuafuaga 3-3 • Faiga Fa'aa'e AHB0 Bus Interface

Igoa o le Taulaga	Fa'atonuga	Fa'amatalaga
DDR_AHB0_SHREADYOUT	IFO	Sauni le pologa AHBL - Pe a maualuga mo se tusi e faʻaalia ai ua sauni le MDDR e talia faʻamatalaga ma pe a maualuga mo se faitau e faʻaalia ai o faʻamatalaga e aoga
DDR_AHB0_SHRESP	IFO	Tulaga tali a le AHBL - A faʻaoso maualuga i le faaiuga o se fefaʻatauaiga e faʻaalia ai ua maeʻa le fefaʻatauaiga i mea sese. A fa'amaulalo i le fa'ai'uga o se fefa'ataua'iga e fa'ailoa mai ai ua mae'a manuia le fefa'ataua'iga.
DDR_AHB0_SHRDATA[31:0]	IFO	AHBL faitau faʻamatalaga - Faitau faʻamatalaga mai le pologa MDDR i le matai ie
DDR_AHB0_SHSEL	IN	Filifilia pologa AHBL - Pe a faʻamaonia, o le MDDR o le pologa AHBL filifilia nei i luga o le ie AHB pasi.
DDR_AHB0_SHADDR[31:0]	IN	tuatusi AHBL - tuatusi byte ile fa'aoga AHBL
DDR_AHB0_SHBURST[2:0]	IN	AHBL Pa'u Umi
DDR_AHB0_SHSIZE[1:0]	IN	AHBL fesiitaiga tele - Faʻaalia le tele o le fesiitaiga o loʻo iai nei (8/16/32 byte fefaʻatauaiga naʻo)
DDR_AHB0_SHTRANS[1:0]	IN	AHBL ituaiga faʻafeiloaʻiga - Faʻaalia le ituaiga fesiitaiga o le fefaʻatauaiga o loʻo iai nei
DDR_AHB0_SHMASTLOCK	IN	loka AHBL - Pe a faʻamaonia o le fesiitaiga o loʻo iai nei o se vaega o se fefaʻatauaiga loka
DDR_AHB0_SHWRITE	IN	Tusi AHBL - Pe a maualuga e faʻaalia o le fefaʻatauaiga o loʻo iai nei o se tusi. Pe a maualalo e faʻaalia ai o le fefaʻatauaiga o loʻo iai nei o se faitau
DDR_AHB0_S_HREADY	IN	AHBL sauni - A maualuga, faʻaalia ua sauni le MDDR e talia se fefaʻatauaiga fou
DDR_AHB0_S_HWDATA[31:0]	IN	AHBL tusi fa'amaumauga - Tusi fa'amaumauga mai le matai ie i le MDDR

Fabry Master AHB1 Bus Interface
Fuafuaga 3-4 • Faiga Fa'aa'e AHB1 Bus Interface

Igoa o le Taulaga	Fa'atonuga	Fa'amatalaga
DDR_AHB1_SHREADYOUT	IFO	Sauni le pologa AHBL - Pe a maualuga mo se tusi e faʻaalia ai ua sauni le MDDR e talia faʻamatalaga ma pe a maualuga mo se faitau e faʻaalia ai o faʻamatalaga e aoga
DDR_AHB1_SHRESP	IFO	Tulaga tali a le AHBL - A faʻaoso maualuga i le faaiuga o se fefaʻatauaiga e faʻaalia ai ua maeʻa le fefaʻatauaiga i mea sese. A fa'amaulalo i le fa'ai'uga o se fefa'ataua'iga e fa'ailoa mai ai ua mae'a manuia le fefa'ataua'iga.
DDR_AHB1_SHRDATA[31:0]	IFO	AHBL faitau faʻamatalaga - Faitau faʻamatalaga mai le pologa MDDR i le matai ie
DDR_AHB1_SHSEL	IN	Filifilia pologa AHBL - Pe a faʻamaonia, o le MDDR o le pologa AHBL filifilia nei i luga o le ie AHB pasi.
DDR_AHB1_SHADDR[31:0]	IN	tuatusi AHBL - tuatusi byte ile fa'aoga AHBL
DDR_AHB1_SHBURST[2:0]	IN	AHBL Pa'u Umi
DDR_AHB1_SHSIZE[1:0]	IN	AHBL fesiitaiga tele - Faʻaalia le tele o le fesiitaiga o loʻo iai nei (8/16/32 byte fefaʻatauaiga naʻo)
DDR_AHB1_SHTRANS[1:0]	IN	AHBL ituaiga faʻafeiloaʻiga - Faʻaalia le ituaiga fesiitaiga o le fefaʻatauaiga o loʻo iai nei
DDR_AHB1_SHMASTLOCK	IN	loka AHBL - Pe a faʻamaonia o le fesiitaiga o loʻo iai nei o se vaega o se fefaʻatauaiga loka
DDR_AHB1_SHWRITE	IN	Tusi AHBL - Pe a maualuga e faʻaalia o le fefaʻatauaiga o loʻo iai nei o se tusi. Pe a maualalo e faʻaalia ai o le fefaʻatauaiga o loʻo iai nei o se faitau.
DDR_AHB1_SHREADY	IN	AHBL sauni - A maualuga, faʻaalia ua sauni le MDDR e talia se fefaʻatauaiga fou
DDR_AHB1_SHWDATA[31:0]	IN	AHBL tusi fa'amaumauga - Tusi fa'amaumauga mai le matai ie i le MDDR

Fa'amama le Manatu Pule Fa'apena AXI Bus Interface
Fuafua 3-5 • Fa'atonu Fa'atonu Fa'alemafaufau Fa'aleaogaina AXI Bus Interface

Igoa o le Taulaga	Fa'atonuga	Fa'amatalaga
SMC_AXI_M_WLAST	IFO	Tusi mulimuli
SMC_AXI_M_WVALID	IFO	Tusi aoga
SMC_AXI_M_AWLEN[3:0]	IFO	Pa'u umi
SMC_AXI_M_AWBURST[1:0]	IFO	Ituaiga pa
SMC_AXI_M_BREADY	IFO	Sauni tali
SMC_AXI_M_AWVALID	IFO	Tusi le tuatusi e aoga
SMC_AXI_M_AWID[3:0]	IFO	Tusi le ID ID
SMC_AXI_M_WDATA[63:0]	IFO	Tusi Faamatalaga
SMC_AXI_M_ARVALID	IFO	Faitau tuatusi aoga
SMC_AXI_M_WID[3:0]	IFO	Tusi ID ID tag
SMC_AXI_M_WSTRB[7:0]	IFO	Tusi strobes
SMC_AXI_M_ARID[3:0]	IFO	Faitau tuatusi ID
SMC_AXI_M_ARADDR[31:0]	IFO	Faitau le tuatusi
SMC_AXI_M_ARLEN[3:0]	IFO	Pa'u umi
SMC_AXI_M_ARSIZE[1:0]	IFO	Tele pa'u
SMC_AXI_M_ARBURST[1:0]	IFO	Ituaiga pa
SMC_AXI_M_AWADDR[31:0]	IFO	Tusi le tuatusi
SMC_AXI_M_RREADY	IFO	Faitau le tuatusi ua saunia
SMC_AXI_M_AWSIZE[1:0]	IFO	Tele pa'u
SMC_AXI_M_AWLOCK[1:0]	IFO	Loka ituaiga O lenei faailo e maua ai faʻamatalaga faaopoopo e uiga i uiga atomika o le fesiitaiga
SMC_AXI_M_ARLOCK[1:0]	IFO	Ituaiga Loka
SMC_AXI_M_BID[3:0]	IN	ID Tali
SMC_AXI_M_RID[3:0]	IN	Faitau ID Tag
SMC_AXI_M_RRESP[1:0]	IN	Faitau Tali
SMC_AXI_M_BRESP[1:0]	IN	Tusi le tali
SMC_AXI_M_AWREADY	IN	Tusi le tuatusi ua saunia
SMC_AXI_M_RDATA[63:0]	IN	Faitau Faamatalaga
SMC_AXI_M_WREADY	IN	Tusi saunia
SMC_AXI_M_BVALID	IN	Tusi tali sa'o
SMC_AXI_M_ARREADY	IN	Faitau le tuatusi ua saunia
SMC_AXI_M_RLAST	IN	Faitau Mulimuli Ole fa'ailoga lea e fa'ailoa ai le fesiitaiga mulimuli ile faitau fa'amata
SMC_AXI_M_RVALID	IN	Faitau Fa'amaonia

Faiga Fa'atonu Fa'atonu AHB0 Feso'ota'iga Pasi
Fuafua 3-6 • Fa'atonu Fa'atonu Mana'oga Fa'aleaogaina AHB0 Bus Interface

Igoa o le Taulaga	Fa'atonuga	Fa'amatalaga
SMC_AHB_M_HBURST[1:0]	IFO	AHBL Pa'u Umi
SMC_AHB_M_HTRANS[1:0]	IFO	AHBL ituaiga faʻafeiloaʻiga - Faʻaalia le ituaiga fesiitaiga o le fefaʻatauaiga o loʻo iai nei.
SMC_AHB_M_HMASTLOCK	IFO	loka AHBL - Pe a faʻamaonia o le fesiitaiga o loʻo iai nei o se vaega o se fefaʻatauaiga loka
SMC_AHB_M_HWRITE	IFO	Tusi AHBL - Pe a maualuga e faʻaalia ai o le fefaʻatauaiga o loʻo iai nei o se tusi. Pe a maualalo e faʻaalia ai o le fefaʻatauaiga o loʻo iai nei o se faitau
SMC_AHB_M_HSIZE[1:0]	IFO	AHBL fesiitaiga tele - Faʻaalia le tele o le fesiitaiga o loʻo iai nei (8/16/32 byte fefaʻatauaiga naʻo)
SMC_AHB_M_HWDATA[31:0]	IFO	AHBL tusi fa'amaumauga - Tusi fa'amaumauga mai le MSS matai ile ie Soft Memory Controller
SMC_AHB_M_HADDR[31:0]	IFO	tuatusi AHBL - tuatusi byte ile fa'aoga AHBL
SMC_AHB_M_HRESP	IN	Tulaga tali a le AHBL - A faʻaoso maualuga i le faaiuga o se fefaʻatauaiga e faʻaalia ai ua maeʻa le fefaʻatauaiga i mea sese. A fa'amaulalo i le fa'ai'uga o se fefa'ataua'iga e fa'ailoa mai ai ua mae'a manuia le fefa'ataua'iga
SMC_AHB_M_HRDATA[31:0]	IN	AHBL faitau faʻamatalaga - Faitau faʻamatalaga mai le ie Soft Memory Controller i le MSS master
SMC_AHB_M_HREADY	IN	AHBL sauni - Maualuga fa'ailoa mai o le pasi AHBL ua sauni e talia se fefa'atauaiga fou

Lagolago oloa

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Asiasi About Us mo lisi o ofisa fa'atau ma feso'ota'iga fa'apisinisi.
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E uiga i Microsemi
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Microsemi SmartFusion2 MSS DDR Pule Fa'atonu [pdf] Taiala mo Tagata Fa'aoga SmartFusion2 MSS DDR Pule Fa'atonu, SmartFusion2 MSS, DDR Pule Fa'atonu, Pule Fa'atonu

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