Intel LOGOInterlaken (2. iran) Intel ®
Agilex™ FPGA IP Oniru Example
Itọsọna olumulo

Awọn akoonu tọju
1 Quick Bẹrẹ Itọsọna
2 Apẹrẹ Example Apejuwe
3 Interlaken (2nd generation) Intel Agilex FPGA IP Design Eksample User Itọsọna Archives
4 Itan Atunyẹwo Iwe-ipamọ fun Interlaken (Iran keji) Intel Agilex FPGA IP Design Example User Itọsọna
5 Awọn iwe aṣẹ / Awọn orisun
5.1 Awọn itọkasi
6 jẹmọ Posts

Quick Bẹrẹ Itọsọna

Interlaken (Iran keji) FPGA IP mojuto n pese bench idanwo kikopa ati apẹrẹ ohun elo kan tẹlẹample ti o atilẹyin akopo ati hardware igbeyewo. Nigbati o ba ṣe ina apẹrẹ example, paramita olootu laifọwọyi ṣẹda awọn files pataki lati ṣe simulate, ṣajọ, ati idanwo apẹrẹ ni hardware. Apẹrẹ example jẹ tun wa fun Interlaken Look-side ẹya-ara.
Awọn testbench ati oniru example ṣe atilẹyin NRZ ati ipo PAM4 fun awọn ẹrọ E-tile. Interlaken (Iran keji) FPGA IP mojuto ṣe ipilẹṣẹ apẹrẹ examples fun gbogbo awọn akojọpọ atilẹyin ti nọmba awọn ọna ati awọn oṣuwọn data.

Nọmba 1. Awọn Igbesẹ Idagbasoke fun Oniru Exampleintel Interlaken 2nd generation Agilex FPGA IP Design Eksample - ORIKI 1

Interlaken (2nd generation) IP mojuto oniru example ṣe atilẹyin awọn ẹya wọnyi:

  • Ti abẹnu TX to RX ni tẹlentẹle loopback mode
  • Laifọwọyi ṣe ipilẹṣẹ awọn apo-iwe iwọn ti o wa titi
  • Awọn agbara iṣayẹwo idii ipilẹ
  • Agbara lati lo System Console lati tun apẹrẹ fun idi idanwo tun-ṣe
  • PMA aṣamubadọgba

Ṣe nọmba 2. Atọka Dina ti ipele giga fun Interlaken (2nd generation) Oniru Exampleintel Interlaken 2nd generation Agilex FPGA IP Design Eksample - ORIKI 2

Alaye ti o jọmọ

  • Interlaken (2. iran) FPGA IP Itọsọna olumulo
  • Interlaken (2. iran) Intel FPGA IP Awọn akọsilẹ Tu

1.1. Hardware ati Software Awọn ibeere
Lati ṣe idanwo exampFun apẹrẹ, lo hardware ati sọfitiwia atẹle:

  • Ẹya sọfitiwia Intel® Prime Pro Edition 21.3
  • Console System
  • Awọn simulators atilẹyin:
    - Siemens * EDA ModelSim* SE tabi QuestaSim *
    - Afoyemọ * VCS*
    - Cadence* Xcelium*
  • Intel Agilex® Quartus™ F-Series Transceiver-SoC Development Kit (AGFB014R24A2E2V)

Alaye ti o jọmọ
Intel Agilex F-Series Transceiver-SoC Development Apo olumulo Itọsọna
1.2. Ilana Ilana
Interlaken (2nd generation) IP mojuto oniru example file awọn ilana ni awọn wọnyi ti ipilẹṣẹ files fun apẹrẹ example.
olusin 3. Ilana Ilana ti ipilẹṣẹ Interlaken (2nd generation) Example Apẹrẹ

intel Interlaken 2nd generation Agilex FPGA IP Design Eksample - ORIKI 3

Iṣeto ni hardware, kikopa, ati idanwo files wa ni be niample_installation_dir>/uflex_ilk_0_example_apẹrẹ.
Table 1. Interlaken (2. iran) IP mojuto Hardware Design Eksample File Awọn apejuwe
Awọn wọnyi files wa ninuample_installation_dir>/uflex_ilk_0_example_design/ example_design / kuotisi liana.

File Awọn orukọ Apejuwe
example_design.qpf Intel Quartus NOMBA ise agbese file.
example_design.qsf Intel Quartus NOMBA eto ise agbese file
example_design.sdc jtag_timing_template.sdc Synopsys Design Idiwọn file. O le daakọ ati yipada fun apẹrẹ tirẹ.
sysconsole_testbench.tcl Akọkọ file fun wiwọle System Console

Table 2. Interlaken (2. iran) IP mojuto Testbench File Apejuwe
Eyi file jẹ ninu awọnample_installation_dir>/uflex_ilk_0_example_design/ example_design / rtl liana.

File Oruko Apejuwe
oke_tb.sv Igbeyewo ipele oke file.

Table 3. nterlaken (2. iran) IP mojuto Testbench awọn iwe afọwọkọ
Awọn wọnyi files wa ninuample_installation_dir>/uflex_ilk_0_example_design/ example_design / testbench liana.

File Oruko Apejuwe
vcstest.sh Iwe afọwọkọ VCS lati ṣiṣẹ testbench.
vlog_pro.ṣe Awọn ModelSim SE tabi QuestaSim iwe afọwọkọ lati ṣiṣe awọn testbench.
xcelium.sh Iwe afọwọkọ Xcelium lati ṣiṣẹ testbench.

1.3. Hardware Design Example irinše
Awọn example oniru so eto ati PLL itọkasi asaju ati awọn ti a beere oniru irinše. Awọn example oniru configures IP mojuto ni ti abẹnu loopback mode ati ki o gbogbo awọn apo-iwe lori IP mojuto TX olumulo data ni wiwo. IP mojuto rán awọn wọnyi awọn apo-iwe lori awọn ti abẹnu loopback ona nipasẹ awọn transceiver.
Lẹhin ti olugba IP mojuto gba awọn apo-iwe lori ọna loopback, o ṣe ilana awọn apo-iwe Interlaken ati gbejade wọn lori wiwo gbigbe data olumulo RX. Awọn example oniru sọwedowo wipe awọn apo-iwe gba ati ki o zqwq baramu.
Awọn hardware example oniru pẹlu ita PLLs. O le ṣayẹwo ọrọ ti o han gbangba files si view sampkoodu le ṣe imuse ọna kan ti o ṣeeṣe lati so awọn PLLs ita si Interlaken (Iran keji) FPGA IP.
Interlaken (2nd generation) hardware oniru example pẹlu awọn eroja wọnyi:

  1. Interlaken (2. iran) FPGA IP
  2. Packet monomono ati Packet Checker
  3. JTAG oludari ti o ibasọrọ pẹlu System Console. O ṣe ibasọrọ pẹlu ọgbọn alabara nipasẹ ẹrọ Console System.

olusin 4. Interlaken (2nd generation) Hardware Design Eksample High Ipele Àkọsílẹ aworan atọka fun E-tile NRZ Ipo Iyatọintel Interlaken 2nd generation Agilex FPGA IP Design Eksample - ORIKI 5

Interlaken (2nd generation) hardware oniru example ti o fojusi awọn iyatọ ipo E-tile PAM4 nilo aago mac_clkin afikun ti IO PLL ṣe ipilẹṣẹ. PLL yii gbọdọ lo aago itọka kanna ti o wakọ pll_ref_clk.

olusin 5. Interlaken (2nd generation) Hardware Design Eksample Ipele giga
Dẹkun aworan atọka fun E-tile PAM4 Ipo Iyatọintel Interlaken 2nd generation Agilex FPGA IP Design Eksample - ORIKI 4

Fun awọn iyatọ ipo E-tile PAM4, nigbati o ba mu awọn ikanni transceiver ti a ko lo pamọ fun paramita PAM4, afikun ibudo aago itọkasi ni afikun (pll_ref_clk [1]). Yi ibudo gbọdọ wa ni ìṣó ni kanna igbohunsafẹfẹ bi telẹ ni IP paramita olootu (Reference aago igbohunsafẹfẹ fun dabo awọn ikanni). Ṣetọju awọn ikanni transceiver ti ko lo fun PAM4 jẹ iyan. PIN ati awọn ihamọ ti o jọmọ ti a sọtọ si aago yii han ni QSF nigbati o yan Intel Stratix® 10 tabi ohun elo idagbasoke Intel Agilex fun iran apẹrẹ.
Fun apẹrẹ example kikopa, testbench nigbagbogbo asọye kanna igbohunsafẹfẹ fun pll_ref_clk[0] ati pll_ref_clk[1].
Alaye ti o jọmọ
Intel Agilex F-Series Transceiver-SoC Development Apo olumulo Itọsọna
1.4. Ti o npese awọn Design

olusin 6. Ilanaintel Interlaken 2nd generation Agilex FPGA IP Design Eksample - ORIKI 6

Tẹle awọn igbesẹ wọnyi lati ṣe ipilẹṣẹ hardware example apẹrẹ ati testbench:

  1. Ninu sọfitiwia Intel Quartus Prime Pro Edition, tẹ File ➤ Oluṣeto Iṣẹ Tuntun lati ṣẹda iṣẹ akanṣe Intel Quartus Prime tuntun, tabi tẹ File ➤ Ṣii Project lati ṣii iṣẹ Intel Quartus Prime ti o wa tẹlẹ. Oluṣeto naa ta ọ lati pato ẹrọ kan.
  2. Pato ẹbi ẹrọ Agilex ki o yan ẹrọ fun apẹrẹ rẹ.
  3. Ninu Katalogi IP, wa ati tẹ Interlaken lẹẹmeji (Iran keji) Intel FPGA IP. Ferese Iyatọ IP Tuntun yoo han.
  4. Pato orukọ ipele oke kan fun aṣa IP iyatọ rẹ. Olootu paramita n fipamọ awọn eto iyatọ IP ni a file ti a npè ni .ip.
  5. Tẹ O DARA. Olootu paramita yoo han.
    Aworan 7. Eksample Design Tab ni Interlaken (2. iran) Intel FPGA IP paramita Olootuintel Interlaken 2nd generation Agilex FPGA IP Design Eksample - ORIKI 7
  6. Lori IP taabu, pato awọn paramita fun iyatọ ipilẹ IP rẹ.
  7. Lori taabu Adaptation PMA, pato awọn paramita aṣamubadọgba PMA ti o ba gbero lati lo adaṣe PMA fun awọn iyatọ ẹrọ E-tile rẹ.
    Igbese yii jẹ iyan:
    • Yan Muu aṣayan IP rirọ fifuye aṣamubadọgba.
    Akiyesi: O gbọdọ mu aṣayan Yiyan PHY Native PHY Debug Master Endpoint (NPDME) ṣiṣẹ lori taabu IP nigbati aṣamubadọgba PMA ti ṣiṣẹ.
    • Yan tito aṣamubadọgba PMA fun aṣamubadọgba PMA Yan paramita.
    Tẹ Iṣagbejade Adaptation PMA lati ṣajọpọ ibẹrẹ ati awọn paramita isọdi igbagbogbo.
    • Pato nọmba awọn atunto PMA lati ṣe atilẹyin nigbati ọpọlọpọ awọn atunto PMA ṣiṣẹ ni lilo Nọmba ti paramita iṣeto PMA.
    • Yan iru iṣeto PMA wo lati ṣajọpọ tabi fipamọ nipa lilo Yan iṣeto PMA kan lati ṣaja tabi tọju.
    • Tẹ Iṣatunṣe Fifuye lati iṣeto PMA ti a yan lati gbe awọn eto iṣeto PMA ti o yan.
    Fun alaye diẹ ẹ sii nipa awọn paramita isọdidọgba PMA, tọka si Itọsọna olumulo E-tile Transceiver PHY.
  8. Lori Examptaabu Oniru, yan aṣayan Simulation lati ṣe ina testbench, ki o yan aṣayan Synthesis lati ṣe ipilẹṣẹ ohun elo example apẹrẹ.
    Akiyesi: O gbọdọ yan o kere ju ọkan ninu awọn aṣayan Simulation tabi Synthesis ṣe ipilẹṣẹ Example Apẹrẹ Files.
  9. Fun Ọna kika HDL ti ipilẹṣẹ, Verilog nikan wa.
  10. Fun Apo Idagbasoke Àkọlé yan aṣayan ti o yẹ.
    Akiyesi: Aṣayan Intel Agilex F-Series Transceiver SoC Development Apo wa nikan nigbati iṣẹ akanṣe rẹ ṣe pato orukọ ẹrọ Intel Agilex ti o bẹrẹ pẹlu AGFA012 tabi AGFA014. Nigbati o ba yan aṣayan Apo Idagbasoke, awọn iṣẹ iyansilẹ pin ti ṣeto ni ibamu si awọn ẹya ara ẹrọ Intel Agilex Development Kit AGFB014R24A2E2V ati pe o le yatọ si ẹrọ ti o yan. Ti o ba pinnu lati ṣe idanwo apẹrẹ lori ohun elo lori PCB ti o yatọ, yan Ko si aṣayan kit idagbasoke ati ṣe awọn iṣẹ iyansilẹ pin ti o yẹ ni .qsf file.
  11. Tẹ ina Example Design. Awọn Yan Example Design Directory window han.
  12. Ti o ba fẹ yi awọn oniru exampọna itọsọna tabi orukọ lati awọn aṣiṣe ti o han (uflex_ilk_0_example_design), lọ kiri si ọna tuntun ki o tẹ apẹrẹ tuntun example liana orukọ.
  13. Tẹ O DARA.

Alaye ti o jọmọ

1.5. Simulating awọn Oniru Example Testbench
Tọkasi Interlaken (2nd generation) Hardware Design Example Idilọwọ Ipele giga fun E-tile Awọn iyatọ Ipo NRZ ati Interlaken (Iran 2nd) Apẹrẹ Hardware Example Ipele Ipele giga fun E-tile PAM4 Ipo Awọn iyatọ dina awọn aworan atọka ti testbench kikopa.

olusin 8. Ilanaintel Interlaken 2nd generation Agilex FPGA IP Design Eksample - ORIKI 8

Tẹle awọn igbesẹ wọnyi lati ṣe adaṣe testbench:

  1. Ni aṣẹ aṣẹ, yipada si iwe ilana kikopa testbench. Awọn liana niample_installation_dir>/ example_design / testbench fun Intel Agilex awọn ẹrọ.
  2. Ṣiṣe awọn iwe afọwọkọ kikopa fun atilẹyin iṣeṣiro ti o fẹ. Awọn akosile akopọ ati ki o nṣiṣẹ testbench ni labeabo. Iwe afọwọkọ rẹ yẹ ki o ṣayẹwo pe SOP ati awọn iṣiro EOP baramu lẹhin ti kikopa ti pari. Tọkasi tabili Awọn igbesẹ lati Ṣiṣe Simulation.
    Table 4. Igbesẹ lati Ṣiṣe Simulation
    Simulator Awọn ilana
    ModelSim SE tabi QuestaSim Ninu laini aṣẹ, tẹ -do vlog_pro.do. Ti o ba fẹ lati ṣe adaṣe lai mu ModelSim GUI soke, tẹ vsim -c -do vlog_pro.do
    VCS Ninu laini aṣẹ, tẹ sh vcstest.sh
    Xcelium Ninu laini aṣẹ, tẹ sh xcelium.sh
  3. Ṣe itupalẹ awọn abajade. Simulation aṣeyọri kan firanṣẹ ati gba awọn apo-iwe, ati ṣafihan “Idanwo ti kọja”.

Awọn testbench fun apẹrẹ example pari awọn iṣẹ wọnyi:

  • Instantiates awọn Interlaken (2. iran) Intel FPGA IP.
  • Tẹjade ipo PHY.
  • Ṣe ayẹwo amuṣiṣẹpọ metaframe (SYNC_LOCK) ati ọrọ (idinaki) awọn aala (WORD_LOCK).
  • Nduro fun awọn ọna onikaluku lati wa ni titiipa ati titọ.
  • Bẹrẹ gbigbe awọn apo-iwe.
  • Ṣiṣayẹwo awọn iṣiro apo-iwe:
    - CRC24 aṣiṣe
    - Awọn SOPs
    - Awọn EOPs

Awọn atẹle sampIṣẹjade le ṣe afihan ṣiṣe idanwo kikopa aṣeyọri ni ipo Interlaken:
**************************************
ALAYE: Nduro fun awọn ọna lati wa ni ibamu.
Gbogbo awọn ọna olugba ti wa ni ibamu ati pe wọn ti ṣetan lati gba ijabọ.
*******************************************
*******************************************
ALAYE: Bẹrẹ gbigbe awọn apo-iwe
*******************************************
*******************************************
ALAYE: Duro gbigbe awọn apo-iwe duro
*******************************************
*******************************************
ALAYE: Ṣiṣayẹwo awọn iṣiro awọn apo-iwe
*******************************************
Awọn aṣiṣe CRC 24 royin: 0
SOPs ti a gbejade: 100
EOPs ti a gbejade: 100
SOPs gba: 100
EOP ti gba: 100
Nọmba aṣiṣe ECC: 0
*******************************************
ALAYE: Idanwo ti kọja
*******************************************
Akiyesi: The Interlaken oniru example kikopa testbench rán 100 awọn apo-iwe ati ki o gba 100 awọn apo-iwe.
Awọn atẹle sampIṣẹjade le ṣe afihan ṣiṣe idanwo kikopa aṣeyọri ni ipo Iwo-ẹgbẹ Interlaken:
Ṣayẹwo TX ati RX Counter dogba tabi rara.
—————————————————————-
READ_MM: adirẹsi 4000014 = 00000001.
—————————————————————-
De-assert Counter dogba bit.
—————————————————————-
WRITE_MM: adirẹsi 4000001 gba 00000001.
WRITE_MM: adirẹsi 4000001 gba 00000000.
—————————————————————-
RX_SOP COUNTER.
—————————————————————-
READ_MM: adirẹsi 400000c = 0000006a.
—————————————————————-
RX_EOP COUNTER.
READ_MM: adirẹsi 400000d = 0000006a.
—————————————————————-
READ_MM: adirẹsi 4000010 = 00000000.
—————————————————————-
Ifihan Ik Iroyin.
—————————————————————-
0 Aṣiṣe ti a rii
0 CRC24 awọn aṣiṣe royin
106 SOPs ti o ti gbe
106 EOPs ti a firanṣẹ
106 SOPs gba
106 EOP ti gba
—————————————————————-
Pari Simulation
—————————————————————-
Idanwo ti kọja
—————————————————————-
Akiyesi: Nọmba ti awọn apo-iwe (SOPs ati EOPs) yatọ ni ọna kan ni Interlaken Lookside design example kikopa sample jade.
Alaye ti o jọmọ
Hardware Design ExampAwọn ohun elo ni oju-iwe 6
1.6. Iṣakojọpọ ati Ṣiṣeto Oniru Example ni Hardware

olusin 9. Ilanaintel Interlaken 2nd generation Agilex FPGA IP Design Eksample - ORIKI 9

Lati ṣajọ ati ṣiṣe idanwo ifihan lori hardware exampFun apẹrẹ, tẹle awọn igbesẹ wọnyi:

  1. Rii daju hardware example oniru iran jẹ pari.
  2. Ninu sọfitiwia Intel Quartus Prime Pro Edition, ṣii iṣẹ akanṣe Intel Quartus Primeample_installation_dir>/ example_design / kuotisi / example_design.qpf>.
  3. Lori awọn Processing akojọ, tẹ Bẹrẹ akopo.
  4. Lẹhin akojọpọ aṣeyọri, a .sof file wa ninu rẹ pàtó kan liana.
    Tẹle awọn igbesẹ wọnyi lati ṣe eto hardware example ṣe apẹrẹ lori ẹrọ Intel Agilex:
  5. So Intel Agilex F-Series Transceiver-SoC Development Apo si kọnputa agbalejo.
    b. Ṣe ifilọlẹ ohun elo Iṣakoso Aago, eyiti o jẹ apakan ti ohun elo idagbasoke, ati ṣeto awọn igbohunsafẹfẹ tuntun fun apẹẹrẹ apẹrẹ.ample. Ni isalẹ ni eto igbohunsafẹfẹ ninu ohun elo Iṣakoso Aago:
    • Si5338 (U37), CLK1- 100 MHz
    • Si5338 (U36), CLK2- 153.6 MHz
    • Si549 (Y2), OUT- Ṣeto si iye pll_ref_clk (1) fun oniru rẹ ibeere.
    c. Lori awọn Irinṣẹ akojọ, tẹ Programmer.
    d. Ni awọn Programmer, tẹ Hardware Setup.
    e. Yan ẹrọ siseto.
    f. Yan ki o ṣafikun Intel Agilex F-Series Transceiver-SoC Development Apo si eyiti igba Intel Quartus Prime le sopọ.
    g. Rii daju pe Ipo ti ṣeto si JTAG.
    h. Yan ẹrọ Intel Agilex ki o tẹ Fi ẹrọ kun. Awọn pirogirama ṣe afihan aworan atọka Àkọsílẹ ti awọn asopọ laarin awọn ẹrọ lori igbimọ rẹ.
    i. Ni ila pẹlu .sof rẹ, ṣayẹwo apoti fun .sof.
    j. Ṣayẹwo apoti ti o wa ninu iwe Eto / Tunto.
    k. Tẹ Bẹrẹ.

Alaye ti o jọmọ

1.7. Idanwo Oniru Hardware Example
Lẹhin ti o ṣe akopọ Interlaken (2nd generation) Intel FPGA IP mojuto design exampati tunto ẹrọ rẹ, o le lo System Console lati ṣe eto ipilẹ IP ati awọn iforukọsilẹ Native PHY IP mojuto rẹ.
Tẹle awọn igbesẹ wọnyi lati mu Eto Console soke ki o ṣe idanwo apẹrẹ ohun elo example:

  1. Ninu sọfitiwia Intel Quartus Prime Pro Edition, lori akojọ Awọn irinṣẹ, tẹ Awọn irinṣẹ N ṣatunṣe aṣiṣe System ➤ System Console.
  2. Yipada si awọnample_installation_dir> Example_design / hwest liana.
  3. Lati ṣii asopọ si JTAG titunto si, tẹ aṣẹ wọnyi: orisun sysconsole_testbench.tcl
  4. O le tan-an ipo loopback ni tẹlentẹle inu pẹlu apẹẹrẹ apẹẹrẹ atẹleample paṣẹ:
    a. iṣiro: Tẹjade alaye ipo gbogbogbo.
    b. sys_reset: Tun eto naa pada.
    c. loop_on: Tan-an ti abẹnu loopback ni tẹlentẹle.
    d. run_example_design: Nṣiṣẹ awọn oniru Mofiample.
    Akiyesi: O gbọdọ ṣiṣẹ loop_on pipaṣẹ ṣaaju ṣiṣe run_example_design pipaṣẹ.
    Awọn run_example_design nṣiṣẹ awọn aṣẹ wọnyi ni ọkọọkan:
    sys_reset->stat->gen_on->stat-> gen_off.
    Akiyesi: Nigbati o ba yan aṣayan IP rirọ fifuye aṣamubadọgba, run_exampaṣẹ le_design n ṣe isọdọtun aṣamubadọgba akọkọ ni ẹgbẹ RX nipa ṣiṣe pipaṣẹ run_load_PMA_configuration.
  5. O le pa ipo loopback ni tẹlentẹle inu pẹlu apẹẹrẹ apẹẹrẹ atẹleample aṣẹ:
    a. loop_off: Pa ti abẹnu loopback ni tẹlentẹle.
  6. O le ṣe eto ipilẹ IP pẹlu apẹrẹ afikun atẹle atẹleample paṣẹ:
    a. gen_on: Ṣiṣẹ monomono soso.
    b. gen_off: Pa soso monomono.
    c. run_test_loop: Ṣiṣe idanwo fun igba fun E-tile NRZ ati PAM4 awọn iyatọ.
    d. clear_err: Pa gbogbo awọn aṣiṣe aṣiṣe alalepo kuro.
    e. ipo_igbeyewo : Ṣeto idanwo lati ṣiṣẹ ni ipo kan pato.
    f. get_test_mode: Ṣe atẹjade ipo idanwo lọwọlọwọ.
    g. ṣeto_burst_size : Ṣeto iwọn ti nwaye ni awọn baiti.
    h. get_burst_size: Awọn atẹjade ti nwaye iwọn alaye.

Idanwo aṣeyọri n tẹ HW_TEST: ifiranṣẹ PASS. Ni isalẹ ni awọn ibeere ti o kọja fun ṣiṣe idanwo kan:

  • Ko si awọn aṣiṣe fun CRC32, CRC24, ati oluṣayẹwo.
  • Awọn SOPs ti a gbejade ati awọn EOP yẹ ki o baramu pẹlu gbigba.

Awọn atẹle sampIṣẹjade le ṣe afihan ṣiṣe idanwo aṣeyọri ni ipo Interlaken:
ALAYE: ALAYE: Duro ṣiṣẹda awọn idii
=== IROYIN IPO ====
TX KHz: 402813
RX KHz: 402813
Awọn titiipa igbohunsafẹfẹ: 0x0000ff
TX PLL titiipa: 0x000001
Tẹle: 0x00c10f
Rx LOA: 0x000000
Tx LOA: 0x000000
titiipa ọrọ: 0x0000ff
titiipa amuṣiṣẹpọ: 0x0000ff
Awọn aṣiṣe CRC32: 0
Awọn aṣiṣe CRC24: 0
Awọn aṣiṣe oluyẹwo: 0
FIFO aṣiṣe awọn asia: 0x000000
Awọn SOP ti a gbejade: 1087913770
EOP ti a gbejade: 1087913770
Awọn SOP ti gba: 1087913770
EOP ti gba: 1087913770
ECC ṣe atunṣe: 0
Aṣiṣe ECC: 0
O ti kọja iṣẹju 161 lati igba agbara
HW_TEST: ṢE
Idanwo aṣeyọri n tẹ HW_TEST: ifiranṣẹ PASS. Ni isalẹ ni awọn ibeere ti o kọja fun ṣiṣe idanwo kan:

  • Ko si awọn aṣiṣe fun CRC32, CRC24, ati oluṣayẹwo.
  • Awọn SOPs ti a gbejade ati awọn EOP yẹ ki o baramu pẹlu gbigba.

Awọn atẹle sampIṣẹjade le ṣe afihan ṣiṣe idanwo aṣeyọri ni ipo Interlaken Lookside:
ALAYE: ALAYE: Duro ṣiṣẹda awọn idii
=== IROYIN IPO ====
TX KHz: 402813
RX KHz: 402812
Awọn titiipa igbohunsafẹfẹ: 0x000ff
TX PLL titiipa: 0x000001
Tẹle: 0x00c10f
Rx LOA: 0x000000
Tx LOA: 0x000000
titiipa ọrọ: 0x000fff
titiipa amuṣiṣẹpọ: 0x000fff
Awọn aṣiṣe CRC32: 0
Awọn aṣiṣe CRC24: 0
Awọn aṣiṣe oluyẹwo: 0
Awọn SOP ti a gbejade: 461
EOP ti a gbejade: 461
Awọn SOP ti gba: 461
EOP ti gba: 461
O ti kọja iṣẹju 171 lati igba agbara
HW_TEST: ṢE

Apẹrẹ Example Apejuwe

Apẹrẹ example ṣe afihan awọn iṣẹ ṣiṣe ti Interlaken IP mojuto.
Alaye ti o jọmọ
Interlaken (2. iran) FPGA IP Itọsọna olumulo
2.1. Oniru Example Iwa
Lati ṣe idanwo apẹrẹ ni ohun elo, tẹ awọn aṣẹ wọnyi ni Console System ::

  1. Orisun iṣeto file:
    % orisunample>uflex_ilk_0_example_design / apẹẹrẹample_design/hwtest/sysconsole_testbench.tcl
  2. Ṣiṣe idanwo naa:
    % run_example_apẹrẹ
  3. Interlaken (2nd generation) hardware oniru example pari awọn igbesẹ wọnyi:
    a. Tun Interlaken (2nd generation) IP tunto.
    b. Tunto Interlaken (2nd generation) IP ni ti abẹnu loopback mode.
    c. Firanṣẹ ṣiṣan ti awọn apo-iwe Interlaken pẹlu data asọye tẹlẹ ninu fifuye isanwo si wiwo olumulo data gbigbe olumulo TX ti ipilẹ IP.
    d. Ṣayẹwo awọn apo-iwe ti o gba ati ṣe ijabọ ipo naa. Oluyẹwo apo-iwe ti o wa ninu apẹrẹ ohun elo example pese awọn agbara iṣayẹwo idii ipilẹ atẹle wọnyi:
    • Ṣayẹwo pe lẹsẹsẹ soso ti a firanṣẹ jẹ deede.
    • Awọn sọwedowo pe data ti o gba ni ibamu pẹlu awọn iye ti a nireti nipa aridaju mejeeji ibẹrẹ ti pakẹti (SOP) ati ipari awọn idii (EOP) ni ibamu nigba ti data n gbejade ati gbigba.

2.2. Awọn ifihan agbara wiwo
Table 5. Design Example Interface Awọn ifihan agbara

Orukọ Port Itọsọna Ìbú (Bits) Apejuwe
mgmt_clk Iṣawọle 1 titẹ sii aago eto. Igbohunsafẹfẹ aago gbọdọ jẹ 100 MHz.
pll_ref_clk /pll_ref_clk[1:0] (2) Iṣawọle 2-Jan Aago itọkasi Transceiver. Wakọ RX CDR PLL.
Orukọ Port Itọsọna Ìbú (Bits) Apejuwe
pll_ref_clk[1] wa nikan nigbati o ba ṣiṣẹ Fipamọ ajeku
Akiyesi: awọn ikanni transceiver fun PAM4 paramita ni ipo E-tile PAM4 IP awọn iyatọ.
rx_pin Iṣawọle Nọmba awọn ọna PIN olugba SErdES data.
tx_pin Abajade Nọmba awọn ọna Ṣe atagba PIN data SErdES.
rx_pin_n Iṣawọle Nọmba awọn ọna PIN olugba SErdES data.
Ifihan agbara yii wa nikan ni awọn iyatọ ẹrọ ipo E-tile PAM4.
tx_pin_n Abajade Nọmba awọn ọna Ṣe atagba PIN data SErdES.
Ifihan agbara yii wa nikan ni awọn iyatọ ẹrọ ipo E-tile PAM4.
mac_clk_pll_ref Iṣawọle 1 Yi ifihan agbara gbọdọ wa ni ìṣó nipasẹ a PLL ati ki o gbọdọ lo kanna aago orisun ti o iwakọ pll_ref_clk.
Ifihan agbara yii wa nikan ni awọn iyatọ ẹrọ ipo E-tile PAM4.
usr_pb_reset_n Iṣawọle 1 Eto titunto.

Alaye ti o jọmọ
Awọn ifihan agbara wiwo
2.3. Forukọsilẹ Map
Akiyesi:

  • Apẹrẹ ExampAdirẹsi iforukọsilẹ le bẹrẹ pẹlu 0x20 *** lakoko ti adirẹsi iforukọsilẹ IP mojuto Interlaken bẹrẹ pẹlu 0x10 ***.
  • Koodu wiwọle: RO-Ka Nikan, ati RW-Ka/Kọ.
  • System console Say oniru Mofiample forukọsilẹ ati awọn ijabọ ipo idanwo loju iboju.

Table 6. Design Example Forukọsilẹ Map fun Interlaken Design Eksample

Aiṣedeede Oruko Wiwọle Apejuwe
8'h00 Ni ipamọ
8'h01 Ni ipamọ
8'h02 Eto PLL atunto RO Awọn die-die atẹle tọkasi ibeere atunto PLL eto ati mu iye ṣiṣẹ:
• Bit [0] - sys_pll_rst_req
• Bit [1] - sys_pll_rst_en
8'h03 Ona RX ni ibamu RO Tọkasi titete ọna RX.
8'h04 ORO titii pa RO [NUM_LANES–1:0] – Ọrọ (ìdènà) idamọ awọn aala.

(2) Nigbati o ba mu awọn ikanni transceiver ti a ko lo pamọ fun paramita PAM4, afikun ibudo aago itọkasi ni afikun lati tọju ikanni ẹru PAM4 ti ko lo.

Aiṣedeede Oruko Wiwọle Apejuwe
8'h05 Amuṣiṣẹpọ ni titiipa RO [NUM_LANES–1:0] – Amuṣiṣẹpọ Metaframe.
8'h06 - 8'h09 CRC32 aṣiṣe kika RO Tọkasi kika aṣiṣe CRC32.
8'h0A CRC24 aṣiṣe kika RO Tọkasi kika aṣiṣe CRC24.
8'h0B Aponsedanu / Underflow ifihan agbara RO Awọn ipin wọnyi tọkasi:
• Bit [3] – TX ifihan agbara labẹ sisan
• Bit [2] - TX aponsedanu ifihan agbara
• Bit [1] - RX aponsedanu ifihan agbara
8'h0C Iwọn SOP RO Tọkasi awọn nọmba ti SOP.
8'h0D Iwọn EOP RO Tọkasi nọmba ti EOP
8'h0E Iṣiro aṣiṣe RO Tọkasi nọmba awọn aṣiṣe wọnyi:
• Isonu ti titete ona
Ọrọ iṣakoso arufin
• Apẹrẹ fireemu fireemu
Sonu SOP tabi EOP Atọka
8'h0F firanṣẹ_data_mm_clk RW Kọ 1 si bit [0] lati mu ifihan agbara monomono ṣiṣẹ.
8'h10 Aṣiṣe oluyẹwo Tọkasi aṣiṣe oluyẹwo. (Aṣiṣe data SOP, aṣiṣe nọmba ikanni, ati aṣiṣe data PLD)
8'h11 Titiipa PLL eto RO Bit [0] tọkasi itọkasi titiipa PLL.
8'h14 Iye owo ti TX SOP RO Tọkasi nọmba ti SOP ti ipilẹṣẹ nipasẹ monomono soso.
8'h15 Iye owo ti TX EOP RO Tọkasi nọmba ti EOP ti ipilẹṣẹ nipasẹ monomono soso.
8'h16 Pakẹti ti o tẹsiwaju RW Kọ 1 si bit [0] lati jeki awọn soso lemọlemọfún.
8'h39 ECC aṣiṣe kika RO Tọkasi nọmba ti awọn aṣiṣe ECC.
8'h40 ECC ṣatunṣe kika aṣiṣe RO Tọkasi nọmba ti atunse ECC aṣiṣe.

Table 7. Design Example Forukọsilẹ Map fun Interlaken Look-side Design Example
Lo yi Forukọsilẹ map nigba ti o ba se ina awọn oniru Mofiample pẹlu Muu ṣiṣẹ paramita ipo-ẹgbẹ Interlaken ti wa ni titan.

Aiṣedeede Oruko Wiwọle Apejuwe
8'h00 Ni ipamọ
8'h01 Atunto counter RO Kọ 1 si bit [0] lati ko TX ati RX counter dogba bit.
8'h02 Eto PLL atunto RO Awọn die-die atẹle tọkasi ibeere atunto PLL eto ati mu iye ṣiṣẹ:
• Bit [0] - sys_pll_rst_req
• Bit [1] - sys_pll_rst_en
8'h03 Ona RX ni ibamu RO Tọkasi titete ọna RX.
8'h04 ORO titii pa RO [NUM_LANES–1:0] – Ọrọ (ìdènà) idamọ awọn aala.
8'h05 Amuṣiṣẹpọ ni titiipa RO [NUM_LANES–1:0] – Amuṣiṣẹpọ Metaframe.
8'h06 - 8'h09 CRC32 aṣiṣe kika RO Tọkasi kika aṣiṣe CRC32.
8'h0A CRC24 aṣiṣe kika RO Tọkasi kika aṣiṣe CRC24.
Aiṣedeede Oruko Wiwọle Apejuwe
8'h0B Ni ipamọ
8'h0C Iwọn SOP RO Tọkasi awọn nọmba ti SOP.
8'h0D Iwọn EOP RO Tọkasi nọmba ti EOP
8'h0E Iṣiro aṣiṣe RO Tọkasi nọmba awọn aṣiṣe wọnyi:
• Isonu ti titete ona
Ọrọ iṣakoso arufin
• Apẹrẹ fireemu fireemu
Sonu SOP tabi EOP Atọka
8'h0F firanṣẹ_data_mm_clk RW Kọ 1 si bit [0] lati mu ifihan agbara monomono ṣiṣẹ.
8'h10 Aṣiṣe oluyẹwo RO Tọkasi aṣiṣe oluyẹwo. (Aṣiṣe data SOP, aṣiṣe nọmba ikanni, ati aṣiṣe data PLD)
8'h11 Titiipa PLL eto RO Bit [0] tọkasi itọkasi titiipa PLL.
8'h13 Iwọn airi RO Tọkasi nọmba lairi.
8'h14 Iye owo ti TX SOP RO Tọkasi nọmba ti SOP ti ipilẹṣẹ nipasẹ monomono soso.
8'h15 Iye owo ti TX EOP RO Tọkasi nọmba ti EOP ti ipilẹṣẹ nipasẹ monomono soso.
8'h16 Pakẹti ti o tẹsiwaju RO Kọ 1 si bit [0] lati jeki awọn soso lemọlemọfún.
8'h17 TX ati RX counter dogba RW Tọkasi TX ati RX counter jẹ dogba.
8'h23 Mu lairi ṣiṣẹ WO Kọ 1 si bit [0] lati mu wiwọn lairi ṣiṣẹ.
8'h24 Lairi setan RO Tọkasi wiwọn lairi ti ṣetan.

Interlaken (2nd generation) Intel Agilex FPGA IP Design Eksample User Itọsọna Archives

Fun awọn ẹya tuntun ati tẹlẹ ti itọsọna olumulo yii, tọka si awọn Interlaken (2 Iran) Intel Agilex FPGA IP Design Example User Itọsọna HTML version. Yan awọn ti ikede ki o si tẹ Download. Ti IP tabi ẹya sọfitiwia ko ba ṣe akojọ, itọsọna olumulo fun IP iṣaaju tabi ẹya sọfitiwia kan.
Awọn ẹya IP jẹ kanna bi awọn ẹya sọfitiwia Intel Quartus Prime Design Suite to v19.1. Lati Intel Quartus Prime Design Suite sọfitiwia ẹya 19.2 tabi nigbamii, awọn ohun kohun IP ni ero ikede IP tuntun kan.

Itan Atunyẹwo Iwe-ipamọ fun Interlaken (Iran keji) Intel Agilex FPGA IP Design Example User Itọsọna

Ẹya Iwe aṣẹ Intel Quartus NOMBA Version Ẹya IP Awọn iyipada
2022.08.03 21.3 20.0.1 Ṣe atunṣe ẹrọ OPN fun Intel Agilex F-Series Transceiver-SoC Development Kit.
2021.10.04 21.3 20.0.1 Atilẹyin ti a ṣafikun fun simulator QuestaSim.
• Atilẹyin ti a yọ kuro fun simulator NCsim.
2021.02.24 20.4 20.0.1 Alaye ti a ṣafikun nipa titọju ikanni transceiver ti ko lo fun PAM4 ni apakan: Apẹrẹ Hardware Example irinše.
Fi kun pll_ref_clk[1] ifihan agbara apejuwe ni apakan: Awọn ifihan agbara ni wiwo.
2020.12.14 20.4 20.0.0 • Imudojuiwọn sampIṣẹjade idanwo ohun elo fun ipo Interlaken ati ipo wiwo-ẹgbẹ Interlaken ni apakan Idanwo Apẹrẹ Hardware Example.
• Maapu iforukọsilẹ imudojuiwọn fun Interlaken Look-side design example ni apakan Forukọsilẹ Map.
• Ṣafikun awọn igbelewọn ti o kọja fun ṣiṣe idanwo ohun elo aṣeyọri ni apakan Idanwo Apẹrẹ Hardware Example.
2020.10.16 20.2 19.3.0 Aṣẹ ti a ṣe atunṣe lati ṣiṣẹ isọdiwọn aṣamubadọgba akọkọ ni ẹgbẹ RX ni Idanwo Apẹrẹ Hardware Example apakan.
2020.06.22 20.2 19.3.0 • Apẹrẹ example wa fun Interlaken Look- ipo apa.
• Hardware igbeyewo ti awọn oniru example wa fun Intel Agilex ẹrọ iyatọ.
• Aworan ti a fikun: Atọka Idina Ipele giga fun Interlaken (2nd generation) Apẹrẹ Example.
• Ṣe imudojuiwọn awọn apakan wọnyi:
– Hardware ati Software ibeere
- Ilana Ilana
• Ṣatunṣe awọn isiro wọnyi lati ni imudojuiwọn ti o jọmọ Interlaken Look-side:
– olusin: Interlaken (2nd generation) Hardware Design Eksample ga
Ipele Idina aworan fun E-tile NRZ Awọn iyatọ Ipo
– olusin: Interlaken (2nd generation) Hardware Design Eksample Aworan Idina Ipele Giga fun E-tile PAM4 Ipo Awọn iyatọ
• Nọmba imudojuiwọn: IP Parameter Editor.
Alaye ti a ṣafikun nipa awọn eto igbohunsafẹfẹ ninu ohun elo iṣakoso aago ni apakan Iṣakojọpọ ati Ṣiṣeto Apẹrẹ Example ni Hardware.
Ẹya Iwe aṣẹ Intel Quartus NOMBA Version Ẹya IP Awọn iyipada

Awọn abajade ṣiṣe idanwo ti a ṣafikun fun Interlaken Look- yato si ni awọn apakan wọnyi:
– Simulating awọn Oniru Example Testbench
– Idanwo awọn Hardware Design Example
Fikun-un wọnyi awọn ifihan agbara titun ni apakan Awọn ifihan agbara Ni wiwo:
– mgmt_clk
– rx_pin_n
- tx_pin_n
– mac_clk_pll_ref
• Fi kun maapu forukọsilẹ fun Interlaken Look-side design example ni apakan: Forukọsilẹ Map.
2019.09.30 19.3 19.2.1

Clk100 kuro. mgmt_clk n ṣiṣẹ bi aago itọkasi si IO PLL ni atẹle yii:
• olusin: Interlaken (2nd generation) Hardware Design Example High Ipele Àkọsílẹ aworan atọka fun E-tile NRZ Ipo Iyatọ.
• olusin: Interlaken (2nd generation) Hardware Design Example High Ipele Àkọsílẹ aworan atọka fun E-tile PAM4 Ipo Iyatọ.
2019.07.01 19.2 19.2 Itusilẹ akọkọ.

Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn aami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ṣiṣe ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ.
* Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.
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Interlaken (Iran keji) Intel® Agilex™ FPGA IP Design Example User Itọsọna

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Ẹya: 2022.08.03

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