Interlaken (2nd Generation) Intel ®
Agilex™ FPGA IP Design Example
Jagorar Mai Amfani

Jagoran Fara Mai Sauri

Interlaken (2nd Generation) FPGA IP core yana ba da gwajin siminti da ƙirar ƙirar kayan aiki.ampwanda ke goyan bayan haɗawa da gwajin kayan aiki. Lokacin da ka samar da zane exampHar ila yau, editan siga yana ƙirƙirar ta atomatik fileya zama dole don kwaikwaya, tarawa, da gwada ƙira a cikin kayan masarufi. Zane exampLe yana samuwa don fasalin Interlaken Look-side.
The testbench da zane exampLe yana goyan bayan yanayin NRZ da PAM4 don na'urorin E-tile. Interlaken (2nd Generation) FPGA IP core yana haifar da ƙira exampLes don duk haɗin haɗin gwiwar adadin hanyoyi da ƙimar bayanai.

Hoto 1. Matakan Ci gaba don Zane Example

Interlaken (2nd Generation) IP core design example yana goyan bayan fasalulluka masu zuwa:

• TX na ciki zuwa yanayin madauki na RX
• Yana haifar da ƙayyadaddun fakiti masu girman kai ta atomatik
• Asalin damar duba fakiti
• Ikon yin amfani da Console System don sake saita ƙira don manufar sake gwadawa
• daidaitawar PMA

Hoto 2. Tsarin Toshe Babban Matsayi don Interlaken (ƙarni na biyu) Zane Example

Bayanai masu alaƙa

• Interlaken (ƙarni na biyu) FPGA IP Jagorar mai amfani
• Interlaken (ƙarni na biyu) Bayanan Sakin Intel FPGA IP

1.1. Bukatun Hardware da Software
Don gwada tsohonampDon ƙira, yi amfani da hardware da software masu zuwa:

• Intel® Prime Pro Edition software 21.3
• Tsarin Console
• Na'urar kwaikwayo masu goyan baya:
  - Siemens* EDA ModelSim* SE ko QuestaSim*
  - Tambayoyi* VCS*
  - Cadence* Xcelium*
• Intel Agilex® Quartus™ F-Series Transceiver-SoC Development Kit (AGFB014R24A2E2V)

Bayanai masu alaƙa
Intel Agilex F-Series Transceiver-SoC Jagoran Mai Amfani da Kit ɗin Haɓakawa
1.2. Tsarin Jagora
Interlaken (2nd Generation) IP core design example file kundin adireshi ya ƙunshi abubuwan da aka samar files don zane example.
Hoto 3. Tsarin Jagora na Ƙirƙirar Interlaken (ƙarni na biyu) Exampda Design

Tsarin hardware, simulation, da gwaji files suna cikinample_installation_dir>/uflex_ilk_0_example_design.
Tebur 1. Interlaken (2nd Generation) IP Core Hardware Design Example File Bayani
Wadannan files suna cikinample_installation_dir>/uflex_ilk_0_example_design/ example_design/quartus directory.

File Sunaye	Bayani
example_design.qpf	Intel Quartus Prime aikin file.
example_design.qsf	Saitunan ayyukan Intel Quartus Prime file
example_design.sdc jtag_time_template.sdc	Ƙuntataccen Ƙira na Synopsys file. Kuna iya kwafa da gyara don ƙirar ku.
sysconsole_testbench.tcl	Babban file don samun damar System Console

Table 2. Interlaken (2nd Generation) IP Core Testbench File Bayani
Wannan file yana cikinample_installation_dir>/uflex_ilk_0_example_design/ example_design/rtl directory.

File Suna	Bayani
saman_tb.sv	Babban matakin gwajin benci file.

Table 3. nterlaken (2nd Generation) IP Core Testbench Scripts
Wadannan files suna cikinample_installation_dir>/uflex_ilk_0_example_design/ example_design/testbench directory.

File Suna	Bayani
vcstest.sh	Rubutun VCS don gudanar da testbench.
vlog_pro.do	Rubutun ModelSim SE ko QuestaSim don gudanar da gwajin benci.
xcelium.sh	Rubutun Xcelium don gudanar da testbench.

1.3. Tsarin Hardware ExampAbubuwan da aka gyara
The example zane yana haɗa tsarin da agogon tunani na PLL da abubuwan ƙira da ake buƙata. The example zane yana daidaita ainihin IP a cikin yanayin madauki na ciki kuma yana haifar da fakiti akan hanyar sadarwar mai amfani ta IP core TX. Babban IP ɗin yana aika waɗannan fakiti akan hanyar madauki na ciki ta hanyar mai karɓa.
Bayan mai karɓar ainihin IP ɗin ya karɓi fakiti akan hanyar madauki, yana aiwatar da fakitin Interlaken kuma yana watsa su akan hanyar musayar bayanan mai amfani na RX. The example zane yana bincika cewa fakitin da aka karɓa kuma sun watsa wasan.
Hardware example zane ya haɗa da PLLs na waje. Kuna iya bincika madaidaicin rubutu files ku view samplambar da ke aiwatar da hanya ɗaya mai yuwuwa don haɗa PLLs na waje zuwa Interlaken (2nd Generation) FPGA IP.
Interlaken (2nd Generation) ƙirar kayan masarufi example ya ƙunshi abubuwa masu zuwa:

1. Interlaken (2nd Generation) FPGA IP
2. Fakiti Generator da Fakiti Checker
3. JTAG mai sarrafawa wanda ke sadarwa tare da Console System. Kuna sadarwa tare da dabarun abokin ciniki ta hanyar Console System.

Hoto 4. Interlaken (2nd Generation) Hardware Design Example High Level Toshe zane don E-tile NRZ Mode Bambancin

Interlaken (2nd Generation) ƙirar kayan masarufi exampwanda ke hari da bambance-bambancen yanayin E-tile PAM4 yana buƙatar ƙarin mac_clkin agogo wanda IO PLL ke haifarwa. Wannan PLL dole ne yayi amfani da agogon tunani iri ɗaya wanda ke tafiyar da pll_ref_clk.

Hoto 5. Interlaken (2nd Generation) Hardware Design Exampda High Level
Toshe zane don E-tile PAM4 Yanayin Yanayin

Don bambance-bambancen yanayin E-tile PAM4, lokacin da kuka kunna tashoshi masu juyawa marasa amfani don sigar PAM4, ana ƙara ƙarin tashar tashar agogo (pll_ref_clk [1]). Dole ne a motsa wannan tashar jiragen ruwa a mitar guda ɗaya kamar yadda aka ayyana a cikin editan sigar IP (Mitar agogon nuni don tashoshi masu kiyayewa). Kiyaye tashoshi transceiver mara amfani don PAM4 zaɓi ne. Ana iya ganin fil da ƙuntatawa masu alaƙa da aka sanya wa wannan agogon a cikin QSF lokacin da kuka zaɓi Intel Stratix® 10 ko kayan haɓakawa na Intel Agilex don tsara ƙira.
Domin zane example simulation, testbench koyaushe yana bayyana mitar guda ɗaya don pll_ref_clk[0] da pll_ref_clk[1].
Bayanai masu alaƙa
Intel Agilex F-Series Transceiver-SoC Jagoran Mai Amfani da Kit ɗin Haɓakawa
1.4. Samar da Zane

Hoto 6. Tsari

Bi waɗannan matakan don samar da hardware example design da testbench:

1. A cikin Intel Quartus Prime Pro Edition software, danna File ➤ Sabon Project Wizard don ƙirƙirar sabon aikin Intel Quartus Prime, ko danna File ➤ Bude Project don buɗe aikin Intel Quartus Prime da ke gudana. Mayen yana tambayarka don saka na'ura.
2. Ƙayyade dangin Agilex na na'urar kuma zaɓi na'urar don ƙirar ku.
3. A cikin Catalog na IP, gano wuri kuma danna Interlaken (2nd Generation) na Intel FPGA IP sau biyu. Sabuwar taga Bambancin IP yana bayyana.
4. Ƙayyade sunan babban matakin don bambancin IP ɗin ku na al'ada. Editan siga yana adana saitunan bambancin IP a cikin a file mai suna .ip.
5. Danna Ok. Editan siga ya bayyana.
   Hoto 7. ExampShafi Zane a cikin Interlaken (2nd Generation) Intel FPGA IP Parameter Edita
6. A shafin IP, ƙididdige sigogi don ainihin bambancin IP ɗin ku.
7. A kan PMA Adaptation tab, saka sigogin daidaitawar PMA idan kuna shirin amfani da karbuwar PMA don bambancin na'urar E-tile.
   Wannan mataki na zaɓi ne:
   • Zaɓi Kunna nauyin daidaitawa mai laushi zaɓi na IP.
   Lura: Dole ne ku kunna zaɓin Ƙarshen Ƙarshen Mahimman Bayanan PHY na asali (NPDME) akan shafin IP lokacin da aka kunna daidaitawar PMA.
   • Zaɓi saitaccen daidaitawar PMA don daidaitawar PMA Zaɓi siga.
   • Danna Preloading Adaftan PMA don ɗaukar matakan daidaitawa na farko da ci gaba.
   • Ƙayyade adadin daidaitawar PMA don tallafawa lokacin da aka kunna saitunan PMA da yawa ta amfani da Adadin ma'auni na PMA.
   • Zaɓi wane saitin PMA don ɗauka ko adanawa ta amfani da Zaɓi tsarin PMA don lodawa ko adanawa.
   • Danna Load adaptation daga zaɓaɓɓen saitin PMA don ɗaukar saitunan daidaitawar PMA da aka zaɓa.
   Don ƙarin bayani game da sigogin daidaitawa na PMA, koma zuwa E-tile Transceiver PHY Guide User.
8. A kan Example Design tab, zaɓi zaɓin Simulation don samar da testbench, kuma zaɓi zaɓi na Synthesis don samar da tsohon hardware.ampzane.
   Lura: Dole ne ku zaɓi aƙalla ɗaya daga cikin zaɓuɓɓukan Simulation ko Synthesis suna haifar da Exampda Design Files.
9. Don Haɓaka Tsarin HDL, Verilog kawai yana samuwa.
10. Don Kit ɗin Ci gaban Target zaɓi zaɓin da ya dace.
    Lura: Zabin Intel Agilex F-Series Transceiver SoC Development Kit yana samuwa kawai lokacin da aikin ku ya ƙayyade sunan na'urar Intel Agilex wanda ya fara da AGFA012 ko AGFA014. Lokacin da kuka zaɓi zaɓin Kit ɗin Haɓakawa, ana saita ayyukan fil bisa ga lambar ɓangaren na'ura ta Intel Agilex Development Kit AGFB014R24A2E2V kuma yana iya bambanta da na'urar da kuka zaɓa. Idan kuna da niyyar gwada ƙira akan hardware akan PCB daban, zaɓi Babu zaɓin kayan haɓakawa kuma kuyi ayyukan fil ɗin da suka dace a cikin .qsf file.
11. Danna Ƙirƙirar Exampda Design. Zaɓi ExampTagar Zane Directory ya bayyana.
12. Idan kana so ka gyara zane examphanyar directory ko suna daga abubuwan da aka nuna (uflex_ilk_0_example_design), bincika zuwa sabuwar hanya kuma rubuta sabon ƙira exampda directory name.
13. Danna Ok.

Bayanai masu alaƙa

• Intel Agilex F-Series Transceiver-SoC Jagoran Mai Amfani da Kit ɗin Haɓakawa
• E-tile Transceiver PHY Jagoran Mai Amfani

1.5. Simulating da Design Exampda Testbench
Koma zuwa Interlaken (2nd Generation) Hardware Design ExampLe Babban Toshe na E-tile NRZ Mode Bambance-bambancen da kuma Interlaken (2nd Generation) Hardware Design Ex.ampLe Babban Toshe don E-tile PAM4 Yanayin Bambance-bambancen toshe zane-zane na benci na simulation.

Hoto 8. Tsari

Bi waɗannan matakan don kwaikwaya testbench:

1. A saurin umarni, canza zuwa littafin simulations na testbench. Littafin shineample_installation_dir>/ misaliample_design/ testbench don na'urorin Intel Agilex.
2. Gudanar da rubutun simintin don goyan bayan na'urar kwaikwayo na zaɓinku. Rubutun yana tattarawa kuma yana gudanar da testbench a cikin na'urar kwaikwayo. Rubutun ku ya kamata ya duba cewa SOP da EOP ƙidaya sun dace bayan an gama simulation. Koma zuwa teburin Matakai don Gudun Kwaikwayo.
   Tebur 4. Matakan Gudun Kwaikwayo

   Na'urar kwaikwayo	Umarni
   ModelSim SE ko QuestaSim	A cikin layin umarni, rubuta -do vlog_pro.do. Idan kun fi son yin kwaikwaya ba tare da kawo ModelSim GUI ba, rubuta vsim -c -do vlog_pro.do
   VCS	A cikin layin umarni, rubuta sh vcstest.sh
   Xcelium	A cikin layin umarni, rubuta sh xcelium.sh

3. Yi nazarin sakamakon. Simulation mai nasara yana aikawa da karɓar fakiti, kuma yana nuna "GWAJI WUCE".

The testbench ga zane exampya kammala ayyuka masu zuwa:

• Yana haɓaka Interlaken (ƙarni na biyu) Intel FPGA IP.
• Yana buga halin PHY.
• Yana duba aiki tare da metaframe (SYNC_LOCK) da iyakoki (katange) (WORD_LOCK).
• Yana jira a kulle da daidaita wayoyi guda ɗaya.
• Fara watsa fakiti.
• Duba kididdigar fakiti:
  - Kurakurai CRC24
  - SOPs
  - EOPs

Mai zuwa sampLe fitarwa yana kwatanta nasarar gwajin siminti a cikin yanayin Interlaken:
***********************************
BAYANI: Ana jira a daidaita hanyoyin.
Dukkan hanyoyin masu karɓa sun daidaita kuma suna shirye don karɓar zirga-zirga.
***************************************
***************************************
BAYANI: Fara watsa fakiti
***************************************
***************************************
BAYANI: Dakatar da fakitin watsawa
***************************************
***************************************
BAYANI: Duba kididdigar fakiti
***************************************
An ruwaito kurakuran CRC 24: 0
SOPs da aka watsa: 100
EOPs da aka watsa: 100
SOPs sun karɓi: 100
An karɓi EOPs: 100
Kuskuren ECC: 0
***************************************
BAYANI: GWAJI WUTA
***************************************
Lura: The Interlaken zane example simulation testbench yana aika fakiti 100 kuma yana karɓar fakiti 100.
Mai zuwa sampLe fitarwa yana kwatanta nasarar gwajin siminti a cikin yanayin kallon-gefe na Interlaken:
Duba TX da RX Counter daidai ko a'a.
———————————————————-
KARANTA_MM: adireshi 4000014 = 00000001.
———————————————————-
De-ssert Counter daidai bit.
———————————————————-
WRITE_MM: adireshin 4000001 yana samun 00000001.
WRITE_MM: adireshin 4000001 yana samun 00000000.
———————————————————-
RX_SOP COUNTER.
———————————————————-
KARANTA_MM: adireshin 400000c = 0000006a.
———————————————————-
RX_EOP COUNTER.
KARANTA_MM: adireshin 400000d = 0000006a.
———————————————————-
KARANTA_MM: adireshi 4000010 = 00000000.
———————————————————-
Nuna Rahoton Karshe.
———————————————————-
0 An Gano Kuskuren
0 CRC24 an ruwaito kurakurai
106 SOPs da aka watsa
106 EOPs da aka watsa
106 SOPs sun samu
An samu EOPs 106
———————————————————-
Kammala Kwaikwayo
———————————————————-
GWAJI YA CI GABA
———————————————————-
Lura: Adadin fakiti (SOPs da EOPs) sun bambanta kowane layi a cikin ƙirar Interlaken Lookside ex.ample simulation sampda fitarwa.
Bayanai masu alaƙa
Tsarin Hardware Example Abubuwan da ke shafi na 6
1.6. Ƙirƙirar da Ƙaddamar da Zane Exampa cikin Hardware

Hoto 9. Tsari

Don haɗawa da gudanar da gwajin gwaji akan hardware exampdon tsarawa, bi waɗannan matakan:

1. Tabbatar da hardware example zane tsara ya cika.
2. A cikin software na Intel Quartus Prime Pro Edition, buɗe aikin Intel Quartus Primeample_installation_dir>/ misaliample_design/quartus/ example_design.qpf>.
3. A cikin menu na sarrafawa, danna Fara Tari.
4. Bayan nasarar hadawa, a .sof file yana samuwa a cikin ƙayyadadden kundin adireshi.
   Bi waɗannan matakan don tsara kayan aikin exampZane akan na'urar Intel Agilex:
5. Haɗa Intel Agilex F-Series Transceiver-SoC Development Kit zuwa kwamfutar mai masaukin baki.
   b. Kaddamar da aikace-aikacen Sarrafa Agogo, wanda wani ɓangare ne na kayan haɓakawa, kuma saita sabbin mitoci don ƙirar ƙira.ample. A ƙasa akwai saitunan mitar a cikin aikace-aikacen Ikon Agogo:
   • Si5338 (U37), CLK1- 100 MHz
   • Si5338 (U36), CLK2- 153.6 MHz
   • Si549 (Y2), OUT- Saita zuwa ƙimar pll_ref_clk (1) gwargwadon buƙatun ƙirar ku.
   c. A cikin Tools menu, danna Programmer.
   d. A cikin Programmer, danna Saitin Hardware.
   e. Zaɓi na'urar shirye-shirye.
   f. Zaɓi kuma ƙara Intel Agilex F-Series Transceiver-SoC Development Kit wanda zaman ku na Intel Quartus Prime zai iya haɗawa.
   g. Tabbatar cewa an saita Yanayin zuwa JTAG.
   h. Zaɓi na'urar Intel Agilex kuma danna Ƙara Na'ura. Mai Shirya shirye-shirye yana nuna zanen toshewar haɗin kai tsakanin na'urorin da ke kan allo.
   i. A cikin jere tare da sof ɗinku, duba akwatin don .sof.
   j. Duba akwatin da ke cikin ginshiƙin Shirin/Sanya.
   k. Danna Fara.

Bayanai masu alaƙa

• Shirye-shiryen na'urorin Intel FPGA shafi na 0
• Nazari da Gyara Zane-zane tare da Console System
• Intel Agilex F-Series Transceiver-SoC Jagoran Mai Amfani da Kit ɗin Haɓakawa

1.7. Gwajin Tsarin Hardware Example
Bayan kun tattara Interlaken (2nd Generation) Intel FPGA IP core design exampkuma saita na'urarka, zaku iya amfani da System Console don tsara ainihin IP da maƙallan sa na asali na PHY IP core rajista.
Bi waɗannan matakan don kawo tsarin Console da gwada ƙirar kayan masarufiampda:

1. A cikin Intel Quartus Prime Pro Edition software, akan menu na Kayan aiki, danna Kayan aikin Debugging System ➤ System Console.
2. Canza zuwaample_installation_dir>example_design/ hwest directory.
3. Don buɗe haɗi zuwa JTAG master, rubuta umarni mai zuwa: source sysconsole_testbench.tcl
4. Kuna iya kunna yanayin madauki na ciki na ciki tare da ƙira mai zuwaampda umarni:
   a. stat: Yana buga bayanan halin gaba ɗaya.
   b. sys_reset: Yana sake saita tsarin.
   c. loop_on: Yana kunna madauki na ciki.
   d. run_example_design: Yana gudanar da zane example.
   Lura: Dole ne ku gudanar da umarnin loop_on kafin run_exampumurnin le_design.
   Run_example_design yana gudanar da umarni masu zuwa a jere:
   sys_reset->stat->gen_on->stat->gen_off.
   Lura: Lokacin da kuka zaɓi Zaɓin Enable adaptation load soft IP option, da run_exampUmurnin le_design yana yin daidaitaccen daidaitawa na farko a gefen RX ta hanyar gudanar da umarnin run_load_PMA_configuration.
5. Kuna iya kashe yanayin madauki na ciki na ciki tare da ƙira mai zuwaampda umurnin:
   a. loop_off: Yana kashe madauki na ciki.
6. Kuna iya tsara tushen IP tare da ƙarin ƙira mai zuwaampda umarni:
   a. gen_on: Yana kunna janareta fakiti.
   b. gen_off: Yana kashe janareta fakiti.
   c. run_test_loop: Yana gudanar da gwajin don sau don E-tile NRZ da PAM4 bambancin.
   d. clear_err: Yana share duk ɓangarorin kurakurai masu ɗaure.
   e. saita_mode_test_mode : Yana saita gwaji don gudana a cikin takamaiman yanayi.
   f. get_test_mode: Yana buga yanayin gwaji na yanzu.
   g. saita_burst_size : Yana saita girman fashe cikin bytes.
   h. get_burst_size: Fashe bayanin girman fashe.

Gwajin nasara yana buga HW_TEST: PASS saƙo. A ƙasa akwai sharuɗɗan wucewa don gwajin gwaji:

• Babu kurakurai don CRC32, CRC24, da mai duba.
• SOPs da aka watsa da EOPs yakamata su dace da karɓa.

Mai zuwa sampLe fitarwa yana kwatanta nasarar gwajin gwagwarmaya a yanayin Interlaken:
BAYANI: BAYANI: Dakatar da samar da fakiti
==== LABARI CIKIN HALI ====
TX KHz: 402813
Saukewa: 402813
Makullin Freq: 0x0000ff
TX PLL kulle: 0x000001
Matsakaicin: 0x00c10f
Rx LOA: 0x000000
Tx LOA: 0x000000
kulle kalma: 0x0000ff
kulle aiki tare: 0x0000ff
Kurakurai CRC32: 0
Kurakurai CRC24: 0
Kurakurai masu dubawa: 0
FIFO kuskuren tutoci: 0x000000
SOPs da aka watsa: 1087913770
An aika EOPs: 1087913770
An karɓi SOPs: 1087913770
An karɓi EOPs: 1087913770
ECC gyara: 0
Kuskuren ECC: 0
Ya ƙare 161 seconds tun lokacin da aka kunna wutar lantarki
HW_TEST : WUCE
Gwajin nasara yana buga HW_TEST : saƙon PASS. A ƙasa akwai sharuɗɗan wucewa don gwajin gwaji:

• Babu kurakurai don CRC32, CRC24, da mai duba.
• SOPs da aka watsa da EOPs yakamata su dace da karɓa.

Mai zuwa sampLe fitarwa yana kwatanta nasarar gwajin gwagwarmaya a yanayin Interlaken Lookside:
BAYANI: BAYANI: Dakatar da samar da fakiti
==== LABARI CIKIN HALI ====
TX KHz: 402813
Saukewa: 402812
Makullin freq: 0x000ff
TX PLL kulle: 0x000001
Matsakaicin: 0x00c10f
Rx LOA: 0x000000
Tx LOA: 0x000000
kulle kalma: 0x000ff
kulle aiki tare: 0x000ff
Kurakurai CRC32: 0
Kurakurai CRC24: 0
Kurakurai masu dubawa: 0
SOPs da aka watsa: 461
An aika EOPs: 461
An karɓi SOPs: 461
An karɓi EOPs: 461
Ya ƙare 171 seconds tun lokacin da aka kunna wutar lantarki
HW_TEST : WUCE

Zane Example Bayanin

Zane example yana nuna ayyukan Interlaken IP core.
Bayanai masu alaƙa
Interlaken (ƙarni na biyu) FPGA IP Jagorar mai amfani
2.1. Zane Exampda Halaye
Don gwada ƙira a cikin hardware, rubuta waɗannan umarni a cikin System Console ::

1. Tushen saitin file:
   % tushenample>uflex_ilk_0_example_design/example_design/hwtest/sysconsole_testbench.tcl
2. Guda gwajin:
   % run_example_design
3. Interlaken (2nd Generation) ƙirar kayan masarufi example kammala wadannan matakai:
   a. Yana sake saita Interlaken (2nd Generation) IP.
   b. Yana saita Interlaken (2nd Generation) IP a yanayin madauki na ciki.
   c. Yana aika rafi na fakitin Interlaken tare da ƙayyadaddun bayanai a cikin abin da ake biya zuwa wurin musayar bayanan mai amfani na TX na tushen IP.
   d. Yana duba fakitin da aka karɓa kuma ya ba da rahoton matsayin. Mai duba fakitin da aka haɗa a cikin ƙirar kayan masarufi example yana ba da damar duba fakiti masu zuwa:
   • Yana duba cewa jerin fakitin da aka watsa daidai ne.
   Yana bincika cewa bayanan da aka karɓa sun yi daidai da ƙimar da ake tsammani ta hanyar tabbatar da farkon fakiti (SOP) da ƙarshen fakiti (EOP) suna daidaitawa yayin da ake watsa bayanai da karɓa.

2.2. Siginonin Sadarwa
Tebur 5. Zane Exampda Alamar Interface

Sunan tashar jiragen ruwa	Hanyar	Nisa (Bits)	Bayani
mgmt_clk	Shigarwa	1	Shigar da agogon tsarin. Mitar agogo dole ne ya zama 100 MHz.
pll_ref_clk /pll_ref_clk[1:0] (2)	Shigarwa	2-Janairu	Agogon magana mai jujjuyawa. Yana fitar da RX CDR PLL.

Sunan tashar jiragen ruwa	Hanyar	Nisa (Bits)	Bayani
			pll_ref_clk[1] yana samuwa ne kawai idan kun kunna Ajiye mara amfani Lura: tashoshin transceiver don PAM4 siga a cikin E-tile PAM4 yanayin IP bambancin.
rx_pin	Shigarwa	Yawan hanyoyi	fil ɗin bayanan mai karɓar SErdES.
tx_pin	Fitowa	Yawan hanyoyi	Aika fil ɗin bayanan SErdES.
rx_pin_n	Shigarwa	Yawan hanyoyi	fil ɗin bayanan mai karɓar SErdES. Ana samun wannan siginar a cikin bambance-bambancen na'urar E-tile PAM4 kawai.
tx_pin_n	Fitowa	Yawan hanyoyi	Aika fil ɗin bayanan SErdES. Ana samun wannan siginar a cikin bambance-bambancen na'urar E-tile PAM4 kawai.
mac_clk_pll_ref	Shigarwa	1	Dole ne PLL ke tafiyar da wannan siginar kuma dole ne yayi amfani da tushen agogo iri ɗaya wanda ke tafiyar da pll_ref_clk. Ana samun wannan siginar a cikin bambance-bambancen na'urar E-tile PAM4 kawai.
usr_pb_reset_n	Shigarwa	1	Sake saitin tsarin.

Bayanai masu alaƙa
Siginonin Sadarwa
2.3. Rajista taswira
Lura:

• Zane Exampadireshin rajista yana farawa da 0x20** yayin da adireshin IP na Interlaken ya fara da 0x10**.
• Lambar shiga: RO — Karanta Kawai, da RW — Karanta/Rubuta.
• Na'urar wasan bidiyo na tsarin tana karanta zanen exampLe yayi rijista kuma yayi rahoton matsayin gwajin akan allon.

Tebur 6. Zane ExampYi Rajista taswirar don Ƙirƙirar Ƙira ta Interlaken Example

Kashewa	Suna	Shiga	Bayani
8'h00	Ajiye
8'h01	Ajiye
8'h02	Sake saitin tsarin PLL	RO	Masu bin ragowa suna nuna buƙatar sake saitin PLL na tsarin kuma yana ba da ƙimar: • Bit [0] - sys_pll_rst_req • Bit [1] - sys_pll_rst_en
8'h03	Hanyar RX ta daidaita	RO	Yana nuna daidaita layin RX.
8'h04	KALMOMI a kulle	RO	[NUM_LANES–1:0] - Kalma (katange) tantance iyakoki.

(2) Lokacin da ka kunna Kiyaye tashoshin transceiver da ba a yi amfani da su ba don sigar PAM4, ana ƙara ƙarin tashar tashar agogon tunani don adana tashar bawa PAM4 da ba a yi amfani da ita ba.

Kashewa	Suna	Shiga	Bayani
8'h05	A kulle sync	RO	[NUM_LANES–1:0] - Aiki tare da metaframe.
8'h06-8h09	Ƙididdigar kuskuren CRC32	RO	Yana nuna ƙidaya kuskuren CRC32.
8 h0a	Ƙididdigar kuskuren CRC24	RO	Yana nuna ƙidaya kuskuren CRC24.
8 h0b	Alamar ambaliya/karɓar ruwa	RO	Abubuwan da ke biyo baya suna nuna: • Bit [3] - TX siginar ƙarƙashin ruwa • Bit [2] – TX siginar ambaliya • Bit [1] – RX siginar ambaliya
8 h0c	Ƙididdigar SOP	RO	Yana nuna adadin SOP.
8 h0d	Adadin EOP	RO	Yana nuna adadin EOP
8 h0e	Ƙidaya kuskure	RO	Yana nuna adadin kurakurai masu zuwa: • Rashin daidaita layi • Kalmar sarrafa ba bisa ka'ida ba • Tsarin ƙira ba bisa ka'ida ba • Rashin SOP ko alamar EOP
8 h0f	aika_data_mm_clk	RW	Rubuta 1 zuwa bit [0] don kunna siginar janareta.
8'h10	Kuskuren dubawa		Yana nuna kuskuren mai duba. (Kuskuren bayanan SOP, Kuskuren lambar tashar, da kuskuren bayanan PLD)
8'h11	Kulle tsarin PLL	RO	Bit [0] yana nuna alamar kulle PLL.
8'h14	Farashin TX SOP	RO	Yana nuna adadin SOP wanda janareta na fakiti ya samar.
8'h15	Farashin TX EOP	RO	Yana nuna adadin EOP wanda janareta na fakiti ya samar.
8'h16	Fakitin ci gaba	RW	Rubuta 1 zuwa bit [0] don kunna fakitin ci gaba.
8'h39	Ƙididdigar kuskuren ECC	RO	Yana nuna adadin kurakuran ECC.
8'h40	ECC ta gyara ƙidayar kuskure	RO	Yana nuna adadin kurakuran ECC da aka gyara.

Tebur 7. Zane Exampda Rijista taswira don Ƙirar Kallon Interlaken Example
Yi amfani da wannan taswirar rajista lokacin da kuke samar da ƙira examptare da Kunna siginar duba-gefe na Interlaken.

Kashewa	Suna	Shiga	Bayani
8'h00	Ajiye
8'h01	Sake saitin Counter	RO	Rubuta 1 zuwa bit [0] don share TX da RX counter daidai bit.
8'h02	Sake saitin tsarin PLL	RO	Masu bin ragowa suna nuna buƙatar sake saitin PLL na tsarin kuma yana ba da ƙimar: • Bit [0] - sys_pll_rst_req • Bit [1] - sys_pll_rst_en
8'h03	Hanyar RX ta daidaita	RO	Yana nuna daidaita layin RX.
8'h04	KALMOMI a kulle	RO	[NUM_LANES–1:0] - Kalma (katange) tantance iyakoki.
8'h05	A kulle sync	RO	[NUM_LANES–1:0] - Aiki tare da metaframe.
8'h06-8h09	Ƙididdigar kuskuren CRC32	RO	Yana nuna ƙidaya kuskuren CRC32.
8 h0a	Ƙididdigar kuskuren CRC24	RO	Yana nuna ƙidaya kuskuren CRC24.

Kashewa	Suna	Shiga	Bayani
8 h0b	Ajiye
8 h0c	Ƙididdigar SOP	RO	Yana nuna adadin SOP.
8 h0d	Adadin EOP	RO	Yana nuna adadin EOP
8 h0e	Ƙidaya kuskure	RO	Yana nuna adadin kurakurai masu zuwa: • Rashin daidaita layi • Kalmar sarrafa ba bisa ka'ida ba • Tsarin ƙira ba bisa ka'ida ba • Rashin SOP ko alamar EOP
8 h0f	aika_data_mm_clk	RW	Rubuta 1 zuwa bit [0] don kunna siginar janareta.
8'h10	Kuskuren dubawa	RO	Yana nuna kuskuren mai duba. (Kuskuren bayanan SOP, Kuskuren lambar tashar, da kuskuren bayanan PLD)
8'h11	Kulle tsarin PLL	RO	Bit [0] yana nuna alamar kulle PLL.
8'h13	Ƙididdigar latency	RO	Yana nuna adadin latency.
8'h14	Farashin TX SOP	RO	Yana nuna adadin SOP wanda janareta na fakiti ya samar.
8'h15	Farashin TX EOP	RO	Yana nuna adadin EOP wanda janareta na fakiti ya samar.
8'h16	Fakitin ci gaba	RO	Rubuta 1 zuwa bit [0] don kunna fakitin ci gaba.
8'h17	TX da RX counter daidai	RW	Yana nuna TX da counter RX daidai suke.
8'h23	Kunna jinkiri	WO	Rubuta 1 zuwa bit [0] don kunna ma'aunin latency.
8'h24	Latency a shirye	RO	Yana nuna an shirya ma'aunin latency.

Interlaken (ƙarni na biyu) Intel Agilex FPGA IP Design ExampRukunin Rubutun Jagorar Mai Amfani

Don sabbin juzu'ai da na baya na wannan jagorar mai amfani, koma zuwa Interlaken (2nd Generation) Intel Agilex FPGA IP Design ExampJagorar Mai Amfani HTML version. Zaɓi nau'in kuma danna Zazzagewa. Idan ba a jera sigar IP ko software ba, jagorar mai amfani na IP ɗin da ta gabata ko sigar software ta shafi.
Sifofin IP iri ɗaya ne da nau'ikan software na Intel Quartus Prime Design Suite har zuwa v19.1. Daga Intel Quartus Prime Design Suite software version 19.2 ko kuma daga baya, IP cores suna da sabon tsarin sigar IP.

Tarihin Bita na Takardu don Interlaken (ƙarni na biyu) Intel Agilex FPGA IP Design ExampJagorar Mai Amfani

Sigar Takardu	Intel Quartus Prime Version	Sigar IP	Canje-canje
2022.08.03	21.3	20.0.1	An gyara na'urar OPN don Intel Agilex F-Series Transceiver-SoC Development Kit.
2021.10.04	21.3	20.0.1	• Ƙara tallafi don na'urar kwaikwayo ta QuestaSim. • Cire tallafi don na'urar kwaikwayo ta NCSim.
2021.02.24	20.4	20.0.1	Ƙarin bayani game da adana tashar transceiver da ba a yi amfani da ita ba don PAM4 a cikin sashe: Hardware Design ExampAbubuwan da aka gyara. • Ƙara bayanin siginar pll_ref_clk[1] a cikin sashe: Siginonin mu'amala.
2020.12.14	20.4	20.0.0	• An sabunta sampFitowar gwajin kayan aikin don yanayin Interlaken da yanayin kallon-gefe na Interlaken a cikin sashe Gwada Tsarin Hardware Ex.ample. • An sabunta taswirar rijista don ƙirar Interlaken Look-side exampa cikin sashe Rajista taswira. • Ƙara ma'auni na wucewa don nasarar gwajin kayan aiki a cikin sashe Gwada Tsarin Hardware Example.
2020.10.16	20.2	19.3.0	Umarnin da aka gyara don gudanar da daidaitawar daidaitawa ta farko a gefen RX a Gwaji da Tsarin Hardware Exampsashe.
2020.06.22	20.2	19.3.0	• The zane example yana samuwa don yanayin kallon gefe na Interlaken. • Gwajin kayan aiki na ƙira example yana samuwa don bambancin na'urar Intel Agilex. • Ƙara Hoto: Babban Matsayin Toshe Hoto don Interlaken (ƙarni na biyu) Zane Example. • Sabunta sassa masu zuwa: – Hardware da Bukatun Software – Tsarin Jagora • Canza waɗannan alkaluman don haɗawa da sabuntawa masu alaƙa da Interlaken Look: – Figure: Interlaken (2nd Generation) Hardware Design Exampda High Tsarin Toshe Mataki na E-tile NRZ Bambance-bambancen Yanayin – Figure: Interlaken (2nd Generation) Hardware Design Example Babban Matsayin Toshe Hoto don E-tile PAM4 Yanayin Bambance-bambance Hoto da aka sabunta: Editan Sigar IP. • Ƙarin bayani game da saitunan mitar a cikin aikace-aikacen sarrafa agogo a sashe Haɗawa da Ƙaddamar da Zane Exampa cikin Hardware.

Sigar Takardu	Intel Quartus Prime Version	Sigar IP	Canje-canje
			• Ƙara abubuwan gudanar da gwajin don Interlaken Look a gefe a cikin sassan masu zuwa: – Simulating da Design Exampda Testbench - Gwajin Zane-zanen Hardware Example • Ƙara waɗannan sabbin sigina a cikin sashin Siginonin Sadarwa: - mgmt_clk - rx_pin_n - tx_pin_n - mac_clk_pll_ref • Ƙara taswirar rajista don ƙirar Interlaken Look-side example a sashe: Rajista taswira.
2019.09.30	19.3	19.2.1	An cire clk100. mgmt_clk yana aiki azaman agogon nuni ga IO PLL a cikin masu zuwa: Hoto: Interlaken (2nd Generation) Hardware Design Example High Level Toshe zane don E-tile NRZ Mode Bambancin. Hoto: Interlaken (2nd Generation) Hardware Design Example Babban Matsayin Toshe Hoto don E-tile PAM4 Mode Bambancin.
2019.07.01	19.2	19.2	Sakin farko.

Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka.
*Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.
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Interlaken (ƙarni na biyu) Intel® Agilex™ FPGA IP Design ExampJagorar Mai Amfani

Online Version
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Saukewa: 683800
Saukewa: UG-20239
Shafin: 2022.08.03

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intel Interlaken (2nd Generation) Agilex FPGA IP Design Example [pdf] Jagorar mai amfani Interlaken 2nd Generation Agilex FPGA IP Design Example, Interlaken, 2nd Generation Agilex FPGA IP Design Example, Agilex FPGA IP Design Example, IP Design Example

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