I-Interlaken (2nd Generation) Intel ®
I-Agilex™ I-FPGA IP Design Example
Umhlahlandlela Womsebenzisi

Quick Start Guide

I-Interlaken (2nd Generation) FPGA IP core inikeza ibhentshi lokuhlola lokulingisa kanye ne-ex yedizayini yehadiwe.ample esekela ukuhlanganiswa nokuhlolwa kwehadiwe. Uma udala i-ex designample, umhleli wepharamitha udala ngokuzenzakalelayo i filekudingekile ukulingisa, ukuhlanganisa, nokuhlola idizayini kuhadiwe. Umklamo exampI-le iyatholakala futhi ngesici se-Interlaken Look-aside.
I-testbench kanye ne-design example isekela imodi ye-NRZ ne-PAM4 yamadivayisi we-E-tile. I-Interlaken (2nd Generation) FPGA IP core ikhiqiza i-design exampi-les yazo zonke izinhlanganisela ezisekelwayo zenani lemizila namazinga wedatha.

Umfanekiso 1. Izinyathelo Zokuthuthukisa Zomklamo Example

I-Interlaken (2nd Generation) IP core design example isekela izici ezilandelayo:

• I-TX yangaphakathi kuya kumodi ye-serial loopback ye-RX
• Yakha ngokuzenzakalelayo amaphakethe osayizi ongashintshi
• Amakhono okuhlola iphakethe ayisisekelo
• Ikhono lokusebenzisa Ikhonsoli Yesistimu ukuze usethe kabusha idizayini ngenjongo yokuhlola kabusha
• Ukushintsha kwe-PMA

Umfanekiso 2. Umdwebo Webhulokhi Osezingeni eliphezulu we-Interlaken (Isizukulwane Sesibili) Umklamo Example

Ulwazi Oluhlobene

• I-Interlaken (2nd Generation) FPGA IP User Guide
• I-Interlaken (2nd Generation) Intel FPGA IP Release Notes

1.1. Izingxenyekazi zekhompuyutha nezidingo zeSoftware
Ukuhlola i-example design, sebenzisa ihadiwe nesoftware elandelayo:

• Isoftware ye-Intel® Prime Pro Edition engu-21.3
• Ikhonsoli Yesistimu
• Izilingisi ezisekelwayo:
  — Siemens* EDA ModelSim* SE noma QuestaSim*
  - Synopsy* VCS*
  -Cadence* Xcelium*
• I-Intel Agilex® Quartus™ F-Series Transceiver-SoC Development Kit (AGFB014R24A2E2V)

Ulwazi Oluhlobene
I-Intel Agilex F-Series Transceiver-SoC Development Kit User Guide
1.2. Ukwakheka Kwemibhalo
I-Interlaken (2nd Generation) IP core design example file uhla lwemibhalo luqukethe okulandelayo okwenziwe files ye-design example.
Umfanekiso 3. Ukwakheka Kwemibhalo Ye-Interlaken Ekhiqizwayo (Isizukulwane Sesibili) Eksample Design

Ukucushwa kwehadiwe, ukulingisa, nokuhlola files atholakala kuample_installation_dir>/uflex_ilk_0_example_design.
Ithebula 1. I-Interlaken (Isizukulwane Sesibili) IP Core Hardware Design Example File Izincazelo
Lezi files zikuample_installation_dir>/uflex_ilk_0_example_design/ example_design/quartus directory.

File Amagama	Incazelo
example_design.qpf	Iphrojekthi ye-Intel Quartus Prime file.
example_design.qsf	Izilungiselelo zephrojekthi ye-Intel Quartus Prime file
example_design.sdc jtag_timing_template.sdc	I-Synopsys Design Constraint file. Ungakopisha futhi ulungisele umklamo wakho.
sysconsole_testbench.tcl	Okuyinhloko file ukuze ufinyelele Ikhonsoli Yesistimu

Ithebula 2. Interlaken (2nd Generation) IP Core Testbench File Incazelo
Lokhu file ikuample_installation_dir>/uflex_ilk_0_example_design/ example_design/rtl directory.

File Igama	Incazelo
top_tb.sv	I-testbench yezinga eliphezulu file.

Ithebula 3. nterlaken (2nd Generation) IP Core Testbench Scripts
Lezi files zikuample_installation_dir>/uflex_ilk_0_example_design/ example_design/testbench directory.

File Igama	Incazelo
vcstest.sh	Iskripthi se-VCS sokuqalisa ibhentshi le-test.
vlog_pro.do	Iskripthi se-ModelSim SE noma i-QuestaSim sokuqalisa ibhentshi le-test.
xcelium.sh	Iskripthi se-Xcelium sokuqalisa ibhentshi lokuhlola.

1.3. I-Hardware Design Example Components
I-exampi-le design ixhuma amawashi ereferensi wesistimu kanye ne-PLL kanye nezingxenye zokuklama ezidingekayo. I-exampi-le design ilungisa i-IP core kumodi ye-loopback yangaphakathi futhi ikhiqize amaphakethe ku-IP core TX yokudlulisa idatha yomsebenzisi. I-IP core ithumela lawa maphakethe kumzila we-loopback wangaphakathi nge-transceiver.
Ngemuva kokuthi umamukeli oyinhloko we-IP ethole amaphakethe endleleni ye-loopback, icubungula amaphakethe e-Interlaken futhi iwathumele kusixhumi esibonakalayo sokudlulisa idatha yomsebenzisi we-RX. I-exampi-le design ihlola ukuthi amaphakethe atholiwe futhi adluliselwe afanayo.
I-hardware example design ihlanganisa ama-PLL angaphandle. Ungakwazi ukuhlola umbhalo ocacile files kwe view sample code esebenzisa indlela eyodwa engenzeka yokuxhuma ama-PLL angaphandle ku-Interlaken (2nd Generation) FPGA IP.
I-Interlaken (2nd Generation) ye-hardware design example ihlanganisa izingxenye ezilandelayo:

1. I-Interlaken (2nd Generation) FPGA IP
2. I-Packet Generator kanye ne-Packet Checker
3. JTAG isilawuli esixhumana ne-System Console. Uxhumana ne-logic yeklayenti nge-System Console.

Umfanekiso 4. I-Interlaken (Isizukulwane Sesibili) I-Hardware Design Example High Level Block Diagram for E-tile NRZ Mode Variations

I-Interlaken (2nd Generation) ye-hardware design example eqondise ukuhluka kwemodi ye-E-tile PAM4 idinga iwashi elengeziwe mac_clkin elenziwa yi-IO PLL. Le PLL kufanele isebenzise iwashi lesithenjwa elifanayo elishayela i-pll_ref_clk.

Umfanekiso 5. I-Interlaken (Isizukulwane Sesibili) I-Hardware Design Example High Level
Vimba Umdwebo Wokuhlukahluka Kwemodi ye-E-tile PAM4

Ngokuhlukahluka kwemodi ye-E-tile PAM4, uma unika amandla okuthi Londoloza amashaneli e-transceiver angasetshenzisiwe kupharamitha ye-PAM4, imbobo yewashi yesithenjwa eyengeziwe iyengezwa (pll_ref_clk [1]). Lesi simboli kufanele sishayelwe ngefrikhwensi efanayo njengoba kuchazwe kusihleli sepharamitha ye-IP (imvamisa yewashi lesithenjwa yamashaneli agciniwe). I-Gcina amashaneli e-transceiver angasetshenzisiwe ye-PAM4 uyazikhethela. Iphinikhodi nezingqinamba ezihlobene ezinikezwe leli washi zibonakala ku-QSF uma ukhetha i-Intel Stratix® 10 noma ikhithi yokuthuthukisa ye-Intel Agilex yokukhiqiza umklamo.
Okokuklama exampngokulingisa, ibhentshi lokuhlola lihlala lichaza imvamisa efanayo ye-pll_ref_clk[0] kanye ne-pll_ref_clk[1].
Ulwazi Oluhlobene
I-Intel Agilex F-Series Transceiver-SoC Development Kit User Guide
1.4. Ikhiqiza Umklamo

Umfanekiso 6. Inqubo

Landela lezi zinyathelo ukuze ukhiqize i-hardware example design kanye ne-testbench:

1. Kuhlelo lwe-Intel Quartus Prime Pro Edition, chofoza File ➤ Iseluleki Sephrojekthi Esisha sokudala iphrojekthi entsha ye-Intel Quartus Prime, noma chofoza File ➤ Vula Iphrojekthi ukuze uvule iphrojekthi ekhona ye-Intel Quartus Prime. Iwizadi ikutshela ukuthi ucacise idivayisi.
2. Cacisa i-Agilex yomndeni wedivayisi bese ukhetha idivayisi yomklamo wakho.
3. Kukhathalogi ye-IP, thola bese uchofoza kabili i-Interlaken (2nd Generation) Intel FPGA IP. Iwindi elisha le-IP elihlukile liyavela.
4. Cacisa igama lezinga eliphezulu ngokuhlukahluka kwakho kwe-IP yangokwezifiso. Umhleli wepharamitha ugcina izilungiselelo zokuhlukahluka kwe-IP ku-a file okuthiwa .ip.
5. Chofoza okuthi KULUNGILE. Umhleli wepharamitha uyavela.
   Umfanekiso 7. Isbample Design Tab ku-Interlaken (2nd Generation) Intel FPGA IP Parameter Editor
6. Kuthebhu ye-IP, cacisa imingcele yokuhluka kwakho okubalulekile kwe-IP.
7. Kuthebhu ye-PMA Adaptation, cacisa imingcele yokujwayela ye-PMA uma uhlela ukusebenzisa ukulungiswa kwe-PMA kokuhluka kwedivayisi yakho ye-E-tile.
   Lesi sinyathelo singokuzithandela:
   • Khetha Vumela i-IP ethambile yokulayisha umthwalo.
   Qaphela: Kumelwe unike amandla inketho Yephoyinti Yokuqeda Iphutha Le-PHY Yomdabu (NPDME) kuthebhu ye-IP uma ukuzivumelanisa ne-PMA kunikwe amandla.
   • Khetha i-PMA adaptation preset for PMA adaptation Khetha ipharamitha.
   • Chofoza i-PMA Adaptation Preload ukuze ulayishe amapharamitha wokuzijwayeza okuqala nokuqhubekayo.
   • Cacisa inombolo yokucushwa kwe-PMA ozoyisekela lapho ukulungiselelwa okuningi kwe-PMA kunikwe amandla kusetshenziswa Inombolo yepharamitha yokumisa ye-PMA.
   • Khetha ukuthi yikuphi ukucushwa kwe-PMA ozokulayisha noma ukukugcina usebenzisa Khetha ukucushwa kwe-PMA ozokulayisha noma ukukugcina.
   • Chofoza Layisha ukulungisa kusuka ekucushweni okukhethiwe kwe-PMA ukuze ulayishe izilungiselelo ezikhethiwe zokucushwa kwe-PMA.
   Ukuze uthole ulwazi olwengeziwe mayelana nemingcele yokujwayela ye-PMA, bheka ku-E-tile Transceiver PHY User Guide.
8. Ku-Example Design ithebhu, khetha inketho yokulingisa ukuze ukhiqize ibhentshi lokuhlola, bese ukhetha inketho ye-Synthesis ukuze ukhiqize i-hardware ex.ampumklamo.
   Qaphela: Kufanele ukhethe okungenani eyodwa yezinketho Zokulingisa noma Zokuhlanganiswa okukhiqiza i-Example Design Files.
9. Ngefomethi ye-HDL Ekhiqiziwe, i-Verilog kuphela etholakalayo.
10. Kukhithi Yokuthuthukiswa Kwethagethi khetha inketho efanelekile.
    Qaphela: Inketho ye-Intel Agilex F-Series Transceiver SoC Development Kit itholakala kuphela uma iphrojekthi yakho icacisa igama ledivayisi ye-Intel Agilex eqala ngo-AGFA012 noma AGFA014. Uma ukhetha inketho Yekhithi Yokuthuthukisa, imisebenzi yephinikhodi isethwa ngokuya ngenombolo yedivayisi ye-Intel Agilex Development Kit engu-AGFB014R24A2E2V futhi ingase ihluke kudivayisi yakho oyikhethile. Uma uhlose ukuhlola idizayini ku-hardware ku-PCB ehlukile, khetha inketho ethi Ayikho ikhithi yokuthuthukisa bese wenza iphinikhodi elifanele ku-.qsf file.
11. Chofoza okuthi Khiqiza Isibample Design. Khetha ExampIwindi le-Design Directory liyavela.
12. Uma ufuna ukushintsha i-design example mkhombandlela noma igama elivela kokumisiwe okubonisiwe (uflex_ilk_0_example_design), phequlula endleleni entsha bese uthayipha umklamo omusha exampigama lesikhombi.
13. Chofoza okuthi KULUNGILE.

Ulwazi Oluhlobene

• I-Intel Agilex F-Series Transceiver-SoC Development Kit User Guide
• I-E-tile Transceiver PHY Umhlahlandlela Womsebenzisi

1.5. Ukulingisa i-Design Example Testbench
Bheka ku-Interlaken (2nd Generation) Hardware Design Example High Level Block ye-E-tile NRZ Mode Variations kanye ne-Interlaken (2nd Generation) Hardware Design Example High Level Block ye-E-tile PAM4 Mode Ukuhlukahluka kwemidwebo yebhulokhi yebhentshi lokulingisa.

Umfanekiso 8. Inqubo

Landela lezi zinyathelo ukuze ulingise i-testbench:

1. Emyalweni womyalo, shintshela kumkhombandlela wokulingisa we-testbench. Inkomba ithiample_installation_dir>/example_design/ testbench yamadivayisi we-Intel Agilex.
2. Qalisa iskripthi sokulingisa sesifanisi esisekelwayo ozikhethele sona. Umbhalo uhlanganisa futhi uqhube ibhentshi lokuhlola kusifanisi. Iskripthi sakho kufanele sihlole ukuthi izibalo ze-SOP ne-EOP ziyafana ngemva kokuqedwa kokulinganisa. Bheka ithebula Izinyathelo Zokuqalisa Ukulingisa.
   Ithebula 4. Izinyathelo Zokuqalisa Ukulingisa

   Isifanisi	Iziyalezo
   ModelSim SE noma QuestaSim	Emugqeni womyalo, thayipha -do vlog_pro.do. Uma ukhetha ukulingisa ngaphandle kokuletha i-ModelSim GUI, thayipha i-vsim -c -do vlog_pro.do
   I-VCS	Emugqeni womyalo, thayipha okuthi sh vcstest.sh
   I-Xcelium	Emugqeni womyalo, thayipha okuthi sh xcelium.sh

3. Hlaziya imiphumela. Ukulingisa okuphumelelayo kuthumela futhi kwamukele amaphakethe, futhi kubonisa "Ukuhlola KUPHASIWE".

Ibhentshi lokuhlola le-ex designample uqeda imisebenzi elandelayo:

• Iqinisekisa i-Interlaken (2nd Generation) Intel FPGA IP.
• Iphrinta isimo se-PHY.
• Ihlola ukuvumelanisa kwe-metaframe (SYNC_LOCK) nemingcele yegama (vimba) (WORD_LOCK).
• Ilinda imizila ngayinye ukuthi ikhiywe futhi iqondaniswe.
• Iqala ukudlulisa amaphakethe.
• Ihlola izibalo zephakethe:
  - CRC24 amaphutha
  - Ama-SOP
  - EOP

Okulandelayo sampokukhiphayo kubonisa ukuhlolwa okuphumelelayo kokulingisa okwenziwa kumodi ye-Interlaken:
******************************************
ULWAZI: Ilinde imizila ukuthi iqondaniswe.
Yonke imizila yabamukeli iqondile futhi ilungele ukwamukela ithrafikhi.
************************************************
************************************************
ULWAZI: Qala ukudlulisa amaphakethe
************************************************
************************************************
ULWAZI: Yeka ukudlulisa amaphakethe
************************************************
************************************************
ULWAZI: Ihlola izibalo zamaphakethe
************************************************
Amaphutha e-CRC 24 abikiwe: 0
Ama-SOP adlulisiwe: 100
Ama-EOP adlulisiwe: 100
Ama-SOP atholiwe: 100
Ama-EOP atholiwe: 100
Isibalo samaphutha e-ECC: 0
************************************************
ULWAZI: Ukuhlolwa KUPHASIWE
************************************************
Qaphela: I-Interlaken design exampI-le simulation testbench ithumela amaphakethe ayi-100 futhi ithola amaphakethe ayi-100.
Okulandelayo sampokukhiphayo kubonisa ukuhlolwa okuphumelelayo kokulingisa okwenziwa kumodi ye-Interlaken Look-aside:
Hlola i-TX ne-RX Counter iyalingana noma cha.
————————————————————-
FUNDA_MM: ikheli 4000014 = 00000001.
————————————————————-
De-assert Counter elinganayo bit.
————————————————————-
WRITE_MM: ikheli 4000001 lithola 00000001.
WRITE_MM: ikheli 4000001 lithola 00000000.
————————————————————-
RX_SOP COUNTER.
————————————————————-
READ_MM: ikheli 400000c = 0000006a.
————————————————————-
RX_EOP COUNTER.
READ_MM: ikheli 400000d = 0000006a.
————————————————————-
FUNDA_MM: ikheli 4000010 = 00000000.
————————————————————-
Bonisa Umbiko Wokugcina.
————————————————————-
0 Iphutha Elitholiwe
0 amaphutha e-CRC24 abikiwe
106 ama-SOP adlulisiwe
106 EOPs adlulisiwe
106 ama-SOP atholiwe
106 EOPs wamukelwe
————————————————————-
Qeda Ukulingisa
————————————————————-
ISIVIVINYO ESIPHUMILE
————————————————————-
Qaphela: Inani lamaphakethe (ama-SOP nama-EOP) liyahlukahluka ngomzila ngamunye ku-Interlaken Lookaside design example simulation sample okukhiphayo.
Ulwazi Oluhlobene
I-Hardware Design Example Izingxenye ekhasini 6
1.6. Ukuhlanganisa kanye nokulungiselela i-Design Exampku-Hardware

Umfanekiso 9. Inqubo

Ukuhlanganisa nokusebenzisa ukuhlolwa kokubonisa ku-hardware example design, landela lezi zinyathelo:

1. Qinisekisa i-hardware exampi-design generation iqedile.
2. Kuhlelo lwe-Intel Quartus Prime Pro Edition, vula iphrojekthi ye-Intel Quartus Primeample_installation_dir>/example_design/quartus/ example_design.qpf>.
3. Kumenyu Yokucubungula, chofoza Qala Ukuhlanganisa.
4. Ngemva kokuhlanganiswa ngempumelelo, i-.sof file iyatholakala ohlwini lwakho lwemibhalo olushilo.
   Landela lezi zinyathelo ukuze uhlele i-hardware example design kudivayisi ye-Intel Agilex:
5. Xhuma i-Intel Agilex F-Series Transceiver-SoC Development Kit kukhompuyutha engusokhaya.
   b. Yethula uhlelo lokusebenza lokulawula iwashi, oluyingxenye yekhithi yokuthuthukisa, bese usetha amafrikhwensi amasha e-design ex.ample. Ngezansi isethingi yefrikhwensi kuhlelo Lokulawula Iwashi:
   • I-Si5338 (U37), CLK1- 100 MHz
   • I-Si5338 (U36), CLK2- 153.6 MHz
   • Si549 (Y2), OKUPHUMILE- Misa inani le-pll_ref_clk (1) ngokwemfuneko yakho yomklamo.
   c. Kumenyu yamathuluzi, chofoza uMhleli.
   d. Ku-Programmer, chofoza Ukusethwa Kwezingxenyekazi zekhompuyutha.
   e. Khetha idivayisi yokuhlela.
   f. Khetha bese wengeza i-Intel Agilex F-Series Transceiver-SoC Development Kit lapho iseshini yakho ye-Intel Quartus Prime ingaxhumeka kuyo.
   g. Qinisekisa ukuthi Imodi isethwe ku-JTAG.
   h. Khetha idivayisi ye-Intel Agilex bese uchofoza Engeza idivayisi. I-Programmer ibonisa idayagramu yebhlokhi yokuxhumana phakathi kwamadivayisi ebhodini lakho.
   i. Emgqeni ne-.sof yakho, hlola ibhokisi le-.sof.
   j. Thikha ibhokisi kokuthi Uhlelo/Lungisa ikholomu.
   k. Chofoza Qala.

Ulwazi Oluhlobene

• Izinhlelo ze-Intel FPGA Amadivayisi ekhasini 0
• Ukuhlaziya nokulungisa amadizayini nge-System Console
• I-Intel Agilex F-Series Transceiver-SoC Development Kit User Guide

1.7. Ihlola i-Hardware Design Example
Ngemva kokuhlanganisa i-Interlaken (2nd Generation) Intel FPGA IP core design exampfuthi ulungiselele idivayisi yakho, ungasebenzisa Ikhonsoli Yesistimu ukuze uhlele umongo we-IP kanye namarejista awo ayinhloko we-PHY IP ashumekiwe.
Landela lezi zinyathelo ukuze uveze Ikhonsoli Yesistimu futhi uhlole i-ex yedizayini yehadiweample:

1. Kuhlelo lwe-Intel Quartus Prime Pro Edition, kumenyu ethi Amathuluzi, chofoza Amathuluzi Okulungisa Amaphutha Esistimu ➤ Ikhonsoli Yesistimu.
2. Shintsha ku-ample_installation_dir>isibample_design/hwtest directory.
3. Ukuze uvule uxhumano ku-JTAG master, thayipha umyalo olandelayo: umthombo sysconsole_testbench.tcl
4. Ungavula imodi ye-serial loopback ye-serial nge-ex yomklamo elandelayoampngiyala:
   a. izibalo: Iphrinta imininingwane yesimo esijwayelekile.
   b. sys_reset: Isetha kabusha isistimu.
   c. i-loop_on: Ivula i-loopback ye-serial yangaphakathi.
   d. gijima_isbample_design: Isebenzisa i-ex designample.
   Qaphela: Kufanele usebenzise umyalo we-loop_on ngaphambi kwe-run_exampumyalo we_design.
   I-run_exampI-le_design isebenzisa imiyalo elandelayo ngokulandelana:
   sys_reset->stat->gen_on->stat->gen_off.
   Qaphela: Uma ukhetha okuthi Vumela i-adaptation load soft inketho ye-IP, run_exampumyalo we-le_design wenza ukulinganisa kokuqala kokujwayela ohlangothini lwe-RX ngokusebenzisa umyalo we-run_load_PMA_configuration.
5. Ungavala imodi ye-serial loopback yangaphakathi nge-ex yomklamo elandelayoampumyalo othi:
   a. i-loop_off: Ivala i-loopback ye-serial yangaphakathi.
6. Ungakwazi ukuhlela i-IP core nge-ex yedizayini eyengeziwe elandelayoampngiyala:
   a. gen_on: Inika amandla ijeneretha yephakethe.
   b. gen_off: Ikhubaza ijeneretha yephakethe.
   c. run_test_loop: Iqalisa ukuhlolwa kwe izikhathi zokuhlukahluka kwe-E-tile NRZ kanye ne-PAM4.
   d. clear_err: Isula zonke izingcezu zamaphutha anamathelayo.
   e. setha_imodi_yokuhlola : Isetha ukuhlolwa ukuze kuqalise ngemodi ethile.
   f. get_test_mode: Iphrinta imodi yokuhlola yamanje.
   g. set_burst_size : Isetha usayizi wokuqhuma ngamabhayithi.
   h. get_burst_size: Imininingwane kasayizi wokuphrinta.

Ukuhlola okuyimpumelelo kuphrinta umlayezo HW_TEST:PASS. Ngezansi imibandela yokuphasa yokuqaliswa kokuhlolwa:

• Awekho amaphutha e-CRC32, CRC24, nesihloli.
• Ama-SOP adlulisiwe kanye nama-EOP kufanele afane nowamukelwe.

Okulandelayo sampi-le output ibonisa ukuhlolwa okuphumelelayo okwenziwa kumodi ye-Interlaken:
ULWAZI: ULWAZI: Yeka ukukhiqiza amaphakethe
==== UMBIKO WEsimo ====
I-TX KHz : 402813
I-RX KHz : 402813
Ukukhiya okuvamisile: 0x0000ff
Ilokhi ye-TX PLL: 0x000001
Qondanisa: 0x00c10f
I-Rx LOA: 0x000000
Tx LOA : 0x000000
ukukhiya amagama: 0x0000ff
ukukhiya kokuvumelanisa: 0x0000ff
CRC32 amaphutha : 0
CRC24 amaphutha : 0
Amaphutha okuhlola : 0
Amafulegi wephutha we-FIFO : 0x000000
Ama-SOP athunyelwe: 1087913770
Ama-EOP adlulisiwe: 1087913770
Ama-SOP atholiwe: 1087913770
Ama-EOP atholiwe: 1087913770
I-ECC ilungisiwe: 0
Iphutha le-ECC: 0
Kudlule amasekhondi angu-161 kusukela ku-powerup
HW_TEST : PASS
Ukuhlolwa okuphumelelayo kuphrinta HW_TEST : Umlayezo we-PASS. Ngezansi imibandela yokuphasa yokuqaliswa kokuhlolwa:

• Awekho amaphutha e-CRC32, CRC24, nesihloli.
• Ama-SOP adlulisiwe kanye nama-EOP kufanele afane nowamukelwe.

Okulandelayo sampi-le okukhiphayo ibonisa ukuhlolwa okuphumelelayo kumodi ye-Interlaken Lookaside:
ULWAZI: ULWAZI: Yeka ukukhiqiza amaphakethe
==== UMBIKO WEsimo ====
I-TX KHz : 402813
I-RX KHz : 402812
Amalokhi avamile: 0x000ffff
Ilokhi ye-TX PLL: 0x000001
Qondanisa: 0x00c10f
I-Rx LOA: 0x000000
Tx LOA : 0x000000
ukukhiya amagama: 0x000ffff
ukukhiya kokuvumelanisa: 0x000ffff
CRC32 amaphutha : 0
CRC24 amaphutha : 0
Amaphutha okuhlola : 0
Ama-SOP athunyelwe: 461
Ama-EOP adlulisiwe: 461
Ama-SOP atholiwe: 461
Ama-EOP atholiwe: 461
Kudlule amasekhondi angu-171 kusukela ku-powerup
HW_TEST : PASS

I-Design Example Incazelo

Umklamo exampI-le ibonisa ukusebenza kwe-Interlaken IP core.
Ulwazi Oluhlobene
I-Interlaken (2nd Generation) FPGA IP User Guide
2.1. Umklamo Example Behaviour
Ukuze uhlole idizayini kuhadiwe, thayipha imiyalo elandelayo kukhonsoli Yesistimu::

1. Umthombo wokusethwa file:
   % umthomboample>uflex_ilk_0_example_design/example_design/hwtest/sysconsole_testbench.tcl
2. Yenza ukuhlolwa:
   % run_example_design
3. I-Interlaken (2nd Generation) ye-hardware design example uqedela izinyathelo ezilandelayo:
   a. Isetha kabusha i-IP ye-Interlaken (yesizukulwane sesibili).
   b. Ilungiselela i-Interlaken (2nd Generation) IP kumodi ye-loopback yangaphakathi.
   c. Ithumela uchungechunge lwamaphakethe e-Interlaken anedatha echazwe kusengaphambili ekulayishweni okukhokhelwayo kusixhumi esibonakalayo sokudlulisa idatha somsebenzisi we-TX somongo we-IP.
   d. Ihlola amaphakethe atholiwe bese ibika isimo. Isihloli sephakethe esifakwe kumklamo we-hardware exampI-le inikeza amakhono alandelayo okuhlola iphakethe:
   • Ihlola ukuthi ukulandelana kwephakethe elidlulisiwe kulungile.
   • Ihlola ukuthi idatha etholiwe ifana namanani alindelekile ngokuqinisekisa ukuthi izibalo zokuqala zephakethe (SOP) kanye nokuphela kwephakethe (EOP) ziqondana ngenkathi idatha idluliswa futhi yamukelwa.

2.2. Izimpawu Zokuxhumana
Ithebula 5. Idizayini Example Interface Signals

Igama Lembobo	Isiqondiso	Ububanzi (Amabhithi)	Incazelo
mgmt_clk	Okokufaka	1	Okokufaka kwewashi lesistimu. Imvamisa yewashi kufanele ibe ngu-100 MHz.
pll_ref_clk /pll_ref_clk[1:0] (2)	Okokufaka	2-Jan	Iwashi lereferensi ye-Transceiver. Ishayela i-RX CDR PLL.

Igama Lembobo	Isiqondiso	Ububanzi (Amabhithi)	Incazelo
			pll_ref_clk[1] itholakala kuphela uma unika amandla Londoloza okungasetshenzisiwe Qaphela: Amashaneli e-transceiver we-PAM4 ipharamitha ekuhlukeni kwe-IP yemodi ye-E-tile PAM4.
rx_pin	Okokufaka	Inombolo yemizila	Isamukeli sedatha yephinikhodi ye-SERDES.
tx_pin	Okukhiphayo	Inombolo yemizila	Dlulisa iphinikhodi yedatha ye-SERDES.
rx_pin_n	Okokufaka	Inombolo yemizila	Isamukeli sedatha yephinikhodi ye-SERDES. Le siginali itholakala kuphela ezinhlobonhlobo zedivayisi yemodi ye-E-tile PAM4.
tx_pin_n	Okukhiphayo	Inombolo yemizila	Dlulisa iphinikhodi yedatha ye-SERDES. Le siginali itholakala kuphela ezinhlobonhlobo zedivayisi yemodi ye-E-tile PAM4.
mac_clk_pll_ref	Okokufaka	1	Lesi siginali kufanele ishayelwe i-PLL futhi kufanele isebenzise umthombo wewashi ofanayo oshayela i-pll_ref_clk. Le siginali itholakala kuphela ezinhlobonhlobo zedivayisi yemodi ye-E-tile PAM4.
usr_pb_reset_n	Okokufaka	1	Ukuhlelwa kabusha kwesistimu.

Ulwazi Oluhlobene
Izimpawu Zokuxhumana
2.3. Bhalisa imephu
Qaphela:

• I-Design ExampIkheli lerejista liqala ngo-0x20** kuyilapho ikheli lerejista eliyinhloko le-Interlaken IP liqala ngo-0x10**.
• Ikhodi yokufinyelela: RO—Funda Kuphela, kanye ne-RW—Funda/Bhala.
• Ikhonsoli yesistimu ifunda umklamo example irejista futhi ibike isimo sokuhlola esikrinini.

Ithebula 6. Idizayini Example Bhalisa imephu ye-Interlaken Design Example

I-Offset	Igama	Ukufinyelela	Incazelo
8h00	Igodliwe
8h01	Igodliwe
8h02	Ukusethwa kabusha kwesistimu ye-PLL	RO	Amabhithi alandelayo abonisa isicelo sokusetha kabusha uhlelo lwe-PLL futhi unike amandla inani: • Ibhithi [0] – sys_pll_rst_req • Ibhithi [1] – sys_pll_rst_en
8h03	Umzila we-RX uqondaniswe	RO	Ibonisa ukuqondanisa komzila we-RX.
8h04	IZWI likhiyiwe	RO	[NUM_LANES–1:0] – Ukuhlonza imingcele yegama (vimba).

(2) Uma unika amandla okuthi Londoloza amashaneli e-transceiver angasetshenzisiwe kupharamitha ye-PAM4, imbobo yewashi yesithenjwa eyengeziwe iyengezwa ukuze kulondolozwe umzila wezigqila we-PAM4 ongasetshenzisiwe.

I-Offset	Igama	Ukufinyelela	Incazelo
8h05	Ukuvumelanisa kukhiyiwe	RO	[NUM_LANES–1:0] – Ukuvumelanisa i-Metaframe.
8'h06 - 8'h09	Isibalo samaphutha se-CRC32	RO	Ibonisa inani lamaphutha e-CRC32.
8h0a	Isibalo samaphutha se-CRC24	RO	Ibonisa inani lamaphutha e-CRC24.
8h0b	Isignali yokuchichima/Ukugeleza ngaphansi	RO	Amabhithi alandelayo abonisa: • I-Bit [3] – isignali ye-TX egelezayo • I-Bit [2] – isignali yokuchichima ye-TX • Ibhithi [1] – Isignali yokuchichima ye-RX
8h0c	Isibalo se-SOP	RO	Ibonisa inombolo ye-SOP.
8h0D	Ukubala kwe-EOP	RO	Ibonisa inombolo ye-EOP
8h0e	Isibalo samaphutha	RO	Ibonisa inombolo yamaphutha alandelayo: • Ukulahleka kwendlela • Igama lokulawula elingekho emthethweni • Iphethini yozimele engekho emthethweni • I-SOP noma inkomba ye-EOP ayikho
8h0f	send_data_mm_clk	RW	Bhala oku-1 kuye kubhithi [0] ukuze unike amandla isignali yokukhiqiza.
8h10	Iphutha lokuhlola		Ibonisa iphutha lokuhlola. (Iphutha ledatha ye-SOP, iphutha lenombolo yesiteshi, kanye nephutha ledatha ye-PLD)
8h11	Ilokhi yesistimu ye-PLL	RO	I-Bit [0] ibonisa inkomba yokukhiya i-PLL.
8h14	Inani le-TX SOP	RO	Ibonisa inombolo ye-SOP ekhiqizwe ijeneretha yephakethe.
8h15	Inani eliphakeme kakhulu lama-TX EOP	RO	Ibonisa inombolo ye-EOP ekhiqizwe ijeneretha yephakethe.
8h16	Iphakethe eliqhubekayo	RW	Bhala 1 kuya kubhithi [0] ukuze unike amandla iphakethe eliqhubekayo.
8h39	Isibalo samaphutha e-ECC	RO	Ibonisa inombolo yamaphutha e-ECC.
8h40	I-ECC ilungise inani lamaphutha	RO	Ibonisa inombolo yamaphutha e-ECC alungisiwe.

Ithebula 7. Idizayini Example Bhalisa imephu ye-Interlaken Bheka eceleni Yomklamo Example
Sebenzisa le mephu yerejista lapho udala i-ex designample nge-Vula ipharamitha yemodi ye-Interlaken Look-aside evuliwe.

I-Offset	Igama	Ukufinyelela	Incazelo
8h00	Igodliwe
8h01	Setha kabusha isibali	RO	Bhala 1 kuya kubhithi [0] ukuze usule i-TX ne-RX counter bit elinganayo.
8h02	Ukusethwa kabusha kwesistimu ye-PLL	RO	Amabhithi alandelayo abonisa isicelo sokusetha kabusha uhlelo lwe-PLL futhi unike amandla inani: • Ibhithi [0] – sys_pll_rst_req • Ibhithi [1] – sys_pll_rst_en
8h03	Umzila we-RX uqondaniswe	RO	Ibonisa ukuqondanisa komzila we-RX.
8h04	IZWI likhiyiwe	RO	[NUM_LANES–1:0] – Ukuhlonza imingcele yegama (vimba).
8h05	Ukuvumelanisa kukhiyiwe	RO	[NUM_LANES–1:0] – Ukuvumelanisa i-Metaframe.
8'h06 - 8'h09	Isibalo samaphutha se-CRC32	RO	Ibonisa inani lamaphutha e-CRC32.
8h0a	Isibalo samaphutha se-CRC24	RO	Ibonisa inani lamaphutha e-CRC24.

I-Offset	Igama	Ukufinyelela	Incazelo
8h0b	Igodliwe
8h0c	Isibalo se-SOP	RO	Ibonisa inombolo ye-SOP.
8h0D	Ukubala kwe-EOP	RO	Ibonisa inombolo ye-EOP
8h0e	Isibalo samaphutha	RO	Ibonisa inombolo yamaphutha alandelayo: • Ukulahleka kwendlela • Igama lokulawula elingekho emthethweni • Iphethini yozimele engekho emthethweni • I-SOP noma inkomba ye-EOP ayikho
8h0f	send_data_mm_clk	RW	Bhala oku-1 kuye kubhithi [0] ukuze unike amandla isignali yokukhiqiza.
8h10	Iphutha lokuhlola	RO	Ibonisa iphutha lokuhlola. (Iphutha ledatha ye-SOP, iphutha lenombolo yesiteshi, kanye nephutha ledatha ye-PLD)
8h11	Ilokhi yesistimu ye-PLL	RO	I-Bit [0] ibonisa inkomba yokukhiya i-PLL.
8h13	Ukubambezeleka kwesibalo	RO	Ikhombisa inombolo yokubambezeleka.
8h14	Inani le-TX SOP	RO	Ibonisa inombolo ye-SOP ekhiqizwe ijeneretha yephakethe.
8h15	Inani eliphakeme kakhulu lama-TX EOP	RO	Ibonisa inombolo ye-EOP ekhiqizwe ijeneretha yephakethe.
8h16	Iphakethe eliqhubekayo	RO	Bhala 1 kuya kubhithi [0] ukuze unike amandla iphakethe eliqhubekayo.
8h17	Ikhawunta ye-TX ne-RX iyalingana	RW	Ikhombisa ukuthi i-TX ne-RX counter ziyalingana.
8h23	Nika amandla ukubambezeleka	WO	Bhala oku-1 kuye kubhithi [0] ukuze unike amandla ukukala kokubambezeleka.
8h24	Ukubambezeleka kulungile	RO	Ikhombisa ukuthi ukukala ukubambezeleka kulungile.

I-Interlaken (2nd Generation) Intel Agilex FPGA IP Design Example Izingobo zomlando zomhlahlandlela womsebenzisi

Ukuze uthole izinguqulo zakamuva nezidlule zalo mhlahlandlela womsebenzisi, bheka ku I-Interlaken (2nd Generation) Intel Agilex FPGA IP Design Example Umhlahlandlela Womsebenzisi Inguqulo ye-HTML. Khetha inguqulo bese uchofoza Landa. Uma i-IP noma inguqulo yesofthiwe ingekho ohlwini, inkomba yomsebenzisi ye-IP yangaphambilini noma inguqulo yesofthiwe iyasebenza.
Izinguqulo ze-IP ziyefana nezinguqulo zesofthiwe ye-Intel Quartus Prime Design Suite kufika ku-v19.1. Kusukela ku-Intel Quartus Prime Design Suite software version 19.2 noma kamuva, ama-IP cores anohlelo olusha lwenguqulo ye-IP.

Umlando Wokubuyekezwa Kombhalo we-Interlaken (Isizukulwane Sesibili) Intel Agilex FPGA IP Design Example Umhlahlandlela Womsebenzisi

Inguqulo Yedokhumenti	Inguqulo ye-Intel Quartus Prime	Inguqulo ye-IP	Izinguquko
2022.08.03	21.3	20.0.1	Kulungiswe idivayisi ye-OPN ye-Intel Agilex F-Series Transceiver-SoC Development Kit.
2021.10.04	21.3	20.0.1	• Ukwesekwa okwengeziwe kwe-QuestaSim simulator. • Ukwesekwa okususiwe kwe-NCSim simulator.
2021.02.24	20.4	20.0.1	• Ulwazi olungeziwe mayelana nokulondoloza isiteshi sokudlulisa ulwazi esingasetshenzisiwe se-PAM4 esigabeni: I-Hardware Design Example Components. • Kwengezwe incazelo yesignali ye-pll_ref_clk[1] esigabeni: Izignali Zokusebenzelana.
2020.12.14	20.4	20.0.0	• Kubuyekeziwe sample hardware test okukhiphayo kwemodi ye-Interlaken kanye nemodi ye-Interlaken Look-aside esigabeni Ukuhlola I-Hardware Design Example. • Imephu yerejista ebuyekeziwe ye-Interlaken Look-aside design example esigabeni Bhalisa imephu. • Kwengezwe indlela yokuphasa yokuhlolwa kwezingxenyekazi zekhompuyutha ngempumelelo esigabeni Ukuhlola I-Hardware Design Example.
2020.10.16	20.2	19.3.0	Umyalo olungisiwe wokuqalisa ukulinganiswa kokujwayela kokuqala ohlangothini lwe-RX ekuhloleni i-Hardware Design Example ngxenye.
2020.06.22	20.2	19.3.0	• Umklamo exampi-le iyatholakala ngemodi ye-Interlaken Look- eceleni. • Ukuhlolwa kwezingxenyekazi zekhompuyutha ze-design example iyatholakala ngokuhlukahluka kwedivayisi ye-Intel Agilex. • Umfanekiso Ongeziwe: Umdwebo Webhulokhi wezinga eliphezulu we-Interlaken (Isizukulwane Sesibili) Idizayini Example. • Kubuyekezwe izigaba ezilandelayo: - I-Hardware ne-Software Izidingo – Directory Ukwakheka • Kulungiswe izibalo ezilandelayo ukuze kufakwe isibuyekezo esihlobene ne-Interlaken Look-aside: – Umfanekiso: Interlaken (2nd Generation) Hardware Design Example High Umdwebo Webhulokhi Yezinga Lokuhlukahluka Kwemodi ye-E- tile NRZ – Umfanekiso: Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E- tile PAM4 Mode Variations • Umfanekiso Obuyekeziwe: Isihleli Sepharamitha ye-IP. • Ulwazi olungeziwe mayelana nezilungiselelo zefrikhwensi ohlelweni lokusebenza lokulawula iwashi esigabeni Ukuhlanganisa kanye Nokulungiselela I-Design Exampku-Hardware.

Inguqulo Yedokhumenti	Inguqulo ye-Intel Quartus Prime	Inguqulo ye-IP	Izinguquko
			• Kwengezwe imiphumela yokuhlola yokubheka eceleni kwe-Interlaken ezigabeni ezilandelayo: - Ukulinganisa i-Design Example Testbench - Ukuhlola i-Hardware Design Example • Kwengezwe amasiginali amasha alandelayo esigabeni Sezimpawu Zokuxhumana: – mgmt_clk – rx_pin_n – tx_pin_n – mac_clk_pll_ref • Kwengezwe imephu yerejista ye-Interlaken Look-aside design example esigabeni: Bhalisa imephu.
2019.09.30	19.3	19.2.1	Kukhishwe i-clk100. I-mgmt_clk isebenza njengewashi eliyireferensi ku-IO PLL kulokhu okulandelayo: • Umfanekiso: I-Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E-tile NRZ Mode Variations. • Umfanekiso: I-Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E-tile PAM4 Mode Variations.
2019.07.01	19.2	19.2	Ukukhishwa kokuqala.

Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo ye-semiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi.
*Amanye amagama namabhrendi angafunwa njengempahla yabanye.
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I-Interlaken (2nd Generation) Intel® Agilex™ FPGA IP Design Example Umhlahlandlela Womsebenzisi

I-Online Version
Thumela Impendulo
Inombolo yepholisi: 683800
UG-20239
Inguqulo: 2022.08.03

Amadokhumenti / Izinsiza

i-intel Interlaken (isizukulwane sesibili) i-Agilex FPGA IP Design Example [pdf] Umhlahlandlela Womsebenzisi I-Interlaken 2nd Generation Agilex FPGA IP Design Example, Interlaken, 2nd Generation Agilex FPGA IP Design Example, Agilex FPGA IP Design Example, IP Design Example

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